Distributed low dropout linear regulator based on digital-analog hybrid
By using a distributed low-dropout linear regulator based on a hybrid analog-digital architecture, the problems of insufficient voltage sensing points and ineffective power consumption of distributed LDOs under high dynamic loads are solved, achieving fast response and efficient power supply, and significantly improving power supply stability and power consumption optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHONGQING UNIV OF POSTS & TELECOMM
- Filing Date
- 2026-02-03
- Publication Date
- 2026-05-08
AI Technical Summary
Existing distributed low-voltage linear regulators suffer from problems such as insufficient number of voltage sensing points, slow dynamic response speed, insufficient load regulation accuracy, and ineffective power consumption under high dynamic loads. Independent hybrid LDOs have problems with current sharing imbalance and device reliability. Distributed LDOs cannot quickly share transition information, resulting in limited power supply stability and transient performance.
A distributed low-dropout linear regulator based on mixed digital and analog circuitry is adopted, which includes four mixed digital and analog low-dropout linear regulator units and an event-driven oscillator. The voltage sensing points are connected through a ring structure. Digital logic modules and offset comparator modules are used to achieve fast response and efficient control of the power transistor array. The power consumption is optimized by combining the event-driven oscillator.
It achieves low IR voltage drop and fast response capability, with a voltage drop of less than 120mV during load transition and a recovery time of less than 400ns, improving dynamic load regulation capability and power supply stability, and reducing overall power consumption by 30%.
Smart Images
Figure CN121996012A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit power management technology and can be applied to scenarios with high requirements for power supply accuracy and stability, such as high-performance computing, the Internet of Things, and smart terminals. In particular, it relates to a distributed low-dropout linear regulator based on mixed-signal circuit. Background Technology
[0002] With the rapid development of modern electronic technology, heterogeneous, high-performance systems are constantly evolving towards higher performance, lower power consumption, and more complex functional integration. Against this backdrop, distributed low-voltage linear regulator (LDO) power supply networks have rapidly developed as a key power management technology. Their purpose is to address many challenges faced by traditional centralized power supply architectures when dealing with large-scale, highly dynamic loads, such as excessive voltage drop (IR drop), slow dynamic response, and insufficient load regulation accuracy. Distributed LDOs break down a single LDO into multiple smaller LDO instances (or replicate multiple small-capacity LDOs) and deploy them spatially across the power grid. This design increases the number of voltage sensing points and significantly reduces Vdrop detection latency. For example… Figure 1 As shown, after a single LDO is split into two smaller LDOs, each LDO can directly sense the local voltage status and simultaneously supply current to the nearby load, thereby solving the two core problems mentioned above more efficiently.
[0003] Existing technologies typically address these issues in two ways. One approach is to use independent hybrid LDOs. However, independent hybrid LDOs suffer from significant current sharing imbalances, impacting power supply stability and long-term device reliability. Furthermore, in independent hybrid LDOs, the power transistors in the digital and analog loops are independent and not multiplexed, resulting in excessively large power transistor footprints and significantly increasing layout complexity and chip manufacturing costs. The second approach is to use distributed LDOs. However, local LDOs cannot quickly share the transition information of their local sensing points with adjacent LDOs, affecting their transient performance. Additionally, spatially distributed layouts do not maximize the collaborative operation of adjacent LDOs, and the oscillator in a distributed LDO is always operational; when the circuit is stable, the oscillator power consumption is ineffective. Summary of the Invention
[0004] To address the problems existing in the prior art, this invention proposes a distributed low-dropout linear regulator based on mixed-signal voltage regulation, comprising four mixed-signal low-dropout linear regulator units and an event-driven oscillator. Each local mixed-signal low-dropout linear regulator unit is used to detect the voltage state of a voltage sensing point, and the four voltage sensing points are connected by a resistor to form a ring structure. The event-driven oscillator is used to generate the square wave required for operation for each local mixed-signal low-dropout linear regulator unit.
[0005] Furthermore, the local mixed-signal low-dropout linear regulator unit includes a digital logic module, a comparator module with offset, an error amplifier module, and a power transistor array, wherein:
[0006] The digital logic module includes a state machine and a shift register. The state machine is used to switch the loop and adjust the step size of the shift register according to the state of the local voltage sensing point and the states of two adjacent voltage sensing points. The shift register is used to store the control signal of each power transistor in the power transistor array.
[0007] The offset comparator module includes two comparators for obtaining the local voltage state based on the detection value of the local voltage sensing point as input, and using the local voltage state as input to the digital logic module in the local and adjacent mixed-signal low-dropout linear regulator units;
[0008] The error amplifier module is used to connect to the analog loop when the voltage sensing point is stable. It maintains output stability by controlling the gate voltage of the power transistor. A cascaded capacitor and resistor are connected between the negative input and output terminals of the error amplifier module for Miller compensation.
[0009] A power transistor array is used to provide a stable current to the load.
[0010] Furthermore, each power transistor in the power transistor array is connected to the output of the digital logic module through an inverter. The output of the inverter is connected to the gate of the power transistor, the input of the inverter is connected to the output of the digital logic module, the source of the power transistor is connected to the power supply, and the drain of the power transistor serves as the output of the local mixed-signal low-dropout linear regulator unit and is connected to the voltage sensing point.
[0011] Furthermore, the error amplifier module is selected as an error amplifier with common-mode feedback. The positive input terminal of the error amplifier is connected to the reference voltage, and the negative input terminal of the error amplifier module is connected to the output terminal of the local mixed-signal low-dropout linear regulator unit.
[0012] Furthermore, the state machine includes three states: digital operating mode, transition mode, and steady-state mode, wherein:
[0013] If the local mixed-signal low-dropout linear regulator unit and its two adjacent mixed-signal low-dropout linear regulator units both detect that the voltage of the corresponding voltage sensing point deviates from the specified range, then it is in digital operating mode. At this time, the shift register shifts the local voltage sensing point status by a set large step size.
[0014] If only the local mixed-signal low-dropout linear regulator unit detects that the voltage of the corresponding voltage sensing point deviates from the specified range, it enters the conversion mode. At this time, the shift register shifts the local voltage sensing point status with a set small step size.
[0015] If the local hybrid analog-digital low-dropout linear regulator unit and its two adjacent hybrid analog-digital low-dropout linear regulator units do not detect a voltage deviation from the specified range at the corresponding voltage sensing point, then it is in steady-state mode.
[0016] Furthermore, in digital operating mode, the digital logic module outputs a 128-bit high level by default as control signals for the 128 power transistors in the power transistor array. The first control signal is low by default. When the first control signal is high, the power supply terminal of the inverter is connected to the power supply terminal and the ground terminal is connected to the ground terminal. The digital logic module outputs a 128-bit high level by default to switch the inverter to low level, and the power transistor is turned on after being connected to the high level.
[0017] Furthermore, in the conversion mode, the digital logic module tracks the state of each power transistor in the power transistor array and performs an XOR operation on the outputs of two adjacent power transistors. If the XOR value of the i-th bit and the (i+1)-th bit is 0, then the data of the (i-12)-(i+11)-th bits is set to low level and the other bits are set to high level, outputting a 128-bit control signal. The first control signal sets the data of the (i-12)-(i+11)-th bits to high level and the other bits to low level, and the second control signal is set to low level. When the first control signal is low level, the power supply terminal of the inverter is connected to the power supply terminal and the ground terminal is connected to the ground terminal. When the first control signal is high level, the inverter outputs a loop signal selected by the second control signal. When the second control signal is low level, half of the power supply voltage is used as the loop signal.
[0018] Furthermore, in steady-state mode, every bit of the first control signal output by the digital logic module is high, at which time the inverter outputs the loop signal selected by the second control signal; the second control signal output by the digital logic module is high, and the signal output by the output error amplifier module serves as the loop signal. Compared with the prior art, the present invention has the following advantages:
[0019] 1. Compared with traditional LDOs, the circuit structure of this invention has low IR voltage drop and fast response capability under large load: 2×2 distributed layout + fast sharing mechanism of transition information, voltage drop ≤120mV (200mA / 50ns) during load transition, recovery time <400ns, effectively solving the problem of power supply and transient response lag of remote load;
[0020] 2. The LDO of the present invention has high cooperative efficiency: adjacent LDOs respond synchronously to load changes, and the change information of the local sensing point is transmitted to the comparator of the adjacent LDO through the comparator, maximizing the cooperative working potential and significantly improving the dynamic load adjustment capability.
[0021] 3. The circuit structure of this invention has the advantage of low power consumption: the event-driven oscillator avoids steady-state invalid power consumption, and with the multi-module optimized design, the overall power consumption is reduced by more than 30% compared with the traditional solution. Attached Figure Description
[0022] Figure 1 This is a structural diagram of the LDO splitting scheme used in existing technologies;
[0023] Figure 2 This is a schematic diagram of the overall circuit architecture of a distributed low-dropout linear regulator based on mixed-signal voltage regulation according to the present invention.
[0024] Figure 3 This is a high-precision comparator circuit diagram of the present invention;
[0025] Figure 4 This is the event-driven OSC circuit diagram of the present invention;
[0026] Figure 5 This is the state diagram of the digital module state machine of the present invention;
[0027] Figure 6 This is a power transistor array architecture diagram of the present invention. Detailed Implementation
[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0029] This invention proposes a distributed low-dropout linear regulator based on mixed-signal voltage regulation, comprising four mixed-signal low-dropout linear regulator units and an event-driven oscillator. Each local mixed-signal low-dropout linear regulator unit is used to detect the voltage state of a voltage sensing point, and the four voltage sensing points are connected by a resistor to form a ring structure. The event-driven oscillator is used to generate the square wave required for operation for each local mixed-signal low-dropout linear regulator unit.
[0030] like Figure 1The spatial distributed layout design of this invention adopts a 2×2 distributed layout with 4 voltage sensing points. Each voltage sensing point is connected to a hybrid analog-digital low-dropout linear regulator unit (i.e., 101~104). A resistor Rline is set between each voltage sensing point. When a transient event occurs at any voltage sensing point, the three adjacent LDO units respond synchronously, maximizing the collaborative working efficiency of the distributed layout and enhancing the dynamic load regulation capability.
[0031] The single analog-digital LDO hybrid operating mode of this invention includes dual operating modes of digital loop and analog loop, with both loops sharing a power transistor array to significantly save chip area; in steady state, the analog loop takes over operation, and the digital loop stops running; when a transient event occurs at the load point, it automatically switches to the digital loop to quickly complete transient response adjustment. Specifically, as shown... Figure 2 This embodiment uses a hybrid analog-digital low-dropout linear regulator unit 101 as an example for illustration, including:
[0032] The digital logic module (DLogic Controller) includes a state machine and a shift register. The state machine is used for loop switching and shift register step size adjustment based on the state of the local voltage sensing point and the states of two adjacent voltage sensing points. The shift register is used to store the control signals of each power transistor in the power transistor array. In this embodiment, the DLogic Controller determines the current system state based on the output Share1 of the local offset comparator module and the outputs (Share2, Share3) of the offset comparator modules in its adjacent mixed-signal low-dropout linear regulator units (102, 103). Based on the state, it determines the outputs of the first control signal COL1 and the second control signal COL2, and determines whether to control the power transistor array according to the 128-bit signal output by the DLogic Controller based on the control signals. The LDO of this invention has high cooperative efficiency, that is, adjacent LDOs respond synchronously to load changes. The change information of the local sensing point is transmitted to the comparator of the adjacent LDO through the comparator, maximizing the cooperative working potential and significantly improving the dynamic load regulation capability.
[0033] like Figure 5 In the local digital logic module, based on the output Share1 of the comparator module and the outputs Share2 and Share3 of the adjacent offset comparator modules, the state machine can determine three states (digital operating mode, transition mode, and steady-state mode). These states can transition between each other.
[0034] If the local mixed-signal low-dropout linear regulator unit and its two adjacent mixed-signal low-dropout linear regulator units both detect that the voltage of the corresponding voltage sensing point deviates from the specified range, then it is in digital operating mode. At this time, the shift register shifts the local voltage sensing point status by a set large step size.
[0035] If only the local mixed-signal low-dropout linear regulator unit detects that the voltage of the corresponding voltage sensing point deviates from the specified range, it enters the conversion mode. At this time, the shift register shifts the local voltage sensing point status with a set small step size.
[0036] If the local hybrid analog-digital low-dropout linear regulator unit and its two adjacent hybrid analog-digital low-dropout linear regulator units do not detect a voltage deviation from the specified range at the corresponding voltage sensing point, then it is in steady-state mode.
[0037] The first control signal, the second control signal, and the 128-bit power transistor array control signal N<0:127> for each state output are all different. The first control signal is used to control the 2-to-1 multiplexer in the power transistors, and the second control signal is used to control the 2-to-1 multiplexer for loop selection and to control the event-driven oscillator. Where:
[0038] In digital operating mode (State1), by default, every bit of the 128-bit power transistor array control signal N<0:127> of the digital logic module is high. Each bit of this signal is used to control one power transistor in the power transistor array. The first control signal is low by default. When the first control signal is high, the power supply terminal of the inverter is connected to the power supply terminal and the ground terminal is connected to the ground terminal. The high level output of the 128-bit power transistor array control signal N<0:127> of the digital logic module turns the inverter low, and the power transistor is turned on after being connected to the high level.
[0039] In the transition mode (State2), the digital logic module tracks the state of each power transistor in the power transistor array and performs an XOR operation on the outputs of two adjacent power transistors. If the XOR value of the i-th bit and the (i+1)-th bit is 0, then the data of bits i-12 to i+11 are set to low level, and the other bits are set to high level to output a 128-bit control signal. The first control signal sets the data of bits i-12 to i+11 to high level and the other bits to low level, and the second control signal is set to low level. When the first control signal is low level, the power supply terminal of the inverter is connected to the power supply terminal and the ground terminal is connected to the ground terminal. When the first control signal is high level, the inverter outputs a loop signal selected by the second control signal. When the second control signal is low level, half of the power supply voltage is used as the loop signal.
[0040] In steady-state mode (State3), every bit of the first control signal output by the digital logic module is high. At this time, the inverter outputs the loop signal selected by the second control signal. The second control signal output by the digital logic module is high, and the signal output by the output error amplifier module serves as the loop signal.
[0041] like Figure 5EN_com is the shift step control signal of the shift register. In this embodiment, the shift step control signal of the register is determined based on the local detection and adjacent detection signals. When EN_com==0, it indicates steady-state mode; when EN_com==1, it indicates switching mode; and when EN_com>1, it indicates digital mode. This embodiment includes four LDOs, with a total of four load points. The initial state of the register is steady-state mode, i.e., EN_com==0. A fault occurs when any local load point or adjacent load point changes, i.e., when the comparator output Q[1:0] of the local LDO or adjacent LDO is 00 or 11. If only the local LDO fails, EN_com+1 is added, i.e., EN_com==1, and the system enters switching mode. If the local LDO fails and at least one of the adjacent LDOs fails, EN_com+2 or EN_com+3 is added, i.e., EN_com>1, and the system switches to digital mode.
[0042] In this embodiment, the offset comparator module includes two comparators COMP, which are used to obtain the local voltage state based on the detection value of the local voltage sensing point as input, and use the local voltage state as input to the digital logic module in the local and adjacent mixed-signal low-dropout linear regulator units. The output Share1 of this module is used as input to the digital logic module in the mixed-signal low-dropout linear regulator unit (101) and the digital logic module in its adjacent mixed-signal low-dropout linear regulator units (102, 103).
[0043] In this embodiment, the two comparators output a high level if the voltage at the voltage sensing point exceeds the set voltage, and a low level otherwise. The two comparators output a two-bit signal. If both signals are low, it indicates that the voltage at the voltage sensing point is lower than the set voltage. If both signals are high, it indicates that the voltage at the voltage sensing point is higher than the set voltage. Otherwise, it indicates that the voltage at the voltage sensing point is within the set voltage range.
[0044] As an alternative implementation method, such as Figure 3 In this embodiment, each comparator includes a current source I1, a first to a sixth N-type MOSFET, and a first to a sixth P-type MOSFET, wherein:
[0045] The source of all P-type MOSFETs is connected to the current inlet of the current source, and the current outlet of the current source is connected to the drain of the first N-type MOSFET MN1.
[0046] The gate of the first N-type MOS transistor is connected to the gate of the third N-type MOS transistor MN3, and the source of the first N-type MOS transistor, the source of the second N-type MOS transistor MN2, the source of the third N-type MOS transistor, and the source of the fourth N-type MOS transistor MN4 are all connected to the ground terminal.
[0047] The gate and drain of the second N-type MOS transistor are connected together with the gate of the fourth second N-type MOS transistor and the drain of the first P-type MOS transistor MP1.
[0048] The drain of the third N-type MOSFET is connected to the source of the fifth N-type MOSFET MN5 and the source of the sixth N-type MOSFET MN6.
[0049] The drain of the fourth N-type MOSFET is connected to the sixth P-type MOSFET and serves as the output of the comparator.
[0050] The gate of the fifth N-type MOS transistor serves as the negative input terminal of the comparator, and the drain of the fifth N-type MOS transistor is connected to the gate of the first P-type MOS transistor MP1, the gate and drain of the second P-type MOS transistor MP2, the gate of the third P-type MOS transistor MP3, and the drain of the fourth P-type MOS transistor MP4.
[0051] The gate of the sixth N-type MOS transistor serves as the positive input terminal of the comparator. The drain of the sixth N-type MOS transistor is connected to the drain of the third P-type MOS transistor MP3, the gate of the fourth P-type MOS transistor MP4, the gate and drain of the fifth P-type MOS transistor MP5, and the gate of the sixth P-type MOS transistor.
[0052] In this embodiment, the error amplifier module is used to connect to the analog loop when the voltage sensing point is stable, and maintains output stability by controlling the gate voltage of the power transistor. In this embodiment, it includes an error amplifier with common-mode feedback. The positive input of the error amplifier is the reference voltage VREF, the negative input is the voltage of the voltage sensing point, and the common-mode feedback voltage is VCMFB. The input of the error amplifier module and half of the power supply voltage VDD / 2 are used as the input of the two-to-one controller. The two-to-one controller is controlled by the second control signal CLO2 and outputs the loop signal.
[0053] In this embodiment, the power transistor array is used to provide a stable current to the load, such as Figure 6 Each power transistor's source is connected to the power supply terminal VDD, and its drain is connected to the voltage sensing point. The gate receives a 128-bit control signal output from the digital logic module through an inverter. Each bit of the signal is used to control one power transistor in the power transistor array. The output of the inverter is connected to the gate of the power transistor, and the input of the inverter is connected to the output of the digital logic module. The source of the power transistor is connected to the power supply terminal.
[0054] This invention optimizes the overall power consumption of the distributed LDO circuit. In this embodiment, the event-driven OSC only starts running when the digital loop is working (controlled by the second control signal in this embodiment). When the circuit enters a steady state and the analog loop takes over, the OSC automatically shuts down, avoiding unnecessary power consumption and significantly optimizing the overall circuit power consumption.
[0055] As an alternative implementation method, such as Figure 4 The circuit of the event-driven oscillator includes the seventh to thirteenth N-type MOSFETs, the seventh to twelfth P-type MOSFETs, the first to fourth inverters, and an AND gate, wherein:
[0056] The gates of the seventh to thirteenth N-type MOS transistors and the drain of the seventh N-type MOS transistor MN7 are connected to the bias voltage terminal VB, and the sources of the seventh to thirteenth N-type MOS transistors are connected to the ground terminal.
[0057] The drain of the eighth N-type MOSFET MN8 is connected to the drain of the seventh P-type MOSFET MP7.
[0058] The drain of the ninth N-type MOSFET MN9 is connected to the ground terminal of the first inverter INV1;
[0059] The drain of the tenth type N MOSFET MN10 is connected to the ground terminal of the second inverter INV2;
[0060] The drain of the eleventh N-type MOSFET MN11 is connected to the ground terminal of the third inverter INV3;
[0061] The drain of the twelfth N-type MOSFET MN12 is connected to the ground terminal of the first inverter;
[0062] The drain of the thirteenth N-type MOSFET MN13 is connected to the ground terminal of the AND gate.
[0063] The gates of the seventh to twelfth P-type MOSFETs are connected together, and the sources of the seventh to twelfth P-type MOSFETs are connected to the internal power supply terminal VCC of the oscillator.
[0064] The drain of the eighth P-type MOSFET MP8 is connected to the power supply terminal of the first inverter.
[0065] The drain of the ninth P-type MOSFET MP9 is connected to the power supply terminal of the second inverter.
[0066] The drain of the tenth P-type MOSFET MP10 is connected to the power supply terminal of the third inverter.
[0067] The drain of the eleventh P-type MOSFET MP11 is connected to the power supply terminal of the fourth inverter INV4.
[0068] The drain of the twelfth N-type MOSFET MP12 is connected to the power supply terminal of the AND gate.
[0069] The output of the AND gate is connected to the input of the first inverter and outputs the first low-dropout linear regulated signal.
[0070] The output of the first inverter is connected to the input of the second inverter, and outputs a second low-dropout linear regulated signal.
[0071] The output of the second inverter is connected to the input of the third inverter, and outputs the third low-dropout linear regulated signal.
[0072] The output of the third inverter is connected to the input of the fourth inverter, and outputs the fourth low-dropout linear regulated signal.
[0073] The output of the fourth inverter serves as one input to the AND gate, and the second control signal of the digital logic module serves as the other input to the AND gate.
[0074] The event-driven oscillator of this invention avoids steady-state ineffective power consumption. With the addition of a multi-module optimized design, the overall power consumption is reduced by more than 30% compared with traditional solutions.
[0075] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry, characterized in that, It includes four mixed-signal low-dropout linear regulator units and an event-driven oscillator. Each local mixed-signal low-dropout linear regulator unit is used to detect the voltage state of a voltage sensing point, and the four voltage sensing points are connected by a resistor to form a ring structure. The event-driven oscillator is used to generate the square wave required for operation for each local mixed-signal low-dropout linear regulator unit.
2. The distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 1, characterized in that, The local mixed-signal low-dropout linear regulator unit includes a digital logic module, a comparator module with offset, an error amplifier module, and a power transistor array, wherein: The digital logic module includes a state machine and a shift register. The state machine is used to switch the loop and adjust the step size of the shift register according to the state of the local voltage sensing point and the states of two adjacent voltage sensing points. The shift register is used to store the control signal of each power transistor in the power transistor array. The offset comparator module includes two comparators for obtaining the local voltage state based on the detection value of the local voltage sensing point as input, and using the local voltage state as input to the digital logic module in the local and adjacent mixed-signal low-dropout linear regulator units; The error amplifier module is used to connect to the analog loop when the voltage sensing point is stable, and maintains output stability by controlling the gate voltage of the power transistor. A power transistor array is used to provide a stable current to the load.
3. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 2, characterized in that, In the power transistor array, each power transistor is connected to the output of the digital logic module through an inverter. The output of the inverter is connected to the gate of the power transistor, the input of the inverter is connected to the output of the digital logic module, the source of the power transistor is connected to the power supply, and the drain of the power transistor serves as the output of the local mixed-signal low-dropout linear regulator unit and is connected to the voltage sensing point.
4. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 2, characterized in that, The error amplifier module selects an error amplifier with common-mode feedback. The positive input terminal of the error amplifier is connected to the reference voltage, and the negative input terminal of the error amplifier module is connected to the output terminal of the local mixed-signal low-dropout linear regulator unit.
5. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 3, characterized in that, A state machine includes three states: digital operating mode, transition mode, and steady-state mode. If the local mixed-signal low-dropout linear regulator unit and its two adjacent mixed-signal low-dropout linear regulator units both detect that the voltage of the corresponding voltage sensing point deviates from the specified range, then it is in digital operating mode. At this time, the shift register shifts the local voltage sensing point status by a set large step size. If only the local mixed-signal low-dropout linear regulator unit detects that the voltage of the corresponding voltage sensing point deviates from the specified range, it enters the conversion mode. At this time, the shift register shifts the local voltage sensing point status with a set small step size. If the local hybrid analog-digital low-dropout linear regulator unit and its two adjacent hybrid analog-digital low-dropout linear regulator units do not detect a voltage deviation from the specified range at the corresponding voltage sensing point, then it is in steady-state mode.
6. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 5, characterized in that, In digital operating mode, the digital logic module outputs 128 high-level signals by default as control signals for the 128 power transistors in the power transistor array. The first control signal is low by default. When the first control signal is high, the power supply terminal of the inverter is connected to the power supply terminal and the ground terminal is connected to the ground terminal. The digital logic module outputs 128 high-level signals by default to switch the inverter to low level. The power transistors are turned on after being connected to the high level.
7. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 5, characterized in that, In the conversion mode, the digital logic module tracks the state of each power transistor in the power transistor array and performs an XOR operation on the outputs of two adjacent power transistors. If the XOR value of the i-th bit and the (i+1)-th bit is 0, then the data of the (i-12)-(i+11)-th bits is set to low level and the other bits are set to high level, outputting a 128-bit control signal. The first control signal sets the data of the (i-12)-(i+11)-th bits to high level and the other bits to low level, and the second control signal is set to low level. When the first control signal is low level, the power supply terminal of the inverter is connected to the power supply terminal and the ground terminal is connected to the ground terminal. When the first control signal is high level, the inverter outputs a loop signal selected by the second control signal. When the second control signal is low level, half of the power supply voltage is used as the loop signal.
8. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 5, characterized in that, In steady-state mode, every bit of the first control signal output by the digital logic module is high, and the inverter outputs the loop signal selected by the second control signal; the second control signal output by the digital logic module is high, and the signal output by the output error amplifier module serves as the loop signal.
9. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 2, characterized in that, Each comparator in the offset comparator module includes a current source, a first to a sixth N-type MOSFET, and a first to a sixth P-type MOSFET, wherein: The source of all P-type MOSFETs is connected to the current inlet of the current source, and the current outlet of the current source is connected to the drain of the first N-type MOSFET. The gate of the first N-type MOS transistor is connected to the gate of the third N-type MOS transistor, and the source of the first N-type MOS transistor, the source of the second N-type MOS transistor, the source of the third N-type MOS transistor, and the source of the fourth N-type MOS transistor are all connected to the ground terminal; The gate and drain of the second N-type MOS transistor are connected together with the gate of the fourth second N-type MOS transistor and the drain of the first P-type MOS transistor. The drain of the third N-type MOSFET is connected to the source of the fifth N-type MOSFET and the source of the sixth N-type MOSFET. The drain of the fourth N-type MOSFET is connected together with the sixth P-type MOSFET MP6 and serves as the output of the comparator. The gate of the fifth N-type MOS transistor serves as the negative input terminal of the comparator, and the drain of the fifth N-type MOS transistor is connected together with the gate of the first P-type MOS transistor, the gate and drain of the second P-type MOS transistor, the gate of the third P-type MOS transistor, and the drain of the fourth P-type MOS transistor. The gate of the sixth N-type MOS transistor serves as the positive input terminal of the comparator. The drain of the sixth N-type MOS transistor is connected to the drain of the third P-type MOS transistor, the gate of the fourth P-type MOS transistor, the gate and drain of the fifth P-type MOS transistor MP5, and the gate of the sixth P-type MOS transistor MP6.
10. A distributed low-dropout linear regulator based on hybrid analog-digital circuitry according to claim 1, characterized in that, The circuit of the event-driven oscillator includes the seventh to thirteenth N-type MOSFETs, the seventh to twelfth P-type MOSFETs, the first to fourth inverters, and an AND gate, wherein: The gates of the seventh to thirteenth N-type MOS transistors and the drain of the seventh N-type MOS transistor are connected to the bias voltage terminal, and the sources of the seventh to thirteenth N-type MOS transistors are connected to the ground terminal; The drain of the eighth N-type MOSFET is connected to the drain of the seventh P-type MOSFET; The drain of the ninth N-type MOSFET is connected to the ground terminal of the first inverter; The drain of the tenth N-type MOSFET is connected to the ground terminal of the second inverter; The drain of the eleventh N-type MOSFET is connected to the ground terminal of the third inverter; The drain of the twelfth N-type MOSFET is connected to the ground terminal of the first inverter; The drain of the thirteenth N-type MOSFET is connected to the ground terminal of the AND gate; The gates of the seventh to twelfth P-type MOS transistors are connected together, and the sources of the seventh to twelfth P-type MOS transistors are connected to the internal power supply terminal of the oscillator. The drain of the eighth P-type MOSFET is connected to the power supply terminal of the first inverter. The drain of the ninth P-type MOSFET is connected to the power supply terminal of the second inverter. The drain of the tenth P-type MOSFET is connected to the power supply terminal of the third inverter. The drain of the eleventh P-type MOSFET is connected to the power supply terminal of the fourth inverter. The drain of the twelfth N-type MOSFET is connected to the power supply terminal of the AND gate. The output of the AND gate is connected to the input of the first inverter, and outputs the first low-dropout linear regulated signal. The output of the first inverter is connected to the input of the second inverter, and outputs a second low-dropout linear regulated signal. The output of the second inverter is connected to the input of the third inverter, and outputs the third low-dropout linear regulated signal. The output of the third inverter is connected to the input of the fourth inverter, and outputs the fourth low-dropout linear regulated signal. The output of the fourth inverter serves as one input to the AND gate, and the second control signal of the digital logic module serves as the other input to the AND gate.