Program flow control device, chip product, processor, equipment and method

Abstract

The invention discloses a program flow control device, a chip product, a processor, equipment and a method, and relates to the technical field of computers. A branch processing unit in the device is used for determining effective signals of a plurality of instruction branches in a first program, the first program is executed by a plurality of threads, and the effective signals of the instruction branches are used for indicating at least one thread used for executing the instruction branches in the threads; a press-in logic unit in the device is used for executing one-time stack pressing operation aiming at a stack under the condition that a first instruction branch is executed preferentially, generating a first entry in the stack and storing the first entry in the stack. The first item comprises a first type of information used for determining address information and effective signals of other instruction branches except the first instruction branch in the plurality of instruction branches, and a second type of information used for determining address information and state information of a convergent point instruction; the state information of the rendezvous point instruction is used for determining whether a condition for executing the rendezvous point instruction is met. The power consumption required by the branch structure in the processing program can be reduced.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a program flow control device, chip product, processor, apparatus, and method. Background Technology

[0002] In the field of computer technology, a program is an ordered set of computer instructions, a process is an execution of a program, and a process can be further subdivided into threads, each of which is an execution path of computer instructions in a program.

[0003] A processor can start multiple threads to execute the same program and process multiple tasks in parallel. When encountering a branching structure in the program, different threads may use different instruction branches to execute tasks depending on the task. Branching structures can be used to execute different instruction branches based on different conditional statements. For example, in a two-branch structure formed by an if-else statement, the code block corresponding to the if branch can be compiled into at least one computer instruction, forming one instruction branch in the program, and the code block corresponding to the else branch can be compiled into at least one computer instruction, forming the other instruction branch in the program.

[0004] In this scenario, the relevant technology first pushes the information related to the convergence instruction corresponding to the branch structure onto the stack from the top of the stack, forming the first entry. Then, it pushes the information related to the subsequent instruction branch onto the stack from the top of the stack, forming the second entry. The convergence instruction can refer to the computer instruction executed by the processor when multiple threads converge again. After the processor executes the first-processed instruction branch, the technology retrieves the information related to the subsequent instruction branch from the top of the stack in the second entry to instruct the processor to execute the subsequent instruction branch. Then, it pops the second entry from the top of the stack so that the first entry can be retrieved from the top of the stack. After the processor executes the subsequent instruction branch, the technology can again retrieve the information related to the convergence instruction from the top of the stack in the first entry to instruct the processor to execute the convergence instruction. This information includes information indicating the state of multiple threads, ensuring that all threads are executed correctly.

[0005] However, each time a branch structure is encountered, the relevant technology needs to perform two push operations and two pop operations on the stack, resulting in significant power consumption. Summary of the Invention

[0006] This application provides a program flow control device, a chip product, a processor, an apparatus, and a method. The technical solution is as follows:

[0007] According to one aspect of the embodiments of this application, a program flow control device is provided, the device comprising: a branch processing unit, a push logic unit, and a stack;

[0008] The branch processing unit is used to determine the valid signal of each of the multiple instruction branches in the first program, the first program being executed by multiple threads, and the valid signal of the instruction branch being used to indicate at least one thread among the multiple threads for executing the instruction branch, the instruction branch including at least one computer instruction;

[0009] The push logic unit is configured to perform a push operation on the stack when the first instruction branch among the plurality of instruction branches is executed first, generating a first entry in the stack. The first entry includes a first type of information and a second type of information. The first type of information is used to determine the address information and valid signals of the other instruction branches among the plurality of instruction branches besides the first instruction branch. The second type of information is used to determine the address information and status information of the convergence point instruction. The convergence point instruction is a computer instruction executed after the execution of the plurality of instruction branches. The status information of the convergence point instruction is used to determine whether the conditions for executing the convergence point instruction are met.

[0010] According to one aspect of the embodiments of this application, a chip product is provided, the chip product including the above-described program flow control device.

[0011] According to one aspect of the embodiments of this application, a processor is provided, the processor including the above-described program flow control device.

[0012] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor, the processor including the above-described program flow control device.

[0013] According to one aspect of the embodiments of this application, a program flow control method is provided, the method comprising:

[0014] The branch processing unit determines the valid signal of each of the multiple instruction branches in the first program, which is executed by multiple threads. The valid signal of the instruction branch is used to indicate at least one thread among the multiple threads that executes the instruction branch, and the instruction branch includes at least one computer instruction.

[0015] When the first instruction branch among the plurality of instruction branches is executed first, the push logic unit performs a push operation on the stack, generating a first entry in the stack. The first entry includes a first type of information and a second type of information. The first type of information is used to determine the address information and valid signals of the other instruction branches among the plurality of instruction branches besides the first instruction branch. The second type of information is used to determine the address information and status information of the convergence point instruction. The convergence point instruction is a computer instruction that is executed after the plurality of instruction branches have been executed. The status information of the convergence point instruction is used to determine whether the conditions for executing the convergence point instruction are met.

[0016] The technical solutions provided in this application embodiment may have the following beneficial effects:

[0017] When a first program is executed by multiple threads and encounters a branching structure within that program, if the first instruction branch among multiple instruction branches is executed first, a single push operation on the stack can generate a first entry on the stack. This entry can be used to determine the address information and valid signals of other instruction branches, as well as the address information and status information of the convergence instruction. Since the status information of the convergence instruction can be used to determine whether the conditions for executing the convergence instruction are met, the program flow control device can guide the processor to execute the convergence instruction after executing multiple instruction branches, based on the first entry. Furthermore, since the valid signals of an instruction branch can be used to instruct at least one thread among multiple threads to execute that instruction branch, the program flow control device can guide the processor to correctly execute multiple threads when executing a particular instruction branch, based on the first entry. This achieves the goal of guiding the correct execution of instruction branches, convergence instructions, and threads with a single push operation, eliminating the need for two push and two pop operations. This reduces the number of push and pop operations, thereby helping to reduce the power consumption required for branching structures in the program.

[0018] Furthermore, when allocating the same stack space for each entry, the technical solution provided in this application only requires the stack space corresponding to one entry for each branch structure. Compared with related technologies, which require the stack space corresponding to two entries for each branch structure, this helps to reduce the stack space requirement when processing branch structures in the program, thereby effectively reducing the storage resource occupation of the stack. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a branch structure provided in one embodiment of this application;

[0020] Figure 2 This is a schematic diagram illustrating the entry generation process in the branch structure processing provided by related technologies;

[0021] Figure 3 This is a schematic diagram of a program flow control device provided in one embodiment of this application;

[0022] Figure 4 This is a schematic diagram of a branch structure provided in another embodiment of this application;

[0023] Figure 5 This is a schematic diagram of entry generation in the branch structure processing process provided in one embodiment of this application;

[0024] Figure 6 This is a schematic diagram of entry generation in the branch structure processing process provided in another embodiment of this application;

[0025] Figure 7 This is a schematic diagram of entry deletion in the branch structure processing provided in one embodiment of this application;

[0026] Figure 8 This is a schematic diagram of branch nesting provided in one embodiment of this application;

[0027] Figure 9 This is a schematic diagram of entry generation in a branch nesting process provided in one embodiment of this application;

[0028] Figure 10 This is a flowchart of a program flow control method provided in one embodiment of this application;

[0029] Figure 11 This is a schematic diagram of the structure of a computer device provided in one embodiment of this application. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] In the field of computer technology, a program is an ordered collection of computer instructions. A program, also known as a computer program, is a set of computer instructions that can be recognized and executed by computer devices (such as processors). For example, a program is a set of computer instructions converted from source code written in a certain language to accomplish a specific task.

[0032] Program flow control refers to the process of controlling the execution path of a program through program logic. It determines the order and manner in which the processor executes computer instructions in the program. Optionally, program flow control involves processes such as instruction fetching, decoding, execution, and output of results to ensure that each computer instruction in the program is executed correctly in a predetermined order.

[0033] In the actual development process of a program, it is inevitable to use some branching structures, such as the branching structure formed by if statements and the branching structure formed by switch statements. Branching structures can be used to execute different instruction branches based on different judgment conditions. For example, in the two-branch structure formed by if-else statements, the code block corresponding to the if branch can be compiled into at least one computer instruction, forming one instruction branch in the program, and the code block corresponding to the else branch can be compiled into at least one computer instruction, forming another instruction branch in the program.

[0034] In the actual development of processors, branching is inevitably used. When a processor has multiple threads, for a given branch structure in the program, some threads need to execute one instruction branch, while others need to execute a different instruction branch. This results in different computer instructions being executed by different threads, causing the multiple threads to diverge. Executing an instruction branch can refer to sequentially executing at least one computer instruction within that branch.

[0035] To address the issue of multiple threads branching, one design approach is to employ a sequential execution strategy when encountering branching structures. This involves executing one instruction branch first, then jumping to execute another, and finally executing the reconvergence point instruction only after all instruction branches have been executed. During the processor's execution of various computer instructions, the states of multiple threads are controlled to ensure correct execution. For example, for an instruction being executed, the thread executing that instruction can be put into an active state, while threads not executing that instruction can be put into an inactive state. In the active state, the thread is executed; in the inactive state, the thread is not executed. The reconvergence point instruction refers to the computer instruction executed by the processor when multiple threads converge again; that is, the instruction to which the processor converges after all instruction branches corresponding to the branching structure have been executed. It is primarily used to handle the convergence and merging of multiple instruction branches, ensuring that all instruction branches are executed before continuing with subsequent computer instructions.

[0036] For example, refer to Figure 1For branch structure 100 in the program, there are corresponding vector branch instructions A, a first instruction branch formed by computer instruction B, a second instruction branch formed by computer instruction C, and a convergence point instruction D. The vector branch instruction is a special type of computer instruction used for control flow operations. It allows the program to execute different code paths based on the conditions of a vector. Vector branch instructions can perform conditional judgments on the entire vector, rather than individual data elements, thus enabling parallel processing and making it suitable for multi-tasking. For example, vector branch instructions include at least one of the following: vfcalss.v and vfsqrt.v. These instructions perform uniform operations or classifications based on the elements of the vector and perform branch structure processing based on the results. In a single-threaded environment, the vector branch instruction can be set up as a regular branch instruction. In a multi-threaded environment, if the jump directions of multiple threads are the same, the vector branch instruction can be executed as a regular branch instruction.

[0037] In this embodiment, vector branch instructions can be used to indicate the rules for determining the jump direction of a thread. For example, each element in the vector can correspond to a thread. Vector branch instructions can be used to perform conditional judgments on the tasks of each thread during an execution process to determine the jump direction of each thread, without having to perform a conditional judgment for each task separately. The jump direction is used to indicate the instruction branch executed by the thread.

[0038] When a processor starts multiple threads to handle multiple tasks for a program, some threads need to execute the first instruction branch, while others need to execute the second instruction branch. If the first instruction branch is executed first, and it is completed, the processor jumps to execute the second instruction branch. After the second instruction branch is completed, the convergence instruction D is executed to ensure all threads are executed correctly. For example, using SIMT (Single Instruction Multiple Thread) technology, the processor can improve computational efficiency by having multiple threads independently execute the same computer instructions but process different data. Normally, 32 threads in the same warp execute the same computer instructions in strict parallel. However, in the case of multi-threaded execution, 16 threads can execute the first instruction branch (i.e., the computer instruction), and the remaining 16 threads can execute the second instruction branch. This application does not limit this approach.

[0039] For multiple threads, a stack can be used to implement program flow control, enabling the serial execution of multiple instruction branches. A stack is an abstract data type in computer science; it's a linear list where insertion and deletion operations can only be performed at one end (called the top). The characteristic of a stack is Last-In-First-Out (LIFO). A stack can be understood as a data structure (a special storage area) used to temporarily store data and address information, ensuring the program can correctly return to its previous execution point. In this embodiment, the stack can be used to ensure the program can be correctly placed back into the convergence point instruction of the instruction branch, and to ensure that multiple threads can re-aggregate and execute the convergence point instruction. Exemplarily, the stack can be a separate stack space allocated for a thread bundle (including multiple threads) to temporarily store address information and related data when processing branch structures.

[0040] In related technologies, reference Figure 1 and Figure 2 When the processor prioritizes executing the second instruction branch (i.e., computer instruction C), the relevant technology first pushes the information related to the convergence instruction D (denoted as D_info) from the top of stack 200 onto stack 200, forming entry 1. Then, it pushes the information related to the first instruction branch (i.e., computer instruction B) from the top of stack 200 onto stack 200, forming entry 2. An entry is the basic unit of storage in the stack, typically including information related to the execution of a computer instruction. Each entry in the stack is allocated the same size of stack space, and the data in this stack space forms an entry. Due to the last-in, first-out (LIFO) characteristic of the stack, only the data in the entry at the top of the stack can be viewed at any time. For example, before entry 2 is popped from the stack, the data in entry 2 can only be viewed from the top of stack 200.

[0041] The aforementioned related information may include information indicating the status of multiple threads, as well as address information. For example, the related information for the convergence instruction D includes the valid signal of the convergence instruction and the address information of the convergence instruction D. The valid signal of the convergence instruction is used to indicate at least one thread among multiple threads that is executing the convergence instruction. Typically, the valid signal of the convergence instruction indicates that multiple threads are in a valid state. The address information of the convergence instruction D indicates the storage location of the convergence instruction D in memory. The related information for the first instruction branch includes the valid signal of the first instruction branch and the address information of the first instruction branch. The valid signal of the first instruction branch is used to indicate at least one thread among multiple threads that is executing the first instruction branch. The address information of the first instruction branch indicates the storage location of the first instruction branch in memory.

[0042] After the processor finishes executing the second instruction branch, the relevant technology retrieves the information related to the first instruction branch from the top of stack 200 (entry 2) to instruct the processor to jump to execute the first instruction branch. This includes instructing the processor to jump to execute the first instruction branch based on its address information, and instructing the processor to adjust the state of at least one thread executing the first instruction branch to a valid state and the state of at least one thread executing the second instruction branch to an invalid state based on the valid signal of the first instruction branch, thereby ensuring that multiple threads are executed correctly. Then, the relevant technology pops entry 2 from the top of stack 200 so that entry 1 can be retrieved from the top of stack 200.

[0043] After the processor completes execution of the first instruction branch, the relevant technology can retrieve information about the convergence instruction from the top of stack 200 (entry 1) to instruct the processor to execute the convergence instruction. For example, based on the valid signal of the convergence instruction, the processor can be instructed to adjust the state of multiple threads to a valid state, thereby enabling the multiple threads to be executed correctly. If no instruction jump is required after the processor completes the instruction branch, the processor continues to execute the convergence instructions sequentially. Finally, the relevant technology pops entry 1 from the top of stack 200.

[0044] The related technology requires two push and two pop operations on stack 200 for each branch structure encountered, resulting in significant power consumption. Additionally, it needs to generate two entries, consuming considerable stack space. The push operation (push) is used to push data onto the stack, and the pop operation (pop) is used to remove data from the stack. The view operation (view) is used to view the data in the stack from the top.

[0045] This application provides a program flow control device that can guide instruction branches, convergence instructions, and threads to be executed correctly based on the first entry generated by a single push operation on the stack, without having to perform two push operations and two pop operations on the stack. This reduces the number of push and pop operations, thereby helping to reduce the power consumption required for branch structures in the processing program.

[0046] In addition, the technical solution provided in this application only requires one stack space for each branch structure, compared with the related technology which requires two stack spaces for each branch structure. This helps to reduce the stack space requirement when processing branch structures in the program, thereby effectively reducing the storage resource occupation of the stack.

[0047] The following will provide a detailed description of the program flow control device provided in the embodiments of this application. For content not described in the embodiments of this application, please refer to the above embodiments, and it will not be repeated here.

[0048] Please refer to Figure 3 This illustration shows a schematic diagram of a program flow control device provided in one embodiment of this application. In this embodiment, the program flow control device 300 can be used to assist the processor in performing program flow control, particularly for program flow control in scenarios involving multiple thread splitting. For example, in a scenario involving multiple thread splitting, the program flow control device 300 can be used to guide the processor to execute multiple instruction branches serially, and to guide the processor to adjust the state of multiple threads; however, this embodiment does not limit the scope of the application.

[0049] The program flow control device 300 can be deployed on the processor or independently of the processor; this embodiment does not limit this. Exemplarily, the program flow control device 300 can be implemented as a chip product, which can be installed on the processor. The program flow control device 300 can be coupled to other devices in the processor to transmit signals. For example, the program flow control device 300 can be coupled to a control unit in the processor. The control unit can be used to determine the state of threads, to read computer instructions from the processor's memory, and to decode computer instructions. In scenarios involving multiple threads, the program flow control device 300 can guide the control unit to read computer instructions to jump to and execute instruction branches. The program flow control device 300 can also guide the control unit to adjust the state of multiple threads.

[0050] Optionally, the control unit may include an instruction register and a program counter. The various computer instructions in the program can be stored in the processor's memory in the order they appear in the program. The control unit can store computer instructions read from memory in the instruction register and then allocate them to the processor's arithmetic logic unit for execution. The value of the program counter can be used to indicate the address information of the computer instruction currently to be read from memory, and the program flow control device 300 can be used to guide the processor to adjust the value of the program counter to achieve jump execution of instruction branches.

[0051] In this embodiment, the processor can be implemented as a multi-threaded processor. A multi-threaded processor allows a single processor core to execute multiple threads simultaneously, meaning multiple threads can execute concurrently on the same processor core. This design enables the multi-threaded processor to process multiple tasks at the same time, thereby improving overall processing performance. This embodiment does not limit the type of processor, which may include at least one of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), General-Purpose Computing on Graphics Processing Units (GPGPU), Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Tensor Processing Unit (TPU), Field-Programmable Gate Array (FPGA), Tensor Core, or Neural Processing Unit (NPU).

[0052] In some embodiments, such as Figure 3 As shown, the program flow control device 300 may include: a branch processing unit 301, a push logic unit 302, and a stack 303.

[0053] In this embodiment, the branch processing unit 301 refers to a unit for processing vector branch instructions, such as hardware circuitry for processing vector branch instructions. The branch processing unit 301 can be used to implement at least one of the following functions:

[0054] 1. Branch processing unit 301, which can be used to obtain vector branch instructions in the first program.

[0055] The term "first program" generally refers to the program currently being executed by the processor. The first program includes multiple computer instructions. Optionally, if the processor starts multiple threads for the first program to concurrently process multiple tasks, the first program can be executed by these multiple threads. Vector branch instructions in the first program can be compiled based on branch instructions for these multiple threads. They can be used to determine the jump direction of multiple threads at the branch structure corresponding to the vector branch instructions. Branch instructions can refer to computer instructions compiled from conditional statements in the code. The first program may include at least one vector branch instruction.

[0056] For example, the branch processing unit 301 is coupled to the control unit in the processor. When the control unit reads a vector branch instruction in the first program, it sends the vector branch instruction to the branch processing unit 301. The branch processing unit 301 is used to receive the vector branch instruction from the control unit.

[0057] 2. Branch processing unit 301 can be used to determine the valid signal of each of the multiple instruction branches in the first program. The valid signal of the instruction branch is used to indicate at least one thread among the multiple threads used to execute the instruction branch.

[0058] The aforementioned multiple instruction branches can refer to all instruction branches included in the branch structure corresponding to the aforementioned vector branch instruction. Instruction branches can be compiled from the code blocks corresponding to the branches in the branch structure, and each instruction branch can include at least one computer instruction. This application does not limit the number of multiple instruction branches; for example, the number of multiple instruction branches can be 2 or more. For example, refer to... Figure 1 For vector branch instruction A, there are two corresponding instruction branches: the first instruction branch formed by the if branch and the second instruction branch formed by the else branch. When the control unit reads vector branch instruction A, it can send vector branch instruction A to the branch processing unit 301. After obtaining vector branch instruction A, the branch processing unit 301 executes vector branch instruction A to determine the valid signals of the first instruction branch and the second instruction branch.

[0059] A valid signal for an instruction branch can be used to determine at least one thread executing that instruction branch. For any computer instruction within the instruction branch, the valid signal can also be used to determine at least one thread executing that instruction. For example, the valid signal can be represented by a multi-bit value, with the bit width matching the number of threads. Each bit corresponds to one thread, used to indicate the thread's state. For instance, each bit corresponds to a binary number: 0 or 1, where 1 indicates the corresponding thread is in a valid state, and 0 indicates the corresponding thread is in an invalid state.

[0060] For example, refer to Figure 4When the processor starts four threads to execute the first program, for the branch structure 400 in the first program, which includes vector branch instruction A, computer instruction B, computer instruction C, and convergence instruction D, during the execution of vector branch instruction A and convergence instruction D, the four threads are in a converged state, that is, all four threads execute vector branch instruction A and convergence instruction D. Therefore, the valid signal of vector branch instruction A can be recorded as mask = 1111, and the valid signal of convergence instruction D can also be recorded as mask = 1111. The first bit from the left of the valid signal corresponds to the first thread, the second bit from the left corresponds to the second thread, the third bit from the left corresponds to the third thread, and the fourth bit from the left corresponds to the fourth thread. When the first and second threads execute computer instruction B, while the third and fourth threads execute computer instruction C, the valid signal of computer instruction B (i.e., the instruction branch formed by the if branch) can be recorded as mask = 1100, and the valid signal of computer instruction C (i.e., the instruction branch formed by the else branch) can be recorded as mask = 0011.

[0061] In a feasible example, the aforementioned multiple instruction branches can also refer to the instruction branches that need to be executed within a certain branch structure, that is, it includes multiple instruction branches involved in the overall multiple threads. For example, when the number of multiple instruction branches is two, all instruction branches need to be executed. When the number of multiple instruction branches is two or more, at least two instruction branches need to be executed. For instance, if the branch structure includes instruction branch 1, instruction branch 2, and instruction branch 3, and if a portion of the multiple threads executes instruction branch 1 while the remaining portion needs to execute instruction branch 2, then the branch processing unit 301 only needs to determine the valid signals for instruction branch 1 and instruction branch 2, but does not need to determine the valid signal for instruction branch 3. Furthermore, the processor does not need to execute instruction branch 3.

[0062] In one example, the branch processing unit 301 may have logical operation functions for executing computer instructions. The process by which the branch processing unit 301 obtains valid signals for each of the multiple instruction branches may include the following:

[0063] (1) Branch processing unit 301 is used to execute vector branch instructions and determine the jump direction of each of the multiple threads when multiple instruction branches are obtained.

[0064] The jump direction is used to indicate the instruction branch that the thread is executing. For example, see [reference]. Figure 4The jump direction of the first thread can be used to indicate that the first thread needs to execute computer instruction B (i.e., the instruction branch formed by the if branch), and the jump direction of the third thread can be used to indicate that the third thread needs to execute computer instruction C (i.e., the instruction branch formed by the else branch).

[0065] Vector branch instructions are used to determine the jump direction of threads. Vector branch instructions can change the original sequential execution mode of the program counter through conditional judgments and jumps, thereby adjusting the program's execution path. The conditions corresponding to the conditional judgments are the rules for determining the jump direction of threads. For example, during the execution of vector branch instructions, the branch processing unit 301 can complete the conditional judgments for the tasks of each thread, thereby determining the jump direction of each thread. For example, see reference... Figure 4 When the judgment rule is greater than the set value, the branch processing unit 301 can compare the data processed by each thread with the set value in turn. If the data processed by the first thread is greater than the set value, the jump direction of the first thread can be determined to be the instruction branch formed by the if branch. If the data processed by the third thread is less than or equal to the set value, the jump direction of the third thread can be determined to be the instruction branch formed by the else branch.

[0066] (2) Branch processing unit 301 is used to determine the valid signal of each instruction branch according to the jump direction of each thread when the jump direction of each thread is different.

[0067] When multiple threads have different jump directions, it can be determined that at least two instruction branches need to be executed, that is, multiple threads diverge. For example, for any instruction branch among multiple instruction branches, based on the jump directions of the multiple threads, at least one thread is determined to execute that instruction branch. The bit values ​​corresponding to the at least one thread are set to 1, and the bit values ​​of the remaining threads among the multiple threads are set to 0, thus obtaining the valid signal of that instruction branch.

[0068] For example, referring to 4, if the first and second threads execute the instruction branch formed by the if branch, while the third and fourth threads execute the instruction branch formed by the else branch, then the valid signal of the instruction branch formed by the if branch can be recorded as mask = 1100, and the valid signal of the instruction branch formed by the else branch can be recorded as mask = 0011.

[0069] Optionally, if multiple threads have the same jump direction, it can be determined that only one instruction branch needs to be executed. In this case, the vector branch instruction can be executed as a regular branch instruction, meaning that only one redirection is needed for the front-end value fetch unit based on the jump direction and jump address, instead of multiple redirections. For example, the branch processing unit 301 can be used to guide the processor to execute the vector branch instruction as a regular branch instruction to jump to the target instruction branch when multiple threads have the same jump direction. The branch processing unit 301 can also be used to prevent the processor from jumping to execute other instruction branches after the target instruction branch has been executed. This target instruction branch is the instruction branch that multiple threads need to execute.

[0070] This application embodiment determines the valid signal for each of the multiple instruction branches only when the jump directions of the multiple threads are different, without having to perform a valid signal determination process for each vector branch instruction. This effectively reduces the power consumption required to process the branch structure and ensures that multiple threads can be executed correctly when multiple threads are differentiated.

[0071] 3. Branch processing unit 301 can be used to update the valid signal of the first instruction branch to the first storage unit 304, and the first storage unit 304 is used to store the valid signal of the currently executed instruction branch.

[0072] The first instruction branch can refer to the instruction branch that is executed first among multiple instruction branches, or it can refer to the first instruction branch among multiple instruction branches. This application does not limit this specific meaning. For example, refer to... Figure 4 You can determine the instruction branch formed by the if branch as the first instruction branch, or the instruction branch formed by the else branch as the first instruction branch, or the instruction branch that the first thread needs to execute as the first instruction branch.

[0073] The currently executing instruction branch can refer to the instruction branch that the processor is executing at the current moment. Optionally, the value in the first memory unit 304 can be used to generate a state adjustment signal, which indicates the state of each thread at the current moment, and the processor can adjust the state of each thread based on the state adjustment signal. For example, refer to... Figure 3When the processor prioritizes executing the first instruction branch, the branch processing unit 301 can update the valid signal of the first instruction branch to the first storage unit 304. The processor's control unit can read the valid signal of the first instruction branch from the first storage unit 304 as a state adjustment signal, and based on the valid signal of the first instruction branch, adjust the state of at least one thread executing the first instruction branch to a valid state, and adjust the state of at least one thread not executing the first instruction branch to an invalid state, so that multiple threads are executed correctly.

[0074] Optionally, the program flow control device 300 may further include a signal transmission unit ( Figure 3 (Not shown in the diagram), the signal transmitting unit is used to output the value in the first storage unit 304 as a state adjustment signal to be sent to the control unit of the processor. Optionally, the first storage unit 304 can be implemented as a register, denoted as the cur_mask register, and the state adjustment signal can be denoted as the mask_out signal.

[0075] 4. Branch processing unit 301 can be used to send valid signals of other instruction branches to push logic unit 302.

[0076] Other instruction branches can refer to instruction branches other than the first instruction branch among multiple instruction branches. The branch processing unit 301 and the push logic unit 302 are coupled to support data transmission.

[0077] In this embodiment, the push logic unit 302 can refer to a unit used to perform a push operation on the stack 303, that is, the push logic unit 302 can be used to push data onto the stack 303. Optionally, the push logic unit 302 can be implemented as a hardware circuit that performs a push operation on the stack 303. The push logic unit 302 can be used to implement at least one of the following functions:

[0078] 1. Push logic unit 302 can be used to receive data from branch processing unit 301.

[0079] For example, the push logic unit 302 can be used to receive valid signals of other instruction branches sent by the branch processing unit 301. The push logic unit 302 can also be used to receive address information sent by the branch processing unit 301, such as address information of other instruction branches, address information of convergence point instructions, etc. This application embodiment does not limit this.

[0080] 2. The push logic unit 302 can be used to perform a push operation on the stack 303 when the first instruction branch in multiple instruction branches is executed first, and generate the first entry in the stack 303.

[0081] Stack 303 can be a separate stack space allocated for a thread bundle (including multiple threads) to temporarily store address information and related data when processing branching structures. For example, see reference... Figure 3 Stack 303 can be implemented as a computationally restricted linear list. Each entry in stack 303 is assigned at least four consecutive domain segments, and the multiple domain segments corresponding to stack 303 can be distributed in a linear list pattern. Push logic unit 302 is coupled to stack 303.

[0082] The first entry mentioned above is generated through a single stack push operation. That is, only one stack push operation is performed on stack 303 to push the data required to generate the first entry from the top of stack 303 onto stack 303, thereby generating the first entry in stack 303. In this embodiment, the data stored in the first entry can be used to instruct the processor to execute multiple instruction branches serially. The data stored in the first entry can also be used to instruct the processor to adjust the state of multiple threads during the execution of the various computer instructions included in the branch structure. This embodiment does not limit the first entry.

[0083] Optionally, the first entry may include a first type of information and a second type of information. The first type of information is used to determine the address information and valid signals of the other instruction branches besides the first instruction branch among the multiple instruction branches. The second type of information is used to determine the address information and status information of the convergence point instruction, which is a computer instruction executed after the execution of the multiple instruction branches is completed.

[0084] The address information of an instruction branch can be used to indicate the storage location of the instruction branch in the processor memory. The address information of a computer instruction can be used to indicate the storage location of the computer instruction in the processor memory; for example, the address information can be implemented as a memory address. The valid signal for other instruction branches can be used to indicate at least one thread among multiple threads that is executing that other instruction branch. The address information of a convergence point instruction is used to indicate the storage location of the convergence point instruction in the processor memory.

[0085] The status information of the convergence point instruction is used to determine whether the conditions for executing the convergence point instruction are met; that is, the status information of the convergence point instruction can be used to determine whether it is necessary to jump to execute other instruction branches. For example, the status information can be represented by at least one numerical value. For instance, when the number of multiple branch instructions is two, one numerical value can be used to represent the status information; when the number of multiple branch instructions is three, two numerical values ​​can be used to represent the status information. This application does not limit this approach.

[0086] For example, taking a scenario with two branch instructions, if the convergence instruction's status is 1, it indicates that besides the currently executing instruction branch, there is another instruction branch that needs to be executed, and the convergence instruction has not yet been hit. If the currently executing instruction branch is completed and the convergence instruction is hit, the processor jumps to execute the other instruction branch without executing the convergence instruction. If the convergence instruction's status is 0, it indicates that besides the currently executing instruction branch, there are no other instruction branches that need to be executed, and the convergence instruction has been hit once. If the currently executing instruction branch is completed and the convergence instruction is hit, the processor does not need to jump to execute other instruction branches and can execute the convergence instruction. Hitting the convergence instruction can mean that the processor's program counter value changes to the address information of the convergence instruction, and the processor will then read the convergence instruction from memory based on the program counter value. Thus, based on the convergence instruction's status information, it is possible to determine whether to guide the processor to jump to execute an instruction branch, and therefore whether to guide the processor to execute the convergence instruction. This is beneficial for guiding the processor to correctly handle the branch structure in a program with multiple threads.

[0087] 3. The push logic unit 302 can be used to determine the status information of the convergence point instruction based on the number of valid signals of other instruction branches.

[0088] The number of valid signals for other instruction branches can be used to indicate the number of other instruction branches. The number of other instruction branches can be used to indicate how many address jump operations the processor needs to execute. The push logic unit 302 can directly determine the number of valid signals for other instruction branches as the initial value of the state information of the convergence point instruction. An address jump operation is the process of switching from one address information to another.

[0089] For example, when the number of valid signals for other instruction branches is 1, the initial value of the state information for the convergence instruction can be set to 1 to indicate that the processor needs to perform one address jump operation before executing the convergence instruction; when the number of valid signals for other instruction branches is 2, the initial value of the state information for the convergence instruction can be set to 10 (composed of binary 1s and 0s) to indicate that the processor needs to perform two address jump operations before executing the convergence instruction. Based on the number of valid signals for other instruction branches, accurate state information can be obtained. Based on accurate state information, the processor can be accurately guided to execute the convergence instruction after executing multiple instruction branches, thereby improving the correctness of branch structure processing in the case of multiple thread differentiation.

[0090] Optionally, the program flow control device 300 may, based on the address information of other instruction branches determined by the first type of information, guide the processor to jump to execute other instruction branches after executing the first instruction branch to achieve serial execution of multiple instruction branches, and may, based on the valid signal of other instruction branches determined by the first type of information, guide the processor to adjust the state of multiple threads to correspond to the currently executed computer instruction so that multiple threads are executed correctly.

[0091] The program flow control device 300 can determine whether a certain instruction branch has been executed based on the address information of the convergence instruction determined by the second type of information, and can guide the processor to adjust the state of multiple threads to correspond to the convergence instruction based on the valid signal of the convergence instruction determined by the second type of information, so that the multiple threads are executed correctly.

[0092] For example, the first type of information may include: the address information of the starting instruction in other instruction branches and the valid signals of other instruction branches; the second type of information may include: the address information of the convergence point instruction and the status information of the convergence point instruction. That is, the push logic unit 302 can be used to perform a push operation on the stack 303, pushing the address information of the starting instruction in other instruction branches, the valid signals of other instruction branches, the address information of the convergence point instruction, and the status information of the convergence point instruction from the top of the stack 303 onto the stack 303, generating the first entry in the stack 303.

[0093] The aforementioned address information can be obtained by the branch processing unit 301 and provided by the branch processing unit 301 to the push logic unit 302. The starting instruction in an instruction branch can be the first computer instruction in the instruction branch. After an instruction branch is executed, if the processor needs to jump to execute other instruction branches, the processor needs to start execution from the starting instruction of the other instruction branch. After the value of the processor's program counter is adjusted to the address information of the starting instruction of other instruction branches, the program counter can automatically update the address information of each computer instruction in other instruction branches in sequence, so that each computer instruction in other instruction branches can be read sequentially by the control unit.

[0094] Optionally, if each piece of information pushed by the push logic unit 302 is assigned a field segment, then the push logic unit 302 is also used to push the address information of the convergence point instruction from the top of the stack 303 into the first field segment of the first entry, push the status information of the convergence point instruction from the top of the stack 303 into the second field segment of the first entry, push the address information of the start instruction in other instruction branches from the top of the stack 303 into the third field segment of the first entry, and push the valid signals of other instruction branches from the top of the stack 303 into the fourth field segment of the first entry. The first, second, third, and fourth field segments are four consecutive field segments, allowing the data in the four field segments corresponding to the first entry to form the first entry. Optionally, the third and fourth field segments can appear in pairs, that is, for each other instruction branch, there is one third and one fourth field segment respectively, used to store address information and valid signals respectively. The number of pairs of third and fourth field segments is the same as the number of pairs of other instruction branches.

[0095] For example, refer to Figures 3 to 5 When computer instruction B is executed first, push logic unit 302 can determine the status information of convergence instruction D as status=1 based on the number of valid signals of other instruction branches (i.e., the instruction branch formed by computer instruction C).

[0096] At time T0, the processor is executing the vector convergence instruction A, and all four threads are executing the vector convergence instruction A. At this time, stack 303 is empty, that is, there are no entries in stack 303. The value cur_mask in the first storage unit 304 is 1111, indicating that the processor should adjust the state of all four threads to the valid state.

[0097] At time T1, the processor is executing computer instruction B, which is executed by the first thread and the second thread. At this time, push logic unit 302 performs a push operation on stack 303 to push the address information of the convergence point instruction D into the first field corresponding to the first entry 3031, push the status information (i.e., 1) of the convergence point instruction D into the second field corresponding to the first entry 3031, push the address information of computer instruction C into the third field corresponding to the first entry 3031, and push the validity signal (i.e., 0011) of computer instruction C into the fourth field corresponding to the first entry 3031, thereby generating the first entry 3031 in stack 303. At this time, the first entry 3031 can only be viewed from the top of stack 303.

[0098] The domain name of the first field is RPC (Reconverge Program Counter), which is a program pointer for a convergence instruction. A program pointer is a pointer to a program and can be used to store address information, such as the address information of a convergence instruction. Optionally, the address information in this embodiment can be pushed onto stack 303 in the form of a program pointer, such as the address information of a convergence instruction. The domain name of the second field is Status, i.e., status information. The domain name of the third field is SPC (Start Program Counter), which is a program pointer for the start instruction in an instruction branch. The domain name of the fourth field is Mask, i.e., valid signal.

[0099] By allocating at least four consecutive field segments to each entry, the embodiments of this application enable the information required to process a branch structure to be pushed onto the stack as an entry. In other words, the technical solution provided by this application only requires the stack space corresponding to one entry for each branch structure, which helps to reduce the stack space requirement when processing branch structures in the program, thereby effectively reducing the storage resource occupation of the stack.

[0100] In one example, the program flow control device 300 further includes a stack control unit 305 and a second storage unit 306. The stack control unit 305 is used to adjust the value in the second storage unit 306, which indicates the entry at the top of the stack 303. Exemplarily, the stack control unit 305 can be implemented as hardware circuitry for adjusting the value in the second storage unit 306, which can be implemented as a register, denoted as the Top register. The value in the second storage unit 306 is the stack pointer of the stack 303, which always points to the top of the stack. Before data is pushed onto the stack, the stack pointer needs to be modified to point to new free stack space to facilitate data pushing.

[0101] 4. The push logic unit 302 can also be used to control the stack control unit 305 to update the value in the second storage unit 306 when the first entry is generated.

[0102] For example, before each entry is generated, the push logic unit 302 may send a push enable signal to the stack control unit 305. Upon receiving the push enable signal, the stack control unit 305 increases the value in the second storage unit 306 to point to the top of the stack 303, and the push logic unit 302 then pushes data from the top of the stack 303.

[0103] For example, refer to Figure 5At time T0, there are no entries in stack 303, and the value in the second storage unit 306 is -1. At time T1, a first entry 3031 is generated in stack 303, and the value in the second storage unit 306 is updated to 0 by the stack control unit 305 to point to the first entry 3031 located at the top of stack 303.

[0104] Based on the value in the second storage unit 306, the program flow control device 300 can always lock the entry at the top of the stack 303, so that the currently processed branch structure will not be affected by other branch structures, which is beneficial to improving the processing correctness of the branch structure.

[0105] In summary, the technical solution provided by this application, when a first program is executed by multiple threads and encounters a branch structure within the first program, if the first instruction branch among multiple instruction branches is executed first, a first entry can be generated on the stack through a single push operation. This entry can be used to determine the address information and valid signals of other instruction branches, as well as the address information and status information of the convergence instruction. Since the status information of the convergence instruction can be used to determine whether the conditions for executing the convergence instruction are met, the program flow control device can guide the processor to execute the convergence instruction after executing multiple instruction branches based on the first entry. Furthermore, since the valid signals of the instruction branches can be used to indicate at least one thread among multiple threads used to execute that instruction branch, the program flow control device can guide the processor to correctly execute multiple threads when executing a certain instruction branch based on the first entry. This achieves the goal of guiding the instruction branch, convergence instruction, and thread to be executed correctly through a single push operation, without requiring two push operations and two pop operations. This reduces the number of push and pop operations, thereby helping to reduce the power consumption required by the branch structure in the processing program.

[0106] Furthermore, when allocating the same stack space for each entry, the technical solution provided in this application only requires the stack space corresponding to one entry for each branch structure. Compared with related technologies, which require the stack space corresponding to two entries for each branch structure, this helps to reduce the stack space requirement when processing branch structures in the program, thereby effectively reducing the storage resource occupation of the stack.

[0107] The generation of the first entry has been explained above; the use of the first entry will be explained below. Content not described in the embodiments of this application can be referred to the above embodiments, and will not be repeated here.

[0108] In some embodiments, reference Figure 3 The program flow control device 300 may further include: a read logic unit ( Figure 3(Not shown in the diagram), first arithmetic unit 307 and second arithmetic unit 308. The read logic unit, first arithmetic unit 307 and second arithmetic unit 308 can be used to cooperate to implement the function of "whether to guide the processor to perform an address jump operation".

[0109] The read logic unit refers to a unit used to examine stack 303, which can be used to read data from the stack. For example, the read logic unit can be used to read data from the top of stack 303 based on the value in the second storage unit 306. For example, refer to... Figure 5 The read logic unit can be used to read data stored in the first entry 3031 from the top of the stack 303 based on the value (i.e., 0) in the second storage unit 306.

[0110] The first arithmetic unit 307 is used to determine whether the currently executed computer instruction is a convergence point instruction, that is, whether the currently executed instruction branch has been completed. The second arithmetic unit 308 is used to determine whether it is necessary to jump to execute a computer instruction and whether it is necessary to jump to execute other instruction branches.

[0111] In one example, the implementation of the function "whether to guide the processor to perform an address jump operation" can be as follows:

[0112] 1. A read logic unit is used to read the address information and status information of the convergence point instruction from the first entry; send the address information of the convergence point instruction to the first arithmetic unit 307, and send the status information of the convergence point instruction to the second arithmetic unit 308.

[0113] The read logic unit can be used to read the address information of the convergence point instruction in the top stack entry into the first arithmetic unit 307, and to read the status information of the convergence point in the top stack entry into the second arithmetic unit 308. Here, the top stack entry refers to the entry located at the top of the stack 303; when the first instruction branch is executed, the top stack entry is recorded as the first entry.

[0114] 2. The first arithmetic unit 307 is used to obtain the first address information, which refers to the address information of the currently executed computer instruction; based on the first address information and the address information of the convergence point instruction, an intermediate signal is generated, which is used to indicate whether the first instruction branch has been completed; and the intermediate signal is sent to the second arithmetic unit 308.

[0115] Optionally, when the processor's control unit needs to read a computer instruction, it first sends the address information of the computer instruction to the first arithmetic unit 307 so that the program flow control device 300 can determine whether an address jump operation needs to be performed.

[0116] Optionally, the first arithmetic unit 307 is configured to output an intermediate signal of a first value when the first address information and the address information of the convergence instruction are the same; and to output an intermediate signal of a second value when the first address information and the address information of the convergence instruction are different. Wherein, when the intermediate signal is the first value, it indicates that the first instruction branch has been completed; and when the intermediate signal is the second value, it indicates that the first instruction branch has not been completed. The first and second values ​​can be set and adjusted according to actual usage requirements. For example, the first value is 1 to indicate that the first instruction branch has been completed, and the processor will acquire and execute the convergence instruction; the second value is 0 to indicate that the first instruction branch has not been completed, and the processor will continue to execute the remaining computer instructions in the first instruction branch.

[0117] For example, refer to Figure 3 The first arithmetic unit 307 is implemented as an arithmetic unit for executing the "=" operation logic, which is used to compare whether two inputs are equal. The first arithmetic unit 307 is used to obtain the first address information cur_pc from the control unit and the address information RPC of the convergence point instruction from the read logic unit; when the first address information cur_pc is equal to the address information RPC of the convergence point instruction, the intermediate signal is output as 1 (i.e., true); when the first address information cur_pc is not equal to the address information RPC of the convergence point instruction, the intermediate signal is output as 0 (i.e., false).

[0118] This application embodiment achieves automatic determination of whether the currently executing instruction branch has been completed by automatically matching the address information of the convergence point in the first entry with the address information of the currently executed computer instruction.

[0119] 3. The second arithmetic unit 308 is used to generate a jump enable signal based on the status information of the intermediate signal and the convergence point instruction. The jump enable signal is used to indicate whether to jump to execute the computer instruction in the first program.

[0120] Optionally, the second arithmetic unit 308 is also used to send a jump enable signal to the processor's control unit, which determines whether to perform an address jump operation based on the jump enable signal.

[0121] For example, if there are other instruction branches that have not been executed and the currently executed instruction branch has been completed, the jump enable signal is output as a first operation value; if there are no other instruction branches that have not been executed and the currently executed instruction branch has been completed, the jump enable signal is output as a second operation value. Wherein, when the jump enable signal is the first operation value, the jump enable signal is used to indicate jumping to execute the computer instructions in the first program, that is, jumping to execute other instruction branches; when the jump enable signal is the second operation value, the jump enable signal is used to indicate not jumping to execute the computer instructions in the first program, that is, not jumping to execute other instruction branches, so as to continue executing the convergence point instruction. For example, the first operation value is 1 to indicate that the processor jumps to execute other instruction branches, and the second operation value is 0 to indicate that the processor does not jump to execute other instruction branches.

[0122] For example, refer to Figure 3 The second arithmetic unit 308 can implement an arithmetic unit for executing "and" operation logic, which is used to determine whether two or more conditions are simultaneously satisfied. The second arithmetic unit 308 is used to acquire intermediate signals from the first arithmetic unit 307 and the status information (Status) of the convergence point instruction from the read logic unit. When the intermediate signal is 1 and the status information (Status) of the convergence point instruction is not 0 (i.e., there is an unexecuted instruction branch), the jump enable signal jump_en_out is output as 1 (i.e., true). When the intermediate signal is 1 (i.e., the currently executed instruction branch has been completed) and the status information (Status) of the convergence point instruction is 0 (i.e., there is no unexecuted instruction branch), the jump enable signal jump_en_out is output as 0 (i.e., false). When the intermediate signal is 0 (i.e., the currently executed instruction branch has not been completed), the jump enable signal jump_en_out is output as 0 (i.e., false).

[0123] For example, refer to Figures 3 to 6At time T2, computer instruction B is executed. The first address information cur_pc is the address information of the convergence instruction D. Based on the first address information cur_pc and the address information of the convergence instruction D, the first arithmetic unit 307 can output an intermediate signal of 1. The second arithmetic unit 308, based on the intermediate signal (i.e., 1) and the status information of the convergence instruction D (i.e., 1), outputs a jump enable signal jump_en_out of 1. When jump_en_out = 1, jump_en_out is used to instruct the processor's control unit to perform an address jump operation. Since the branch structure 400 only includes two instruction branches, the program flow control device 300 can be used to guide the processor to jump and execute computer instruction C, that is, to guide the control unit to adjust the value of the program counter to the address information of computer instruction C.

[0124] In this embodiment of the application, the first arithmetic unit 307 and the second arithmetic unit 308 automatically determine whether to jump to execute other instruction branches based on the address information of the convergence point, the status information of the convergence point, and the address information of the currently executed computer instruction in the first entry.

[0125] In one example, when the processor needs to jump to execute other instruction branches, the logic read unit is also used to read the address information of the other instruction branches to be executed to the processor's control unit, so that the control unit can jump to read the other instruction branches based on the address information of the other instruction branches, thereby realizing the jump execution of the other instruction branches.

[0126] For example, the process by which the program flow control device 300 provides the processor with address information of other instruction branches to be executed may include the following:

[0127] 1. Read logic unit, used to read the address information of the starting instruction in the second instruction branch and the valid signal of the second instruction branch from the first entry when the jump enable signal is the first operation value.

[0128] The second instruction branch is another instruction branch among multiple instruction branches besides the first instruction branch. The second instruction branch can be used to refer to any other instruction branch to be executed by jump. When the jump enable signal is the first operation value, the jump enable signal is used to indicate that the computer instruction in the first program should be executed by jump.

[0129] Optionally, the second arithmetic unit 308 can be used to send a jump enable signal to a read logic unit. The read logic unit is used to read the address information of the starting instruction in the second instruction branch and the valid signal of the second instruction branch from the first entry when the jump enable signal is detected as the first arithmetic value; and not to perform a viewing operation on the stack 303 when the jump enable signal is detected as the second arithmetic value.

[0130] In one feasible example, the second arithmetic unit 308 only sends the jump enable signal to the processor's control unit. The processor's control unit is used to control the read logic unit to read the address information of the start instruction in the second instruction branch and the valid signal of the second instruction branch from the first entry when the jump enable signal is detected as the first arithmetic value. When the jump enable signal is detected as the second arithmetic value, the logic read unit is not controlled to perform a viewing operation on the stack 303. This application embodiment does not limit this.

[0131] For example, refer to Figures 3 to 6 At time T2, the read logic unit is also used to read the address information of computer instruction C and the valid signal of computer instruction C (i.e., mask = 0011) from the first entry 3031 when jump_en_out = 1. Since the else branch forms an instruction branch that only includes computer instruction C, the address information of the starting instruction in the instruction branch is the address information of computer instruction C, and the valid signal of the instruction branch is the valid signal of computer instruction C.

[0132] 2. Read logic unit, used to update the valid signal of the second instruction branch to the first memory unit 304.

[0133] When the processor needs to jump to execute the second execution branch after executing the first instruction branch, the processor needs to adjust the states of multiple threads to correspond to the second instruction branch. For example, after the valid signal of the second instruction branch is updated in the first memory unit 304, the processor's control unit can adjust the state of at least one thread executing the second instruction branch to a valid state, and adjust the state of the remaining threads that are not executing the second instruction branch to an invalid state, based on the value in the first memory unit 304.

[0134] For example, refer to Figures 3 to 6 At time T2, the read logic unit is also used to update the valid signal (i.e., mask = 0011) of computer instruction C to the first storage unit 304, so that the processor control unit adjusts the state of the first thread and the second thread to the invalid state, and adjusts the state of the third thread and the fourth thread to the valid state.

[0135] 3. The read logic unit is used to output the address information of the starting instruction in the second instruction branch as a jump address signal. The jump address signal is used to indicate the jump to execute the second instruction branch.

[0136] Optionally, after acquiring the jump address signal, the processor's control unit can update the program counter value to the address information of the starting instruction in the second instruction branch indicated by the jump address signal. Then, based on the address information of the starting instruction in the second instruction branch, it can read the starting instruction of the second instruction branch from the processor memory and finally allocate it to the logic unit for execution. The program counter can automatically adjust its value based on the address information of the starting instruction in the second instruction branch, so that the control unit sequentially acquires each computer instruction in the second instruction branch, thereby realizing the jump execution of the second instruction branch.

[0137] For example, refer to Figures 3 to 6 At time T2, the read logic unit is also used to output the address information of computer instruction C as a jump address signal jump_pc_out, so that the processor control unit can read computer instruction C from the processor memory based on jump_pc_out to realize the jump execution of computer instruction C.

[0138] The embodiments of this application can accurately provide the processor with the address information of the instruction branch to be executed based on the address information of the starting instruction in other instruction branches in the first entry, and based on the valid signals of other instruction branches in the first entry, can accurately guide the processor to adjust the state of multiple threads, thereby effectively improving the processing accuracy of the branch structure.

[0139] In one example, the push logic unit 302 is also used to update the status information of the convergence point instruction in the first entry after each instruction branch has been executed. Exemplarily, after each instruction branch has been executed, the push logic unit 302 is used to decrement the value of the status information of the convergence point instruction by 1 to indicate how many instruction branches remain to be executed.

[0140] In this embodiment, when the status information of the convergence point instruction is a third value, the status information of the convergence point instruction is used to indicate that there are no unexecuted instruction branches among the multiple instruction branches. The third value can be set and adjusted based on actual usage requirements, and this application embodiment does not limit this. For example, when the third value is 0, the status information of the convergence point instruction is used to indicate that there are no unexecuted instruction branches among the multiple instruction branches.

[0141] Optionally, the push logic unit 302 may also update the status information of the convergence point instruction in the first entry based on the number of other instruction branches that have not been executed. For example, when the number of the aforementioned multiple instruction branches is 2, the initial value of the status information of the convergence point instruction is 1. When the execution of the first instruction branch is completed and the execution of the second instruction branch is initiated, there are no instruction branches that have not been executed, so the push logic unit 302 may update the status information of the convergence point instruction to 0.

[0142] In a feasible example, the push logic unit 302 decrements the status information of the convergence point instruction by 1 each time it detects that the intermediate signal output by the first arithmetic unit 307 becomes 1.

[0143] For example, refer to Figure 6 At time T2, after the processor finishes executing computer instruction B, it jumps to execute computer instruction C. The push logic unit 302 is used to update the status information of the convergence point instruction in the first entry 3031 from 1 to 0, so as to indicate that there is no instruction branch that has not been executed in the branch structure 400.

[0144] When the status information of the convergence point instruction changes to 0, even if the processor executes the convergence point instruction again, the jump enable signal output by the second arithmetic unit 308 will also be 0. That is, the jump enable signal will not trigger the processor to perform an address jump operation, and thus continue to automatically execute the convergence point instruction.

[0145] This application embodiment dynamically updates the status information of the convergence point instruction based on the completion status of the instruction branches, enabling the program flow control device 300 to grasp the completion status of the instruction branches. This allows it to automatically guide the processor to jump to execute instruction branches and automatically guide the processor to execute the convergence point instruction after executing multiple instruction branches.

[0146] The execution of the convergence point instruction will be described below. For content not described in the embodiments of this application, please refer to the above embodiments, and it will not be repeated here.

[0147] 1. Read logic unit, used to read the valid signal of the convergence point instruction from the first entry when the third instruction branch in multiple instruction branches has been executed and the status information of the convergence point instruction is the third value.

[0148] The third instruction branch can refer to the last instruction branch executed among multiple instruction branches. When the status information of the convergence instruction is the third value, there are no remaining instruction branches among the multiple instruction branches, except for the currently executing third instruction branch. After the third instruction branch has been executed, all instruction branches have been completed. At this point, the processor should continue executing the convergence instruction without performing an address jump operation.

[0149] A valid signal for a convergence point instruction is used to activate multiple threads. All threads need to execute the convergence point instruction, therefore, when the convergence point instruction is executed, the states of all threads should be adjusted to the active state.

[0150] Optionally, the first entry is removed from the top of stack 303 after the read logic unit reads the valid signal of the convergence instruction. Exemplarily, the program flow control device 300 also includes a pop logic unit for performing a pop operation on stack 303. After the valid signal of the convergence instruction is read, the pop logic unit can perform a pop operation on stack 303 to pop the first entry from the top of stack 303, that is, to remove the first entry located at the top of the stack.

[0151] 2. The read logic unit is also used to update the valid signal of the convergence point instruction to the first storage unit 304.

[0152] Optionally, after the valid signal of the convergence point instruction is updated to the first storage unit 304, the processor's control unit can adjust the state of each of the multiple threads to the valid state based on the value of the first storage unit 304, thereby enabling multiple threads to converge and execute the convergence point instruction.

[0153] For example, refer to Figure 7 At time T3, both computer instructions B and C have been executed. The processor will continue to execute the convergence instruction D. The read logic unit can be used to read the valid signal (i.e., 1111) of the convergence instruction D from the first entry 3031 into the first memory unit 304, so that the processor's control unit can adjust the states of multiple threads to the valid state. With the valid signal of the convergence instruction D read, the pop logic unit is used to remove the first entry 3031 from the stack 303 and control the stack control unit 305 to decrease the value in the second memory unit 306, so that the value in the second memory unit 306 is restored to -1, i.e., the stack 303 is empty.

[0154] In one example, push logic unit 302 is also used to push the valid signal of the convergence point instruction into the first entry. For example, push logic unit 302 is also used to push the valid signal of the convergence point instruction from the top of stack 303 into the fifth field of the first entry, and the read logic unit can directly read the valid signal of the convergence point instruction from the fifth field.

[0155] In one example, the program flow control device 300 further includes a third arithmetic unit 309. The third arithmetic unit 309 is used to generate a valid signal for a convergence point instruction. Exemplarily, the third arithmetic unit 309 is used to perform logical operations on the valid signals of multiple instruction branches to obtain a valid signal for a convergence point instruction, and to update the valid signal for the convergence point instruction to a first entry such that the first entry includes the valid signal for the convergence point instruction.

[0156] Optionally, the third arithmetic unit 309 can be implemented as an arithmetic unit that performs bitwise OR logical operations (i.e., bitwise OR), which refers to performing an OR operation on each corresponding binary bit of two numbers. For example, the third arithmetic unit 309 is used to perform bitwise OR logical operations on the valid signals of multiple instruction branches to obtain the valid signal of the convergence point instruction. The third arithmetic unit 309 can also be used to store the valid signal of the convergence point instruction in any fourth field segment.

[0157] Optionally, the third arithmetic unit 309 can be used to generate a valid signal for the convergence point instruction after all instruction branches have been executed, or it can be used to generate a valid signal for the convergence point instruction after each instruction branch has been executed. This application embodiment does not limit this.

[0158] For example, refer to Figure 3 and Figure 6 When computer instruction B is executed and execution jumps to computer instruction C, the third arithmetic unit 309 can first read the value in the first storage unit 304 (i.e., the valid signal mask of computer instruction B = 1100), and after the valid signal of computer instruction C is updated to the first storage unit 304, read the value in the first storage unit 304 again (mask = 0011). Then, it performs a bitwise OR logical operation on the two read values ​​to obtain the valid signal of the convergence point instruction D (mask = 1111). Finally, the third arithmetic unit 309 updates the valid signal of computer instruction C in the first entry 3031 to the valid signal of convergence point instruction D (mask = 1111). Optionally, the third arithmetic unit 309 can also update the valid signal of convergence point instruction D into the first entry 3031 by pushing logic unit 302. This embodiment of the application does not limit this.

[0159] 3. The second arithmetic unit 308 is used to output a jump enable signal as the second arithmetic value when the third instruction branch has been executed and the status information of the convergence point instruction is the third value.

[0160] When the jump enable signal is the second operation value, the jump enable signal is used to indicate that the computer instructions in the first program are not executed by jumping, so as to continue executing the convergence point instructions.

[0161] For example, refer to Figures 3 to 6When the status information of the convergence instruction D is 0, the second arithmetic unit 308 always outputs a jump enable signal of 0. Even if the computer instruction C is also executed, the jump enable signal is still 0. Therefore, the jump enable signal will not trigger the processor to perform an address jump operation. That is, after all instruction branches are executed, the program flow control device 300 no longer guides the processor to jump to execute computer instructions. Then the processor can execute the convergence instruction in sequence.

[0162] In this embodiment, the valid signal of the convergence point instruction is obtained through the third arithmetic unit 309, without the need to allocate a separate field segment for the valid signal of the convergence point instruction. This helps to reduce the stack space requirement when processing branch structures in the program, thereby effectively reducing the storage resource occupation of the stack.

[0163] In addition, a valid signal based on the convergence point instruction in the first entry can enable multiple threads to automatically reconverge after divergence, thereby ensuring that multiple threads are executed correctly.

[0164] In one example, refer to Figures 3 to 7 Taking the example of a processor encountering a two-branch structure when processing a task with four threads, the technical solution provided in this application embodiment will be described. The embodiments of this application may further include the following:

[0165] At time T0: The processor executes vector branch instruction A, and all four threads are in an active state. At this time, the first memory unit 304 stores the active signal mask of vector branch instruction A, which is 1111, and the value of the second memory unit 306 points to -1, indicating that stack 303 is empty.

[0166] At time T1:

[0167] 1. Branch processing unit 301 is used to execute vector branch instruction A when it is obtained, so as to determine the jump direction of the first thread, the jump direction of the second thread, the jump direction of the third thread and the jump direction of the fourth thread.

[0168] 2. Branch processing unit 301 is used to generate the valid signal for computer instruction B as mask = 1100 and the valid signal for computer instruction C as mask = 0011 when the jump directions of the four threads are different. If the jump direction of the first thread and the second thread is computer instruction B, and the jump direction of the third thread and the fourth thread is computer instruction C.

[0169] 3. Branch processing unit 301 is used to update the valid signal mask=1100 of computer instruction B to the second storage unit 304 when the processor prioritizes the execution of computer instruction B, so that the processor's control unit adjusts the state of the third thread and the fourth thread to an invalid state, and keeps the state of the first thread and the second thread in an valid state.

[0170] 4. Branch processing unit 301 is used to send the address information of the convergence point instruction D, the address information of the computer instruction C, and the valid signal of the computer instruction C to the push logic unit 302.

[0171] 5. Push logic unit 302, used to set the status information of the convergence point instruction D to status=1.

[0172] 6. Push logic unit 302 is used to control stack control unit 305 to update the value of second storage unit 306 from -1 to 0. 0 points to the stack space at the top of stack 303, which is the 4 consecutive field segments allocated for the first entry 3031.

[0173] 7. Push logic unit 302 is used to perform a push operation on stack 303 to push the address information of convergence instruction D, the status information of convergence instruction D status=1, the address information of computer instruction C, and the valid signal mask=0011 of computer instruction C from the top of stack 303 onto stack 303, thereby generating the first entry 3031 in stack 303.

[0174] 8. The read logic unit is used to read the address information of the convergence point instruction D in the first entry 3031 into the first arithmetic unit 307, and to read the status information status=1 of the convergence point instruction D in the first entry 3031 into the second arithmetic unit 308.

[0175] 9. The first arithmetic unit 307 is used to obtain the first address information of the control unit from the processor; when the first address information is the address information of computer instruction B, the first address information is different from the address information of the convergence point instruction D, and the output intermediate signal is 0; when the first address information is the address information of the convergence point instruction D, the first address information is the same as the address information of the convergence point instruction D, and the output intermediate signal is 1.

[0176] 10. The second arithmetic unit 308 is used to perform an "AND" logical operation on the intermediate signal and the status information status=1 of the convergence instruction D, and output a jump enable signal jump_en_out; wherein, when the intermediate signal is 0 and status=1, jump_en_out=0 is output to indicate that the processor does not perform an address jump operation; when the intermediate signal is 1 and status=1, jump_en_out=1 is output to indicate that the processor jumps to perform an address jump operation, that is, jumps to execute computer instruction C, instead of continuing to execute the convergence instruction D.

[0177] At time T2:

[0178] 11. A read logic unit is used to read the address information of computer instruction C from the first entry 3031 when jump_en_out = 1, and to output the address information of computer instruction C as a jump address signal. The processor's control unit can jump to execute computer instruction C based on the jump address signal, without executing the convergence point instruction D. The unit reads the valid signal mask = 0011 of computer instruction C from the first entry 3031, and updates the valid signal mask = 0011 of computer instruction C to the first storage unit 304. The processor's control unit can adjust the states of the third and fourth threads to valid states, and adjust the states of the first and second threads to invalid states, based on the valid signal mask = 0011 of computer instruction C.

[0179] 12. The third arithmetic unit 309 is configured to read the valid signal mask = 1100 of computer instruction B from the first storage unit 304 when computer instruction B is executed, and to read the valid signal mask = 0011 of computer instruction C from the first storage unit 304 when computer instruction C is executed; perform a bitwise OR logical operation on the valid signal mask = 1100 of computer instruction B and the valid signal mask = 0011 of computer instruction C to obtain the valid signal mask = 1111 of the convergence point instruction D; and update the valid signal mask = 0011 of computer instruction C in the first entry 3031 to the valid signal mask = 1111 of the convergence point instruction D. Optionally, the valid signal mask = 1100 of computer instruction B may also be sent to the third arithmetic unit 309 by the branch processing unit 301, and the valid signal mask = 0011 of computer instruction C may also be sent to the third arithmetic unit 309 by the read logic unit. This embodiment of the application does not limit this.

[0180] 13. Push logic unit 302 is used to update the status information of the convergence instruction D in the first entry 3031 from status=1 to status=0 when the intermediate signal is 1 or jump_en_out=1, so as to indicate that there is no unprocessed instruction branch in the branch structure 400.

[0181] 14. A read logic unit, used to read the address information of the convergence point instruction D in the first entry 3031 into the first arithmetic unit 307, and to read the status information status=0 of the convergence point instruction D in the first entry 3031 into the second arithmetic unit 308.

[0182] 15. The first arithmetic unit 307 is used to obtain the first address information of the control unit from the processor; when the first address information is the address information of computer instruction C, the first address information is different from the address information of the convergence point instruction D, and the output intermediate signal is 0; when the first address information is the address information of the convergence point instruction D, the first address information is the same as the address information of the convergence point instruction D, and the output intermediate signal is 1.

[0183] 16. The second arithmetic unit 308 is used to perform an "AND" logical operation on the intermediate signal and the status information status=0 of the convergence instruction D, and output a jump enable signal jump_en_out; wherein, when the intermediate signal is 0 and status=0, jump_en_out=0 is output to indicate that the processor does not perform an address jump operation; when the intermediate signal is 1 and status=0, jump_en_out=0 is output to indicate that the processor does not perform an address jump operation, so as to continue to execute the convergence instruction D in sequence.

[0184] 17. A read logic unit is used to read the valid signal mask = 1111 of the convergence point instruction from the first entry 3031 and update the valid signal mask = 1111 of the convergence point instruction to the first storage unit 304. The processor's control unit can keep the state of the third thread and the fourth thread in a valid state and adjust the state of the first thread and the second thread to a valid state based on the valid signal mask = 1111 of the convergence point instruction.

[0185] At time T3:

[0186] 18. A pop logic unit, used to pop the first entry 3031 from the stack 303, and to control the stack control unit 305 to readjust the value in the second storage unit 306 to -1, so as to indicate that the stack 303 is empty.

[0187] In one example, the push logic unit 301, the read logic unit, the stack control unit 305, the pop logic unit, and the second storage unit 306 can be implemented as a stack control module to uniformly manage the stack 303.

[0188] In summary, the technical solution provided by this application, when a first program is executed by multiple threads and encounters a branch structure within the first program, if the first instruction branch among multiple instruction branches is executed first, a first entry can be generated on the stack through a single push operation. This entry can be used to determine the address information and valid signals of other instruction branches, as well as the address information and status information of the convergence instruction. Since the status information of the convergence instruction can be used to determine whether the conditions for executing the convergence instruction are met, the program flow control device can guide the processor to execute the convergence instruction after executing multiple instruction branches based on the first entry. Furthermore, since the valid signals of the instruction branches can be used to indicate at least one thread among multiple threads used to execute that instruction branch, the program flow control device can guide the processor to correctly execute multiple threads when executing a certain instruction branch based on the first entry. This achieves the goal of guiding the instruction branch, convergence instruction, and thread to be executed correctly through a single push operation, without requiring two push operations and two pop operations. This reduces the number of push and pop operations, thereby helping to reduce the power consumption required by the branch structure in the processing program.

[0189] Furthermore, when allocating the same stack space for each entry, the technical solution provided in this application only requires the stack space corresponding to one entry for each branch structure. Compared with related technologies, which require the stack space corresponding to two entries for each branch structure, this helps to reduce the stack space requirement when processing branch structures in the program, thereby effectively reducing the storage resource occupation of the stack.

[0190] In some embodiments, the technical solutions provided in this application are also applicable to nested branch scenarios. Nested branch refers to a branch structure nested within a branch structure, such as at least one instruction branch in a branch structure containing a nested branch structure. The following description uses the example of a nested branch structure in the first instruction branch as an example. This application embodiment may also include the following:

[0191] 1. The branch processing unit 301 is further configured to, when obtaining a sub-vector branch instruction in the first instruction branch, execute the sub-vector branch instruction and determine the valid signals of multiple sub-instruction branches corresponding to the sub-vector branch instruction in the first instruction branch.

[0192] In the embodiments of this application, the nested branch structure in the instruction branch can be referred to as the sub-branch structure. The vector branch instruction, instruction branch and convergence point instruction included in the sub-branch structure can be collectively referred to as the sub-vector branch instruction, sub-instruction branch and sub-convergence point instruction, respectively.

[0193] During the execution of the first instruction branch, if the processor executes a sub-vector branch instruction within the first instruction branch, it will send the sub-vector branch instruction to the branch processing unit 301. The branch processing unit 301 can be used to execute the sub-vector branch instruction, determine the jump direction of each thread for the sub-vector branch instruction, and, if the jump directions of the multiple threads for the sub-vector branch instruction are different, determine the valid signal of each of the multiple sub-instruction branches based on the jump directions of the multiple threads for the sub-vector branch instruction. Optionally, the branch processing unit 301 can also execute the sub-vector branch instruction, determine the jump direction of at least one thread executing the first instruction branch, and determine the valid signal of each of the multiple sub-instruction branches based on the jump direction of at least one thread executing the first instruction branch; however, this application does not limit this implementation.

[0194] The jump direction of a thread to a sub-vector branch instruction is used to indicate the sub-instruction branch executed by the thread, and the valid signal of the sub-instruction branch is used to indicate at least one thread among multiple threads that is executing the sub-instruction branch.

[0195] This application does not limit the number of sub-instruction branches, which can be set and adjusted based on actual usage requirements. Optionally, the aforementioned multiple sub-instruction branches correspond to the same sub-vector branch instruction, that is, the aforementioned multiple sub-instruction branches refer to the sub-instruction branches that need to be executed among the sub-instruction branches corresponding to the aforementioned sub-vector branch instruction. After all the multiple sub-instruction branches have been executed, the processor executes the sub-convergence point instruction.

[0196] For example, refer to Figure 8 Branch structure 800 includes vector branch instruction A, instruction branch 801, instruction branch 802, and convergence instruction J. Instruction branch 801 includes sub-vector branch instruction B, a sub-instruction branch formed by computer instruction D, a sub-instruction branch formed by computer instruction E, and a sub-convergence instruction H. Instruction branch 802 includes sub-vector branch instruction C, a sub-instruction branch formed by computer instruction F, a sub-instruction branch formed by computer instruction G, and a sub-convergence instruction I. The processor starts four threads to execute the program. The first and second threads execute instruction branch 801, and the third and fourth threads execute instruction branch 802. The valid signal for instruction branch 801 is mask = 1100, and the valid signal for instruction branch 802 is mask = 0011.

[0197] When the processor prioritizes instruction branch 802, the push logic unit 302 pushes the address information of the convergence instruction J, the status information of the convergence instruction J (i.e., status = 1), the address information of the starting instruction (i.e., calculation instruction B) in instruction branch 801, and the valid signal of instruction branch 801 (i.e., mask = 1100) from the top of the stack 303 onto the stack 303, generating the first entry 3032 in the stack 303. The value in the second storage unit 306 is also adjusted by the stack control unit 305 to point to the first entry 3032, and the value in the first storage unit 304 is also updated by the branch processing unit to the valid signal mask of instruction branch 802 (mask = 0011).

[0198] The branch processing unit 301 is further configured to, upon obtaining the sub-vector branch instruction C of instruction branch 802, execute the sub-vector branch instruction C to determine the jump direction of the third thread and the fourth thread. If the jump direction of the third thread is computer instruction F and the jump direction of the fourth thread is computer instruction G, the valid signal of the sub-instruction branch formed by computer instruction F is mask = 0010, the valid signal of the sub-instruction branch formed by computer instruction G is mask = 0001, and the valid signal of the sub-convergence instruction I is mask = 0011. That is, after the sub-instruction branches formed by computer instruction F and computer instruction G are executed, the third thread and the fourth thread converge to execute the sub-convergence instruction I. After the sub-convergence instruction I is executed, the processor jumps to execute instruction branch 801.

[0199] In one example, the branch processing unit 301 is further configured to update the validity signal of the first sub-instruction branch in the first storage unit 304 when the first sub-instruction branch among multiple sub-instruction branches is executed first, so that the processor's control unit adjusts the state of multiple threads to match the first sub-instruction branch. The address information and validity signals of the other sub-instruction branches besides the first sub-instruction branch, as well as the address information of the convergence point instruction, are sent to the push logic unit 302.

[0200] The first sub-instruction branch refers to the sub-instruction branch that is executed first among multiple sub-instruction branches. It can be any sub-instruction branch among multiple sub-instruction branches, or it can refer to the first sub-instruction branch among multiple sub-instruction branches. This application embodiment does not limit this.

[0201] 2. The push logic unit 302 is also used to perform a push operation on the stack when the first sub-instruction branch in multiple sub-instruction branches is executed first, and to generate a second entry in the stack.

[0202] Optionally, the push logic unit 302 can be used to receive valid signals of other sub-instruction branches, address information of other sub-instruction branches, address information of sub-convergence point instructions, etc., sent by the branch processing unit 301.

[0203] The aforementioned second entry is also generated through a single stack push operation. That is, by performing a single stack push operation on stack 303, the data required to generate the second entry is pushed from the top of stack 303 onto stack 303, thus generating the second entry in stack 303. In this embodiment, the data stored in the second entry can be used to instruct the processor to correctly execute multiple sub-instruction branches sequentially. The data stored in the second entry can also be used to instruct the processor to correctly adjust the state of multiple threads during the execution of the various computer instructions included in the sub-branch structure. This embodiment does not limit the scope of the second entry.

[0204] Optionally, the second entry includes a third type of information and a fourth type of information. The third type of information is used to determine the address information and valid signals of the sub-instruction branches other than the first sub-instruction branch among the multiple sub-instruction branches. The fourth type of information is used to determine the address information and status information of the sub-convergence instruction. The sub-convergence instruction is a computer instruction that is executed after the execution of the multiple sub-instruction branches. The status information of the sub-convergence instruction is used to determine whether the conditions for executing the sub-convergence instruction are met. The address information of the sub-instruction branch can be used to indicate the storage location of the sub-instruction branch in the processor memory.

[0205] After the second entry is generated, it occupies the top position of stack 303, while the first entry is located at the bottom of stack 303. Optionally, before generating the second entry, the push logic unit 302 is also used to control the stack control unit 305 to update the value in the second storage unit 306, so that the value in the second storage unit 306 points to the free stack space at the top of stack 303, thereby facilitating the push logic unit 302 to generate the second entry at the top of stack 303. For example, refer to... Figure 9 Before generating the second entry 3033, the push logic unit 302 is also used to control the stack control unit 305 to update the value in the second storage unit 306 so that the value in the second storage unit 306 points to the free stack space at the top of the stack 303, and then the push logic unit 302 generates the second entry 3033 in the free space.

[0206] Optionally, the program flow control device 300 may, based on the address information of other sub-instruction branches determined by the third type of information, guide the processor to jump to execute other sub-instruction branches after executing the first sub-instruction branch to achieve serial execution of multiple sub-instruction branches, and may, based on the valid signals of other sub-instruction branches determined by the third type of information, guide the processor to adjust the state of multiple threads to correspond to the currently executed computer instructions so that multiple threads are executed correctly.

[0207] The program flow control device 300 can determine whether a sub-instruction branch has been executed based on the address information of the sub-convergence instruction determined by the fourth type of information, and can guide the processor to adjust the state of multiple threads to correspond to the sub-convergence instruction based on the valid signal of the sub-convergence instruction determined by the fourth type of information, so that multiple threads are executed correctly.

[0208] In one example, the third type of information includes: the address information of the starting instruction in other sub-instruction branches and the valid signals of other sub-instruction branches; the fourth type of information includes: the address information of the sub-convergence point instruction and the status information of the sub-convergence point instruction. That is, the push logic unit 302 can be used to perform a push operation on the stack 303, pushing the address information of the starting instruction in other sub-instruction branches, the valid signals of other sub-instruction branches, the address information of the sub-convergence point instruction, and the status information of the sub-convergence point instruction from the top of the stack 303 onto the stack 303, generating a second entry in the stack 303. The starting instruction in a sub-instruction branch can be the first computer instruction in the sub-instruction branch.

[0209] For example, the push logic unit 302 is further configured to push the address information of the sub-convergence point instruction from the top of the stack 303 into the first field of the second entry, push the status information of the sub-convergence point instruction from the top of the stack 303 into the second field of the second entry, push the address information of the start instruction in other sub-instruction branches from the top of the stack 303 into the third field of the second entry, and push the valid signals of other sub-instruction branches from the top of the stack 303 into the fourth field of the second entry.

[0210] Optionally, the push logic unit 302 can also be used to determine the status information of the sub-convergence instruction based on the number of valid signals of other sub-instruction branches. The number of valid signals of other sub-instruction branches can be used to indicate the number of other sub-instruction branches, and the number of other sub-instruction branches can be used to indicate how many address jump operations the processor needs to perform for the sub-branch structure. The push logic unit 302 can directly determine the number of valid signals of other sub-instruction branches as the initial value of the status information of the sub-convergence instruction.

[0211] For example, refer to Figure 8 and Figure 9When computer instruction G is executed first, push logic unit 302 can determine the initial value of the status information of sub-convergence instruction I as status = 1 based on the number of valid signals of other sub-instruction branches (i.e., the instruction branch formed by computer instruction F).

[0212] During the execution of the subvector convergence point instruction C, the third and fourth threads are in an active state, the value in the first storage unit 304 is cur_mask = 0011, the first entry 3032 has been generated in the stack 303, and the value in the second storage unit 306 is 0.

[0213] The push logic unit 302 can be used to control the stack control unit 305 to update the value in the second storage unit 306 to 1, so that the value in the second storage unit 306 points to the free stack space at the top of the stack 303.

[0214] The push logic unit 302 can be used to perform a push operation on the stack 303 to push the address information of the sub-convergence instruction I into the first field corresponding to the second entry 3033, push the status information (i.e., status = 1) of the sub-convergence instruction D into the second field corresponding to the second entry 3033, push the address information of the computer instruction F into the third field corresponding to the second entry 3033, and push the valid signal (i.e., mask = 0010) of the computer instruction F into the fourth field corresponding to the second entry 3033, thereby generating the second entry 3033 in the stack 303. At this time, the read logic unit can only view the second entry 3033 from the top of the stack 303, and cannot view the first entry 3032. The value in the first storage unit 304 is updated to the valid signal mask = 0001 of the computer instruction G.

[0215] After computer instruction G is executed, program flow control device 300 can guide the processor to jump to execute computer instruction F based on second entry 3033 (such as address information of sub-convergence instruction I, status information status=1 of sub-convergence instruction I, and address information of computer instruction F). Furthermore, program flow control device 300 can guide the processor to set the status of only the third thread to an active state based on the valid signal mask=0010 of computer instruction F in second entry 3033.

[0216] The program flow control device 300 can be used to update the status information of the sub-convergence point instruction I in the second entry 3033 to status=0, and to update the valid signal of the computer instruction F in the second entry 3033 to the valid signal mask=0011 of the sub-convergence point instruction I.

[0217] The program flow control device 300 can be used, based on the second entry 3033 (such as the address information of sub-convergence instruction I and the status information of sub-convergence instruction I, status=0), to guide the processor to not perform an address jump operation, and thus continue to execute sub-convergence instruction I. The program flow control device 300 can also be used, based on the valid signal mask=0011 of sub-convergence instruction I in the second entry 3033, to guide the processor to set the status of only the third and fourth threads to a valid state, thereby causing the third and fourth threads to converge and execute sub-convergence instruction I.

[0218] It should be noted that the usage method of the second item is the same as that of the first item described above. For any content not described in the embodiments of this application, please refer to the above embodiments, which will not be repeated here.

[0219] After the sub-convergence instruction I is executed (i.e., instruction branch 802 is executed), the stack pop logic unit is used to pop the second entry 3033 from the stack 303 so that the read logic unit can view the first entry 3032.

[0220] After the sub-convergence instruction I is executed, the processor will read and execute the convergence instruction J. The processor sends the address information of the convergence instruction J to the program flow control device 300. When the program flow control device 300 obtains the first address information (i.e., the address information of the convergence instruction J), since the first address information is the same as the address information of the convergence instruction J in the first entry 3032, the intermediate signal is output as 1. When the intermediate signal is 1 and the status in the first entry 3032 is 1, the jump use signal is output as 1 to instruct the processor to perform an address jump operation instead of executing the convergence instruction J.

[0221] The program flow control device 300 is further configured to output an address jump signal for the address information of computer instruction B in the first entry 3032, thereby causing the processor to jump to execute instruction branch 801. The program flow control device 300 is further configured to update the valid signal of instruction branch 801 in the first entry 3032 to the first memory unit 304, so that the processor sets the states of only the first thread and the second thread to a valid state, thereby causing the first thread and the second thread to converge and execute instruction branch 801.

[0222] After the first instruction branch 801 is executed, the program flow control device 300 is further configured to, based on the first entry 3032, guide the processor not to perform an address jump operation, so as to continue executing the convergence instruction J. The program flow control device 300 is further configured to update the valid signal of the convergence instruction J in the first entry 3032 to the first memory unit 304, so that the processor sets the states of the first thread, the second thread, the third thread and the fourth thread to a valid state, thereby enabling the four threads to converge and execute the convergence instruction J.

[0223] In summary, the technical solution provided in this application, when encountering nested branches, if the first sub-instruction branch among multiple sub-instruction branches is executed first, a second entry can be generated on the stack through a single push operation. This entry can be used to determine the address information and valid signals of other sub-instruction branches, as well as the address information and status information of the sub-convergence instruction. Since the status information of the sub-convergence instruction can be used to determine whether the conditions for executing the sub-convergence instruction are met, the program flow control device can guide the processor to execute the sub-convergence instruction after executing multiple sub-instruction branches based on the second entry. Furthermore, since the valid signals of the sub-instruction branch can be used to indicate at least one thread among multiple threads for executing that sub-instruction branch, the program flow control device can guide the processor to correctly execute multiple threads when executing a certain sub-instruction branch based on the second entry. This achieves the goal of guiding the correct execution of sub-instruction branches, sub-convergence instructions, and threads through a single push operation, without requiring two push operations and two pop operations. This reduces the number of push and pop operations, thereby helping to reduce the power consumption required by the branch structure in the processing program.

[0224] Furthermore, when allocating the same stack space for each entry, the technical solution provided in this application only requires the stack space corresponding to one entry for each branch structure. Compared with related technologies, which require the stack space corresponding to two entries for each branch structure, this helps to reduce the stack space requirement when processing branch structures in the program, thereby effectively reducing the storage resource occupation of the stack.

[0225] In addition, in the field of multi-threaded processors, stack operations are frequent in branching scenarios. The technical solution provided in this application can reduce the number of push and pop operations, which helps to reduce the power consumption of accessing the stack and the amount of stack space required, resulting in a smaller chip area and thus effectively improving the competitiveness of the product.

[0226] refer to Figure 10 The diagram illustrates a flowchart of a program flow control method provided in one embodiment of this application. The execution entity for each step of this method can... Figure 3The program flow control device shown. The method includes at least one of the following steps 1001 to 1002.

[0227] Step 1001: The branch processing unit determines the valid signal of each of the multiple instruction branches in the first program, the first program being executed by multiple threads, and the valid signal of the instruction branch is used to indicate at least one thread among the multiple threads for executing the instruction branch, the instruction branch including at least one computer instruction.

[0228] In one example, when the branch processing unit obtains the vector branch instructions corresponding to the plurality of instruction branches, it executes the vector branch instructions to determine the jump direction of each of the plurality of threads. The jump direction is used to indicate the instruction branch executed by the thread, and the vector branch instructions are used to indicate the determination rules of the jump direction of the thread.

[0229] When the jump directions of the multiple threads are different, the branch processing unit determines the valid signal of each of the multiple instruction branches according to the jump directions of the multiple threads.

[0230] The branch processing unit updates the valid signal of the first instruction branch to the first storage unit, and the first storage unit is used to store the valid signal of the currently executed instruction branch.

[0231] In one example, the branch processing unit sends valid signals of the other instruction branches to the push logic unit; the push logic unit determines the status information of the convergence point instruction based on the number of valid signals of the other instruction branches.

[0232] Step 1002: If the first instruction branch among the plurality of instruction branches is executed first, the push logic unit performs a push operation on the stack, generating a first entry in the stack. The first entry includes a first type of information and a second type of information. The first type of information is used to determine the address information and valid signals of the other instruction branches among the plurality of instruction branches besides the first instruction branch. The second type of information is used to determine the address information and status information of the convergence point instruction. The convergence point instruction is a computer instruction that is executed after the plurality of instruction branches have been executed. The status information of the convergence point instruction is used to determine whether the conditions for executing the convergence point instruction are met.

[0233] In one example, the first type of information includes: the address information of the starting instruction in the other instruction branch and the valid signal of the other instruction branch; the second type of information includes: the address information of the convergence point instruction and the status information of the convergence point instruction; and each entry in the stack is allocated at least four consecutive domain segments.

[0234] The push logic unit pushes the address information of the convergence point instruction from the top of the stack into the first field of the first entry, pushes the status information of the convergence point instruction from the top of the stack into the second field of the first entry, pushes the address information of the start instruction in the other instruction branch from the top of the stack into the third field of the first entry, and pushes the valid signal of the other instruction branch from the top of the stack into the fourth field of the first entry.

[0235] In one example, the program flow control device further includes a read logic unit, a first arithmetic unit, and a second arithmetic unit;

[0236] The reading logic unit reads the address information and status information of the convergence point instruction from the first entry; sends the address information of the convergence point instruction to the first processing unit, and sends the status information of the convergence point instruction to the second processing unit;

[0237] The first processing unit acquires first address information, which refers to the address information of the currently executed computer instruction; based on the first address information and the address information of the convergence point instruction, it generates an intermediate signal, which is used to indicate whether the first instruction branch has been completed; and sends the intermediate signal to the second processing unit.

[0238] The second arithmetic unit generates a jump enable signal based on the status information of the intermediate signal and the convergence point instruction. The jump enable signal is used to indicate whether to jump to execute the computer instructions in the first program.

[0239] In one example, the program flow control device further includes a first storage unit for storing valid signals of the currently executing instruction branch;

[0240] When the jump enable signal is the first operation value, the read logic unit reads the address information of the start instruction in the second instruction branch and the valid signal of the second instruction branch from the first entry. The second instruction branch is another instruction branch among the plurality of instruction branches besides the first instruction branch. When the jump enable signal is the first operation value, the jump enable signal is used to indicate the jump to execute the computer instruction in the first program.

[0241] The read logic unit updates the valid signal of the second instruction branch to the first storage unit;

[0242] The read logic unit outputs the address information of the starting instruction in the second instruction branch as a jump address signal, which is used to indicate the jump to execute the second instruction branch.

[0243] In one example, when the first address information and the address information of the convergence point instruction are the same, the first arithmetic unit outputs the intermediate signal as a first value;

[0244] Alternatively, if the first arithmetic unit outputs the intermediate signal as a second value when the first address information and the address information of the convergence point instruction are different; wherein, when the intermediate signal is the first value, the intermediate signal is used to indicate that the first instruction branch has been completed, and when the intermediate signal is the second value, the intermediate signal is used to indicate that the first instruction branch has not been completed.

[0245] In one example, after each instruction branch is executed, the push logic unit updates the status information of the convergence point instruction in the first entry; wherein, when the status information of the convergence point instruction is a third value, the status information of the convergence point instruction is used to indicate that there are no unexecuted instruction branches among the plurality of instruction branches.

[0246] In one example, the program flow control device further includes a read logic unit, a first storage unit, and a second arithmetic unit, wherein the first storage unit is used to store the valid signal of the currently executing instruction branch;

[0247] When the third instruction branch in the plurality of instruction branches is executed and the status information of the convergence point instruction is the third value, the read logic unit reads the valid signal of the convergence point instruction from the first entry. The valid signal of the convergence point instruction is used to activate the plurality of threads. The first entry is deleted from the top of the stack after the read logic unit reads the valid signal of the convergence point instruction.

[0248] The read logic unit updates the valid signal of the convergence point instruction to the first storage unit;

[0249] When the third instruction branch is completed and the status information of the convergence point instruction is the third value, the second arithmetic unit outputs a jump enable signal as a second arithmetic value. When the jump enable signal is the second arithmetic value, the jump enable signal is used to indicate that the computer instructions in the first program are not jumped to continue executing the convergence point instruction.

[0250] In one example, the device further includes a third arithmetic unit;

[0251] The third arithmetic unit performs logical operations on the valid signals of the plurality of instruction branches to obtain the valid signal of the convergence point instruction, and updates the valid signal of the convergence point instruction to the first entry; or, the push logic unit pushes the valid signal of the convergence point instruction into the first entry.

[0252] In one example, the program flow control device further includes a stack control unit and a second storage unit;

[0253] When the first entry is generated, the push logic unit controls the stack control unit to update the value in the second storage unit, the value in the second storage unit being used to indicate the entry located at the top of the stack.

[0254] In one example, when the branch processing unit obtains a sub-vector branch instruction in the first instruction branch, it executes the sub-vector branch instruction and determines the valid signals of multiple sub-instruction branches corresponding to the sub-vector branch instruction in the first instruction branch. The valid signals of the sub-instruction branches are used to indicate at least one thread among the multiple threads that executes the sub-instruction branch.

[0255] When the first sub-instruction branch among the plurality of sub-instruction branches is executed first, the push logic unit performs a push operation on the stack, generating a second entry in the stack. The second entry includes a third type of information and a fourth type of information. The third type of information is used to determine the address information and valid signals of the other sub-instruction branches among the plurality of sub-instruction branches besides the first sub-instruction branch. The fourth type of information is used to determine the address information and status information of the sub-convergence point instruction. The sub-convergence point instruction is a computer instruction that is executed after the execution of the plurality of sub-instruction branches. The status information of the sub-convergence point instruction is used to determine whether the conditions for executing the sub-convergence point instruction are met.

[0256] In summary, the technical solution provided by this application, when a first program is executed by multiple threads and encounters a branch structure within the first program, if the first instruction branch among multiple instruction branches is executed first, a first entry can be generated on the stack through a single push operation. This entry can be used to determine the address information and valid signals of other instruction branches, as well as the address information and status information of the convergence instruction. Since the status information of the convergence instruction can be used to determine whether the conditions for executing the convergence instruction are met, the program flow control device can guide the processor to execute the convergence instruction after executing multiple instruction branches based on the first entry. Furthermore, since the valid signals of the instruction branches can be used to indicate at least one thread among multiple threads used to execute that instruction branch, the program flow control device can guide the processor to correctly execute multiple threads when executing a certain instruction branch based on the first entry. This achieves the goal of guiding the instruction branch, convergence instruction, and thread to be executed correctly through a single push operation, without requiring two push operations and two pop operations. This reduces the number of push and pop operations, thereby helping to reduce the power consumption required by the branch structure in the processing program.

[0257] Furthermore, when allocating the same stack space for each entry, the technical solution provided in this application only requires the stack space corresponding to one entry for each branch structure. Compared with related technologies, which require the stack space corresponding to two entries for each branch structure, this helps to reduce the stack space requirement when processing branch structures in the program, thereby effectively reducing the storage resource occupation of the stack.

[0258] Please refer to Figure 11 This diagram illustrates a simplified structural block diagram of a computer device provided in one embodiment of this application. The computer device 1100 can be any electronic device capable of data calculation, processing, and storage.

[0259] Computer device 1100 includes a processor 1101 and a memory 1102.

[0260] The processor 1101 may include the program flow control device described above.

[0261] Processor 1101 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1101 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1101 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1101 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 1101 may also include an AI processor for handling computational operations related to machine learning.

[0262] The memory 1102 may include one or more computer-readable storage media, which may be non-transitory. The memory 1102 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1102 are used to store a computer program configured to be executed by one or more processors.

[0263] Those skilled in the art will understand that Figure 11 The structure shown does not constitute a limitation on the computer device 1100 and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0264] Optionally, the computer device 1100 may be a personal computer, workstation, game console, and some mobile devices (such as tablet computers, smartphones, etc.), or it may be an in-vehicle terminal device, smart home device, smart TV, smart robot, etc., or it may be a server, server cluster, artificial intelligence computing cluster, cloud computing cluster, etc., wherein the artificial intelligence computing cluster may also be referred to as an intelligent computing cluster or intelligent computing cluster, and this application does not limit it.

[0265] In some embodiments, a chip product is also provided, which includes the program flow control device described above. Optionally, the program flow control device described above can also be implemented as a separate chip product.

[0266] In some embodiments, a processor is also provided, which includes the program flow control means described above.

[0267] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0268] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A program flow control device, characterized in that, The device includes: a branch processing unit, a push logic unit, and a stack; The branch processing unit is used to determine the valid signal of each of the multiple instruction branches in the first program, the first program being executed by multiple threads, and the valid signal of the instruction branch being used to indicate at least one thread among the multiple threads for executing the instruction branch, the instruction branch including at least one computer instruction; The push logic unit is configured to perform a push operation on the stack when the first instruction branch among the plurality of instruction branches is executed first, generating a first entry in the stack. The first entry includes a first type of information and a second type of information. The first type of information is used to determine the address information and valid signals of the other instruction branches among the plurality of instruction branches besides the first instruction branch. The second type of information is used to determine the address information and status information of the convergence point instruction. The convergence point instruction is a computer instruction executed after the execution of the plurality of instruction branches. The status information of the convergence point instruction is used to determine whether the conditions for executing the convergence point instruction are met.

2. The apparatus according to claim 1, characterized in that, The first type of information includes: the address information of the starting instruction in the other instruction branches and the valid signal of the other instruction branches; the second type of information includes: the address information of the convergence point instruction and the status information of the convergence point instruction; each entry in the stack is allocated at least four consecutive domain segments. The push logic unit is used to push the address information of the convergence point instruction from the top of the stack into the first field segment of the first entry, push the status information of the convergence point instruction from the top of the stack into the second field segment of the first entry, push the address information of the start instruction in the other instruction branch from the top of the stack into the third field segment of the first entry, and push the valid signal of the other instruction branch from the top of the stack into the fourth field segment of the first entry.

3. The apparatus according to claim 1 or 2, characterized in that, The branch processing unit is also used to send the valid signals of the other instruction branches to the push logic unit; The push logic unit is also used to determine the status information of the convergence point instruction based on the number of valid signals of the other instruction branches.

4. The apparatus according to any one of claims 1 to 3, characterized in that, The device further includes a read logic unit, a first arithmetic unit, and a second arithmetic unit; The reading logic unit is configured to read the address information and status information of the convergence point instruction from the first entry; send the address information of the convergence point instruction to the first processing unit; and send the status information of the convergence point instruction to the second processing unit. The first arithmetic unit is configured to acquire first address information, which refers to the address information of the currently executed computer instruction; generate an intermediate signal based on the first address information and the address information of the convergence point instruction, the intermediate signal being used to indicate whether the first instruction branch has been completed; and send the intermediate signal to the second arithmetic unit. The second arithmetic unit is used to generate a jump enable signal based on the status information of the intermediate signal and the convergence point instruction. The jump enable signal is used to indicate whether to jump to execute the computer instructions in the first program.

5. The apparatus according to claim 4, characterized in that, The device further includes a first storage unit, which is used to store the valid signal of the currently executed instruction branch; The read logic unit is also used for: When the jump enable signal is the first operation value, the address information of the starting instruction in the second instruction branch and the valid signal of the second instruction branch are read from the first entry. The second instruction branch is another instruction branch among the plurality of instruction branches other than the first instruction branch. When the jump enable signal is the first operation value, the jump enable signal is used to indicate the jump to execute the computer instructions in the first program. Update the valid signal of the second instruction branch to the first memory unit; The address information of the starting instruction in the second instruction branch is output as a jump address signal, which is used to indicate the jump to execute the second instruction branch.

6. The apparatus according to claim 4 or 5, characterized in that, The first arithmetic unit is used for: If the address information of the first address information and the address information of the convergence point instruction are the same, the intermediate signal is output as the first value; or, If the address information of the first address information and the address information of the convergence point instruction are different, the intermediate signal is output as the second value; Wherein, when the intermediate signal is the first value, the intermediate signal is used to indicate that the first instruction branch has been completed; when the intermediate signal is the second value, the intermediate signal is used to indicate that the first instruction branch has not been completed.

7. The apparatus according to any one of claims 1 to 6, characterized in that, The push-in logic unit is also used for: After each instruction branch is executed, update the status information of the convergence point instruction in the first entry; Wherein, when the status information of the convergence point instruction is a third value, the status information of the convergence point instruction is used to indicate that there are no unexecuted instruction branches among the plurality of instruction branches.

8. The apparatus according to claim 7, characterized in that, The device further includes a read logic unit, a first storage unit, and a second arithmetic unit, wherein the first storage unit is used to store the valid signal of the currently executed instruction branch; The read logic unit is used to read the valid signal of the convergence point instruction from the first entry when the third instruction branch in the plurality of instruction branches has been executed and the status information of the convergence point instruction is the third value. The valid signal of the convergence point instruction is used to activate the plurality of threads. The first entry is deleted from the top of the stack after the read logic unit reads the valid signal of the convergence point instruction. The read logic unit is also used to update the valid signal of the convergence point instruction to the first storage unit; The second arithmetic unit is configured to output a jump enable signal as a second arithmetic value when the third instruction branch is completed and the status information of the convergence point instruction is the third value. When the jump enable signal is the second arithmetic value, the jump enable signal is used to indicate that the computer instruction in the first program is not jumped to continue executing the convergence point instruction.

9. The apparatus according to claim 8, characterized in that, The device also includes a third arithmetic unit; The third arithmetic unit is used to perform logical operations on the valid signals of the multiple instruction branches to obtain the valid signal of the convergence point instruction, and to update the valid signal of the convergence point instruction to the first entry. or, The push-in logic unit is also used to push the valid signal of the convergence point instruction into the first entry.

10. The apparatus according to any one of claims 1 to 9, characterized in that, The device also includes a stack control unit and a second storage unit; The push logic unit is further configured to control the stack control unit to update the value in the second storage unit when the first entry is generated, the value in the second storage unit being used to indicate the entry located at the top of the stack.

11. The apparatus according to any one of claims 1 to 10, characterized in that, The branch processing unit is further configured to: When the vector branch instructions corresponding to the plurality of instruction branches are obtained, the vector branch instructions are executed to determine the jump direction of each of the plurality of threads. The jump direction is used to indicate the instruction branch executed by the thread, and the vector branch instructions are used to indicate the determination rules of the jump direction of the thread. When the jump directions of the multiple threads are different, the valid signals of the multiple instruction branches are determined according to the jump directions of the multiple threads. The valid signal of the first instruction branch is updated to the first storage unit, which is used to store the valid signal of the currently executing instruction branch.

12. The apparatus according to any one of claims 1 to 11, characterized in that, The branch processing unit is further configured to, upon obtaining a sub-vector branch instruction in the first instruction branch, execute the sub-vector branch instruction, determine the valid signals of multiple sub-instruction branches corresponding to the sub-vector branch instruction in the first instruction branch, and the valid signals of the sub-instruction branches are used to indicate at least one thread among the multiple threads for executing the sub-instruction branch; The push logic unit is further configured to perform a push operation on the stack when the first sub-instruction branch among the plurality of sub-instruction branches is executed first, generating a second entry in the stack. The second entry includes a third type of information and a fourth type of information. The third type of information is used to determine the address information and valid signals of the other sub-instruction branches among the plurality of sub-instruction branches besides the first sub-instruction branch. The fourth type of information is used to determine the address information and status information of the sub-convergence point instruction. The sub-convergence point instruction is a computer instruction executed after the execution of the plurality of sub-instruction branches. The status information of the sub-convergence point instruction is used to determine whether the conditions for executing the sub-convergence point instruction are met.

13. A chip product, characterized in that, The chip product includes the program flow control device as described in any one of claims 1 to 12.

14. A processor, characterized in that, The processor includes the program flow control device as described in any one of claims 1 to 12.

15. A computer device, characterized in that, The computer device includes a processor, the processor including a program flow control device as described in any one of claims 1 to 12.

16. A program flow control method, characterized in that, The method includes: The branch processing unit determines the valid signal of each of the multiple instruction branches in the first program, which is executed by multiple threads. The valid signal of the instruction branch is used to indicate at least one thread among the multiple threads that executes the instruction branch, and the instruction branch includes at least one computer instruction. When the first instruction branch among the plurality of instruction branches is executed first, the push logic unit performs a push operation on the stack, generating a first entry in the stack. The first entry includes a first type of information and a second type of information. The first type of information is used to determine the address information and valid signals of the other instruction branches among the plurality of instruction branches besides the first instruction branch. The second type of information is used to determine the address information and status information of the convergence point instruction. The convergence point instruction is a computer instruction that is executed after the plurality of instruction branches have been executed. The status information of the convergence point instruction is used to determine whether the conditions for executing the convergence point instruction are met.

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