Quantum bit target working frequency determination method and device and quantum computer
By establishing a topological structure diagram and frequency constraint model in a quantum computer, the target operating frequency was selected, solving the crosstalk and coupling problems in the operation of qubit logic gates and improving the fidelity and execution accuracy of the logic gates.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ORIGIN QUANTUM COMPUTING TECH (HEFEI) CO LTD
- Filing Date
- 2024-10-30
- Publication Date
- 2026-05-08
AI Technical Summary
In quantum computers, the logic gate operations of qubits are susceptible to XY crosstalk and residual ZZ coupling, which can lead to errors in logic gate execution. Existing technologies are unable to effectively reduce these interferences.
By establishing a topology diagram of the quantum processor, conducting random benchmark tests, constructing a frequency constraint model, and selecting the target operating frequency that conforms to the frequency constraint model, the influence of XY crosstalk and residual ZZ coupling can be reduced.
At the target operating frequency, the quantum logic gates exhibit high fidelity, effectively avoiding the effects of XY crosstalk and residual ZZ coupling, thus improving the execution accuracy of the quantum logic gates.
Smart Images
Figure CN121998110A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of quantum computing technology, and in particular to a method, apparatus and quantum computer for determining the target operating frequency of a qubit. Background Technology
[0002] Quantum computing and quantum information is an interdisciplinary field that uses the principles of quantum mechanics to perform computational and information processing tasks. It is closely related to quantum physics, computer science, and informatics. It has experienced rapid development in the last two decades. Quantum algorithms based on quantum computers in scenarios such as factorization and unstructured search have demonstrated performance far exceeding that of existing algorithms based on classical computers, leading to expectations that this field will surpass current computing capabilities. Because quantum computing has the potential to far exceed the performance of classical computers in solving specific problems, realizing a quantum computer requires a quantum processor containing a sufficient number and quality of qubits, capable of performing high-fidelity quantum logic gate operations and readouts on these qubits. The quantum processor is to a quantum computer what a CPU is to a traditional computer; it is the core component of a quantum computer, the processor that performs quantum computations. Before each quantum processor is officially put into use, the parameters of the qubits in the quantum processor must be tested and characterized.
[0003] For each qubit in a quantum processor, to complete as many calculations as possible within its finite lifetime, the fastest possible qubit logic gates are required. Generally, the execution time of a qubit logic gate is three to four orders of magnitude faster than its lifetime. However, fast qubit logic gate operations can lead to errors during execution. Many factors can cause qubit logic gate errors, with crosstalk being a significant one. Examples include signal crosstalk on the drive lines of neighboring qubits (XY crosstalk) and leakage crosstalk from couplers between adjacent qubits (residual ZZ coupling). When all qubits in the quantum processor operate at appropriate frequencies, the impact of these interferences can be effectively reduced.
[0004] It should be noted that the information disclosed in the background section of this application is intended only to enhance the understanding of the general background of this application, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0005] The purpose of this application is to provide a method, apparatus and quantum computer for determining the target operating frequency of a qubit. The determined target operating frequency can make the quantum logic gate applied to the qubit have a relatively high fidelity and can avoid the effects of XY crosstalk and residual ZZ coupling.
[0006] To solve the above technical problems, the technical solution of this application is as follows:
[0007] The first aspect of this application provides a method for determining the target operating frequency of a qubit, comprising:
[0008] A corresponding topological structure diagram is established based on the relative physical positions of each qubit on the quantum processor;
[0009] The system iterates through several preset initial frequency values for each qubit. During the iteration, a random benchmark test is performed on the quantum logic gate applied to each qubit, and the allocatable operating frequency of each qubit is determined based on the fidelity of the quantum state obtained from the test.
[0010] A frequency constraint model is constructed for the target operating frequency of each qubit; wherein, the frequency constraint model is used to characterize the correspondence between the magnitude of XY crosstalk and residual ZZ coupling between each qubit and its neighboring qubit and the operating frequency;
[0011] The target operating frequency is determined from the allocatable operating frequencies of each of the qubits based on the topology diagram and the frequency constraint model.
[0012] Optionally, the method described above may involve iterating through several preset initial frequency values for each qubit, performing random benchmark tests on the quantum logic gates applied to each qubit during the iteration, and determining the allocatable operating frequency of each qubit based on the fidelity of the quantum states obtained from the tests, including:
[0013] An initial operating frequency range is preset for each qubit; wherein, the initial operating frequency range includes several initial frequency values;
[0014] The operating frequency of each qubit is set to the initial value, and the logic gate parameters of each qubit are calibrated according to a directed acyclic graph; wherein, the directed acyclic graph is a number of node graphs composed of the qubit and the performance parameters of the resonant cavity coupled to the qubit.
[0015] A random benchmark test is performed on the calibrated logic gate parameters to obtain the initial frequency value of the quantum state fidelity of the qubit within a preset threshold. The initial value of this frequency is the operating frequency to be assigned to the qubit. The random benchmark test is used to test the correspondence between the quantum state fidelity of the qubit and the applied logic gate.
[0016] Optionally, the method described above involves performing a random benchmark test on the calibrated logic gate parameters to obtain the initial frequency value of the quantum state fidelity of the qubit within a preset threshold as the operating frequency to be assigned to the qubit, including:
[0017] The driving signals applied to the qubit are iterated so that the operating frequency of the qubit corresponds to each of the initial frequency values in the initial operating frequency range.
[0018] When the operating frequency of the qubit is each of the initial values of the frequency, a combination of logic gates and an inverse logic gate are applied to the qubit; wherein, the combination of logic gates includes several single quantum logic gates for controlling the quantum state of the qubit from the initial state to the target state, and the inverse logic gate is used to control the quantum state of the qubit from the target state to the initial state;
[0019] The fidelity of measuring the quantum state of the qubit as its initial state;
[0020] When the fidelity is within the preset threshold, the initial frequency value is determined as the operating frequency to be assigned; when the fidelity is not within the preset threshold, the corresponding initial frequency value is discarded.
[0021] Optionally, the frequency constraint model includes the following components as described above:
[0022] |f i -f j |≥δ A1 ;
[0023] f i -f j -α j |≥δ A2 ;
[0024]
[0025] f i -f j |<δ H1 ;
[0026] Among them, f i f is the allocatable operating frequency of the target qubit i. j δ is the target operating frequency of qubit j adjacent to the target qubit. A1 For the first threshold set, α j δ is the anharmonic size of qubit j. A2 For the second threshold set, g ik f is the value of the residual ZZ coupling between the target qubit and the diagonal qubit k. k δ is the target operating frequency of the diagonal qubit k. Z1 The third threshold is defined as follows: the diagonal qubit is the qubit that has a diagonal relationship with the target qubit i on the topological diagram.
[0027] Optionally, the method described above, determining the target operating frequency from the allocatable operating frequencies of each qubit based on the topology diagram and the frequency constraint model, includes:
[0028] The qubit at the center of the topology diagram is determined as the basic qubit, and one of the allocatable operating frequencies of the basic qubit is determined as the target operating frequency.
[0029] Based on the order of increasing distance between each of the other qubits and the fundamental qubit, the next qubit is selected as the target qubit.
[0030] Select a frequency value that conforms to the frequency constraint model from the allocatable operating frequencies of the target qubit as the target operating frequency.
[0031] Optionally, in the method described above, selecting a frequency value that conforms to the frequency constraint model from the allocatable operating frequencies of the target qubit as the target operating frequency includes:
[0032] By substituting the target operating frequencies of all the determined qubits as known parameters into the frequency constraint model, the target operating frequency of the next target qubit is obtained.
[0033] Optionally, using the method described above, the target operating frequencies of all known qubits can be substituted into the frequency constraint model as known parameters to obtain the target operating frequency of the next target qubit, including:
[0034] When there are multiple allocatable working frequencies for each target qubit that conform to the frequency constraint model, the allocatable working frequency with the largest frequency value is selected as the target working frequency.
[0035] A second aspect of this application provides a device for determining the target operating frequency of a qubit, comprising:
[0036] The first modeling module is used to establish the topological structure diagram of the quantum processor based on the relative physical positions of each qubit on the quantum processor;
[0037] The testing module is used to traverse several preset initial frequency values for each qubit. During the traversal, random benchmark tests are performed on the quantum logic gates applied to each qubit, and the allocatable operating frequency of each qubit is determined based on the fidelity of the quantum state obtained from the test.
[0038] The second modeling module is used to construct a frequency constraint model for the target operating frequency of each qubit. The frequency constraint model is used to limit the magnitude of XY crosstalk and residual ZZ coupling between each qubit and its neighboring qubits.
[0039] The determination module is used to determine the target operating frequency from the allocatable operating frequencies of each of the qubits based on the topology diagram and the frequency constraint model.
[0040] A third aspect of this application provides a quantum computer, including the apparatus for determining the target operating frequency of qubits as described in the second aspect above, or the method for determining the target operating frequency of qubits on a quantum processor as described in any of the first aspects.
[0041] The fourth aspect of this application provides a readable storage medium having a computer program stored thereon, characterized in that, when the computer program is executed by a processor, it can implement the method for determining the target operating frequency of a qubit as described in the first aspect.
[0042] Compared with the prior art, this application has the following beneficial effects:
[0043] Based on the established topology of the quantum processor, several initial frequencies that ensure high fidelity of quantum logic gates are determined for each qubit through random benchmark tests. Then, considering the constraints on the qubit's operating frequency imposed by XY crosstalk and residual ZZ coupling in the frequency constraint model, frequencies that meet the requirements of the frequency constraint model can be selected from the allocatable operating frequencies as the target operating frequency. At this target operating frequency, the quantum logic gates applied to the qubit exhibit high fidelity and avoid the effects of XY crosstalk and residual ZZ coupling.
[0044] The apparatus, quantum computer, and readable storage medium for determining the target operating frequency of qubits proposed in this application belong to the same concept as the method for determining the target operating frequency of qubits, and therefore have the same beneficial effects, which will not be elaborated here. Attached Figure Description
[0045] Figure 1 This is a flowchart illustrating a method for determining the target operating frequency of a qubit according to an embodiment of this application.
[0046] Figure 2 This is a schematic diagram of a process for determining the allocatable operating frequency of each qubit according to an embodiment of this application;
[0047] Figure 3 This is a flowchart illustrating a method for calibrating logic gate parameters of qubits according to an embodiment of this application.
[0048] Figure 4 This is a schematic diagram of a directed acyclic graph proposed in an embodiment of this application;
[0049] Figure 5 This is a schematic diagram of a process for performing a random benchmark test according to an embodiment of this application;
[0050] Figure 6 This is a schematic diagram of the topology of a quantum processor proposed in an embodiment of this application;
[0051] Figure 7 This is a schematic diagram illustrating a process for determining a target operating frequency from the allocatable operating frequencies of each qubit, as proposed in an embodiment of this application.
[0052] Figure 8 This is a schematic diagram of a device for determining the target operating frequency of a qubit according to an embodiment of this application. Detailed Implementation
[0053] The specific embodiments of this application will be described in more detail below with reference to the schematic diagrams. The advantages and features of this application will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this application.
[0054] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0055] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0056] A qubit is a two-level quantum system, which can be understood as an oscillator consisting of an inductor (i.e., a superconducting Josephson junction loop formed by two parallel superconducting Josephson junctions) and a capacitor connected in parallel. Its oscillation frequency can be understood as its operating frequency. By applying a microwave signal to the qubit to adjust the equivalent inductance of the inductor, the operating frequency of the qubit can be adjusted; that is, the operating frequency of the qubit is directly related to the applied microwave signal. Furthermore, when the applied microwave signal is affected by crosstalk, the operating frequency of the qubit changes.
[0057] When qubits execute quantum logic gates, their operating frequency must first be tuned to a set target frequency. If the operating frequency deviates from the target frequency, it directly affects the execution accuracy of the quantum logic gate; that is, crosstalk between qubits affects the execution accuracy. The crosstalk between qubits is related to the distance between them and the frequency difference. For example, when two qubits are close together on the quantum processor, the closer the frequency difference, the more significant the crosstalk. If the two qubits are far apart, the crosstalk is very weak, and the frequency difference has an even weaker impact on crosstalk. Therefore, it is necessary to allocate the operating frequencies of the multiple qubits on the quantum processor.
[0058] like Figure 1 As shown in the figure, this embodiment provides a method for determining the target operating frequency of a qubit, including the following steps.
[0059] Step S10: Establish the corresponding topological structure diagram based on the relative physical positions of each qubit on the quantum processor.
[0060] Step S20: Iterate through several preset initial frequency values for each qubit. During the iteration, perform random benchmark tests on the quantum logic gates applied to each qubit, and determine the allocatable operating frequency of each qubit based on the fidelity of the quantum state obtained from the test.
[0061] For each qubit, several initial frequency values can be preset. Then, at each initial frequency value of the qubit, a random benchmark test is performed on the quantum logic gate applied to the qubit to obtain the correspondence between the fidelity of the quantum state of the qubit and the applied quantum logic gate. Based on the obtained fidelity, the initial frequency value corresponding to the required fidelity is selected as the qualified frequency value and used as the working frequency to be assigned. When each qubit is at a suitable working frequency, the fidelity of the quantum logic gate is relatively high, effectively reducing the impact of interference.
[0062] Step S30: Construct a frequency constraint model for the target operating frequency of each qubit; wherein, the frequency constraint model is used to characterize the correspondence between the magnitude of XY crosstalk and residual ZZ coupling between each qubit and its neighboring qubit and the operating frequency.
[0063] Each qubit is connected to a flux modulation control line and a quantum state control line. The driving signal applied by the flux modulation control line is used to control the operating frequency of the qubit, and the driving signal applied by the quantum state control line is used to control the quantum state of the qubit. XY crosstalk refers to the phenomenon where the driving signal applied by the quantum state control line of a certain qubit causes other neighboring qubits to produce anharmonic drive. Residual ZZ coupling refers to unwanted coupling that still exists after the coupling between qubits is turned off. Coupling between two qubits is a necessary condition for implementing a two-qubit gate, but when the two-qubit gate is not working, the coupling between them needs to be turned off to avoid exciting unnecessary effects.
[0064] Both XY crosstalk and residual ZZ coupling directly affect the precision of logic gates executed by qubits. XY crosstalk and residual ZZ coupling can be reduced by allocating frequencies to each qubit. Therefore, a frequency constraint model incorporating the magnitudes of XY crosstalk and residual ZZ coupling can be constructed to characterize the correspondence between the qubit's operating frequency and these factors. By constraining the qubit's operating frequency using this frequency constraint model, target operating frequencies that can resolve XY crosstalk and residual ZZ coupling can be selected.
[0065] Step S40: Determine the target operating frequency from the allocatable operating frequencies of each qubit based on the topology diagram and frequency constraint model.
[0066] Based on the established topology of the quantum processor, several initial frequencies that ensure high fidelity of quantum logic gates are determined for each qubit through random benchmark tests. Then, considering the constraints on the qubit's operating frequency imposed by XY crosstalk and residual ZZ coupling in the frequency constraint model, frequencies that meet the requirements of the frequency constraint model can be selected from the allocatable operating frequencies as the target operating frequency. At this target operating frequency, the quantum logic gates applied to the qubit exhibit high fidelity and avoid the effects of XY crosstalk and residual ZZ coupling.
[0067] like Figure 2 As shown, several preset initial frequency values for each qubit are traversed. During the traversal, random benchmark tests are performed on the quantum logic gates applied to each qubit, and the allocatable operating frequency of each qubit is determined based on the fidelity of the quantum states obtained from the tests, including:
[0068] Step S201: Preset the initial operating frequency range for each qubit; wherein, the initial operating frequency range includes several initial frequency values.
[0069] The initial operating frequency range of the qubits can be predetermined, such as 4GHz-6GHz. Within this range, a step value can be set to obtain several initial frequency values. For example, setting the step value to 100kHz will yield 20 initial frequency values. Furthermore, adjacent qubits are coupled together via a coupler. This coupler is an adjustable coupler with a modulated operating frequency, which can also be preset.
[0070] It is conceivable that the larger the initial operating frequency range is set, and the more initial frequency values there are, the longer the time will be required to perform subsequent testing experiments. Furthermore, the operating frequency of a qubit is controlled by the applied modulation signal, and there is a sinusoidal correspondence between the qubit's operating frequency and the modulation signal; the rate of change of the qubit's operating frequency with the modulation signal is not constant.
[0071] Step S202: Set the operating frequency of each qubit to an initial value, and calibrate the logic gate parameters of each qubit according to a directed acyclic graph; wherein, the directed acyclic graph consists of several node graphs composed of the qubit and the performance parameters of the resonant cavity coupled to the qubit.
[0072] After several initial frequency values for the qubit are preset in step S201, the logic gate parameters of the qubit can be calibrated. In this step, the logic gate parameters can include not only the characteristic parameters of the qubit and the resonant cavity, but also the signal parameters for controlling and measuring the qubit. These parameters are characterized using a directed acyclic graph.
[0073] A directed acyclic graph consists of several nodes, each corresponding to one of the parameters mentioned above. Each parameter needs to be calibrated, requiring different experiments and procedures, which will not be detailed in this embodiment. Calibration determines the logic gate parameters of the qubits, which can then be used in subsequent testing experiments.
[0074] Step S203: Perform a random benchmark test on the calibrated logic gate parameters to obtain the initial value of the frequency of the quantum state fidelity of the qubit within a preset threshold as the working frequency to be assigned to the qubit. The random benchmark test is used to test the correspondence between the quantum state fidelity of the qubit and the applied logic gate.
[0075] After calibrating the logic gate parameters of each qubit in step S202, random benchmark tests can be performed using the calibrated logic gate parameters. Specifically, the frequency of the qubit is tuned to one of its initial frequency values, and then a logic gate with calibrated parameters is applied to that qubit. The fidelity of the quantum state of that qubit is measured. The applied logic gate can be one or a combination of multiple gates. The test is repeated multiple times, and the fidelity of the quantum state of the qubit is determined based on the results of these multiple tests. The results obtained from these multiple tests are compared with a preset threshold. The initial frequency value that meets the preset threshold is considered qualified and is used as the operating frequency to be assigned.
[0076] As described above, the operating frequency of a qubit directly affects the execution precision (i.e., fidelity) of the applied logic gates. Therefore, random benchmark tests are performed on several preset initial frequency values, and the fidelity of the quantum state in the test results can be used to determine whether the initial frequency value is a qualified frequency value, thereby realizing the allocation of the operating frequency of the qubit.
[0077] like Figure 3 As shown, the logic gate parameters include the characteristic parameters of the qubit and the resonant cavity, the readout parameters, and the control parameters. The operating frequency of the qubit is set to the initial frequency value, and the logic gate parameters of each qubit are calibrated according to the directed acyclic graph, including the following steps.
[0078] Step S2021: Obtain a directed acyclic graph consisting of feature parameters, read parameters, and control parameters, which includes several nodes.
[0079] Step S2022: Traverse several initial frequency values within the initial operating frequency range, and calibrate the characteristic parameters, read the parameters, and control parameters in sequence according to the node order of the directed acyclic graph.
[0080] like Figure 4 The directed acyclic graph shown includes the resonant cavity frequency, bit frequency, frequency and power of the readout signal used to read the quantum state of the qubit, amplitude of the control signal used to control the quantum state of the qubit, and the qubit's T1 (relaxation time) and T2 (decoherence time), etc. Among these, Figure 4 The nodes and the logic gate parameters represented by each node are only examples. In the actual execution process, there are many more logic gate parameters. There are many kinds of logic gates used for quantum state control alone, such as Pauli gates (X gate, Y gate, Z gate) and Hartmann gates (H gate).
[0081] After obtaining the directed acyclic graph (DAG), calibration can be performed according to the type and specific meaning of the logic gate parameters defined for each node in the DAG. The calibration of each logic gate parameter involves executing the corresponding experiment and procedure.
[0082] In this embodiment, the logic gate parameters of the qubits are defined using a directed acyclic graph (DAG) and calibrated sequentially according to the DAG method to ensure the accuracy of the calibrated logic gate parameters, thereby ensuring the accuracy of the fidelity measured during subsequent random benchmark tests.
[0083] like Figure 5 As shown, as one implementation of this embodiment, a random benchmark test is performed on the calibrated logic gate parameters to obtain the initial value of the frequency at which the fidelity of the quantum state of the qubit is within a preset threshold. This includes the following steps.
[0084] S2031: Iterate through the driving signals applied to the qubits so that the operating frequency of the qubits corresponds to the initial values of each frequency in the initial operating frequency range.
[0085] For each preset initial frequency value of a qubit, it needs to be controlled by an applied driving signal to make the qubit be at that initial frequency value.
[0086] S2032: When the operating frequency of the qubit is the initial value of each frequency, a combination of logic gates and an inverse logic gate are applied to the qubit; wherein, the combination of logic gates includes several single quantum logic gates, which are used to control the quantum state of the qubit from the initial state to the target state, and the inverse logic gate is used to control the quantum state of the qubit from the target state to the initial state.
[0087] S2033: The fidelity of measuring the quantum state of a qubit as its initial state.
[0088] When performing random benchmark tests, a logic gate combination is first constructed. This combination includes several single quantum logic gates, such as the Pauli X gate, Pauli Y gate, and H gate mentioned above. Furthermore, this logic gate combination corresponds to an inverse logic gate, whose effect on the quantum state of the qubit is opposite to that of the logic gate combination. For example, if the logic gate combination modulates the quantum state of the qubit from the initial state to the excited state, then the inverse logic gate is used to modulate the quantum state of the qubit from the excited state back to the initial state.
[0089] For a given combination of logic gates and its inverse, during execution, several single quantum logic gates from the combination are first applied sequentially to the qubit, followed by the application of the inverse logic gate, and then the measurement of the qubit's quantum state is performed. Ideally, when the qubit's operating frequency is unbiased and there are no other influencing factors, the qubit's quantum state is the initial state after applying the inverse logic gate, and the measurement fidelity is 100%. In reality, the preset initial frequency is not necessarily the ideal operating frequency; therefore, the fidelity of the measured quantum state will vary accordingly.
[0090] Furthermore, during the above measurement process, the logic gate combination and the inverse logic gate are applied repeatedly to perform multiple measurements. The average value of the fidelity obtained from the multiple measurements is then taken, and the average fidelity value is compared with a preset threshold to select the initial frequency value corresponding to the qualified fidelity.
[0091] In addition, the number and type of logic gates in the logic gate combination can be changed, and the above steps S2032-S2033 can be repeated. Each logic gate combination and inverse logic gate corresponds to an average fidelity. By comparing multiple average fidelity values with a preset threshold, the initial frequency value obtained is more accurate.
[0092] S2034: When the fidelity is within the preset threshold, the initial frequency value is determined as the working frequency to be allocated; when the fidelity is not within the preset threshold, the corresponding initial frequency value is discarded.
[0093] For example, the preset threshold is set to be no less than 99.95%. The average value of the fidelity obtained by the above steps S2031-S2033 is compared with the preset threshold. When the fidelity is within the preset threshold, the initial frequency value is determined as the target operating frequency. Several target operating frequencies form a set of operating frequencies to be allocated. When the fidelity is not within the preset threshold, the corresponding initial frequency value is discarded.
[0094] As one implementation method, this embodiment provides a frequency constraint model, which includes a first sub-frequency constraint model, a second sub-frequency constraint model, a third sub-frequency constraint model, and a fourth sub-frequency constraint model, respectively:
[0095] First sub-frequency constraint model: |f i -f j |≥δ A1 ;
[0096] Second sub-frequency constraint model: |f i -f j -α j |≥δ A2 ;
[0097] Third sub-frequency constraint model:
[0098] Fourth sub-frequency constraint model: |f i -f j |<δ H1 ;
[0099] Among them, f i f is the allocatable operating frequency of the target qubit i. j For the target operating frequency of qubit j adjacent to the target qubit, δ A1For the first threshold set, α j δ is the anharmonic size of qubit j. A2 For the second threshold set, g ik f is the value of the residual ZZ coupling between the target qubit and the diagonal qubit k. k δ is the target operating frequency of the diagonal qubit k. Z1 The third threshold is defined as follows: the diagonal qubit is the qubit that has a diagonal relationship with the target qubit i in the topological structure diagram.
[0100] As shown in the correspondence of the frequency constraint models above, the first sub-frequency constraint model is used to limit the influence of XY crosstalk. When the target qubit i is excited, it is necessary to avoid the driving signal applied to the quantum state control signal line causing its neighboring qubit j to transition from state 0 to state 1. The first sub-frequency constraint model is also used to limit the influence of XY crosstalk. The difference between the first sub-frequency constraint model and the first sub-frequency constraint model is that when the target qubit i is excited, it is also necessary to avoid the driving signal applied to the quantum state control signal line causing its neighboring bit j to transition from state 1 to state 2.
[0101] It should be noted that the first threshold and the second threshold need to be set according to the parameters of the specific quantum processor. In this embodiment, both the first threshold and the second threshold can be set to 40MHz. In other embodiments, the first threshold and the second threshold can also be other values, which are not limited here.
[0102] As shown in the correspondence of the frequency constraint models above, the third sub-frequency constraint model is used to control the influence of residual ZZ coupling, considering the residual ZZ coupling between the target qubit i and its diagonal qubit k, so as to... Figure 6 The example topology diagram includes a 36-qubit quantum processor, assuming the target qubit i is qubit Q. 33 Then the diagonal qubit k is Q. 22 Q 24 Q 42 Q 44 We need to control the residual ZZ coupling value to be less than a set value in order to control its effect on the target qubit i.
[0103] It should be noted that the third threshold needs to be set according to the parameters of the specific quantum processor. In this embodiment, the third threshold can be set to 0.01MHz. In other embodiments, the third threshold can also be other values, which are not limited here. ik In this embodiment, it is set to 0.4MHz.
[0104] As shown in the frequency constraint model above, the fourth sub-frequency constraint model is used to limit the frequency difference between two adjacent qubits. Considering that quantum processors need to execute not only single-qubit logic gates but also two-qubit logic gates, if the operating frequency difference between two adjacent qubits is too large, it will cause hardware errors when executing two-qubit logic gates, preventing them from being executed correctly.
[0105] The fourth threshold needs to be set according to the parameters of the specific quantum processor. In this embodiment, the fourth threshold can be set to 600MHz. In other embodiments, the fourth threshold can be other values, which are not limited here.
[0106] like Figure 7 As shown, as one implementation method, the target operating frequency is determined from the allocatable operating frequencies of each qubit based on the topology diagram and frequency constraint model, including the following steps.
[0107] Step S401: Determine the qubit at the center of the topology diagram as the basic qubit, and determine one of the assignable operating frequencies of the basic qubit as the target operating frequency.
[0108] In this embodiment, the target operating frequency of the qubits that are close to the center of the topology diagram can be obtained first, and then the target operating frequency of the qubits that are far from the center of the topology diagram can be obtained. This approach can maximize the performance of the quantum processor and make qubits whose suitable target operating frequency cannot be determined appear at the edge of the topology diagram of the quantum processor as much as possible, thus effectively improving the utilization rate of resources in the quantum processor.
[0109] by Figure 6 Taking the quantum processor shown in the figure as an example, Figure 6 The diagram below shows a topological structure of a quantum processor containing 36 qubits in one embodiment. Point A is the center of the topological structure. According to the scheme of this application, when there are several qubits equidistant from the center of the topological structure, they can be obtained from these qubits in a random order. For example, Figure 6 The quantum bit Q in 33 Q 34 Q 43 Q 44 Since these four qubits are equidistant from point A, we can randomly select one of them as the base qubit, determine one of its allocable operating frequencies as the target operating frequency, and then randomly select the remaining three as target qubits.
[0110] Step S402: Select the next qubit as the target qubit in order of increasing distance between the other qubits and the fundamental qubit.
[0111] The distances of each qubit in the quantum processor from point A are sequentially obtained. Then, each qubit is selected as the target qubit in ascending order of distance, or in descending order of distance. It is important to note that when several qubits are equidistant from the center of the topology, the corresponding target operating frequency is obtained from these qubits in a random order. For example, Figure 6 The quantum bit Q in 33 Q 34 Q 43 Q 44 These four qubits are equidistant from point A, therefore, these four qubits can acquire the corresponding target operating frequency in a random order without restriction.
[0112] Step S403: Select a frequency value that conforms to the frequency constraint model from the allocatable operating frequencies of the target qubit as the target operating frequency.
[0113] After selecting one qubit as the target qubit in sequence according to steps S401-S402, the frequency value that conforms to the frequency constraint model can be selected from the allocatable operating frequencies of the target qubit as the target operating frequency.
[0114] Furthermore, in the process of sequentially selecting qubits as target qubits to determine the target frequency in steps S401-S403 above, there is a sequence of qubits. When selecting a frequency value that conforms to the frequency constraint model from the allocable working frequencies of the later selected target qubits as the target working frequency, the target working frequencies of all the determined qubits are substituted into the frequency constraint model as known parameters to obtain the target working frequency of the next target qubit.
[0115] by Figure 6 Taking the example in the middle, after selecting Q33, Q34, Q43, and Q44 as target qubits to determine their target operating frequencies, when selecting Q32 as the next target qubit to determine its operating frequency through the frequency constraint model, the target operating frequencies of Q33, Q34, Q43, and Q44 need to be substituted into the frequency constraint model as known parameters.
[0116] Furthermore, each qubit has several allocatable operating frequencies, and there may be cases where several allocatable operating frequencies of a qubit satisfy the frequency constraint model. Therefore, by substituting the target operating frequencies of all known qubits into the frequency constraint model as known parameters, and when there are multiple allocatable operating frequencies of each target qubit that satisfy the frequency constraint model, selecting the allocatable operating frequency with the largest frequency value as the target operating frequency can effectively reduce the noise influence of the qubit's flux modulation control line.
[0117] like Figure 8 As shown, based on the same concept, this embodiment also provides a device for determining the target operating frequency of a qubit, including a first modeling module, a testing module, a second modeling module, and a determination module. Specifically, the first modeling module is used to establish a topology diagram of the quantum processor based on the relative physical positions of each qubit on the quantum processor; the testing module is used to traverse several preset initial frequency values for each qubit, and during the traversal, random benchmark tests are performed on the quantum logic gates applied to each qubit, and the allocatable operating frequency of each qubit is determined based on the fidelity of the quantum states obtained from the tests; the second modeling module is used to construct a frequency constraint model for the target operating frequency of each qubit, and the frequency constraint model is used to limit the magnitude of XY crosstalk and residual ZZ coupling between each qubit and its neighboring qubits; the determination module is used to determine the target operating frequency from the allocatable operating frequencies of each qubit based on the topology diagram and the frequency constraint model.
[0118] It is understood that the first modeling module, the test module, the second modeling module, and the determination module can be implemented in a single device, or any one of these modules can be divided into multiple sub-modules. Alternatively, at least some of the functions of one or more of these modules can be combined with at least some of the functions of other modules and implemented in a single functional module. According to embodiments of this application, at least one of the first modeling module, the test module, the second modeling module, and the determination module can be at least partially implemented as a hardware circuit, such as a Field-Programmable Gate Array (FPGA), a Programmable Logic Array (PLA), a System-on-Chip, a System-on-a-Substrate, a System-on-Package, an Application-Specific Integrated Circuit (ASIC), or any other reasonable method of integrating or packaging the circuit, or as hardware or firmware, or as a suitable combination of software, hardware, and firmware implementations. Alternatively, at least one of the first modeling module, the test module, the second modeling module, and the determination module can be at least partially implemented as a computer program module, which, when run by a computer, can execute the functions of the corresponding module.
[0119] Based on the same concept, this embodiment also provides a quantum computer, including the above-described apparatus for determining the target operating frequency of qubits, or using any of the above-described methods for determining the target operating frequency of qubits to determine the target operating frequency of qubits on a quantum processor.
[0120] Based on the same concept, this embodiment also provides a readable storage medium storing a computer program thereon, which, when executed by a processor, enables the determination of the target operating frequency of the qubit as described above.
[0121] A readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. Networks can include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage on a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this application can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions to implement various aspects of this application.
[0122] Various aspects of this application are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program includes an article of manufacture comprising instructions for implementing various aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.
[0123] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.
[0124] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0125] The above are merely preferred embodiments of this application and do not constitute any limitation on this application. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in this application without departing from the scope of the technical solutions of this application shall still fall within the protection scope of this application.
Claims
1. A method for determining the target operating frequency of a qubit, characterized in that, include: A corresponding topological structure diagram is established based on the relative physical positions of each qubit on the quantum processor; The system iterates through several preset initial frequency values for each qubit. During the iteration, a random benchmark test is performed on the quantum logic gate applied to each qubit, and the allocatable operating frequency of each qubit is determined based on the fidelity of the quantum state obtained from the test. A frequency constraint model is constructed for the target operating frequency of each qubit; wherein, the frequency constraint model is used to characterize the correspondence between the magnitude of XY crosstalk and residual ZZ coupling between each qubit and its neighboring qubit and the operating frequency; The target operating frequency is determined from the allocatable operating frequencies of each of the qubits based on the topology diagram and the frequency constraint model.
2. The method as described in claim 1, characterized in that, The system iterates through several preset initial frequency values for each qubit. During the iteration, a random benchmark test is performed on the quantum logic gates applied to each qubit. Based on the fidelity of the quantum states obtained from the test, the allocatable operating frequency of each qubit is determined, including: An initial operating frequency range is preset for each qubit; wherein, the initial operating frequency range includes several initial frequency values; The operating frequency of each qubit is set to the initial value, and the logic gate parameters of each qubit are calibrated according to a directed acyclic graph; wherein, the directed acyclic graph is a number of node graphs composed of the qubit and the performance parameters of the resonant cavity coupled to the qubit. A random benchmark test is performed on the calibrated logic gate parameters to obtain the initial frequency value of the quantum state fidelity of the qubit within a preset threshold. The initial value of this frequency is the operating frequency to be assigned to the qubit. The random benchmark test is used to test the correspondence between the quantum state fidelity of the qubit and the applied logic gate.
3. The method as described in claim 2, characterized in that, Perform random benchmark tests on the calibrated logic gate parameters to obtain the initial frequency value of the quantum state fidelity of the qubit within a preset threshold, which is the operating frequency to be assigned to the qubit, including: The driving signals applied to the qubit are iterated so that the operating frequency of the qubit corresponds to each of the initial frequency values in the initial operating frequency range. When the operating frequency of the qubit is each of the initial values of the frequency, a combination of logic gates and an inverse logic gate are applied to the qubit; wherein, the combination of logic gates includes several single quantum logic gates for controlling the quantum state of the qubit from the initial state to the target state, and the inverse logic gate is used to control the quantum state of the qubit from the target state to the initial state; The fidelity of measuring the quantum state of the qubit as its initial state; When the fidelity is within the preset threshold, the initial frequency value is determined as the operating frequency to be assigned; when the fidelity is not within the preset threshold, the corresponding initial frequency value is discarded.
4. The method as described in claim 1, characterized in that, The frequency constraint model includes: f i -f j | ≥δ A1 ; f i -f j -a j | ≥d A2 ; f i -f j | <δ H1 ; Among them, f i f is the allocatable operating frequency of the target qubit i. j δ is the target operating frequency of qubit j adjacent to the target qubit. A1 For the first threshold set, α j δ is the anharmonic size of qubit j. A2 For the second threshold set, g ik f is the value of the residual ZZ coupling between the target qubit and the diagonal qubit k. k δ is the target operating frequency of the diagonal qubit k. Z1 The third threshold is defined as follows: the diagonal qubit is the qubit that has a diagonal relationship with the target qubit i on the topological diagram.
5. The method as described in claim 4, characterized in that, Determining the target operating frequency from the allocatable operating frequencies of each qubit based on the topology diagram and the frequency constraint model includes: The qubit at the center of the topology diagram is determined as the basic qubit, and one of the allocatable operating frequencies of the basic qubit is determined as the target operating frequency. Based on the order of increasing distance between each of the other qubits and the fundamental qubit, the next qubit is selected as the target qubit. Select a frequency value that conforms to the frequency constraint model from the allocatable operating frequencies of the target qubit as the target operating frequency.
6. The method as described in claim 5, characterized in that, Selecting a frequency value that conforms to the frequency constraint model from the allocatable operating frequencies of the target qubit as the target operating frequency includes: By substituting the target operating frequencies of all the determined qubits as known parameters into the frequency constraint model, the target operating frequency of the next target qubit is obtained.
7. The method as described in claim 6, characterized in that, By substituting the target operating frequencies of all determined qubits as known parameters into the frequency constraint model, the target operating frequency of the next target qubit is obtained, including: When there are multiple allocatable working frequencies for each target qubit that conform to the frequency constraint model, the allocatable working frequency with the largest frequency value is selected as the target working frequency.
8. A device for determining the operating frequency of a target qubit, characterized in that, include: The first modeling module is used to establish the topological structure diagram of the quantum processor based on the relative physical positions of each qubit on the quantum processor; The testing module is used to traverse several preset initial frequency values for each qubit. During the traversal, random benchmark tests are performed on the quantum logic gates applied to each qubit, and the allocatable operating frequency of each qubit is determined based on the fidelity of the quantum state obtained from the test. The second modeling module is used to construct a frequency constraint model for the target operating frequency of each qubit. The frequency constraint model is used to limit the magnitude of XY crosstalk and residual ZZ coupling between each qubit and its neighboring qubits. The determination module is used to determine the target operating frequency from the allocatable operating frequencies of each of the qubits based on the topology diagram and the frequency constraint model.
9. A quantum computer, characterized in that, The device includes the apparatus for determining the target operating frequency of qubits as described in claim 8, or the method for determining the target operating frequency of qubits on a quantum processor as described in any one of claims 1-7.
10. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it can implement the method for determining the target operating frequency of the qubit as described in any one of claims 1 to 7.