Digital line formation in vertical three-dimensional (3D) memory

Abstract

The invention relates to digital line formation in a vertical three-dimensional (3D) memory. Systems, methods, and apparatus are provided for a vertically stacked array of memory cells having horizontally directed access devices and storage nodes. The horizontally directed access device has a first source / drain region and a second source / drain region separated by a channel region. A gate at the channel region is formed entirely around each surface of the channel region as a gate-all-around GAA structure separated from the channel region by a gate dielectric. The memory cell has a horizontally directed storage node connected to the second source / drain region and a digital line connected to the first source / drain region.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and more specifically to the formation of digital lines in vertical three-dimensional (3D) memory. Background Technology

[0002] Memory is typically implemented in electronic systems such as computers, mobile phones, and handheld devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory requires power to maintain its data and can include Random Access Memory (RAM), Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Synchronous Dynamic Random Access Memory (SDRAM). Non-volatile memory provides persistent data by retaining the stored data when no power is supplied and can include NAND flash memory, NOR flash memory, Nnitride read-only memory (NROM), phase-change memory (e.g., phase-change random access memory), resistive memory (e.g., resistive random access memory), crosspoint memory, ferroelectric random access memory (FeRAM), or similar types.

[0003] As design rules shrink, less semiconductor space is available for fabricating memories containing DRAM arrays. A corresponding memory cell in a DRAM may include access means, such as a transistor, having first and second source / drain regions separated by an epitaxially grown channel region. A gate may be opposite to and separated from the channel region by a gate dielectric. Access lines (e.g., word lines) are electrically connected to the gate of the DRAM cell. A DRAM cell may include memory nodes, such as capacitor cells, connected to digital lines via access means. Access means can be activated (e.g., for selecting a cell) via access lines connected to access transistors. Capacitors may store charge corresponding to the data value (e.g., logic "1" or "0") of the corresponding cell. Summary of the Invention

[0004] On one hand, this disclosure provides a method for forming a three-dimensional (3D) memory, comprising: forming a vertical stack having alternating layers of silicon germanium (SiGe) and silicon (Si) materials from a substrate, the vertical stack having vertically stacked memory cells having horizontally oriented access devices and horizontally oriented memory nodes, the horizontally oriented access devices having a gate, a channel region, a first source / drain region separated by the channel region, and a second source / drain region horizontally formed at different layer levels; and forming a first vertical opening through the vertical stack and extending primarily in a first horizontal direction to expose the stack. The first vertical sidewall in the first vertical opening; in the exposed first vertical sidewall, a surrounding material is three-dimensionally recessed from the Si material to create a three-dimensional exposed surface on the Si material; Si material is epitaxially grown from the three-dimensional exposed Si material to form an enlarged epitaxially grown Si material contact with a cross-sectional size larger than the original cross-sectional size of the Si material; a plurality of spaced vertical pillars are formed between the Si material contacts in the first vertical opening; and conductive material is deposited between the plurality of spaced vertical pillars to form a plurality of spaced vertical digital lines electrically connected to the first source / drain region in the first vertical opening.

[0005] On the other hand, this disclosure provides a method for forming a three-dimensional (3D) memory, comprising: forming a vertical stack having alternating layers of silicon-germanium (SiGe) and silicon (Si) materials from a substrate, the vertical stack having vertically stacked memory cells having horizontally oriented access devices and horizontally oriented memory nodes, the horizontally oriented access devices having a gate, a channel region, a first source / drain region separated by the channel region, and a second source / drain region formed horizontally at different layer levels; forming a first vertical opening through the vertical stack and extending primarily in a first horizontal direction to expose a first vertical sidewall in the stack; and in the... The method involves exposing a first vertical sidewall by causing a surrounding material to be three-dimensionally recessed from the Si material to create a three-dimensional exposed surface on the Si material; epitaxially growing gradient-doped Si material from the three-dimensional exposed Si material to form an enlarged epitaxially grown Si material contact having a cross-sectional size larger than the original cross-sectional size of the Si material; forming a plurality of spaced vertical pillars having a plurality of spaced vertical openings therebetween, wherein the enlarged Si material contact is located in the plurality of spaced vertical openings; and depositing conductive material in the plurality of spaced vertical openings to form a plurality of spaced vertical digital lines electrically connected to the first source / drain region in the first vertical opening.

[0006] On the other hand, this disclosure provides a memory device comprising: a vertically stacked memory cell array having a horizontally oriented access device and a horizontally oriented memory node, wherein: the horizontally oriented access device includes a channel region, a first source / drain region separated by the channel region, a second source / drain region, and a gate on a gate dielectric material; and the horizontally oriented memory node is horizontally formed on the second source / drain region of the horizontally oriented access device; and a vertical digital line having gradient-doped expanded Si material contacts and conductive material deposited in a plurality of vertical openings, wherein the vertical digital line is connected to the first source / drain region of the horizontally oriented access device. Attached Figure Description

[0007] Figure 1A This is a schematic diagram of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0008] Figure 1B This is a perspective view illustrating a portion of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0009] Figure 2 This describes a portion of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0010] Figure 3 This describes a portion of a vertical 3D memory array according to several embodiments of the present disclosure.

[0011] Figure 4 This is a cross-sectional view at a stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure.

[0012] Figures 5A to 5B This invention describes an example method at a stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure.

[0013] Figures 6A to 6C This describes an example method at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure.

[0014] Figures 7A to 7C This describes an example method at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure.

[0015] Figures 8A to 8CThis describes an example method at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure.

[0016] Figures 9A to 9C This invention describes the epitaxial growth of Si material at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure, to form enlarged epitaxially grown Si material contacts.

[0017] Figures 10A to 10B This invention describes the formation of a plurality of spaced vertical pillars having a plurality of spaced vertical openings between them at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure.

[0018] Figure 11 This invention describes how, according to several embodiments of the present disclosure, a plurality of spaced vertical openings are formed at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory.

[0019] Figure 12 This invention describes how, according to several embodiments of the present disclosure, multiple spaced multilayer vertical digital lines are formed at another stage of the semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory.

[0020] Figure 13 This invention describes how, according to several embodiments of the present disclosure, multiple spaced multilayer vertical digital lines are formed at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory.

[0021] Figure 14 This is a block diagram of a device in the form of a computing system including a memory device, according to several embodiments of the present disclosure. Detailed Implementation

[0022] Embodiments of this disclosure describe the formation of digital lines in a vertical three-dimensional (3D) memory. Vertically oriented digital lines are formed together with horizontally oriented access devices and access lines in a vertically stacked memory cell array. The horizontal access devices are integrated with the horizontally oriented access lines, having a first source / drain region and a second source / drain region separated by a channel region and integrated with the vertically oriented digital lines. In a vertically stacked memory array structure, such as a transistor structure, polycrystalline silicon (also called polysilicon) may leak, allowing current to leak through the polycrystalline structure, thus making the transistor less efficient. Single-crystal silicon is less prone to leakage. However, single-crystal silicon cannot be grown on amorphous dielectric materials (e.g., oxides or nitrides), which are common materials for forming transistors.

[0023] However, as disclosed in the embodiments of this disclosure, a silicon wafer can be used for transistors, and the silicon wafer can serve as a substrate during the high-temperature processes required for the formation of single-crystal silicon. In such embodiments, a silicon-germanium layer can be grown on the silicon substrate. Subsequently, single-crystal silicon can be grown on the silicon-germanium.

[0024] For example, this can be achieved by providing a thin monocrystalline silicon-germanium layer as a seed layer and then forming the monocrystalline silicon-germanium layer thickness. Once the desired layer thickness is formed, a silicon layer can be formed into the surface of the silicon-germanium layer. Similar to the silicon-germanium layer, this can be achieved, for example, by providing a thin monocrystalline silicon layer as a seed layer and then forming the thin monocrystalline silicon layer thickness into a thicker monocrystalline silicon layer.

[0025] Depending on the silicon-germanium concentration, if silicon is in the quantity x and germanium in the quantity y, and if y is less than x, then the silicon / silicon-germanium ratio has a small lattice mismatch with respect to the single-crystal silicon lattice. This allows silicon to form in a single-crystal structure on top of silicon-germanium. If a thin layer of single-crystal silicon is applied to the surface of silicon-germanium, then the entire silicon layer acts as a seed for the growth of the single-crystal silicon layer. This layering can be accomplished in alternating iterations (e.g., SiGe / Si / SiGe / Si, etc.) to create a superlattice structure in a vertically stacked form, for example... Figure 4 As shown in the image.

[0026] For example, a silicon-germanium seed layer with a thickness (height) of 100 angstroms can be formed, and said seed layer can be grown to, for example, 1000 angstroms. A thin silicon seed layer, for example, 50 angstroms, can be formed on the surface of the silicon-germanium layer, and said thin seed layer can be grown to, for example, a thickness of 300 angstroms. These thicknesses are provided by way of example only and should not be considered limiting unless expressly stated in a particular claim.

[0027] The transistor device disclosed herein will have better performance in terms of I-on, improved I-off, drive capability, and / or leakage current because there are no grain boundaries and therefore current cannot leak through the grain boundaries, which are common sites of leakage in polycrystalline silicon. In some embodiments, the device may have, for example, three orders of magnitude lower I-off (leakage).

[0028] Compared to silicon-based access devices (such as transistors), the advantages of the structures and processes described herein may include lower cutoff current (Ioff), better DRAM refresh requirements, and / or reduced gate / drain induced leakage (GIDL). The gate-all-around (GAA) structure at the channel region of the semiconductor material provides better electrostatic control of the channel, better sub-threshold slope, and a more cost-effective process.

[0029] During the formation of a 3D memory array, a step in the semiconductor manufacturing process may include forming digital lines. In the process described herein, the digital lines may be vertically oriented within the 3D memory array. The digital lines may be formed in vertical openings within the 3D memory array to electrically interconnect memory cells along vertical pillars.

[0030] However, previous methods have variable contact junction surface areas between the digital lines and the source / drain regions. This variability degrades current cutoff and increases the likelihood of electrical short circuits occurring between the digital lines and word lines.

[0031] The digital line formation in the vertical 3D memory according to this disclosure allows for improved utilization of the contact junction surface area. Epitaxial growth of the Si material used to form enlarged Si material contacts provides a larger surface area for the contact junction between the digital line and the source / drain regions, thereby improving current conduction distribution.

[0032] The figures in this document follow a numbering convention, where the first one or a few digits correspond to the figure number and the remaining digits identify the elements or components within the figure. Similar elements or components between different figures can be identified by using similar digits. For example, reference digit 103 can refer to element "03" in Figure 1, and similar elements in… Figure 2 The reference number can be labeled as 203. Multiple similar elements within a single drawing can be designated using a reference number followed by a character and another number or letter. For example, 302-1 can refer to... Figure 3 Components 302-1 and 302-2 in the text may refer to component 302-2 that is similar to component 302-1. Such similar components may be generally labeled without hyphens and additional numbers or letters. For example, components 302-1 and 302-2 or other similar components may be generally labeled as 302.

[0033] Figure 1AThis is a schematic diagram of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure. Figure 1A The illustration shows a circuit diagram of a cell array of a 3D semiconductor memory device according to an embodiment of the present disclosure. Figure 1A The cell array can have multiple sub-cell arrays 101-1, 101-2, ..., 101-N. Sub-cell arrays 101-1, 101-2, ..., 101-N can be arranged along a second direction (D2) 105. Each sub-cell array (e.g., sub-cell array 101-2) can contain multiple access lines 107-1, 107-2, ..., 107-P (which may also be called word lines). Furthermore, each sub-cell array (e.g., sub-cell array 101-2) can contain multiple digital lines 103-1, 103-2, ..., 103-Q (which may also be called bit lines, data lines, or sensing lines). Figure 1A In this document, access lines 107-1, 107-2, ..., 107-P are described as extending in a first direction (D1) 109, and digital lines 103-1, 103-2, ..., 103-Q are described as extending in a third direction (D3) 111. According to an embodiment, the first direction (D1) 109 and the second direction (D2) 105 can be considered as being in a horizontal (“XY”) plane. The third direction (D3) 111 can be considered as being in a vertical (“Z”) plane. Therefore, according to the embodiment described herein, digital lines 103-1, 103-2, ..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0034] A memory cell (e.g., memory cell 110) may include access means (e.g., access transistors) and memory nodes located at the intersections of each access line 107-1, 107-2, ..., 107-P and each digital line 103-1, 103-2, ..., 103-Q. The memory cell can be written to or read from using the access lines 107-1, 107-2, ..., 107-P and the digital lines 103-1, 103-2, ..., 103Q. The access lines 107-1, 107-2, ..., 107-P can provide a horizontal interconnection of the memory cells along the horizontal axis of each sub-cell array 101-1, 101-2, ..., 101-N, and the digital lines 103-1, 103-2, ..., 103-Q can provide a vertical interconnection of the memory cells along the vertical pillars of each sub-cell array 101-1, 101-2, ..., 101-N. A memory cell (e.g., 110) may be located between an access line (e.g., 107-2) and a digital line (e.g., 103-2). Each memory cell can be uniquely addressed by a combination of access lines 107-1, 107-2, ..., 107-P and digital lines 103-1, 103-2, ..., 103-Q.

[0035] Access lines 107-1, 107-2, ..., 107-P may be or include conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. Access lines 107-1, 107-2, ..., 107-P may extend in a first direction (D1) 109. Access lines 107-1, 107-2, ..., 107-P in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0036] Digital lines 103-1, 103-2, ..., 103-Q may be or be contained in conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., on a third direction (D3) 111) about the substrate. Digital lines in a sub-cell array (e.g., 101-2) may be spaced apart from each other in a first direction (D1) 109.

[0037] The gate of a memory cell (e.g., memory cell 110) may be connected to an access line (e.g., 107-2), and a first conductive node (e.g., a first source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a digital line (e.g., 103-2). Each of the memory cells (e.g., memory cell 110) may be connected to a storage node (e.g., a capacitor). A second conductive node (e.g., a second source / drain region) of an access means (e.g., a transistor) of memory cell 110 may be connected to a storage node (e.g., a capacitor). Although the references to first and second source / drain regions are used herein to denote two separate and distinct source / drain regions, the source / drain regions referred to as “first” and / or “second” are not intended to have any particular meaning. They simply mean that one of the source / drain regions is connected to a digital line (e.g., 103-2) and the other may be connected to a storage node.

[0038] Figure 1B This is part of an illustration of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure (e.g. Figure 1A The image shown is a perspective view of a sub-cell array 101-2 of vertically oriented memory cell stacks in the array.

[0039] like Figure 1B As shown, a bonding can be formed on the substrate 100. Figure 1A One of the described arrays of sub-cells, such as 101-2. For example, substrate 100 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0040] like Figure 1B As shown in the example embodiments, the substrate 100 may have memory cells (e.g., extending in a vertical direction (D3) 111) fabricated thereon. Figure 1A The memory cells 110 in the memory are vertically oriented stacked. According to some embodiments, the vertically oriented memory cell stack can be manufactured such that each memory cell (e.g., Figure 1A The memory cells 110 are formed on multiple vertical layers, such as a first layer (L1), a second layer (L2), and a third layer (L3). Repeated vertical layers L1, L2, and L3 can be arranged in the vertical direction (e.g., ...). Figure 1A The components are arranged (e.g., “stacked”) on the third direction (D3) 111 shown and can be separated from the substrate 100 by an insulating material. Each of the repeating vertical layers L1, L2, and L3 may include multiple discrete components (e.g., regions) to the horizontally oriented access device 130 (e.g., transistors) and storage nodes (e.g., capacitors), including access lines 107-1, 107-2, ..., 107-P connections and digital lines 103-1, 103-2, ..., 103-Q connections. The multiple discrete components to the horizontally oriented access device 130 (e.g., transistors) may be formed in multiple iterations of the vertical repeating layers within each layer, as described in more detail below, and may be arranged in the second direction (D2) 105 (similar to Figure 1A The second direction (D2) 105 shown in the figure extends horizontally upwards.

[0041] Multiple discrete components to a laterally oriented access device 130 (e.g., a transistor) may include a first source / drain region 121 and a second source / drain region 123 separated by a channel region 125, which extends laterally in a second direction (D2) 105 and is formed within the body of the access device. In some embodiments, the channel region 125 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first and second source / drain regions 121 and 123 may comprise n-type dopant regions formed within a p-type doped body to the access device to form an n-type conductive transistor. In some embodiments, the first and second source / drain regions 121 and 123 may comprise p-type dopant formed within an n-type doped body to the access device to form a p-type conductive transistor. For example, but not limited to, the n-type dopant may comprise phosphorus (P) atoms and the p-type dopant may comprise boron (B) atoms formed in the opposite doped body region of a polycrystalline silicon semiconductor material. However, embodiments are not limited to these examples.

[0042] Storage node 127 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 1BAs shown, storage node 127 (e.g., a capacitor) can be connected to the second source / drain region 123 of the access device. Storage nodes can be or contain memory elements capable of storing data. Each of the storage nodes can be a memory element using a capacitor, a magnetic tunnel junction pattern, and / or a variable resistance body containing a phase change material, etc. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g., Figure 1A The memory node associated with each access device of the memory cell 110 in the second direction (D2) 105 (similar to) Figure 1A The second direction (D2) 105 shown in the figure extends upwards.

[0043] like Figure 1B As shown, multiple horizontally oriented access lines 107-1, 107-2, ..., 107-P are in the first direction (D1) 109 (similar to...). Figure 1A Extending along the first direction (D1) 109). Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-P can be similar to... Figure 1A Access lines 107-1, 107-2, ..., 107-P are shown in the diagram. Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-P may be arranged along a third direction (D3) 111, for example, "stacked". Multiple horizontally oriented access lines 107-1, 107-2, ..., 107-P may contain conductive materials. For example, the conductive material may include one or more of the following: doped semiconductors, such as doped silicon, doped germanium, etc.; conductive metal nitrides, such as titanium nitride, tantalum nitride, etc.; metals, such as tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.; and / or metal semiconductor compounds, such as tungsten silicide, cobalt silicide, titanium silicide, etc. However, the embodiments are not limited to these examples.

[0044] In each of the vertical hierarchies (L1), (L2), and (L3), the horizontally oriented memory cell (e.g.) Figure 1AThe memory cells 110 in the horizontally oriented access device 130 may be horizontally spaced apart from each other in the first direction (D1) 109. However, multiple discrete components of the horizontally oriented access device 130 (e.g., the first source / drain region 121 and the second source / drain region 123 separated by the channel region 125 extending laterally in the second direction (D2) 105) and multiple horizontally oriented access lines 107-1, 107-2, ..., 107-P extending laterally in the first direction (D1) 109 may be formed in different vertical layers within each layer. For example, multiple horizontally oriented access lines 107-1, 107-2, ..., 107-P extending in the first direction (D1) 109 may be formed on the top surface opposite to and electrically connected to the channel region 125, separated from the channel region 125 by the gate dielectric, and orthogonal to the horizontally oriented access device 130 (e.g., transistors) extending laterally in the second direction (D2) 105. In some embodiments, multiple horizontally oriented access lines 107-1, 107-2, ..., 107-P extending in the first direction (D1) 109 are formed in a vertical layer that is higher than the layer in which discrete components of the horizontally oriented access device (e.g., the first source / drain region 121 and the second source / drain region 123 separated by the channel region 125) are formed within a layer (e.g., in layer (L1)), and the vertical layer is farther from the substrate 100.

[0045] like Figure 1B As shown in the example embodiments, the digital lines 103-1, 103-2, ..., 103-Q extend in a vertical direction relative to the substrate 100 (e.g., on a third direction (D3) 111). Furthermore, as... Figure 1B As shown, the digital lines 103-1, 103-2, ..., 103-Q are in a sub-cell array (e.g. Figure 1AThe sub-cell arrays 101-2 in the first direction (D1) 109 may be spaced apart from each other. The digital lines 103-1, 103-2, ..., 103-Q may be configured to extend vertically relative to the substrate 100 and the source / drain region serving as the first source / drain region 121 in the third direction (D3) 111, or as shown, vertically adjacent to the first source / drain region 121 of each of the horizontally oriented access devices 130 (e.g., transistors) extending laterally in the second direction (D2) 105, but adjacent to each other in the first direction (D1) 109 at one level (e.g., the first level (L1)). Each of the digital lines 103-1, 103-2, ..., 103-Q may extend vertically in the third direction (D3) on the sidewall of the first source / drain region 121 of the corresponding one of the vertically stacked horizontally oriented access devices 130 (e.g., transistors). In some embodiments, multiple vertically oriented digital lines 103-1, 103-2, ..., 103-Q extending on the third-party direction (D3) 111 may be directly and / or connected to the side of the first source / drain region 121 via additional contacts containing metal silicide.

[0046] For example, the first vertically extending digital line (e.g., 103-1) may be adjacent to the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., transistor) in the first layer (L1), the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., transistor) in the second layer (L2), and the sidewall of the first source / drain region 121 of the first horizontally oriented access device 130 (e.g., transistor) in the third layer (L3). Similarly, the second vertically extending digital line (e.g., 103-2) may be adjacent to the sidewall of the first source / drain region 121 of the second horizontally oriented access device 130 (e.g., transistor) in the first layer (L1) that is spaced apart from the first horizontally oriented access device 130 (e.g., transistor) in the first layer (L1) in the first direction (D1) 109. Furthermore, the second vertically extending digital line (e.g., 103-2) may be adjacent to the sidewall of the first source / drain region 121 of the second lateral access device 130 (e.g., transistor) in the second layer (L2) and the sidewall of the first source / drain region 121 of the second lateral access device 130 (e.g., transistor) in the third layer (L3). The embodiments are not limited to a specific number of layers.

[0047] The vertically extending digital lines 103-1, 103-2, ..., 103-Q may contain conductive materials, such as (for example) one of doped semiconductor materials, conductive metal nitrides, metals, and / or metal-semiconductor compounds. The digital lines 103-1, 103-2, ..., 103-Q may correspond to... Figure 1A The described digital line (DL).

[0048] like Figure 1B As shown in the example embodiment, the conductive body contact may be formed extending above the substrate 100 along the end face of the horizontally oriented access device (e.g., transistors in each layer (L1), (L2), and (L3)) in a first direction (D1) 109. The body contact may be connected to each memory cell (e.g., Figure 1A The body (e.g., body region) of the horizontally oriented access device (e.g., transistor) in the memory cell 110. The body contacts may contain a conductive material, such as (for example) a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal semiconductor compound.

[0049] although Figure 1B Not shown, but insulating material may fill other spaces in the vertically stacked array of memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0050] Figure 2 This describes a portion of a horizontal access device in a vertical three-dimensional (3D) memory according to several embodiments of the present disclosure. Figure 2 A more detailed description is provided of the unit cells (e.g., memory cell 110 in FIG1) of a vertically stacked array of memory cells (e.g., within sub-cell arrays 101-2 of FIG1) according to some embodiments of the present disclosure. Figure 2 As shown, the first and second source / drain regions 221 and 223 can be impurity-doped regions of the lateral access device 230 (e.g., a transistor). The first and second source / drain regions can be separated by a channel region 225 formed in the body of the semiconductor material (e.g., the body region of the lateral access device 230 (e.g., a transistor)). The first and second source / drain regions 221 and 223 can be formed by n-type or p-type dopants doped in the body region. However, the embodiments are not limited thereto.

[0051] For example, in an n-type conductive transistor configuration, the body region of the lateral access device 230 (e.g., a transistor) may be formed of a lightly doped p-type (p-) semiconductor material. In one embodiment, the body region and channel region 225 separating the first and second source / drain regions 221 and 223 may comprise a lightly doped p-type (e.g., low dopant concentration (p-)) polysilicon (Si) material composed of boron (B) atoms as impurity dopants to the polysilicon. The first and second source / drain regions 221 and 223 may also comprise metals and / or metal composites formed using an atomic layer deposition process, containing ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), a highly doped degenerate semiconductor material, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2- x Sn x At least one of O3). However, the embodiments are not limited to these examples. As used herein, degenerate semiconductor materials are intended to mean semiconductor materials containing high doping levels and significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.), such as polycrystalline silicon. In contrast, non-degenerate semiconductors contain moderate doping levels, where dopant atoms are well separated from each other in the semiconductor host lattice and their interactions are negligible.

[0052] In this example, the first and second source / drain regions 221 and 223 may contain highly doped, n-type conductive impurities (e.g., highly doped (n+)) doped in the first and second source / drain regions 221 and 223. In some embodiments, the highly doped, n-type conductive first and second drain regions 221 and 223 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the horizontally oriented access device 230 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurity (e.g., dopant) will be reversed.

[0053] like Figure 2 As shown, the first and second source / drain regions 221 and 223 may be impurity-doped regions of the lateral access device 230 (e.g., a transistor). The first and second source / drain regions may be separated by a channel region 225 formed in the body of the semiconductor material (e.g., the body region of the lateral access device 230 (e.g., a transistor)). The first and second source / drain regions 221 and 223 may be formed by n-type or p-type dopants doped in the body region. However, the embodiments are not limited thereto.

[0054] The first source / drain region 221 may occupy the upper portion of the body of the lateral access device 230 (e.g., a transistor). For example, the first source / drain region 221 may have a bottom surface within the body of the lateral access device 230, the bottom surface being positioned vertically higher than the bottom surface of the body of the lateral access device 230 in a third direction (D3) 211. Therefore, the lateral access device 230 may have a body portion located below the first source / drain region 221 and in electrical contact with the body contacts. Furthermore, as... Figure 2 As shown in the example embodiments, access lines, such as 207 (similar to access lines 107-1, 107-2, ..., 107-P shown in Figure 1), can be disposed on the top surface opposite to and connected to the channel region 225, separated from the channel region 225 by the gate dielectric material 204. The gate dielectric material 204 can be, for example, a high-k dielectric material, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The embodiments are not limited thereto. For example, in the high-k dielectric material example, the gate dielectric material 204 may comprise one or more of the following: hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobium iron ore, etc.

[0055] like Figure 2 As shown in the example embodiment, a digital line, such as 203-1 (similar to digital lines 103-1, 103-2, ..., 103-Q in Figure 1), may extend vertically along a third direction (D3) 211 adjacent to the sidewall of a first source / drain region 221 in the body of a horizontally oriented access device 230 (e.g., a transistor), the body being horizontally conductive between the first and second source / drain regions 221 and 223 along a second direction (D2) 205. In this embodiment, the vertically oriented digital line 203-1 is symmetrically formed, vertically aligned with and electrically contacting the first source / drain region 221. The digital line 203-1 may be formed to contact an insulating material such that there are no body contacts within the channel region 225.

[0056] like Figure 2As shown in the example embodiment, digital line 203-1 may be symmetrically formed within the first source / drain region 221, such that the first source / drain region 221 surrounds the digital line 203-1. The first source / drain region 221 may occupy the upper portion of the body of the lateral access device 230 (e.g., a transistor). For example, the first source / drain region 221 may have a bottom surface within the body of the lateral access device 230, the bottom surface being positioned vertically above the bottom surface of the body of the lateral access device 230 in a third direction (D3) 211. Thus, the lateral access device 230 may have a body portion located below the first source / drain region 221 and in contact with the body contacts. An insulating material may fill the body contacts so that the first source / drain region 221 is not electrically in contact with the channel region 225. Furthermore, as Figure 2 As shown in the example embodiments, access lines, such as 207 (similar to access lines 107-1, 107-2, ..., 107-P shown in Figure 1), may be disposed around and connected to the channel region 225, and separated from the channel region 225 by the gate dielectric 204.

[0057] Although the digital line 203-1 is described above as being symmetrically formed within the first source / drain region 221 such that the first source / drain region 221 surrounds the digital line 203-1, the embodiments are not limited thereto. For example, in some instances, the digital line 203-1 may be formed asymmetrically. In this embodiment, the vertically oriented digital line is asymmetrically formed adjacent to the first source / drain region 221, making electrical contact with the first source / drain region 221. The digital line may be asymmetrically formed to reserve space for the main contact in the channel region 225.

[0058] Figure 3 This describes a portion of a vertical 3D memory array according to several embodiments of the present disclosure. Figure 3 It includes a first conductive material 377, a Si material 332, a photolithography mask material (e.g., a mask material) 335, an interlayer dielectric (ILD) filling material 367, a second conductive material 370, a metal material 372, a first dielectric material 339, a second dielectric material 333, a second interlayer dielectric material 342, and multiple memory nodes (e.g., capacitors) 374.

[0059] Figure 3 Explanation based on Figures 4 to 13 This is part of a vertical 3D memory array formed by the process described herein, as further described herein. The 3D memory array may comprise a vertically stacked array of memory cells with multiple layers. Each of the multiple layers may comprise horizontally oriented access devices and memory nodes.

[0060] Each memory node may include a horizontally oriented access device having a first source / drain region and a second source / drain region separated by a channel region, and a gate on a gate dielectric material. The array may further include horizontally oriented access lines formed to the gates of the horizontally oriented access devices. The horizontally oriented access lines may be gate-all-around (GAA) structures. The memory node may further include a horizontally oriented memory node electrically connected to the second source / drain region of the horizontally oriented access device.

[0061] The horizontal access device of the vertical 3D memory array may include a second dielectric material 333, a first dielectric material 377, a first dielectric material 339, and an ILD filling material 367. The access device may be connected to a plurality of memory nodes 374. In some embodiments, the plurality of memory nodes 374 may be double-sided capacitors. The access device can be used to transfer current between the metal material 372 and the plurality of memory nodes 374.

[0062] Further included in the vertical 3D memory array is the epitaxial formation of vertical digital lines for the first source / drain region connected to a horizontally oriented access device. This document further describes the apparatus and method for forming epitaxially grown vertical digital lines.

[0063] Figure 4 This is a cross-sectional view at a stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, as illustrated in, for example, Figures 1 to 3, according to several embodiments of the present disclosure.

[0064] exist Figure 4 In the example embodiments shown in the examples, the method includes forming alternating layers of silicon germanium (SiGe) materials 430-1, 430-2, ..., 430-N (collectively referred to as silicon germanium (SiGe) 430) and silicon (Si) materials 432-1, 432-2, ..., 432-N (collectively referred to as epitaxially grown single-crystal silicon (Si) material 432) in repeated iterations to form a vertical stack 402 on the working surface of the semiconductor substrate 400. In one embodiment, silicon germanium (SiGe) 430 may be deposited on dielectric 431 to have a thickness in the range of five (5) nm to thirty (30) nm, for example, a vertical height in a third direction (D3). In one embodiment, silicon material 432 may be deposited to have a thickness (t2) in the range of thirty (30) nanometers (nm) to sixty (60) nm, for example, a vertical height. However, the embodiments are not limited to these examples. Figure 4 As shown, the vertical direction 411 is described as the third direction (D3), such as the z direction in the xyz coordinate system, similar to the third direction (D3) in the first, second and third directions shown in Figures 1 and 2.

[0065] In some embodiments, silicon-germanium (SiGe) 430-1, 430-2, ..., 430-N may be a mixture of silicon and germanium. For example, but not limited to, silicon-germanium (SiGe) 430 may be grown epitaxially on dielectric 431. Embodiments are not limited to these examples. In some embodiments, single-crystal silicon (Si) materials 432-1, 432-2, ..., 432-N may include polycrystalline and / or amorphous silicon (Si) materials. Single-crystal silicon (Si) materials 432-1, 432-2, ..., 432-N may be lightly doped p-type (p-) epitaxially grown single-crystal silicon (Si) materials. Silicon materials 432-1, 432-2, ..., 432-N may also be epitaxially grown on silicon-germanium (SiGe) 430. After the epitaxially grown silicon-germanium (SiGe) 430 has been formed, the seed crystal is converted to pure silicon. However, embodiments are not limited to these examples.

[0066] In semiconductor manufacturing equipment, alternating layers of silicon germanium (SiGe) 430-1, 430-2, ..., 430-N and epitaxially grown single-crystal silicon (Si) material 432-1, 432-2, ..., 432-N can be deposited in repeated iterations using semiconductor manufacturing processes such as chemical vapor deposition (CVD). However, the embodiments are not limited to this example, and other suitable semiconductor manufacturing techniques can be used to deposit alternating layers of epitaxially grown silicon germanium (SiGe) and epitaxially grown single-crystal silicon (Si) material in repeated iterations to form a vertical stack 402.

[0067] Layers can be repeatedly iterated vertically. Figure 4 In the example, N+1 layers of repeated iterations are shown, numbered 1, 2, 3, N, and N+1. For example, in another repeated iteration, the stack may include: a first silicon germanium (SiGe) 430-1, a first Si material 432-1, a second SiGe material 430-2, a second Si material 432-2, a third SiGe material 430-3, and a Si material 432-3. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0068] Figures 5A to 5B This invention describes an example method at a stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, as illustrated in Figures 1 to 3, according to several embodiments of the present disclosure.

[0069] Figure 5A This illustrates a top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments. Figure 5AIn the example embodiment shown in the examples, the method includes forming a plurality of first vertical openings 515 through a vertically stacked substrate using an etchant process, having a first horizontal direction (D1) 509 and a second horizontal direction (D2) 505. In one example, such as Figure 5A As shown, a plurality of first vertical openings 515 extend primarily in the second horizontal direction (D2) 505 and may form elongated vertical pillars 513-1, 513-2, ..., 513-M (collectively and / or independently referred to as 513), wherein sidewalls 514 are in a vertical stack. Photolithography can be used to form the plurality of first vertical openings 500 to pattern a photomask 535 on the vertical stack prior to etching the plurality of first vertical openings 515 to, for example, form a hard mask (HM). Similar semiconductor process techniques may be used at other points in the semiconductor manufacturing process described herein.

[0070] Figure 5B It is along Figure 5A The cross-sectional view taken by the cutting line A-A' in the image shows another view of the semiconductor structure at a specific point in the semiconductor manufacturing process. Figure 5B The cross-sectional view shown illustrates alternating layers of silicon germanium (SiGe) 530 and silicon (Si) material 532 repeatedly iterating on the semiconductor substrate 500 to form a vertical stack, for example... Figure 4 The 402 error is shown in the image.

[0071] like Figure 5B As shown, multiple first vertical openings can be formed through layers within a vertically stacked memory cell to expose the vertical sidewalls in the vertical stack and to form elongated vertical pillars 513, which are then filled with a first dielectric material 539. Vertical openings can be formed through repeated iterations of silicon-germanium (SiGe) 530 and silicon (Si) material 532.

[0072] A vertical opening may be formed to expose the vertical sidewalls in the vertical stack. The vertical opening may extend in the second horizontal direction (D2) 505 to form an elongated vertical column with a first vertical sidewall in the vertical stack and then be filled with dielectric material 539.

[0073] like Figure 5BAs shown, a first dielectric material 539 (e.g., an oxide or other suitable spin dielectric (SOD)) can be deposited in the vertical openings using a process such as CVD to fill the vertical openings. The first dielectric material 539 can also be formed from silicon nitride (Si3N4) material. In another example, the first dielectric material 539 may comprise silicon oxynitride (SiOxNy) and / or combinations thereof. Embodiments are not limited to these examples. Photolithography techniques can be used to form a plurality of first vertical openings to pattern a photomask 535 on a vertical stack prior to etching the plurality of first vertical openings to, for example, form a hard mask (HM). In one embodiment, the hard mask 535 may be deposited on silicon germanium (SiGe) 530. Similar semiconductor process techniques can be used at other points in the semiconductor manufacturing processes described herein.

[0074] Figures 6A to 6C This describes an example method at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure. Figure 6A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments.

[0075] exist Figure 6A In an example embodiment, the method includes using a photolithography process to pattern a photomask 635. The photomask 635 can be used to form a plurality of second vertical openings 670.

[0076] For example, a semiconductor manufacturing process may include using an etchant process to form a plurality of second vertical openings 670, extending primarily in a first direction (D1) 609 through a vertical stack by patterning and selectively removing silicon (Si) 632 and silicon germanium (SiGe) 630 materials in the plurality of second vertical openings 670 to expose second vertical sidewalls adjacent to first regions (e.g., access device regions) of Si and SiGe materials 632 and 630.

[0077] The semiconductor manufacturing process may further include a first source / drain region doped with Si material 632. That is, a first Si material 632-1, a second Si material 632-2, a third Si material 632-3 may be doped, and then iteratively repeated. For example, the first source / drain region may be formed by vapor-doping a dopant into a side surface portion of the Si material 632. In some embodiments, the source / drain region may be a first source / drain region that will be connected to a digital line connection. In one example, vapor-phase doping may be used to achieve high isotropy (e.g., non-directional doping) to form the first source / drain region of a horizontally oriented access device. In another example, thermal annealing using a dopant gas (e.g., phosphorus (P)) may be used in conjunction with high-energy plasma-assisted bonding to disconnect the junction. However, the embodiments are not limited thereto and other suitable semiconductor manufacturing techniques may be utilized.

[0078] Figure 6B Explanation along Figure 6A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 6B The cross-sectional view shown in the figure illustrates the repeated iterations of alternating layers of silicon germanium (SiGe) 630 and silicon (Si) material 632 on semiconductor substrate 600.

[0079] like Figure 6A As mentioned above, the semiconductor manufacturing process may include forming a second vertical opening 670 through layers within a vertically stacked memory cell (e.g., Figure 6A (As described in the text) to expose the vertical sidewalls in the vertical stack 402, as Figure 4 As shown in the figure. The vertical opening 670 may extend primarily in the first horizontal direction (D1) 609.

[0080] like Figure 6C As shown, the semiconductor manufacturing process may further include selectively isotropically etching silicon germanium (SiGe) 630 to form a plurality of first horizontal openings in a first region of the layer separating Si material 632. The etching process may be a timed, selective etching process that also reduces (e.g., "thins") the vertical thickness (vt) or vertical height of each of the silicon (Si) 632 layers extending in a third direction (D3) 611. An etchant may be allowed to flow into the second vertical opening 631 to selectively etch a portion of the epitaxially grown silicon germanium (SiGe) 630 inside and outside the stack. Thus, the etchant may target the first silicon germanium (SiGe) 630-1, the second silicon germanium (SiGe) 630-2, and the third silicon germanium (SiGe) 630-3 within the stack. The timed, selective etchant process may etch the silicon germanium (SiGe) 630 to completely remove the SiGe 630 material extending a first length (L1) from the second vertical opening 670 to form a plurality of first horizontal openings 673. As a result of the etchant process, the vertical thickness of the Si material 632 layer (e.g., in the third direction (D3)) appears.

[0081] Selective etchant processes may include selective etch chemicals such as phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or the use of selective solvents to dissolve silicon germanium (SiGe) 630, as well as other possible etch chemicals or solvents. Alternatively or additionally, selective etching for removing silicon germanium (SiGe) 630 may consist of one or more etch chemicals selected from aqueous etch chemicals, semi-aqueous etch chemicals, vapor etch chemicals, or plasma etch chemicals, as well as other possible selective etch chemicals. For example, dry etch chemicals using oxygen (O2) or O2 and sulfur dioxide (SO2) may be used. As another example, dry etch chemicals using O2 or O2 and nitrogen (N2) may be used to selectively etch silicon germanium (SiGe) 630.

[0082] The silicon-germanium (SiGe) 630 has now been selectively and isotropically etched to form a plurality of first horizontal openings 673 in a first region of the layer separating the Si material 632.

[0083] like Figure 6C As shown, a second dielectric material 633 may be conformally deposited around the first horizontal opening 673. The second dielectric material 633 may be deposited completely around the exposed surfaces in the plurality of first horizontal openings 673. The second dielectric material 633 may serve as a pad around the plurality of first horizontal openings 673. The second dielectric material 633 may flow into a vertical opening 631 to cover the exposed surfaces of the silicon (Si) material, wherein silicon germanium (SiGe) is removed to form the plurality of first horizontal openings 673 within the stack.

[0084] In one embodiment, the second dielectric material 633 may comprise a nitride material. In another embodiment, the second dielectric material 633 may comprise a silicon nitride (Si3N4) material (also referred to herein as “SiN”). In another embodiment, the second dielectric material 633 may comprise a silicon dioxide (SiO2) material. In yet another embodiment, the second dielectric material 633 may comprise a silicon oxycarbide (SiOxCy) material and / or a combination thereof. Embodiments are not limited to these examples.

[0085] In one embodiment, the second dielectric material 633 may be conformally deposited around the exposed surface in a plurality of first horizontal openings 673 to have a thickness (t1) of approximately 100 to 300 angstroms (Å). However, the embodiments are not limited to these examples.

[0086] exist Figure 6CIn an exemplary embodiment, the semiconductor manufacturing process may further include depositing another selectively etchable dielectric material (e.g., a first dielectric material 639) to fill a plurality of first horizontal openings 673. For example, on the exposed surface of the second dielectric material 633, the first dielectric material 639 (e.g., an oxide or other suitable spin-on dielectric (SOD)) is deposited into the plurality of first horizontal openings 673 to fill the first horizontal openings 673. The first dielectric material 639 may completely fill the plurality of first horizontal openings 673. The first dielectric material 639 may flow into a vertical opening 631 to fill the vertical opening 631 and fill the plurality of first horizontal openings 673 within the stack. Thus, the first dielectric material 639 may fill the first horizontal openings 673 within the first silicon-germanium (SiGe) 630-1, the second silicon-germanium (SiGe) 630-2, and the third silicon-germanium (SiGe) 630-3 within the stack.

[0087] The semiconductor manufacturing process may further include selectively etching a second length (L2) of a second dielectric material 633 from a second vertical opening 670 within a plurality of first horizontal openings 673. An etchant may be allowed to flow into the second vertical opening 670 to selectively etch a portion of the second length (L2) of the second dielectric material 633 from the second vertical opening 670 within the stack. Thus, the etchant can target the second dielectric material 633 within the stack. A selective etchant process can etch the second length L2 of the second dielectric material 633. Any selective etchant chemical described herein or otherwise may be used in this selective etchant process.

[0088] Figure 6C Explanation along Figure 6A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of the present disclosure. Figure 6C The cross-sectional view shown is illustrated by the axis of repeated iterations along the second horizontal direction (D2) 605 in the plane of the page, which extends left and right along the second horizontal direction (D2) 605.

[0089] exist Figure 6C In the illustration, the first dielectric material 639 is shown as vertically spaced extending along a first horizontal direction (D1) 609 of a three-dimensional array of vertically oriented memory cells, extending into and out of the page plane. Repeated iterations of alternating layers of the first dielectric material 639 are shown at the left end of the page.

[0090] A first conductive material 667 may be deposited in the second vertical opening 670 to fill the first horizontal opening 673. The first conductive material 667 may be formed on the gate dielectric material 642.

[0091] Therefore, the semiconductor manufacturing process may further include first conformally depositing a gate dielectric material 642 to form a gate dielectric material on an exposed surface of the Si material 632 with a reduced vertical thickness (vt). For example, the gate dielectric material 642 may be formed on the exposed surface of the Si material 632 to form a horizontal access device. In some embodiments, the gate dielectric material may be an oxide material 642. In other embodiments, the gate dielectric material 642 may be a high dielectric constant (K) composite material (high K dielectric material) with a dielectric constant (K) of nine (9) or greater. The embodiments are not limited thereto. The gate dielectric material 642 may be conformally deposited completely around each surface of the Si material 632 to form a gate all around (GAA) gate structure at the channel of the access device region.

[0092] Gate dielectric material 642 can be deposited on the exposed surface of Si material 632 using atomic layer deposition (ALD). In some embodiments, the gate dielectric material may be an oxide material. Oxide material or other high-k dielectric material 642 can be selectively deposited on the exposed surface of Si material 632 using ALD. A thermal oxidation process can be used to densify the ALD-deposited dielectric material 642. The thermal oxidation process involves forming an oxide material from a mixed oxide material. The mixed oxide material may combine low-temperature oxide materials with high-temperature oxide materials.

[0093] In a semiconductor manufacturing process, a first conductive material 667 may be deposited on a gate dielectric material 642. The first conductive material 667 may be deposited around a Si material 632, such that the first conductive material 667 has a top above the Si material 632 and a bottom below the Si material 632 to form a gate all-around (GAA) gate structure in the channel of the access device region. The first conductive material 667 may be conformally deposited into a vertical opening 670 and fill a continuous second horizontal opening 643 up to the unetched portion of the oxide material 642, the first dielectric material 639, and the second dielectric material 633. The first conductive material 667 may be conformally deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes.

[0094] In some embodiments, the first conductive material 667 may include one or more of the following: doped semiconductors, such as doped silicon, doped germanium, etc.; conductive metal nitrides, such as titanium nitride, tantalum nitride, etc.; metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.); and / or metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.); and / or some other combination thereof. The first conductive material 667 wound with the gate dielectric material may form a horizontally oriented access line (also referred to as a word line) opposite to the channel region of the epitaxially grown single-crystal silicon (Si) material.

[0095] like Figure 6C As shown, the first conductive material 667 may be recessed into the channel region. For example, the first conductive material 667 formed on the gate dielectric material 642 may be recessed and etched away from the third vertical opening 670. In some embodiments, an atomic layer etching (ALE) process may be used to etch the first conductive material 667. In some embodiments, an isotropic etching process may be used to etch the first conductive material 667. The first conductive material 667 may be selectively etched to keep the oxide material 642 covering the Si material 632 and the first dielectric material 639 intact. The first conductive material 667 may be selectively etched in a second direction from the third vertical opening 670 to a third distance (DIST3) in the range of twenty (20) to fifty (50) nanometers (nm) in a series of second horizontal openings. The first conductive material 667 may be selectively etched around the Si material 632 into a series of second horizontal openings extending in a first horizontal direction.

[0096] A first conductive material 667 may be deposited completely around each surface of the Si material 632 on the gate dielectric material 642 to form a gate all-around (GAA) gate structure in the channel of the access device region. The first conductive material 667 may fill the space adjacent to the bridging Si material 632. Thus, the Si material 632 may be surrounded by the first conductive material 667 formed on the gate dielectric material 642.

[0097] Figures 7A to 7C This describes an example method, according to several embodiments of the present disclosure, at another stage of a semiconductor manufacturing process for forming digital lines in, for example, a vertical three-dimensional (3D) memory illustrated in Figures 1 to 3. Figure 7A This describes a top view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process, according to one or more embodiments.

[0098] exist Figure 7A In an example embodiment, the second vertical opening may be filled with another selectively etchable dielectric material 767 (such as...). Figure 7C (As shown in the illustration). In some instances, the selectively etchable dielectric 767 can be a nitride cap. The dielectric 767 can have a thickness greater than a threshold thickness. For example, the threshold thickness can be 90 nanometers (nm), and the thickness of the dielectric 767 can be 100 nm, but the examples disclosed herein are not limited to this. The thickness can be used to fill gaps between stacked layers. The thickness of the nitride cap can help control the thickness between contacts of the epitaxially grown Si material, as further described herein.

[0099] In some embodiments, the selectively etchable dielectric material may be... Figure 6C The second dielectric material 633 shown is the same dielectric material. Figure 7AIn one example embodiment, another photomask may be used to form the third vertical opening 751. The third vertical opening 751 is formed using a photolithographic etchant process through a vertical stack and extends primarily in the first horizontal direction (D1) 709.

[0100] Figure 7B Explanation along Figure 7A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure.

[0101] like Figure 7B As shown, the vertical direction 711 is described as the third direction (D3), such as the z-direction in the xyz coordinate system, similar to the third direction (D3) 711 in the first, second, and third directions shown in Figures 1 to 3. The plane of the page extends to the right and left, on the first direction (D1) 709.

[0102] exist Figure 7B In an example embodiment, the first electrode 761 (e.g., the bottom electrode to be connected to the source / drain region of the horizontal access device) and the second electrode 756 are described as being separated by a unit dielectric material 763 extending into and out of the page plane in a second direction (D2).

[0103] Figure 7C Explanation along Figure 7A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 7C The cross-sectional view shown is illustrated as extending left and right along the plane of the page in the second horizontal direction (D2) 705 along the axis of the sacrificial oxide material 738 and the Si material 732.

[0104] like Figure 7C As described herein, ILD filler material 767 may be deposited in vertical opening 770. ILD filler material 767 may be, for example, a capping nitride material. In some instances, capping nitride material may be conformally deposited in vertical opening 770. In some instances, capping nitride material may be deposited in vertical opening 770 to fill vertical opening 770.

[0105] The capping nitride material can be deposited to have a thickness greater than a threshold thickness. For example, the thickness of the capping nitride material can be 100 nanometers (nm). However, embodiments of this disclosure are not limited to a thickness of 100 nm. For example, the thickness of the capping nitride material can be greater than 100 nm or less than 100 nm. The capping nitride material can have a thickness greater than the threshold to fill any gaps between layers through the ends of the silicon material.

[0106] Figures 8A to 8C This describes an example method, according to several embodiments of the present disclosure, at another stage of a semiconductor manufacturing process for forming digital lines in, for example, a vertical three-dimensional (3D) memory illustrated in Figures 1 to 3. Figure 8A A top view illustrating a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments.

[0107] Figure 8A The method further illustrates the use of a photolithographic mask to reopen the second vertical opening 855 adjacent to the access device area. Figures 8A to 8C In this process, one or more selective etchant processes may be used to reopen the second vertical opening 851 in the access device region, which extends through the vertical stack and primarily in the first horizontal direction (D1) 809. One or more selective etchant processes reform the second vertical opening (e.g., a fourth vertical opening 851) to re-expose the sidewalls in repeated iterations of alternating layers of silicon (Si), first dielectric material 839, and dielectric material 867 in the first horizontal opening 863. Dielectric material 867 (e.g., the same dielectric material as the second dielectric material 833) may be retained to separate and isolate the recessed first conductive material 877.

[0108] Figure 8B Explanation along Figure 8A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8B The cross-sectional view shown is far from the multiple individual horizontal access lines 877. For example... Figure 8B As shown, the vertical direction 811 is described as the third direction (D3), such as the z-direction in the xyz coordinate system, similar to the third direction (D3) 811 in the first, second, and third directions shown in Figures 1 to 3. The plane of the page extends to the right and left, on the first direction (D1) 809.

[0109] Figure 8C Explanation along Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 8C The cross-sectional view shown is illustrated as a repeated iteration of alternating layers along the second electrode 856, extending left and right along the plane of the page in the second horizontal direction (D2) 805 along the axis of the horizontally oriented access device.

[0110] exist Figure 8CThe diagram illustrates the adjacent horizontal access line 877 adjacent to the second dielectric material 833, wherein a portion of the first conductive material 877 is located above the Si material 832 and a portion of the first conductive material 877 is located below the Si material 832, indicating the position disposed inward from the plane and orientation on the page.

[0111] The first and second source / drain regions can be formed by vapor-phase doping of a dopant in the side surface of the Si material 832 from the third horizontal opening to form a second source / drain region horizontally adjacent to the channel region. In some embodiments, the dielectric material 867 has been removed from the fourth vertical opening 855, but still fills the first horizontal opening 863 that separates the continuous first conductive material 877, extending in and out of the drawing plane, all the way to the unetched portion of the oxide material 839 and the fourth vertical opening 855.

[0112] Additionally, semiconductor manufacturing processes may include isotropically recessing the surrounding material from the Si material in three dimensions to control the gate-to-vertical digital line contact gate pitch. For example, as previously described... Figure 7C As mentioned, the capping nitride material can be conformally deposited in the vertical opening, and the capping nitride material can be three-dimensionally isotropically recessed using etching techniques. For example, the capping nitride material can be recessed in the D3 direction 811, the D2 direction 805, and the D1 direction (e.g., in and out of a page, such as...). Figure 8C (Direction in China).

[0113] Figures 9A to 9C This invention describes the epitaxial growth of Si material at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure, to form enlarged epitaxially grown Si material contacts. Figure 9A Explanation along Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 9A The cross-sectional view in the figure is shown as extending left and right along the plane of the page in the second horizontal direction (D2) 905. Figures 9A to 9C The method further illustrates the storage node, such as a horizontally oriented capacitor cell, formed in the third vertical opening. This cross-sectional view shows the completed horizontally oriented capacitor cell, which has a first electrode 961 (e.g., a bottom cell contact electrode), a cell dielectric 963, and a second electrode 956 (e.g., a top common node electrode) on a semiconductor substrate 900 to form a vertical stack.

[0114] At this stage, the semiconductor manufacturing process may include epitaxial growth of Si material from three-dimensional exposed Si material to form enlarged epitaxially grown Si material contacts 990. In some instances, the epitaxially grown Si material contacts 990 may be lightly doped, p-type (p-) epitaxially grown single-crystal Si material. In some instances, the epitaxially grown Si material contacts 990 may have gradient doping concentrations, as further described herein.

[0115] The epitaxially grown Si material contact 990 can be grown such that the epitaxially grown Si material contact 990 has a cross-sectional size larger than the original cross-sectional size of the Si material. For example, the epitaxially grown Si material contact 990 can be grown until it is larger than the Si material from which the epitaxially grown Si material contact 990 is grown. Compared to previous methods, growing the epitaxially grown Si material contact 990 can increase the contact area between the epitaxially grown Si material contact 990 and the digital line, while improving current conduction without current cutoff degradation, and increasing the contact-to-gate distance.

[0116] After epitaxially growing Si material from three-dimensional exposed Si material to form enlarged epitaxially grown Si material contacts 990, a horizontally oriented memory node can be formed. The horizontally oriented memory node (e.g., a capacitor cell) is illustrated as having been formed in this semiconductor manufacturing process, and shows a first electrode 961 (e.g., a bottom electrode to be connected to the source / drain region of the horizontal access device) and a second electrode 956 (e.g., a top electrode to be connected to a common electrode plane, such as a ground plane), separated by a cell dielectric 963. However, the embodiment is not limited to this example. In other embodiments, the first electrode 961 (e.g., a bottom electrode to be connected to the source / drain region of the horizontal access device) and the second electrode 956 (e.g., a top electrode to be connected to a common electrode plane, such as a ground plane), separated by a cell dielectric 963, can be formed after the first source / drain region, channel region, and second source / drain region are formed in a region of Si material 932, intended for positioning (e.g., placement formation) of the horizontally oriented access device.

[0117] exist Figure 9C In an example embodiment, a horizontally oriented memory node having a first electrode 961 (e.g., a bottom electrode) is connected to a second source / drain region of a horizontal access device. In some embodiments, the second source / drain region may be doped using vapor phase doping or other suitable doping techniques prior to forming the first electrode 961. A second electrode 956 (e.g., a top electrode) connected to a common electrode plane (e.g., a ground plane) is shown formed in a second horizontal opening 951 and separated from the first electrode 961 by a cell dielectric 963. The second electrode 956 may extend laterally in the drawing plane in a second direction (D2) 905, with a third vertical opening (e.g., a third vertical opening formed in the vertical stack) in the vertical stack. Figure 7B The first electrode 961 is 951) located at a third distance and can extend into the interior of the first electrode 961. In some embodiments, such as Figure 9C As shown, the second electrode 956 can be opposite the inner and outer surfaces of the first electrode 961 to form a double-sided storage node, such as a capacitor, as if separated by the orientation axis of the horizontal access device and the horizontal storage node of the vertically stacked memory cell array of the three-dimensional (3D) memory by the cell dielectric.

[0118] Figure 9B This invention describes an example method, according to several embodiments of the present disclosure, at another stage of a semiconductor manufacturing process for engraving Si material for epitaxial digital line growth in a vertical three-dimensional (3D) memory. Figure 9B Explanation along Figure 8A The cross-sectional view taken by the cutting line A-A' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 9B The cross-sectional view shown is illustrated as extending left and right along the plane of the drawing in the second horizontal direction (D2), while the vertical direction 911 is illustrated as the third direction (D3), such as the z-direction in the xyz coordinate system, similar to the third direction (D3) 911 among the first, second, and third directions shown in Figures 1 to 3. The plane of the drawing extends right and left along the first direction (D1) 909.

[0119] like Figure 9B As explained, the epitaxially grown Si material contacts 990 can be grown in a specific amount such that the epitaxially grown Si material contacts 990 are electrically isolated from each other. For example, the epitaxially grown Si material contacts 990 can be grown in a specific amount such that the cross-section of the epitaxially grown Si material contacts 990 is larger than the Si material grown from them, but they do not contact each other in the horizontal D1 direction 909 or the vertical D3 direction 911.

[0120] Figure 9C This describes an example method at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure. Figure 9C Explanation along again Figure 8A The cross-sectional view taken by the cutting line B-B' in the figure shows another view of the semiconductor structure at this particular point in an example semiconductor manufacturing process of an embodiment of this disclosure. Figure 9C The cross-sectional view shown is illustrated as a repeated iteration of alternating layers along the second electrode 956 extending left and right along the plane of the page in the second horizontal direction (D2) 905 along the axis of the horizontally oriented access device, and the horizontally oriented storage nodes (e.g., capacitor cells) can be formed within layers of epitaxially grown single-crystal silicon (Si) material 932.

[0121] As previously combined Figure 9A The semiconductor manufacturing process may include epitaxially growing Si material from three-dimensional exposed Si material to form enlarged epitaxially grown Si material contacts 990. In some instances, the epitaxially grown Si material contacts 990 may have a gradient doping concentration. For example, the epitaxially grown Si material contacts 990 may include a doping concentration that increases outward from the Si material.

[0122] To achieve a gradient doping concentration at the 990 contact point of the epitaxially grown Si material, the semiconductor manufacturing process may include epitaxially growing Si material by growing a multilayer of Si material from a three-dimensional exposed Si material.

[0123] For example, a semiconductor manufacturing process may include epitaxially growing a first layer 996 of Si material having a first thickness. The first layer 996 may be epitaxially grown to have a first thickness between 5 nm and 20 nm. The first layer 996 of Si material may have a first doping concentration. For example, the first layer 996 of Si material may be undoped epitaxially grown Si material.

[0124] Furthermore, the semiconductor manufacturing process may further include epitaxially growing a second layer 998 of Si material having a second thickness. For example, the second layer 998 may have a thickness less than that of the first layer 996 and may be used to control the gate-to-vertical digital line contact spacing. The second layer 998 may be epitaxially grown to have a second thickness between 0 nm and 20 nm. The second layer 998 of Si material may have a second doping concentration different from the first doping concentration of the first layer 996. For example, the second layer 998 may contain 1e 18 cm -3 With 5e 21 cm -3 The doping concentration between the two layers. The second 998 layer can be phosphorus-doped epitaxially grown Si material.

[0125] Figures 10A to 10B This invention describes the formation of a plurality of spaced vertical pillars having a plurality of spaced vertical openings between them at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory, according to several embodiments of the present disclosure. Figure 10A This illustrates a cross-sectional view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 10A The cross-sectional view is illustrated as extending from left to right in the plane of the page along the second horizontal direction (D2) 1005.

[0126] After epitaxially growing the Si material contact 1090, the semiconductor manufacturing process may include forming a plurality of spaced vertical pillars with a plurality of spaced vertical openings between them in the vertical opening 1055. The epitaxially grown Si material contact 1090 may ultimately be located between the plurality of spaced vertical pillars, as further described herein.

[0127] To form multiple spaced vertical pillars, dielectric material 1088 can be deposited into vertical openings 1055 to fill them. For example, dielectric material 1088 can fill vertical openings 1055 all the way to the top of the stack.

[0128] Figure 10B This illustrates a cross-sectional view of a semiconductor structure at a specific point in time during a semiconductor manufacturing process according to one or more embodiments. Figure 10B The cross-sectional view is illustrated as extending in the first horizontal direction (D1) 1009 and the vertical direction (D3) 1011. Figure 10B In the cross-sectional view, dielectric material 1088 is located in the vertical opening 1055.

[0129] The semiconductor manufacturing process may further include patterning the mask 1083 on the top surface of the vertically stacked structure. For example, the photolithography mask 1083 may be patterned using photolithography techniques to form a hard mask on the top of the vertically stacked structure.

[0130] Figure 11 This invention describes how, according to several embodiments of the present disclosure, a plurality of spaced vertical openings 1199 are formed at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory. Figure 11 The cross-sectional view is illustrated as extending in the first horizontal direction (D1) 1009 and the vertical direction (D3) 1011. Figure 11 In the cross-sectional view, the mask 1183 is patterned on top of the vertically stacked mask.

[0131] To form a plurality of spaced vertical pillars 1197, a semiconductor manufacturing process may include selectively removing portions of dielectric material 1188 from vertical openings to form a plurality of spaced vertical openings 1199. The plurality of spaced vertical openings 1199 are located between the plurality of spaced vertical pillars 1197. For example, an etchant process may be used to selectively remove portions of dielectric material 1188 by etching to form the plurality of spaced vertical openings 1199, thereby forming the plurality of spaced vertical pillars 1197.

[0132] The etchant process may include selective etching chemicals such as phosphoric acid (H3PO4) or hydrogen fluoride (HF) and / or the use of selective solvents and other possible etch chemicals or solvents to dissolve the dielectric material 1188. Alternatively or additionally, selective etching for selectively removing portions of the dielectric material 1188 may consist of one or more etch chemicals selected from aqueous etch chemicals, semi-aqueous etch chemicals, vapor etch chemicals, or plasma etch chemicals and other possible selective etch chemicals. For example, a dry etch chemical of oxygen (O2) or O2 and sulfur dioxide (SO2) may be used. As another example, a dry etch chemical of O2 or O2 and nitrogen (N2) may be used.

[0133] Selectively removing a portion of the dielectric material 1188 can expose the expanded epitaxially grown Si material contact 1190. For example, the expanded epitaxially grown Si material contact 1190 can be exposed in a plurality of spaced vertical openings 1199 and located between a plurality of spaced vertical posts 1197.

[0134] Figure 12 This invention describes how, according to several embodiments of the present disclosure, multiple spaced multilayer vertical digital lines are formed at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory. Figure 12 The cross-sectional view is illustrated as extending in the first horizontal direction (D1) 1009 and the vertical direction (D3) 1011. Figure 12 In the cross-sectional view, conductive material is deposited in multiple spaced vertical openings.

[0135] Once multiple vertical openings are formed, the semiconductor manufacturing process can include depositing conductive material between multiple spaced vertical pillars to form multiple spaced vertical digital lines 1292 electrically connected to a first source / drain region. The conductive material can be deposited in the multiple spaced vertical openings such that the conductive material is formed around an expanded epitaxial growth Si material contact 1290 in each of the multiple spaced vertical openings. The conductive material can be, for example, titanium or titanium nitride. The multiple spaced vertical digital lines 1292 are separated from each other by multiple spaced vertical pillars 1297. The multiple spaced vertical digital lines 1292 can be used with vertical openings having a high aspect ratio, such as a 5:1 vertical / horizontal aspect ratio specification, or even higher.

[0136] Figure 13 This invention describes how, according to several embodiments of the present disclosure, multiple spaced multilayer vertical digital lines are formed at another stage of a semiconductor manufacturing process for forming digital lines in a vertical three-dimensional (3D) memory. Figure 13 The cross-sectional view shown is illustrated as an axis of repeated iterations along the alternating layers of the second electrode 1356 extending laterally along the plane of the page in the second horizontal direction (D2) 805. Figure 13In this process, the dielectric material deposited in the vertical opening 1355 has been selectively removed to form a plurality of spaced vertical pillars and a plurality of spaced vertical openings located between the plurality of spaced vertical pillars.

[0137] In some instances, semiconductor manufacturing processes may involve forming multiple layers of vertical digital lines. For example, a digital line may include a first layer of 1394 and a second layer of 1395, as further described herein.

[0138] Semiconductor manufacturing processes may include depositing a first layer 1394 of material in multiple spaced vertical openings. The first layer 1394 of material may contact epitaxially grown Si material contacts 1390. In some instances, the first layer 1394 of material may contact epitaxially grown Si material contacts 1390 that can be gradient-doped, as previously described. Figure 9C describe.

[0139] The first layer 1394 can be conformally deposited in multiple spaced vertical openings. The first layer 1394 can be conformally deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or other suitable deposition processes. In some instances, the first layer 1394 can be a doped polycrystalline silicon material.

[0140] The second layer 1395 can then be deposited into multiple spaced vertical openings. The second layer 1395 can be deposited into the multiple spaced vertical openings all the way to the top of the vertical stack and fill the multiple spaced vertical openings. In some instances, the second layer 1395 can be titanium nitride (TiN) material.

[0141] Therefore, the digital line formation in the vertical 3D memory according to this disclosure allows for increased utilization of the contact junction surface area. Epitaxial growth of Si material to form enlarged Si material contacts provides a larger surface area for the contact junction between the digital line and the source / drain regions, and increases the contact-to-gate distance between the gate and the digital line, thereby improving current conduction distribution.

[0142] Figure 14 This is a block diagram of a device in the form of a computing system 1400 including a memory device 1403, according to several embodiments of the present disclosure. As used herein, for example, the memory device 1403, the memory array 1410, and / or the host 1402 may also be individually considered as a "device". According to embodiments, the memory device 1403 may include at least one memory array 1410, wherein, according to the embodiments described herein, the memory cells are formed with digital lines and body contacts.

[0143] In this example, system 1400 includes a host 1402 connected to memory device 1403 via interface 1404. The computing system 1400 may be a personal laptop computer, desktop computer, digital camera, mobile phone, memory card reader, or device with Internet of Things (IoT) capabilities, as well as various other types of systems. Host 1402 may include several processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry) capable of accessing memory 1403. System 1400 may include a separate integrated circuit, or both host 1402 and memory device 1403 may be on the same integrated circuit. For example, host 1402 may be a system controller for a memory system including multiple memory devices 1403, wherein system controller 1402 provides access to the respective memory devices 1403 through another processing resource, such as a central processing unit (CPU).

[0144] exist Figure 14 In the example shown, host 1402 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., from memory device 1403 via controller 1402). The OS and / or various applications can be loaded from memory device 1403 by providing access commands from host 1402 to memory device 1403 to access data including the OS and / or various applications. Host 1402 can also access data used by the OS and / or various applications by providing access commands to memory device 1403 to retrieve data used in the execution of the OS and / or various applications.

[0145] For clarity, system 1400 has been simplified to focus on features particularly relevant to this disclosure. Memory array 1410 may be a DRAM array, including at least one memory cell having digital lines and body contacts formed according to the techniques described herein. For example, memory array 1410 may be an unshielded DL 4F2 array, such as a 3D-DRAM memory array. Array 1410 may include memory cells arranged in rows connected by word lines (which may be referred to herein as access lines or select lines) and columns connected by digital lines (which may be referred to herein as sense lines or data lines). Although Figure 14 The illustration shows a single array 1410, but the embodiments are not limited thereto. For example, a memory device 1403 may include several arrays 1410 (e.g., several memory banks of DRAM cells).

[0146] Memory device 1403 includes address circuitry 1406 to latch address signals provided via interface 1404. For example, the interface may include a physical interface employing a suitable protocol (e.g., a data bus, address bus, and command bus, or a combined data / address / command bus). This protocol may be custom or proprietary, or interface 1404 may employ a standardized protocol, such as PCIe, Gen-Z, CCIX, or similar. Address signals are received and decoded by row decoder 1408 and column decoder 1412 to access memory array 1410. Data can be read from memory array 1410 by sensing voltage and / or current changes on a sensing line using sensing circuitry 1411. For example, sensing circuitry 1411 may include a sensing amplifier that can read and latch a page (e.g., a row) of data from memory array 1410. I / O circuitry 1407 can be used for bidirectional data communication with host 1402 via interface 1404. The read / write circuitry 1413 is used to write data to or read data from the memory array 1410. As an example, the circuitry 1413 may include various drivers, latching circuitry, etc.

[0147] The control circuitry system 1405 decodes signals provided by the host 1402. These signals may be commands provided by the host 1402. These signals may include chip enable signals, write enable signals, and address latch signals for controlling operations performed on the memory array 1410 (including data read operations, data write operations, and data erase operations). In various embodiments, the control circuitry system 1405 is responsible for executing instructions from the host 1402. The control circuitry system 1405 may include a state machine, a sequencer, and / or some other type of control circuitry system, which may be implemented in hardware, firmware, or software, or any combination thereof. In some instances, the host 1402 may be a controller external to the memory device 1403. For example, the host 1402 may be a memory controller connected to the processing resources of a computing device.

[0148] The term "semiconductor" can refer to, for example, a material, wafer, or substrate and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon supported by a substrate semiconductor structure, and other semiconductor structures. Furthermore, when reference to semiconductors has been made in the preceding description, prior process steps may have been used to form regions / junctions in the substrate semiconductor structure, and the term "semiconductor" may include an underlying material containing such regions / junctions.

[0149] The figures in this document follow a numbering convention, where the first few digits correspond to the figure number and the remaining digits identify the elements or components in the figure. Similar (e.g., identical) elements or components between different figures can be identified by using similar digits. It should be understood that the elements shown in the various embodiments herein may be added, interchanged, and / or eliminated to provide several additional embodiments of this disclosure. Furthermore, it should be understood that the scale and relative dimensions of the elements provided in the figures are intended to illustrate embodiments of this disclosure and should not be considered as intended to be limiting.

[0150] As used herein, “several” or “a certain number” of something may refer to one or more such things. For example, “several” or “a certain number” of memory cells may refer to one or more memory cells. “A certain number” of something means two or more. As used herein, performing multiple actions simultaneously means that the actions at least partially overlap within a specific time period. As used herein, the term “connection” may include electrical connections, direct connections and / or direct connections without intermediaries (e.g., through direct physical contact), indirect connections and / or connections with intermediaries or wireless connections. The term connection may further include two or more elements that cooperate or interact with each other (e.g., in a causal relationship). An element connected between two elements may be between and connected to each of the two elements.

[0151] It should be recognized that the term "vertical" takes into account variations relative to "fully" vertical caused by routine manufacturing, measurement, and / or assembly changes, and those skilled in the art should understand the meaning of the term "vertical." For example, vertical may correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element may cover the other element, may be on top of the other element, or may be transverse to the other element and / or may be in direct physical contact with the other element. For example, "transverse to" may refer to a horizontal direction that may be perpendicular to the z-direction (e.g., the y-direction or x-direction).

[0152] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of various embodiments of this disclosure. It should be understood that the above description has been carried out in an illustrative rather than restrictive manner. Those skilled in the art will understand, upon review of the above description, combinations of the above embodiments and other embodiments not explicitly described herein. The scope of the various embodiments of this disclosure includes other applications in which the above structures and methods are used. Therefore, the scope of the various embodiments of this disclosure should be determined with reference to the appended claims, together with the full scope of the equivalents granted thereto.

Claims

1. A method for forming a three-dimensional 3D memory, comprising: A vertical stack having alternating layers of silicon germanium (SiGe) and silicon (Si) is formed from a substrate. The vertical stack has a vertical stack memory cell having horizontally oriented access devices and horizontally oriented memory nodes. The horizontally oriented access devices have a gate, a channel region, a first source / drain region separated from the channel region, and a second source / drain region formed horizontally at different layer levels. A first vertical opening is formed through the vertical stack and extends primarily in the first horizontal direction to expose the first vertical sidewall in the stack; In the exposed first vertical sidewall, the surrounding material is three-dimensionally recessed from the Si material to create a three-dimensional exposed surface on the Si material; Si material is epitaxially grown from the three-dimensional exposed Si material to form an enlarged epitaxially grown Si material contact with a cross-sectional size larger than the original cross-sectional size of the Si material; A plurality of spaced vertical posts are formed between the Si material contacts in the first vertical opening; and Conductive material is deposited between the plurality of spaced vertical pillars to form a plurality of spaced vertical digital lines electrically connected to the first source / drain region in the first vertical opening.

2. The method of claim 1, wherein the method comprises epitaxially growing a specific amount of the Si material to form the enlarged Si material contacts such that the enlarged Si material contacts are electrically isolated from each other.

3. The method of claim 1, wherein the method comprises epitaxially growing the Si material to form the enlarged Si material contacts having a gradient doping concentration.

4. The method according to claim 1, wherein the method comprises: A first dielectric material is deposited in the first vertical opening to fill the first vertical opening; A patterned mask is applied to the top surface of the vertically stacked mask; and Selectively removing a portion of the first dielectric material in the first vertical opening to form a plurality of spaced vertical openings between the plurality of spaced vertical posts, wherein the selective removal of the portion of the first dielectric material exposes the enlarged Si material contacts in the plurality of spaced vertical openings.

5. The method of claim 4, wherein the method comprises depositing the conductive material in the plurality of spaced vertical openings to form the plurality of spaced vertical digital lines.

6. The method of claim 1, wherein epitaxial growth of the Si material comprises epitaxially growing a plurality of layers of Si material from the three-dimensional exposed Si material.

7. The method of claim 6, wherein epitaxially growing the plurality of layers of the Si material comprises: The first layer of the plurality of layers of the Si material is epitaxially grown to have a first thickness; and The second layer of the plurality of layers of the Si material is epitaxially grown to have a second thickness that is less than the first thickness of the first layer in order to control the gate-to-vertical digital line contact spacing distance.

8. The method of claim 7, wherein the method comprises epitaxially growing the first layer to have a first doping concentration and epitaxially growing the second layer to have a second doping concentration different from the first doping concentration.

9. The method of claim 7, wherein the method comprises: The first layer is epitaxially grown to have a thickness between 1 nanometer (nm) and 20 nm; and The second layer is epitaxially grown to have a thickness between 1 nm and 20 nm.

10. The method of claim 1, wherein forming the horizontally oriented access device and the horizontally oriented storage node at each level of the vertical stack comprises: Multiple second vertical openings with a first horizontal direction and a second horizontal direction are formed through the vertical stack. The second vertical openings extend mainly in the second horizontal direction to form slender vertical columns with first vertical sidewalls in the stack, separating memory cells on each level. The first source / drain region of the Si layer is doped at the second vertical opening; A first dielectric is deposited in the plurality of second vertical openings; and A third vertical opening is formed through the vertical stack and extends primarily in the first horizontal direction to expose the second vertical sidewall in the stack.

11. The method of claim 10, wherein forming the horizontally oriented access device and the horizontally oriented storage node at each level of the vertical stack further comprises: The silicon-germanium (SiGe) layer is selectively etched and the vertical thickness of the Si layer is reduced to form a plurality of first horizontal openings at a first length (L1) from the third vertical opening; A second dielectric material is conformally deposited on the exposed surfaces in the plurality of first horizontal openings; The second dielectric material is recessed to expose the first source / drain region; Deposit the first dielectric material to fill the plurality of first horizontal openings; The second dielectric material is selectively etched from the plurality of first horizontal openings to a second length (L2) from the second vertical opening; A gate dielectric material is formed on the exposed surface of the Si layer with reduced vertical thickness; A first conductive material is deposited on the Si layer to form a gate all-around (GAA) structure at the channel region of the access device. The first conductive material is recessed into the channel region; and The first horizontal opening is sealed with the second dielectric material.

12. A method for forming a three-dimensional 3D memory, comprising: A vertical stack having alternating layers of silicon germanium (SiGe) and silicon (Si) is formed from a substrate. The vertical stack has a vertical stack memory cell having horizontally oriented access devices and horizontally oriented memory nodes. The horizontally oriented access devices have a gate, a channel region, a first source / drain region separated from the channel region, and a second source / drain region formed horizontally at different layer levels. A first vertical opening is formed through the vertical stack and extends primarily in the first horizontal direction to expose the first vertical sidewall in the stack; In the exposed first vertical sidewall, the surrounding material is three-dimensionally recessed from the Si material to create a three-dimensional exposed surface on the Si material; Gradient-doped Si material is epitaxially grown from the three-dimensional exposed Si material to form an enlarged epitaxially grown Si material contact with a cross-sectional size larger than the original cross-sectional size of the Si material; Multiple spaced vertical columns are formed therebetween, with multiple spaced vertical openings therebetween, wherein the enlarged Si material contacts are located in the multiple spaced vertical openings; and Conductive material is deposited in the plurality of spaced vertical openings to form a plurality of spaced vertical digital lines electrically connected to the first source / drain region in the first vertical opening.

13. The method of claim 12, wherein the method comprises: A first dielectric material is deposited in the first vertical opening to fill the first vertical opening; A patterned mask is applied to the top surface of the vertically stacked mask; and Selectively remove a portion of the first dielectric material from the first vertical opening to form the plurality of spaced vertical openings between the plurality of spaced vertical posts.

14. A memory device comprising: A vertically stacked memory cell array, comprising a horizontally oriented access device and horizontally oriented memory nodes, wherein: The horizontally oriented access device includes a channel region, a first source / drain region separated from the channel region, a second source / drain region, and a gate on a gate dielectric material; and The horizontally oriented storage node is horizontally formed on the second source / drain region of the horizontally oriented access device; and A vertical digital line having gradient-doped expanded Si material contacts and conductive material deposited in multiple vertical openings, wherein the vertical digital line is connected to the first source / drain region of the horizontally oriented access device.

15. The memory device of claim 14, wherein the array includes a horizontally oriented access line formed to the gate of the horizontally oriented access device.

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