Semiconductor device and manufacturing method thereof

Abstract

A method of manufacturing a semiconductor device includes: alternately depositing sacrificial layers and channel layers over a substrate such that a second channel layer below a first channel layer is thinner than the first channel layer; patterning the semiconductor stack to form a fin; recessing the fin to form a source / drain opening; a semiconductor material is epitaxially deposited in the source / drain opening to form a source / drain structure. The method further comprises the following steps: removing the sacrificial layer to expose the surface of the channel layer; depositing a gate dielectric over a surface of the channel layer, and depositing a conductive material over the gate dielectric to form a gate electrode surrounding the channel layer; and depositing a conductive material over the source / drain structure in the source / drain opening to form a source / drain contact having a bottom surface lower than a bottom surface of the first channel layer. The embodiment of the invention also relates to a semiconductor device.

Description

Technical Field

[0001] This application relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] As the semiconductor industry advances towards nanometer-scale technology nodes, it faces significant manufacturing and design challenges driven by the need for higher device density, enhanced performance, and reduced costs. These challenges have led to the adoption of three-dimensional structures, such as multi-gate field-effect transistors (FETs), including FinFETs, Gate-All-Around FETs (GAA-FETs), forked-edge transistors, and complementary FETs (CFETs). For example, in a FinFET, the gate electrode is connected to three sides of the channel region, separated by a gate dielectric layer. This configuration effectively provides control over the current flowing through the channel because the gate surrounds three of the channel surfaces. However, the fourth side, forming the bottom of the channel, remains far from the gate electrode and therefore suffers from poor gate control. In contrast, GAA-FETs feature a gate electrode surrounding all sides of the channel region, enabling more comprehensive channel depletion and achieving reduced short-channel effects through a steeper subthreshold swing and lower drain-induced barrier reduction. As transistor sizes continue to shrink, further improvements to GAA-FET technology are needed to meet the growing demands of modern semiconductor devices. Summary of the Invention

[0003] One embodiment of this application provides a method for manufacturing a semiconductor device, comprising: alternately depositing a sacrificial layer and a channel layer to form a semiconductor stack over a substrate, wherein the channel layer includes a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; patterning the semiconductor stack to form fins; recessing the fins in a source / drain region to form source / drain openings; epitaxially depositing semiconductor material in the source / drain openings to form a source / drain structure; removing the sacrificial layer in a channel region adjacent to the source / drain region, thereby exposing the surface of the channel layer; depositing a gate dielectric above the surface of the channel layer and depositing a conductive material above the gate dielectric to form a gate electrode surrounding the channel layer; and depositing a conductive material in the source / drain openings above the source / drain structure to form a source / drain contact having a bottom surface lower than the bottom surface of the first channel layer.

[0004] Another aspect of this application provides a method for manufacturing a semiconductor device, comprising: forming an all-around gate field-effect transistor structure including a plurality of stacked channel layers and source / drain regions, wherein the plurality of stacked channel layers include a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; depositing a first epitaxial semiconductor layer over the surface of the source / drain regions; depositing a dielectric layer over the first epitaxial semiconductor layer; depositing a second epitaxial semiconductor layer over the dielectric layer; etching the second epitaxial semiconductor layer to form an extended contact trench extending to a depth below the bottom surface of the first channel layer; and depositing a conductive material over the second epitaxial semiconductor layer in the extended contact trench to form source / drain contacts having a bottom surface lower than the bottom surface of the first channel layer.

[0005] Another aspect of this application provides a semiconductor device, including: a plurality of spaced-apart stacked channel layers and source / drain regions, wherein the plurality of stacked channel layers include a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; a source / drain structure including a first epitaxial semiconductor layer formed above the source / drain regions, such that the source / drain structure is in contact with the plurality of stacked channel layers; and a source / drain contact formed above the source / drain structure, such that the bottom surface of the source / drain contact is lower than the bottom surface of the first channel layer. Attached Figure Description

[0006] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. For clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A This is a first vertical cross-sectional view of a semiconductor device configured as a full-ring gate field-effect transistor (GAAFET) according to various embodiments;

[0008] Figure 1B According to various embodiments Figure 1A A second vertical cross-sectional view of a semiconductor device;

[0009] Figure 2 It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0010] Figure 3 It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0011] Figure 4It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0012] Figure 5 It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0013] Figure 6 It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0014] Figure 7 It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0015] Figure 8 It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0016] Figure 9A It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0017] Figure 9B According to various embodiments, Figure 9A A vertical cross-sectional view of a semiconductor device formed by the structure;

[0018] Figure 9C It is a vertical cross-sectional view of a structure for forming a semiconductor device according to various embodiments;

[0019] Figure 9D According to various embodiments, Figure 9C A vertical cross-sectional view of a semiconductor device formed by the structure;

[0020] Figure 10A This is a vertical cross-sectional view of a semiconductor device having two channel layers according to various embodiments;

[0021] Figure 10B This is a vertical cross-sectional view of a semiconductor device having two channel layers according to various embodiments;

[0022] Figure 11A This is a vertical cross-sectional view of a semiconductor device having four channel layers according to various embodiments;

[0023] Figure 11B This is a vertical cross-sectional view of a semiconductor device having four channel layers according to various embodiments;

[0024] Figure 11C This is a vertical cross-sectional view of a semiconductor device having four channel layers according to various embodiments;

[0025] Figure 12AThis is a vertical cross-sectional view of a structure for forming a semiconductor device with back contact elements according to various embodiments;

[0026] Figure 12B According to various embodiments, Figure 12A A vertical cross-sectional view of a semiconductor device formed by the structure;

[0027] Figure 13 This is a flowchart illustrating the operation of a method for manufacturing a semiconductor device according to various embodiments;

[0028] Figure 14 This is a flowchart illustrating the operation of a method for manufacturing a semiconductor device according to various embodiments. Detailed Implementation

[0029] It should be understood that the following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, the dimensions of elements are not limited to the disclosed range or values, but may also depend on process conditions and / or the desired characteristics of the device. Furthermore, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. For simplicity and clarity, various features may be drawn at any scale.

[0030] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. Additionally, the term “made of” may mean “comprising” or “consisting of.” In this invention, the phrase “one of A, B, and C” refers to “A, B, and / or C” (A, B, C, A and B, A and C, B and C, or A, B, and C), and unless otherwise stated, does not refer to an element from A, an element from B, and an element from C.

[0031] One or more of the disclosed embodiments advantageously disclose a method for manufacturing a semiconductor device having improved source / drain conductivity, reduced short-channel effects, and reduced drain-induced barrier reduction effects. In this regard, the semiconductor device of the embodiments is configured as a full-to-all-gate transistor structure, wherein source / drain contacts are formed in source / drain epitaxial layers such that the bottom surface of the source / drain contacts is lower than the bottom surface of one or more channel layers. The semiconductor device also includes a heavily doped region formed below the bottom surface of the source / drain contacts. This configuration of the source / drain contacts and the heavily doped region improves source / drain conductivity, thereby reducing ohmic losses and RC delay. To avoid short-channel effects and drain-induced barrier reduction effects, the channel layer closest to the heavily doped region and / or closest to the bottom surface of the source / drain contacts is selected to have a thickness less than the thickness of the other channel layers.

[0032] Figure 1A This is a first vertical cross-sectional view of a semiconductor device 100 configured as a full-ring gate field-effect transistor (GAA-FET) device according to various embodiments. Figure 1B yes Figure 1A A second vertical cross-sectional view of the semiconductor device 100. (Definition) Figure 1A The section of the view lies in the XZ plane and is composed of... Figure 1B The section A-A' in the diagram represents this. Similarly, the definition is... Figure 1B The section of the view lies in the YZ plane and is composed of... Figure 1A The section B-B' in the diagram represents this.

[0033] Semiconductor device 100 includes multiple semiconductor nanostructure layers (e.g., nanosheets or nanowires), each layer configured as a channel layer (208a, 208b, 208c). Semiconductor device 100 also includes a gate structure 240 surrounding a portion of each channel layer (208a, 208b, 208c). See below for reference. Figure 8 In more detail, the gate structure 240 also includes a conductive material formed through the gate dielectric layer 242. Figure 1A and Figure 1B (Not shown in the image) Gate electrode layer 244 separated from multiple channel layers (208a, 208b, 208c).

[0034] Multiple channel layers (208a, 208b, 208c) have their own thicknesses (T1, T2, T3). According to various embodiments, the first thickness T1 of the first channel layer 208a is thicker than the second thickness T2 of the second channel layer 208b. The selection of different channel thicknesses is used to reduce drain-induced barrier reduction (DIBL) and short-channel effects, as described in more detail below.

[0035] The semiconductor device 100 also includes an epitaxial source / drain component 232 formed to contact the end of each of the plurality of channel layers (208a, 208b, 208c). See below for reference. Figure 6 In more detail, the source / drain component 232 is configured as a source component 232S in the source region 205S of the semiconductor device 100, and as a drain component 232D in the drain region 205D of the semiconductor device 100. According to some embodiments, the source component 232S and the drain component 232D (e.g., see...) Figure 6 These are similar structures, collectively referred to as source / drain components 232. In other embodiments, source components 232S and drain components 232D have different structures and compositions.

[0036] According to various embodiments, the semiconductor device 100 is formed above the semiconductor substrate 201. In this regard, according to some embodiments, Figure 1A The plane intersects the semiconductor substrate 201 along the longitudinal direction (i.e., along the

[110] crystal direction of the source / drain component 232). Various other substrate orientations are provided in other embodiments. For example... Figure 1A As shown, the semiconductor device 100 includes a first epitaxial semiconductor layer 106 formed in a source / drain trench 108, and an isolation dielectric layer 230 formed between the first epitaxial layer 106 and a source / drain component 232, which itself is a second epitaxial layer. As described in more detail below, the first epitaxial layer 106 is undoped, and the source / drain component 232 is a doped epitaxially deposited semiconductor material. According to some embodiments, a second isolation dielectric layer 908 is also formed between the gate structure 240 and the substrate 201.

[0037] like Figure 1A As shown, the semiconductor device 100 includes an internal spacer component 220 formed between the gate structure 240 and the source / drain component 232. In some embodiments, the internal spacer component 220 is formed of a dielectric material, such as a silicon-containing dielectric material, including but not limited to silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, and / or oxygen-doped silicon carbonitride. In some embodiments, the internal spacer component 220 is formed of a low dielectric constant (low k) material. For example, in some embodiments, the dielectric constant (k) value of the internal spacer component 220 is lower than that of silicon oxide, for example, lower than 4.2, equal to or lower than about 3.9, or in the range of about 3.5 to about 3.9.

[0038] In some embodiments, the internal spacer component 220 is formed by deposition processes such as atomic layer deposition (ALD), chemical vapor deposition (CVD) such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or high aspect ratio process (HARP) CVD, other suitable techniques, and / or combinations thereof. In some embodiments, an etch-back process is implemented, which includes anisotropic etching processes such as dry plasma etching, isotropic etching processes such as dry chemical etching, remote plasma etching, wet chemical etching, and / or combinations of these techniques, as referenced. Figure 4 and Figure 5 A more detailed description.

[0039] The semiconductor device 100 also includes a front contact 102a comprising a conductive material coupled to the source / drain component 232. The front contact 102a is configured as a source / drain contact, having a bottom surface 110 lower than the bottom surface 112 of the first channel layer 208a. This configuration improves the conductive contact between the front contact 102a and the source / drain component 232. In this respect, contact resistance is reduced, thereby improving device performance by reducing resistive losses and RC delay.

[0040] Placing the front contact 102a below the first channel layer 208a may introduce an increased electric field strength near the second channel layer 208b, which could lead to an increase in short-channel and DI-BL effects. These effects are mitigated, as described above and in more detail below, by reducing the thickness T2 of the second channel layer 208b relative to the thickness T1 of the first channel layer 208a. According to various embodiments, the front contact 102a is placed at various depths relative to the first channel layer 208a and the second channel layer 208b. In such embodiments, the channel layers 208 are configured with different thicknesses, thereby improving the conductivity of the source / drain contact 102 and reducing DI-BL and short-channel effects, as referenced below. Figures 9A to 11C As further described.

[0041] Gate structure 240 and front contact 102a are formed within interlayer dielectric (ILD) layer 236 (see, for example, see...). Figure 8 The semiconductor device 100 also includes a contact etch stop layer 234 formed between the ILD layer 236 and the source / drain components 232, as described in more detail below. The semiconductor device 100 also includes a pad layer 104 separating the ILD layer 236 from the front contact 102a, and a gate spacer layer 216 separating the ILD layer 236 from the gate structure 240, as described in more detail below.

[0042] According to various embodiments, the source / drain component 232 is formed of a doped semiconductor material (e.g., silicon, SiGe, etc.), and the conductive material of the front contact 102a is metallic. In other embodiments, a silicide layer 120 is formed between the source / drain component 232 and the front contact 102a (e.g., see [link to relevant documentation]). Figure 9B ), as described in more detail below.

[0043] According to various embodiments, the source / drain component 232 is an epitaxial n-type doped semiconductor layer. For example, according to some embodiments, the source / drain component 232 is an n-type doped silicon layer. In some embodiments, the source / drain component 232 is doped with a doping density of approximately 5 x 10⁻⁶. 19 atoms / cm 3 With approximately 1 x 10 22 atoms / cm 3 The phosphorus dopant concentration is between [specific values]. In other embodiments, the source / drain component 232 is an epitaxial p-type doped semiconductor layer. For example, according to some embodiments, the source / drain component 232 is a p-type doped SiGe alloy layer. In some embodiments, the source / drain component 232 has a Si [specific composition]. x Ge 1-x A SiGe alloy layer, wherein x is between about 0.4 and about 0.6. In some embodiments, the source / drain component 232 is doped with a matrix having a matrix of about 5 x 10⁻⁶. 19 atoms / cm 3 With approximately 1 x 10 22 atoms / cm 3 The dopant concentration of boron.

[0044] In embodiments where the semiconductor device 100 is formed as an n-channel nanostructure device such as an n-channel GAA FET, the source / drain component 232 comprises a semiconductor material, such as silicon phosphide (SiP), silicon arsenide (SiAs), silicon phosphide carbide (SiCP), silicon carbide (SiC), silicon, gallium arsenide (GaAs), or other suitable semiconductor materials, or combinations thereof. In some embodiments, the source / drain component 232 is doped with an n-type dopant during the epitaxial growth process. For example, in some embodiments, the n-type dopant is phosphorus or arsenic. In some embodiments, the source / drain component 232 is epitaxially grown phosphorus-doped silicon to form silicon phosphide (SiP).

[0045] In embodiments where the semiconductor device 100 is formed as a p-channel nanostructure device such as a p-channel GAA FET, the source / drain component 232 is fabricated using a semiconductor material such as SiGe, Si, gallium arsenide (GaAs), or other suitable semiconductor materials, or combinations thereof. In some embodiments, the source / drain component 232 is doped with a p-type dopant during the epitaxial growth process. For example, in some embodiments, the p-type dopant is boron or boron difluoride (BF2). In some embodiments, the source / drain component 232 is epitaxially grown boron-doped SiGe to form the SiGe source / drain component 232.

[0046] In some embodiments, the epitaxial growth process for forming the source / drain component 232 is periodic deposition-etch epitaxy (CDE). CDE involves a periodic deposition operation in which the semiconductor structure is exposed to a precursor pulse for deposition and doping, and then exposed to an etchant gas for a first cycle. This is followed by a second cycle during which the semiconductor device is exposed only to the etchant gas, without a precursor. The process is then repeated, and in a third cycle, the semiconductor device is again exposed to a precursor pulse for deposition and doping, followed by the etchant gas. This cycle is repeated until the source / drain component 232 of the desired thickness is formed. Reference is made below. Figures 2 to 8 Further details of the processing operations used to form the semiconductor device 100 are described in more detail.

[0047] Figure 2 This is a vertical cross-sectional view of a structure 200 for forming a semiconductor device 100 according to various embodiments. Structure 200 includes a substrate 201. In embodiments, substrate 201 is a bulk silicon substrate (i.e., including bulk single-crystal silicon). In other embodiments, substrate 201 includes other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof, or other suitable materials. In some alternative embodiments, substrate 201 is a semiconductor-on-insulator (SOI) substrate (not shown), such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. The semiconductor-on-insulator substrate is fabricated using separation by oxygen implantation (SIMOX), wafer bonding, and / or other suitable methods. In some embodiments, the semiconductor layer 204 is silicon, silicon germanium, germanium, or other suitable material, and is either undoped or doped with a low dose of dopant.

[0048] Structure 200 includes a fin structure 205 disposed above substrate 201. The fin structure 205 extends longitudinally along the X direction and is divided into a channel region 205C, a source region 205S, and a drain region 205D overlapped by a sacrificial gate stack 210 (as described below). In this example, Figure 2 The diagram shows two channel regions 205C, one source region 205S, and two drain regions 205D, but in other embodiments, structure 200 includes additional source / drain regions (205S, 205D) and channel region 205C.

[0049] A fin structure 205 is formed from a portion of substrate 201 and a vertically stacked arrangement of alternating semiconductor layers (206, 208) using a combination of photolithography and etching steps. Exemplary photolithography processes involve spin-coating a photoresist layer, soft-baking the photoresist layer, aligning a mask, exposure, post-exposure baking, developing the photoresist layer, rinsing, and drying (e.g., hard baking). In some cases, the patterning of the fin structure 205 uses dual-patterning or multi-patterning processes to create patterns with a smaller pitch than that achievable using a single direct photolithography process. Etching processes include dry etching, wet etching, and / or other suitable techniques.

[0050] In the depicted embodiment, the vertical stack of alternating semiconductor layers (206, 208) includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206. Each of the channel layers 208 is composed of Si, and each of the sacrificial layers 206 is composed of SiGe. The channel layers 208 and sacrificial layers 206 are epitaxially deposited on a substrate 201 using molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and / or other suitable epitaxial growth processes.

[0051] Although Figure 2 Not shown, but the isolation component surrounds the fin structure 205 to isolate it from adjacent fin structures (i.e., to separate them from each other along the Y direction). In some embodiments, the isolation component is deposited in trenches defining the fin structure 205. These trenches extend through the channel layer 208 and the sacrificial layer 206 and terminate in the substrate 201. The isolation component, also known as a shallow trench isolation (STI) component, is formed using a dielectric material deposited over the structure 200 using processes such as chemical vapor deposition (CVD), subatmospheric CVD (SACVD), flowable CVD (FCVD), physical vapor deposition (PVD), spin coating, and / or other suitable processes. The deposited dielectric material is planarized and recessed until the fin structure 205 rises above the isolation component. Dielectric materials used for the isolation component include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. Figure 2 As further shown, according to certain embodiments, an isolation dielectric layer 908L is also provided between the substrate 201 and the lowest sacrificial layer 206.

[0052] As described above, structure 200 includes a sacrificial gate stack 210 disposed above the channel region 205C of fin structure 205. The channel region 205C and the sacrificial gate stack 210 define a source region 205S and a drain region 205D, which are not regions that are vertically overlapped by the sacrificial gate stack 210. Each channel region 205C is located between the source region 205S and the drain region 205D along the X direction. Figure 2 Two sacrificial gate stacks 210 are shown, but other embodiments of the structure 200 include additional sacrificial gate stacks 210.

[0053] In this embodiment, a gate replacement process (or a post-gate process) is employed, wherein the sacrificial gate stack 210 is used as a functional gate structure (e.g., Figure 1A The placeholder for the gate structure 240 shown is shown in the image. The sacrificial gate stack 210 includes a sacrificial dielectric layer 211, a sacrificial gate electrode layer 212 above the sacrificial dielectric layer 211, and a gate top hard mask layer 215 above the sacrificial gate electrode layer 212. The sacrificial dielectric layer 211 includes silicon oxide, the sacrificial gate electrode layer 212 is made of polysilicon, and the gate top hard mask layer 215 is a multilayer comprising a silicon oxide layer 213 and a silicon nitride layer 214 formed on the silicon oxide layer 213. The sacrificial gate stack 210 is formed using suitable deposition, photolithography, and etching processes.

[0054] like Figure 2As shown, structure 200 includes a gate spacer layer 216 disposed above structure 200. Gate spacer layer 216 includes a first gate spacer layer 216a and a second gate spacer layer 216b conformally deposited above structure 200, covering the top surface and sidewalls of the sacrificial gate stack 210 and the top surface of the fin structure 205. The term "conformally" describes a layer having a substantially uniform thickness over different regions. In some embodiments, the dielectric constant of the second gate spacer layer 216b exceeds the dielectric constant of the first gate spacer layer 216a, and the second gate spacer layer 216b exhibits greater etch resistance compared to the first gate spacer layer 216a. In some embodiments, the first gate spacer layer 216a comprises silicon oxide, silicon carbide, or a suitable low-k dielectric material. In some embodiments, the second gate spacer layer 216b comprises silicon carbonitride, silicon nitride, zirconium oxide, aluminum oxide, or a suitable dielectric material. A first gate spacer layer 216a and a second gate spacer layer 216b are deposited over the sacrificial gate stack 210 using processes such as CVD, SACVD, FCVD, atomic layer deposition (ALD), PVD, or other suitable processes.

[0055] Figure 3 This is a vertical cross-sectional view of a structure 300 for forming a semiconductor device 100a according to various embodiments. According to various embodiments, structure 300 is formed from structure 200 by recessing the source region 205S and two drain regions 205D of the fin structure 205 to form source openings 218S and two drain openings 218D. In some embodiments, anisotropic etching is performed on the source regions 205S and drain regions 205D of the fin structure not covered by the sacrificial gate stack 210 and the gate spacer layer 216 using a dry etching process or a suitable etching technique. The dry etching process uses oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma, or combinations thereof. Source opening 218S and drain opening 218D extend through the vertical stack of channel layer 208 and sacrificial layer 206. These openings partially extend into substrate 201. Figure 3 As shown, the sidewalls of the channel layer 208 and the sacrificial layer 206 are exposed within the source opening 218S and the drain opening 281D. As also shown, the isolation dielectric layer 908L is etched to produce the above reference. Figure 1A and Figure 1B The second isolation dielectric layer 908 is described.

[0056] refer to Figure 4 and Figure 5 After forming the source opening 218S and drain opening 218D, the internal spacer component 220 is formed. Once the source opening 218S and drain opening 218D are formed, the sacrificial layer 206 is exposed within these openings. Figure 4 As shown, the sacrificial layer 206 is selectively and partially recessed to form the internal spacer recess 219, while the exposed channel layer 208 is not significantly etched. In embodiments where the channel layer is made of silicon (Si) and the sacrificial layer 206 is made of silicon germanium (SiGe), the selective and partial recessing of the sacrificial layer 206 involves a selective isotropic etching process, which may include a selective dry etching process or a selective wet etching process. The degree of recess is controlled by the duration of the etching process. After forming the internal spacer recess, an internal spacer material layer is deposited over the structure, including within the recess. The internal spacer material layer includes silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, metal nitride, or other suitable dielectric material. Then, as... Figure 5 As shown, the deposited internal spacer material layer is etched back to remove excess material from the sidewalls of the channel layer 208, thereby forming the internal spacer component 220. In some embodiments, the etch-back process is a dry etching process, similar to the process used to form the source opening 218S and the drain opening 218D.

[0057] Figure 6 This is a vertical cross-sectional view of a structure 600 for forming a semiconductor device 100 according to various embodiments. For example... Figure 6 As shown, a source component 232S is formed in a source opening 218S, and a drain component 232D is formed in a drain opening 218D. Before forming the source component 232S and the drain component 232D, a first epitaxial layer 106 is deposited in the source opening 218S and the drain opening 218D, and an isolation dielectric layer 230 is formed over the first epitaxial layer 106 at the bottom of the source opening 218S and the bottom of the drain opening 218D. As described above, the first epitaxial layer 106 is an undoped semiconductor layer, such as undoped Si or other suitable semiconductor material.

[0058] The isolation dielectric layer 230 is a dielectric layer, referred to in some embodiments as a "flexible bottom isolation" structure. The isolation dielectric layer 230 reduces or substantially prevents current leakage between the source component 232S, the drain component 232D, and the substrate 201, or additional features formed on the back side of the structure 200. In some embodiments, the isolation dielectric layer 230 comprises silicon oxide, silicon nitride, SiCN, SiCON, SiOC, SiC, or other suitable materials, and is formed by oxidation (e.g., to form silicon oxide) or by a conformal deposition process, followed by further processing as described below.

[0059] An isolation dielectric layer 230 is formed by performing one or more conformal film deposition processes, such as plasma-enhanced atomic layer deposition (PEALD) or PECVD, followed by film treatment processes, such as etching back. The resulting conformal film inherits the shape of the underlying structure on which the conformal film is formed. The film deposition process employs a periodic PEALD method, using reactive gases such as dichlorosilane (DCS) and ammonia / argon (NH3 / Ar) plasma. The subsequent film treatment process uses argon / nitrogen (Ar / N2) plasma for etching.

[0060] In some embodiments, the first epitaxial layer 106 is formed as an epitaxial semiconductor component, which is epitaxially and selectively formed above the exposed top surface of the substrate 201 using epitaxial processes such as molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), metal-organic chemical vapor deposition (MOCVD), or other suitable epitaxial growth processes. In such embodiments, the bottom surface of the first epitaxial layer 106 generally follows the shape of the bottom surface of the source and drain openings (218S, 218D). Because the surface of the internal spacer component 220 is unfavorable for epitaxial deposition, the first epitaxial layer 106 is formed from the exposed surface of the substrate 201 of the substrate 201 in a bottom-up manner. In cross-section, in the illustrated embodiment, the first epitaxial layer 106 exhibits a curved bottom shape and a flat top shape. The first epitaxial layer 106 comprises different compositions depending on the conductivity type of the source component 232S. In some embodiments, for the n-type source device 232S, the first epitaxial layer 106 comprises undoped silicon (Si), and for the p-type source device 232S, the isolation dielectric layer 230 comprises undoped silicon germanium (SiGe).

[0061] Source components 232S and drain components 232D are formed over an isolation dielectric layer 230 using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), or other suitable processes. The epitaxial process utilizes gaseous and / or liquid precursors that interact with the composition of the isolation dielectric layer 230. Source components 232S and drain components 232D are coupled to a channel layer 208 in a channel region 205C of the fin structure 205. Depending on the conductivity type of the formed transistor, source components 232S and drain components 232D are n-type and p-type source / drain components, respectively.

[0062] Exemplary n-type source / drain components include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, which can be in-situ doped during epitaxial processes by introducing n-type dopants such as phosphorus, arsenic, or antimony, or ex-situ doped using ion implantation. Exemplary p-type source / drain components include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, which can be in-situ doped during epitaxial processes by introducing p-type dopants such as boron or gallium, or ex-situ doped using ion implantation. In some embodiments, a lightly doped epitaxial semiconductor layer is formed between the source / drain components (232S, 232D) and the corresponding isolation dielectric layer 230, and the doping concentration of the lightly doped epitaxial semiconductor layer is lower than the doping concentration of the source / drain components (232S, 232D).

[0063] Figure 7 According to various embodiments, Figure 6 The formed structure includes a contact etch stop layer (CESL) 234 and an interlayer dielectric (ILD) layer 236. CESL 234 comprises silicon nitride, silicon oxynitride, and / or similar materials, and is formed by atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), or other suitable deposition or oxidation processes. Figure 7 As shown, CESL 234 is deposited on the top surfaces of source component 232S, drain component 232D, and the sidewalls of gate spacer layer 216. An ILD layer 236 is deposited over CESL 234 using a PECVD process or another suitable deposition technique. The ILD layer 236 is made of a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borosilicate glass (BPSG), fused silica glass (FSG), phosphate silicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, structure 700 is annealed after the formation of ILD layer 236 to improve the overall integrity of ILD layer 236.

[0064] Figure 8 According to various embodiments, Figure 7Structure 700 forms structure 800. According to various embodiments, structure 800 is formed by replacing the sacrificial gate stack 210 with gate structure 240. A planarization process, such as chemical mechanical polishing (CMP), is performed on structure 700 to remove excess material and expose the top surface of the sacrificial gate electrode layer 212 in the sacrificial gate stack 210. After exposing the sacrificial gate electrode layer 212, the next step is to remove the sacrificial gate stack 210 of structure 700. The removal of the sacrificial gate stack 210 includes one or more etching processes that are selective for the material in the sacrificial gate stack 210. For example, selective wet etching, selective dry etching, or a combination thereof are used to remove the sacrificial gate stack 210. After removing the sacrificial gate stack 210, the sacrificial layer 206 is selectively removed to release the channel layer 208 in the channel region 205C. The selective removal of the sacrificial layer 206 is achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0065] like Figure 8 As shown, each of the gate structures 240 includes a gate dielectric layer 242 and a gate electrode layer 244 above the gate dielectric layer 242. In some embodiments, the gate dielectric layer 242 includes an interface layer disposed on the channel layer 208 and a high-k dielectric layer above the interface layer. A high-k dielectric layer refers to a dielectric material having a dielectric constant greater than that of silicon dioxide, which is about 3.9. A low-k dielectric layer refers to a dielectric material having a dielectric constant no greater than that of silicon dioxide. In some embodiments, the interface layer includes silicon oxide. The high-k dielectric layer is then deposited above the interface layer using ALD, CVD, or other suitable methods. According to various embodiments, the high-k dielectric layer includes hafnium oxide. Alternatively, according to various embodiments, the high-k dielectric layer includes other high-k dielectrics, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, SrTiO3, BaTiO3, BaZrO3, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba,Sr)Ti3 (BST), silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials.

[0066] A gate electrode layer 244 is deposited over the gate dielectric layer 242 using ALD, PVD, CVD, electron beam evaporation, deposition, or other suitable methods. The gate electrode layer 244 comprises a single-layer or multi-layer structure, such as a metal layer (work function metal layer), pad layer, wetting layer, adhesive layer, metal alloy, or various combinations of metal silicides having a selected work function to improve device performance. For example, the gate electrode layer 244 comprises titanium nitride, aluminum titanium nitride, aluminum titanium nitride, tantalum nitride, aluminum tantalum nitride, aluminum tantalum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, silicon tantalum nitride, copper, other refractory metals, or other suitable metallic materials, or combinations thereof. Furthermore, in embodiments where the structure 800 includes n-type and p-type transistors, different gate electrode layers are formed for the n-type and p-type transistors, each layer comprising a different work function metal layer (e.g., to provide different n-type and p-type work function metal layers).

[0067] Figure 9A This is a vertical cross-sectional view of a structure 900a for forming a semiconductor device 900b according to various embodiments. Figure 9B It is by Figure 9A A vertical cross-sectional view of the semiconductor device 900b formed by the structure. By etching the ILD layer 236 to form a contact trench 902 through the ILD layer 236, the source / drain structure 232 is exposed, allowing it to be viewed from... Figure 8 Structure 800 forms structure 900a. Then, the source / drain components 232 are doped by implementing an implantation process to generate the heavily doped region 904.

[0068] For example, in some embodiments, the heavily doped region 904 is doped with n-type or p-type dopant at a concentration of approximately 5 x 10⁻⁶. 20 atoms / cm 3 With approximately 1 x 10 22 atoms / cm 3 Between these, the remaining portions of the source / drain components 232 are doped with the same type of conductive dopant, but at a lower concentration, approximately 5 × 10⁻⁶. 19 atoms / cm 3 With approximately 3 x 10 21 atoms / cm 3 Between. As described above, in some embodiments, the first epitaxial layer 106 is undoped. Figure 9A and Figure 9BAs shown, the source / drain component 232 does not need to completely fill the space above the isolation dielectric layer 230, and in some embodiments, one or more gaps 906 are formed between the isolation dielectric layer 230 and the source / drain component 232. According to some embodiments, structure 900a and semiconductor device 900b further include a second isolation dielectric layer 908 formed between the substrate and the bottom surface of the gate structure 240, as referenced above. Figures 1A to 8 As described. According to various embodiments, the second isolation dielectric layer 908 comprises a material similar to that of the isolation dielectric layer 230.

[0069] In some embodiments, the contact trench 902 is filled with a conductive material to form a front contact 102a (not shown) that contacts the heavily doped region 904 of the source / drain component 232. In other embodiments, the source / drain component 232 is further etched to form an extended contact trench 903 (see, for example, see...). Figure 9C Then, the trench is filled with a conductive material to form a front contact 102a, such as... Figure 9B As shown in the figure. According to various embodiments, a liner layer 104 is formed in the contact trench 902. The liner layer 104 comprises silicon nitride, or other materials that serve as a barrier between the front contact 102a and the ILD layer 236. For example, in some embodiments, the liner layer 104 comprises Si3N4, SiN, SiO2, SiON, SiCN, SiCON, SiCO, or a high-k dielectric such as HfO2, ZrO2, Al2O3, TiO2, La2O3, Y2O3, BaSrTiO3, or the like. In some embodiments, the liner layer 104 is also formed in the extended contact trench 903 such that the liner layer 104 extends below the bottom surface 112 of the first channel layer 208a (e.g., see [reference]). Figure 10A Alternatively, in some embodiments, the liner layer 104 is formed only above the contact groove 902, such that the liner layer 104 is located above the top surface 113 of the first channel layer 208a, as shown below. Figure 9B As shown in the image.

[0070] According to various embodiments, the semiconductor device 900b further includes a silicide layer 120 formed between the source / drain component 232 and the front contact 102a, such as Figure 9B As shown in the figure. In some embodiments, as hereinafter, a silicide layer 120 is formed over the source / drain component 232. A thin layer of a metal such as titanium, tantalum, cobalt, tungsten, or nickel (not shown) is deposited onto the source / drain component 232 (e.g., Figure 9CThe metal layer is applied to the area above and around the extended contact trench 903. This metal layer then undergoes a rapid thermal annealing process, during which it reacts with the underlying silicon or SiGe layer to form a silicide layer 120. The selection of metals and annealing conditions are controlled to optimize the formation of desired silicide phases, such as titanium silicide, cobalt silicide, or nickel silicide, which exhibit lower resistivity than the source / drain components and stable electrical properties.

[0071] After the formation of the silicide layer 120, in some embodiments, any unreacted metal and metal silicide is removed from unrelated areas, for example, by a selective etching process. This results in a highly conductive silicide layer 120 that is in direct contact with the source / drain components 232. Therefore, the presence of the silicide layer 120 provides highly conductive contact with the subsequently formed front contact 102a. Alternatively, in some embodiments, the selective etching process is omitted, leaving a thin layer of metal on the exposed surface of the ILD layer 236 (not shown) before the formation of the front contact 102a.

[0072] According to various embodiments, then through the contact groove 902 and the extended contact groove 903 (e.g., see...) Figure 9C A conductive material is deposited over a silicide layer 120 within the silicide layer to form a front contact 102a. According to various embodiments, the conductive material is a combination of a metal backing layer (such as a metal nitride or metal carbide) and a metal filler material. Each metal backing layer includes one or more of TiN, TaN, WN, TiC, TaC, or WC, and each metal filler portion includes W, Cu, Al, Co, Ru, Mo, Ta, Ti, their alloys, and / or combinations thereof. Other suitable metal backing and metal filler materials may also be used within the scope of this disclosure.

[0073] As described above, the front contact 102a is configured as a source / drain contact, with its bottom surface 110 lower than the bottom surface 112 of the first channel layer 208a. By placing the front contact 102a below the first channel layer 208a, the conductive contact between the front contact 102a and the source / drain component 232 is improved, thereby improving the conductivity of the source / drain contact. In this respect, the contact resistance is reduced, thereby improving device performance by reducing resistive losses and RC delay. However, placing the front contact 102a below the first channel layer 208a introduces an increased electric field strength near the second channel layer 208b, which may lead to an increase in short-channel effects and DIBL effects.

[0074] Other effects include dopant intrusion from heavily doped region 904 into one or more channel regions (208a, 208b, 208c), which alters the electrostatic field distribution and leads to adverse effects. Dopant intrusion and short-channel effects are related but distinct phenomena. Short-channel effects refer to a set of problems that become more pronounced as the channel length of the transistor decreases. These effects include threshold voltage roll-off and subthreshold slope degradation, which occur due to the reduced electrostatic control of the gate structure 240 over the channel layers (208a, 208b, 208c) as the device shrinks. On the other hand, dopant intrusion occurs when dopant atoms from source / drain components 232 inadvertently diffuse into the channel layers (208a, 208b, 208c). This exacerbates short-channel effects by altering the doping distribution of the channel, particularly near the junction, resulting in unexpectedly high or low doping concentrations.

[0075] These changes make devices more susceptible to problems like DI BL, where a reduced drain voltage lowers the potential blockage at the source-channel junction, allowing current to flow even when the transistor should be off. Additionally, dopant intrusion can increase leakage current by reducing electrostatic control through making the channel region more conductive. This exacerbates the threshold voltage roll-off, which decreases as the channel length shortens. Therefore, while the short-channel effect primarily stems from the challenges of controlling transistors at small sizes, dopant intrusion can further contribute by disrupting the doping distribution of the channel, exacerbating gate control losses, increasing leakage current, and ultimately reducing device performance at smaller nodes.

[0076] According to various embodiments, as described above, these effects are mitigated by reducing the thickness T2 of the second channel layer 208b relative to the thickness T1 of the first channel layer 208a. In this regard, Figure 9B The multiple channel layers (208a, 208b, 208c) have their own thicknesses (T1, T2, T3). According to various embodiments, the first thickness T1 of the first channel layer 208a is thicker than the second thickness T2 of the second channel layer 208b. The selection of different channel thicknesses can reduce the DI-BL effect and improve the conductivity of the channel layers (208a, 208b, 208c). For example, the channel layers near regions with lower dopant concentrations have a larger thickness to reduce resistance, while the channel layers near regions with higher dopant concentrations have a smaller thickness to reduce the DI-BL effect.

[0077] In some configurations, there may be fewer dopant atoms near the first channel layer 208a, which increases the relative resistivity of the portion of the source / drain component 232 near the first channel layer 208a. This may be because the heavily doped region 904 was partially removed during the formation of the extended contact trench 903 (e.g., compared to...). Figure 9A and Figure 9B Alternatively, see the following references. Figure 9D In more detail, the heavily doped region 904 is formed at a lower depth in the source / drain component 232, thus resulting in fewer dopant atoms near the first channel layer 208a. In both cases, the conductivity of the first channel layer 208a is improved by increasing the first thickness T1 of the first channel layer 208a relative to the second thickness T2 of the second channel layer 208b. Similarly, near the more heavily doped region (e.g., see...), the conductivity of the first channel layer 208a is improved. Figure 9C and Figure 9D The channel layer (e.g., the second channel layer 208b) of the heavily doped region 904 is configured to have a relatively small thickness T2 to reduce the DI BL effect.

[0078] According to some embodiments, each of the first thickness T1 and the second thickness is between about 2 nm and about 10 nm, and the difference between the first thickness T1 and the second thickness T2 is between about 0.5 nm and about 5 nm. Additionally, according to various embodiments, the third thickness T3 (i.e., the thickness T3 of the third channel layer 208c) is comparable to the first thickness T1 and the second thickness T2, but can have various values ​​relative to the first thickness T1 and the second thickness T2. For example, the third thickness T3 can also be between about 2 nm and about 10 nm. According to various embodiments, the thicknesses (T1, T2, T3) can be ordered in different ways, such as T1 > T2 = T3; T1 = T3 > T2; T1 > T3 > T2; etc.

[0079] Figure 9C This is a vertical cross-sectional view of a structure 900c for forming a semiconductor device 900d according to various embodiments. Figure 9D It is by Figure 9C A vertical cross-sectional view of the semiconductor device 900d formed by structure 900c. In this respect, the process for forming semiconductor device 900d is similar to the process for forming semiconductor device 900b, except that after etching the source / drain components 232 to form the extended contact trench 903, a heavily doped region 904 is formed. Therefore, the heavily doped region 904 in structure 900c extends to a greater extent than... Figure 9A and Figure 9B The heavily doped region 904 has a greater depth. In some embodiments, this configuration of the heavily doped region 904 being deeper within the source / drain component 232 may have the same characteristics as... Figure 9A and Figure 9BDifferent configurations can produce different electrical characteristics. For example, compared to some embodiments where the heavily doped region 904 is placed at a reduced depth, the front contact 102a formed in the semiconductor device 900d can have different contact resistances and corresponding RC delays. Therefore, these different configurations can provide flexibility in circuit design, allowing optimization of electrical characteristics by modifying the depth and doping concentration of the heavily doped region 904. Additionally, as... Figure 9C and Figure 9D As further shown, in some embodiments, the second isolation dielectric layer 908 is omitted.

[0080] As described above, the lower position of the heavily doped region 904 tends to increase the electric field strength near the second channel layer 208b relative to the first channel layer 208a. This may lead to an increase in the short-channel and DIBL effects, where the electrical characteristics of the second channel layer 208b are controlled by the electrical characteristics of the first channel layer 208a. Additionally, the position of the heavily doped region 904 may lead to an increase in dopant intrusion into the second channel layer 208b. To mitigate this effect, the second thickness T2 is chosen to be smaller than the first thickness T1 of the first channel layer 208a. The relative thicknesses and order of the various thicknesses (T1, T2, T3) are similar to those described above. Figure 9A and Figure 9B The relative thicknesses and ordering of the described embodiments are as described above. For example, each of the thicknesses (T1, T2, T3) is between about 2 nm and about 10 nm, and the difference between the first thickness T1 and the second thickness T2 is between about 0.5 nm and about 5 nm. Furthermore, according to various embodiments, the thicknesses (T1, T2, T3) are ordered in different ways, such as T1 > T2 = T3; T1 = T3 > T2; T1 > T3 > T2; etc.

[0081] Figures 10A to 11C These are vertical cross-sectional views of various semiconductor devices (1000a, 1000b, 1100a, 1100b, 1100c) with different numbers of channel layers according to various embodiments. In this regard, Figure 10A and Figure 10B The semiconductor device (1000a, 1000b) includes two channel layers (208a, 208b), while Figure 11A , Figure 11B ,and Figure 11C The semiconductor devices (1100a, 1100b, 1100c) include four channel layers (208a, 208b, 208c, 208d). In each of the individual semiconductor devices (1000a, 1000b, 1100a, 1100b, 1100c), the thicknesses (T1, T2, T3, T4) are adjusted relative to the depth of the front contact 102a and relative to the depth of the heavily doped region 904 to improve device characteristics.

[0082] As described above, the liner layer 104 can be configured to extend below the bottom surface 112 of the first channel layer 208a, as shown in Figure 10A Alternatively, the liner layer 104 can be configured to extend only to a depth above the top surface 113 of the first channel layer 208a, as shown in Figure 10B In addition, as described above, in different embodiments, the heavily doped regions 904 are placed at different depths. For example, as shown in Figure 10A the heavily doped region 904 of the semiconductor device 1000a is located above Figure 10B the heavily doped region 904 of the semiconductor device 1000b. The placement of the heavily doped region 904 and other design considerations, such as the number of channel layers (208a, 208b) and the thicknesses (T1, T2) of the channel layers (208a, 208b), are selected based on a specific application and can be optimized by using numerical simulation techniques. In some embodiments, there are more than four channel layers in the semiconductor device.

[0083] In each of the embodiments in Figures 10A to 11C the thinnest channel layers (208b, 208c) are the channel layers closest to the heavily doped region 904 and / or the front contact 102a to reduce the short-channel and DIBL effects. Similarly, the thickness of the channel layer away from the heavily doped region 904 and / or the front contact 102a is adjusted to be relatively thick to reduce the contact resistance and RC delay associated with the corresponding channel layer. For example, in the semiconductor device 1100b in Figure 11B the second channel layer 208b has the minimum thickness T2, while in the semiconductor device 1100c in Figure 11C the third channel layer 208c has the minimum thickness T3. In embodiments having a greater number of channel layers (208a, 208b, 208c, 208d), there are more combinations of sorting the various thicknesses (T1, T2, T3, T4).

[0084] For example, in some embodiments, Figure 11A and Figure 11B the semiconductor devices (1100a, 1100b) are each sorted as T1>T2 = T3 = T4. In other embodiments, Figure 11B the semiconductor device 1100b is sorted as T1 = T3 = T4>T2 or T1>T3 = T4<T2. In other embodiments, Figure 11CThe semiconductor device 1100c is ordered as T1=T2=T4>T3. These examples demonstrate that numerous design choices can be made based on the number of channel layers and the depths of the heavily doped region 904 and the front contact 102a. For instance, based on the results of numerical simulations employing optimization algorithms, various thicknesses and thickness orders can be optimized to improve device performance.

[0085] Figure 12A This is a vertical cross-sectional view of a structure 1200a for forming a semiconductor device 1200b having a back contact 102b, according to various embodiments. Figure 12B It is by Figure 12A A vertical cross-sectional view of the semiconductor device 1200b formed from structure 1200a. Structure 1200a is formed from semiconductor device 1100c by etching a back trench 1202 through the substrate 201, the undoped semiconductor layer 106, the first isolation dielectric layer 230, and the back portion of the source / drain structure 232. Figure 12A As shown in the figure, according to some embodiments, an implantation operation is performed to create an additional heavily doped region 904 in the lower part of the source / drain component 232.

[0086] In some embodiments, a pad layer 104 is then deposited over the sidewalls of the back trench 1202. A back contact 102b is then formed by depositing a conductive material over the pad layer 104. The process for forming the back contact 102b is similar to the process for forming the front contact 102a. According to various embodiments, a silicide layer 120 is formed between the heavily doped region 904 and the back contact 102b using processing operations similar to those described above. According to various embodiments, an additional silicide layer 120 is also formed between the front contact 102a and the drain component 232.

[0087] Figure 13This is a flowchart illustrating the operation of a method 1300 for manufacturing semiconductor devices (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) according to various embodiments. According to operation 1302, method 1300 includes alternately depositing a sacrificial layer 206 and a channel layer 208 to form a semiconductor stack (206, 208) over a substrate 201, such that the channel layer 208 includes a first channel layer 208a and a second channel layer 208b located below the first channel layer 208a and thinner than the first channel layer 208a. According to operation 1304, method 1300 includes patterning a semiconductor stack 205 to form fins 205. According to operation 1306, method 1300 includes recessing fin 205 in the source / drain regions (205S, 205D) to form source / drain openings (218S, 218D). According to operation 1308, method 1300 includes epitaxially depositing semiconductor material in the source / drain openings (218S, 218D) to form a source / drain structure 232.

[0088] According to operation 1310, method 1300 includes removing the sacrificial layer 206 in the channel region 205C adjacent to the source / drain regions (205S, 205D), thereby exposing the surface of the channel layer 208. According to operation 1312, method 1300 includes depositing a gate dielectric 242 over the surface of the channel layer 208 and depositing a conductive material over the gate dielectric 242 to form a gate electrode 244 surrounding the channel layer 208. According to operation 1314, method 1300 includes depositing a conductive material over the source / drain structure 232 in the source / drain openings (218S, 218D) to form a source / drain contact 102 having a bottom surface 110 lower than the bottom surface 112 of the first channel layer 208a.

[0089] According to various embodiments, method 1300 further includes epitaxially depositing an undoped semiconductor layer 106 over the surface of the source / drain openings (218S, 218D) before epitaxially depositing semiconductor material to form the source / drain structure 232, and depositing a first isolation dielectric layer 230 over the undoped semiconductor layer 106. According to various embodiments, the first channel layer 208a has a first thickness T1, the second channel layer 208b has a second thickness T2, between about 2 nm and about 10 nm, and the difference between the first thickness T1 and the second thickness T2 is between about 0.5 nm and about 5 nm.

[0090] According to various embodiments, method 1300 further includes depositing an interlayer dielectric layer 236 over the source / drain structure 232; etching the interlayer dielectric layer 236 to form a contact trench 902 through the interlayer dielectric layer 236, thereby exposing the source / drain structure 232; etching the source / drain structure 232 through the contact trench 902 to form an extended contact trench 903; performing an implantation operation to form a doped region 904 in the source / drain structure through the extended contact trench 903; and forming a source / drain contact 102 in the extended contact trench 903 over the source / drain structure 232. According to various embodiments, method 1300 further includes forming a pad layer 104 on the sidewall of contact trench 902, forming a silicide layer 120 over the doped region 904, and forming source / drain contacts 102 over the silicide layer 120 before etching source / drain structure 232.

[0091] According to various embodiments, alternatingly depositing the sacrificial layer 206 and the channel layer 208 to form the semiconductor stack 205 further includes depositing at least three channel layers (208a, 208b, 208c) such that the third channel layer 208c is formed below the second channel layer 208b. According to various embodiments, the at least three channel layers (208a, 208b, 208c) include the thinnest channel layer (208b, 208c) closest to the doped region 904. According to various embodiments, method 1300 further includes forming a second isolation dielectric layer 908 between the substrate 201 and the bottom surface of the gate electrode 244. In various embodiments, the first isolation dielectric layer 230 and the second isolation dielectric layer 908 include silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxide, or one or more high-k dielectrics including HfO2, ZrO2, Al2O3, TiO2, La2O3, Y2O3, and BaSrTiO3.

[0092] According to various embodiments, method 1300 further includes etching a back trench 1202 through the substrate 201, through the undoped semiconductor layer 106, the first isolation dielectric layer 230, and the back portion of the source / drain structure 232, and depositing conductive material into the back trench 1202 to form a back source / drain contact 102b. According to various embodiments, a gap 906 is formed between the bottom of the source / drain structure 232 and the top of the first isolation dielectric layer 230.

[0093] Figure 14This is a flowchart illustrating the operation of a method 1400 for manufacturing semiconductor devices (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) according to various embodiments. According to operation 1402, method 1400 includes forming a full-to-the-loop gate field-effect transistor 100 structure comprising a plurality of stacked channel layers (208a, 208b, 208c) and source / drain regions (205S, 205D), such that the plurality of stacked channel layers 208 include a first channel layer 208a and a second channel layer 208b located below the first channel layer 208a and thinner than the first channel layer 208a. According to operation 1404, method 1400 includes depositing a first epitaxial semiconductor layer 106 over the surfaces of the source / drain regions (205S, 205D). According to operation 1406, method 1400 includes depositing a dielectric layer 230 over a first epitaxial semiconductor layer 106. According to operation 1408, method 1400 includes depositing a second epitaxial semiconductor layer 232 over the dielectric layer 230.

[0094] According to operation 1410, method 1400 includes etching a second epitaxial semiconductor layer 232 to form an extended contact trench 903 extending to a depth below the bottom surface of the first channel layer 208a. According to operation 1412, method 1400 includes depositing a conductive material in the extended contact trench 903 over the second epitaxial semiconductor layer 232 to form a source / drain contact 102, the bottom surface 110 of which is lower than the bottom surface 112 of the first channel layer 208a.

[0095] According to various embodiments, method 1400 further includes performing an implantation operation before depositing conductive material over the second epitaxial semiconductor layer 232 to form a doped region 904 in the second epitaxial semiconductor layer 232 by extending the contact trench 903, such that a heavily doped region 904 exists below the extended contact trench 903, a silicide layer 120 is formed over the doped region 904, and conductive material is deposited over the silicide layer 120. According to various embodiments, epitaxially depositing the first epitaxial semiconductor layer 106 further includes depositing undoped Si or SiGe. According to various embodiments, method 1400 further includes depositing a pad layer 104 over the sidewalls of the extended contact trench 903 before depositing conductive material, such that the pad layer 104 extends below the bottom surface of the first channel layer 208a.

[0096] According to various embodiments, method 1400 further includes depositing a pad layer 104 over the sidewalls of the source / drain regions (205S, 205D) before etching the second epitaxial semiconductor layer 232 to form the extended contact trench 903, such that the pad layer 104 extends to a depth above the top surface 113 of the first channel layer 208a. According to various embodiments, the plurality of stacked channel layers 208 include at least three channel layers (208a, 208b, 208c) having the thinnest channel layer (208b, 208c) closest to the doped region 904.

[0097] Referring to all the accompanying drawings, according to various embodiments of the present invention, a semiconductor device (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) is provided. The semiconductor device (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) includes a plurality of stacked channel layers (208a, 208b, 208c, 208d) and source / drain regions (205S, 205D), wherein the plurality of stacked channel layers 208 include a first channel layer 208a and a layer 208a thinner than the first channel layer 208a located below the first channel layer 208a. The second channel layer 208b of 08a has a source / drain structure 232 including a first epitaxial semiconductor layer 232 formed above the source / drain regions (205S, 205D), such that the source / drain structure 232 contacts a plurality of stacked channel layers 208, and a source / drain contact 102 is formed above the source / drain structure 232, such that the bottom surface 110 of the source / drain contact 102 is lower than the bottom surface 112 of the first channel layer 208a.

[0098] According to various embodiments, the semiconductor device (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) further includes a second epitaxial semiconductor layer 106 formed below the first epitaxial semiconductor layer 232, and an isolation dielectric layer 230 formed between the first epitaxial semiconductor layer 232 and the second epitaxial semiconductor layer 106. According to various embodiments, the semiconductor device (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) further includes a doped portion 904 of the first epitaxial semiconductor layer 232 located below the bottom surface 110 of the source / drain contact 102. According to various embodiments, the plurality of stacked channel layers 208 include at least three channel layers (208a, 208b, 208c), which have the thinnest channel layer (208b, 208c) closest to the doped portion 904, and the plurality of stacked channel layers 208 are nanosheets or nanowires.

[0099] According to various embodiments, the semiconductor devices (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) further include a pad layer 104 formed above the sidewalls of the source / drain regions (205S, 205D), such that the pad layer 104 extends to a depth below the bottom surface 110 of the first channel layer 208a (e.g., see...). Figure 10A ), and a silicide layer 120, which is formed between the doped portion 904 of the first epitaxial semiconductor layer 232 and the bottom surface 110 of the source / drain contact 102.

[0100] One or more of the disclosed embodiments advantageously disclose methods for manufacturing semiconductor devices (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) having improved source / drain conductivity, reduced short-channel effect, and reduced drain-induced barrier reduction effect.

[0101] In this regard, the semiconductor devices (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) of the embodiments are configured as a full-ring gate transistor structure, wherein source / drain contacts 102 are formed in the source / drain epitaxial layer 232, such that the bottom surface 110 of the source / drain contacts 102 is lower than the bottom surface 112 of one or more channel layers (208a, 208b, 208c, 208d). The semiconductor devices (100, 900b, 900d, 1000a, 1000b, 1100a, 1100b, 1100c, 1200b) also include a heavily doped region 904 formed below the bottom surface 110 of the source / drain contacts 102. By configuring the source / drain contacts 102 and the heavily doped region 904 in this manner, the source / drain conductivity can be improved, thereby reducing ohmic losses and RC delay. To avoid short-channel effects and drain-induced blocking degradation effects, the channel layers (208b, 208c) closest to the heavily doped region 904 and / or closest to the bottom surface 112 of the source / drain contacts 102 have thicknesses (T2, T3) smaller than those of other channel layers.

[0102] According to various embodiments, a method of manufacturing a semiconductor device includes: alternately depositing a sacrificial layer and a channel layer to form a semiconductor stack over a substrate, such that the channel layer includes a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; patterning the semiconductor stack to form fins; recessing the fins in the source / drain regions to form source / drain openings; and epitaxially depositing semiconductor material in the source / drain openings to form a source / drain structure. The method further includes: removing the sacrificial layer in the channel regions adjacent to the source / drain regions, such that the surface of the channel layer is exposed; depositing a gate dielectric above the surface of the channel layer and depositing a conductive material above the gate dielectric to form a gate electrode surrounding the channel layer; and depositing conductive material in the source / drain openings above the source / drain structure to form source / drain contacts having a bottom surface lower than the bottom surface of the first channel layer.

[0103] According to various embodiments, the method further includes: epitaxially depositing an undoped semiconductor layer over the surface of the source / drain opening before epitaxially depositing semiconductor material to form the source / drain structure, and depositing a first isolation dielectric layer over the undoped semiconductor layer. According to various embodiments, the first channel layer has a first thickness, the second channel layer has a second thickness, each between 2 nm and 10 nm, and the difference between the first thickness and the second thickness is between 0.5 nm and 5 nm.

[0104] According to various embodiments, the method further includes: depositing an interlayer dielectric layer over the source / drain structure; etching the interlayer dielectric layer to form a contact trench through the interlayer dielectric layer, thereby exposing the source / drain structure; etching the source / drain structure through the contact trench to form an extended contact trench; performing an implantation operation to form a doped region in the source / drain structure through the extended contact trench; and forming source / drain contacts over the source / drain structure in the extended contact trench. According to various embodiments, the method further includes: forming a pad on the sidewalls of the contact trench before etching the source / drain structure, forming a silicide layer over the doped region, and forming source / drain contacts over the silicide layer.

[0105] According to various embodiments, alternately depositing sacrificial layers and channel layers to form a semiconductor stack further includes depositing at least three channel layers, such that a third channel layer is formed beneath the second channel layer. According to various embodiments, the at least three channel layers include the thinnest channel layer closest to the doped region. According to various embodiments, the method further includes forming a second isolation dielectric layer between the substrate and the bottom surface of the gate electrode. According to various embodiments, the first and second isolation dielectric layers comprise one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbide, or high-k dielectrics, wherein the high-k dielectric comprises one or more of HfO2, ZrO2, Al2O3, TiO2, La2O3, Y2O3, and BaSrTiO3.

[0106] According to various embodiments, the method further includes: etching a back trench through the substrate, through the undoped semiconductor layer, the first isolation dielectric layer, and the back portion of the source / drain structure, and depositing conductive material into the back trench to form a back source / drain contact. According to various embodiments, a gap is formed between the bottom of the source / drain structure and the top of the first isolation dielectric layer.

[0107] According to various embodiments, a method of manufacturing a semiconductor device includes: forming an all-around gate field-effect transistor structure comprising a plurality of stacked channel layers and source / drain regions, wherein the plurality of stacked channel layers include a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; depositing a first epitaxial semiconductor layer over a surface of the source / drain regions; depositing a dielectric layer over the first epitaxial semiconductor layer; and depositing a second epitaxial semiconductor layer over the dielectric layer. According to various embodiments, the method further includes: etching the second epitaxial semiconductor layer to form an extended contact trench extending to a depth below the bottom surface of the first channel layer; and depositing a conductive material in the extended contact trench over the second epitaxial semiconductor layer to form source / drain contacts having a bottom surface lower than the bottom surface of the first channel layer.

[0108] According to various embodiments, the method further includes: performing an implantation operation before depositing conductive material over the second epitaxial semiconductor layer to form a doped region in the second epitaxial semiconductor layer by extending a contact trench, such that a heavily doped region exists below the extended contact trench, a silicide layer is formed over the doped region, and conductive material is deposited over the silicide layer. Epitaxially depositing the first epitaxial semiconductor layer also includes depositing undoped Si or SiGe. According to various embodiments, the method further includes depositing a pad layer over the sidewalls of the extended contact trench before depositing the conductive material, such that the pad layer extends below the bottom surface of the first channel layer.

[0109] According to various embodiments, the method further includes depositing a pad layer over the sidewalls of the source / drain region before etching the second epitaxial semiconductor layer to form an extended contact trench, such that the pad layer extends to a depth above the top surface of the first channel layer. According to various embodiments, the plurality of stacked channel layers include at least three channel layers, having the thinnest channel layer closest to the doped region.

[0110] According to various embodiments, the semiconductor device includes: a plurality of spaced-apart stacked channel layers and source / drain regions, such that the plurality of stacked channel layers include a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; a source / drain structure including a first epitaxial semiconductor layer formed above the source / drain regions, such that the source / drain structure contacts the plurality of stacked channel layers; and a source / drain contact formed above the source / drain structure, such that the bottom surface of the source / drain contact is lower than the bottom surface of the first channel layer. According to various embodiments, the semiconductor device further includes: a second epitaxial semiconductor layer formed below the first epitaxial semiconductor layer; and a dielectric layer formed between the first epitaxial semiconductor layer and the second epitaxial semiconductor layer.

[0111] According to various embodiments, the semiconductor device includes: a doped portion of a first epitaxial semiconductor layer located below the bottom surface of a source / drain contact. According to various embodiments, a plurality of stacked channel layers include at least three channel layers having a thinnest channel layer closest to the doped portion, and the plurality of stacked channel layers are nanosheets or nanowires. According to various embodiments, the semiconductor device includes a pad layer formed above the sidewalls of the source / drain region such that the pad layer extends to a depth below the bottom surface of the first channel layer; and a silicide layer formed between the doped portion of the first epitaxial semiconductor layer and the bottom surface of the source / drain contact.

[0112] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes as this disclosure and / or achieving the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: Alternately deposit sacrificial layers and channel layers to form a semiconductor stack over a substrate, wherein the channel layer includes a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; Pattern the semiconductor stack to form fins; The fins are recessed in the source / drain region to form source / drain openings; Semiconductor material is epitaxially deposited in the source / drain opening to form a source / drain structure; Remove the sacrificial layer in the channel region adjacent to the source / drain region, so that the surface of the channel layer is exposed; A gate dielectric is deposited above the surface of the channel layer, and a conductive material is deposited above the gate dielectric to form a gate electrode surrounding the channel layer; and Conductive material is deposited in the source / drain opening above the source / drain structure to form a source / drain contact with a bottom surface lower than the bottom surface of the first channel layer.

2. The method according to claim 1, further comprising: Before epitaxially depositing the semiconductor material to form the source / drain structure: An undoped semiconductor layer is epitaxially deposited above the surface of the source / drain opening; and A first isolation dielectric layer is deposited over the undoped semiconductor layer.

3. The method according to claim 1, wherein: The first trench layer has a first thickness, and the second trench layer has a second thickness; Each of the first thickness and the second thickness is between 2 nm and 10 nm; and The difference between the first thickness and the second thickness is between 0.5 nm and 5 nm.

4. The method according to claim 1, further comprising: An interlayer dielectric layer is deposited above the source / drain structure; The interlayer dielectric layer is etched to form contact trenches through the interlayer dielectric layer, thereby exposing the source / drain structure; The source / drain structure is etched through the contact trench to form an extended contact trench; An implantation operation is performed to form a doped region in the source / drain structure through the extended contact trench; and The source / drain contacts are formed in the extended contact trench above the source / drain structure.

5. The method according to claim 4, further comprising: Before etching the source / drain structure, a liner is formed on the sidewall of the contact trench; A silicide layer is formed over the doped region; and The source / drain contacts are formed above the silicide layer.

6. The method according to claim 5, wherein, Alternatingly depositing the sacrificial layer and the channel layer to form the semiconductor stack further includes depositing at least three channel layers such that a third channel layer is formed beneath the second channel layer.

7. The method according to claim 6, wherein, The at least three channel layers include the thinnest channel layer closest to the doped region.

8. The method according to claim 2, further comprising: A second isolation dielectric layer is formed between the substrate and the bottom surface of the gate electrode; The first isolation dielectric layer and the second isolation dielectric layer include one or more of silicon nitride, silicon oxide, silicon oxynitride, silicon carbonitride, silicon carbon oxyoxide, or high-k dielectrics, wherein the high-k dielectrics include one or more of HfO2, ZrO2, Al2O3, TiO2, La2O3, Y2O3, and BaSrTiO3.

9. A method for manufacturing a semiconductor device, comprising: A full-ring gate field-effect transistor structure is formed, comprising multiple stacked channel layers and source / drain regions, wherein the multiple stacked channel layers include a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; A first epitaxial semiconductor layer is deposited over the surface of the source / drain region; A dielectric layer is deposited above the first epitaxial semiconductor layer; A second epitaxial semiconductor layer is deposited above the dielectric layer; Etching the second epitaxial semiconductor layer to form an extended contact trench extending to a depth below the bottom surface of the first channel layer; and Conductive material is deposited over the second epitaxial semiconductor layer in the extended contact trench to form a source / drain contact having a bottom surface lower than the bottom surface of the first channel layer.

10. A semiconductor device, comprising: Multiple spaced-apart stacked channel layers and source / drain regions, wherein the multiple stacked channel layers include a first channel layer and a second channel layer located below the first channel layer and thinner than the first channel layer; A source / drain structure, including a first epitaxial semiconductor layer formed over the source / drain regions, such that the source / drain structure contacts the plurality of stacked channel layers; and Source / drain contacts are formed above the source / drain structure, such that the bottom surface of the source / drain contacts is lower than the bottom surface of the first channel layer.

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