Enhanced transistor and manufacturing method thereof

Abstract

The invention provides an enhanced transistor and a manufacturing method thereof, and belongs to the technical field of semiconductors. The enhanced transistor comprises a channel layer, a barrier layer, a gate dielectric layer and a plurality of gates. The channel layer, the barrier layer and the gate dielectric layer are stacked in sequence; the plurality of grid electrodes are located at one side, far away from the channel layer, of the grid dielectric layer and are arranged at intervals along a first direction, and the grid electrode distance between two adjacent grid electrodes is smaller than 200nm. The performance of the device can be improved.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, and specifically relates to an enhancement transistor and a method for manufacturing the same. Background Technology

[0002] Transistors, especially gallium nitride high electron mobility transistors, have shown great application potential in the field of high-frequency, high-power electronic devices due to their excellent wide bandgap characteristics.

[0003] In related technologies, to improve device performance (such as pinch-off efficiency), extremely narrow and fully depleted channels are typically constructed in transistors. That is, a typical transistor structure includes a channel layer, a barrier layer stacked on the channel layer, a gate dielectric layer stacked on the barrier layer, and multiple gates located on the gate dielectric layer. Each gate applies an electric field to the channel layer through the gate dielectric layer to deplete the underlying two-dimensional electron gas, forming a depletion region.

[0004] However, due to the limitations of current photolithography process precision, the spacing between adjacent gates is typically greater than 200 nm. This size limitation makes it difficult for the depletion regions generated by adjacent gates to overlap sufficiently, preventing the two-dimensional electron gas in the region between the two gates from being completely pinched off. This affects the effective control of carriers in the channel layer and restricts further improvements in device performance. Summary of the Invention

[0005] This disclosure provides an enhancement transistor and a method for fabricating the same, which can improve device performance. The technical solution is as follows: This disclosure provides an enhancement transistor, which includes a channel layer, a barrier layer, a gate dielectric layer, and a plurality of gates; the channel layer, the barrier layer, and the gate dielectric layer are stacked sequentially; the plurality of gates are located on the side of the gate dielectric layer away from the channel layer and are arranged at intervals along a first direction, and the gate spacing between two adjacent gates is less than 200 nm.

[0006] In another implementation of this disclosure, the enhancement transistor further includes a first dielectric layer stacked on the barrier layer, the first dielectric layer having first grooves corresponding one-to-one with the plurality of gates; the barrier layer and the channel layer below the first grooves have a plurality of second grooves, the second grooves corresponding one-to-one with the first grooves and communicating to form gate grooves; along the first direction, the spacing between two adjacent first grooves is less than 200 nm.

[0007] In another implementation of this disclosure, the opening size of the first groove is larger than the opening size of the second groove, and the opening sizes of both the first groove and the second groove are the lengths of the openings along the first direction.

[0008] In another implementation of this disclosure, the opening size of the first groove is greater than 500 nm and less than 600 nm, and the opening size of the second groove is not less than 400 nm.

[0009] In another implementation of this disclosure, the first dielectric layer is a SiO2 layer, an Al2O3 layer, a SiN layer, or a SiO2 layer. x N y layer.

[0010] In another implementation of this disclosure, the enhancement transistor further includes a first passivation layer and a stop layer sequentially stacked on the barrier layer, the stop layer being located on the side of the first dielectric layer facing the barrier layer; the first groove penetrates the first passivation layer and the stop layer, and the sidewall of the first groove located at the interface between the first passivation layer and the stop layer has a third step and a fourth step, the third step and the fourth step being located on both sides of the first groove along a direction perpendicular to the first direction.

[0011] In another implementation of this disclosure, the first passivation layer is a SiN layer and the stop layer is an AlN layer.

[0012] On the other hand, this disclosure also provides a method for fabricating an enhancement transistor, the method comprising: sequentially forming a stacked channel layer, a barrier layer and a gate dielectric layer; forming a plurality of gates on the gate dielectric layer, the plurality of gates being arranged at intervals along a first direction, the gate spacing between two adjacent gates being less than 200 nm.

[0013] In another implementation of this disclosure, the sequential formation of the channel layer, barrier layer, and gate dielectric layer includes: forming the channel layer, barrier layer, and first dielectric layer sequentially stacked on a substrate; performing wet etching on the first dielectric layer to form a pre-groove for defining a first trench; etching the first dielectric layer, the channel layer, and the barrier layer to transform the pre-groove into a first trench, and forming a plurality of second trenches in the barrier layer and the channel layer below the first trench, wherein the second trenches correspond one-to-one with and communicate with the first trenches to form a gate trench, the first trenches extending from the upper surface of the first dielectric layer to the surface of the barrier layer facing the first dielectric layer; the opening size of the first trench is larger than the opening size of the second trenches, the opening size of both the first trenches and the second trenches is the length of the opening along the first direction, and the spacing between two adjacent first trenches is less than 200 nm; forming the gate dielectric layer, the gate dielectric layer covering the bottom and sidewalls of the gate trench and the upper surface of the first dielectric layer.

[0014] In another implementation of this disclosure, the wet etching of the first dielectric layer, the channel layer, and the barrier layer includes: forming a metal mask layer on the first dielectric layer, the metal mask layer completely filling the pre-grooves and covering the upper surface of the first dielectric layer; forming a dielectric mask layer on the metal mask layer, the dielectric mask layer having dielectric grooves aligned one-to-one with the plurality of pre-grooves; using the dielectric mask layer as a mask, wet etching the metal mask layer to form a plurality of metal grooves connecting the corresponding pre-grooves and the dielectric grooves, the opening size of the metal grooves along the first direction being larger than the opening size of the pre-grooves; removing the dielectric mask layer, and using the metal mask layer as a mask, etching the first dielectric layer, the channel layer, and the barrier layer, thereby transforming the pre-grooves into the first grooves, and forming corresponding second grooves in the barrier layer and the channel layer directly below each first groove.

[0015] The beneficial effects of the technical solutions provided in this disclosure are: When the enhancement transistor provided in this embodiment is used, since the gate spacing between two adjacent gates in the enhancement transistor is less than 200nm, when each gate applies an electric field to the channel layer through the gate dielectric layer, the depletion regions under the adjacent gates will overlap, thereby achieving full depletion turn-off of the channel layer and improving the performance of the device. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This disclosure provides a schematic diagram of the structure of an enhancement transistor. Figure 2 for Figure 1 Top view; Figure 3 for Figure 2 A cross-sectional view along the BB direction; Figure 4 This is a flowchart illustrating a method for fabricating an enhancement transistor according to an embodiment of this disclosure; Figure 5 This is a flowchart illustrating a method for fabricating an enhancement transistor according to an embodiment of this disclosure; Figure 6 This is a schematic diagram of the extensional structure; Figure 7This is a schematic diagram of an extensional structure with pre-grooved grooves; Figure 8 This is a schematic diagram of the structure of a metal mask layer deposited on an epitaxial structure; Figure 9 This is a schematic diagram of the structure of the deposition medium mask layer on top of the metal mask layer; Figure 10 This is a schematic diagram of the metal mask layer after wet etching. Figure 11 This is a schematic diagram after the dielectric mask layer has been removed.

[0018] The symbols in the diagram represent the following meanings: 1. Channel layer; 2. Barrier layer; 3. Gate dielectric layer; 4. Gate; 5. First dielectric layer; 6. First passivation layer; 7. Stop layer; 8. Buffer layer; 9. Second passivation layer; 10. Source; 20. Drain; 40. Gate metal layer; 100. Substrate; 105. Metal mask layer; 106. Dielectric mask layer; 201, pre-groove; 101, first groove; 102, second groove; 301, dielectric groove; 401, metal groove; 300, second photoresist mask; 601. First step; 602. Second step; 603. Third step; 604. Fourth step. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0020] This disclosure provides an enhanced transistor, such as... Figure 1 As shown, the enhancement-mode transistor includes a channel layer 1, a barrier layer 2, a gate dielectric layer 3, and multiple gates 4. The channel layer 1, the barrier layer 2, and the gate dielectric layer 3 are stacked sequentially.

[0021] Figure 2 for Figure 1 Top view ( Figure 1 for Figure 2 (Cross-sectional view along the AA direction), see Figure 2 Multiple gates 4 are located on the side of the gate dielectric layer 3 away from the channel layer 1 and are arranged at intervals along the first direction, with the gate spacing d between two adjacent gates 4 being less than 200nm.

[0022] When the enhancement transistor provided in this embodiment is used, since the gate spacing d between two adjacent gates 4 is less than 200nm, when each gate 4 applies an electric field to the channel layer 1 through the gate dielectric layer 3, the depletion regions under the adjacent gates 4 will overlap, thereby achieving full depletion turn-off of the channel layer 1 and improving the performance of the device.

[0023] In this embodiment, the gate spacing d between two adjacent gates 4 is 120, 130, or 150 nm. This can effectively improve the performance of the device.

[0024] Optionally, the channel layer 1 is a GaN layer, and the barrier layer 2 is an AlGaN layer. This allows for the formation of a heterojunction, inducing a high concentration of two-dimensional electron gas density in the channel layer 1 through polarization effects.

[0025] Figure 3 for Figure 2 See the sectional view along the BB direction. Figure 3 Optionally, the enhancement-mode transistor further includes a first dielectric layer 5 stacked on the barrier layer 2, the first dielectric layer 5 having first recesses 101 corresponding one-to-one with a plurality of gates 4. The barrier layer 2 and the channel layer 1 below the first recesses 101 have a plurality of second recesses 102, the second recesses 102 corresponding one-to-one with the first recesses 101 and communicating to form gate recesses. Along the first direction, the spacing between two adjacent first recesses 101 is less than 200 nm.

[0026] In the above implementation, the first dielectric layer 5 is used to contact the barrier layer 2 (AlGaN) and effectively passivate the surface states of the barrier layer, suppressing current collapse and ensuring the dynamic characteristics and long-term reliability of the device. The first groove 101 and the second groove 102 are connected to define the gate groove for accommodating the gate.

[0027] Optionally, the opening size of the first groove 101 is larger than the opening size of the second groove 102, and the opening size of both the first groove 101 and the second groove 102 is the length (i.e. the width) of the opening along the first direction a.

[0028] That is, the sidewall of the first groove 101 near the gate dielectric layer 3 has a first step 601, and the sidewall at the connection with the corresponding second groove 102 has a second step 602.

[0029] Optionally, the opening size of the first groove 101 is greater than 500 nm and less than 600 nm, and the opening size of the second groove 102 is not less than 400 nm.

[0030] This ensures that the spacing between two adjacent first grooves 101 is less than 200nm, thereby making the gate spacing between two adjacent gates 4 less than 200nm.

[0031] Optionally, the first dielectric layer 5 is a SiO2 layer, an Al2O3 layer, a SiN layer, or a Si x N y layer.

[0032] SiO2 layer, Al2O3 layer, SiN layer or Si x N y The channels are all excellent insulators with extremely high resistivity. They form a large conduction band and valence band offset with common semiconductor materials (such as GaN, GaAs, and Si). This large band difference acts like a high barrier above the channel layer, effectively preventing gate electrons from tunneling into the channel layer, thereby significantly reducing the gate leakage current of the device.

[0033] Optionally, the thickness of the first dielectric layer 5 is 80nm-200nm.

[0034] In the above implementation, this thickness ensures that the first dielectric layer 5 has sufficient process redundancy in wet etching and subsequent dry etching in order to form stepped sidewalls, providing the necessary mechanical support and insulation strength for the gate field plate, while avoiding excessive stress and parasitic capacitance introduced by an excessively thick dielectric.

[0035] See also Figure 1 and Figure 3 Optionally, the enhancement transistor further includes a first passivation layer 6 and a stop layer 7 sequentially stacked on the barrier layer 2, with the stop layer 7 located on the side of the first dielectric layer 5 facing the barrier layer 2.

[0036] The first groove 101 penetrates the first passivation layer 6 and the stop layer 7, and the sidewall of the first groove 101 located at the interface between the first passivation layer 6 and the stop layer 7 has a third step 603 and a fourth step 604, which are located on both sides of the first groove 101 along a direction perpendicular to the first direction.

[0037] In the above implementation, by setting a first passivation layer 6 and a stop layer 7, and utilizing the difference in etching selectivity between the two materials during the etching process, a third step 603 and a fourth step 604 can be formed at the interface. The third step 603 and the fourth step 604 provide a laterally extended support substrate for the subsequently deposited gate metal, allowing the gate metal to fill the first groove 101 to form the gate while simultaneously covering the third step 603 and the fourth step 604, thus integrating them into a gate field plate structure. This design eliminates the need for additional photolithography steps in forming the gate field plate, simplifying the process, more effectively modulating the gate edge electric field, and improving the device's breakdown voltage and reliability.

[0038] Optionally, the first passivation layer 6 is a SiN layer. The first passivation layer 6 is made of SiN material, whose high density can effectively block the intrusion of water vapor and impurities to protect the surface of the barrier layer and suppress interlayer diffusion. Its excellent insulation and dielectric properties can reduce gate leakage current, optimize gate switching performance, and improve the interfacial compatibility and structural stability of the film layers.

[0039] Optionally, the stop layer 7 is an AlN layer. The high thermal stability and chemical inertness of the stop layer 7 can effectively block the diffusion of interlayer materials and avoid cross-interference of film functions. At the same time, its excellent lattice compatibility improves the interfacial adhesion between upper and lower layers and can define the stacked structure boundary, ensuring the structural integrity and electrical performance stability of the transistor gate region.

[0040] See also Figure 1 Optionally, the enhancement transistor also includes a substrate 100 and a buffer layer 8 sequentially stacked on the substrate 100, wherein the side of the buffer layer 8 away from the substrate 100 is connected to the channel layer 1.

[0041] In the above implementation, the buffer layer 8 connects the substrate 100 and the channel layer 1, which can optimize the interface matching between the substrate 100 and the channel layer 1 and help improve the electrical performance and stability of the device.

[0042] The buffer layer 8 is an AlN layer. This further enhances the lattice matching between the substrate 100 and the channel layer 1, while improving the thermal stability and electrical performance of the device.

[0043] Optionally, the enhancement transistor further includes a second passivation layer 9, which covers the surface of the first dielectric layer 5 and the surfaces and sidewalls of the plurality of gates 4.

[0044] The second passivation layer 9 can achieve all-round encapsulation protection. On the one hand, it isolates external interference such as moisture and impurities, and prevents the first dielectric layer 5 and gate 4 from being eroded or oxidized, reducing interface defects and leakage current. On the other hand, it strengthens the structural stability of gate 4, prevents gate 4 from being physically damaged or its electrical performance degraded in subsequent processes or operations, and improves the structural integrity of the overall film stack, ensuring the electrical stability and reliability of the transistor during long-term operation.

[0045] Optionally, the second passivation layer 9 is a SiN layer. The second passivation layer 9 is made of SiN material, whose high density and excellent barrier properties can isolate moisture, impurities and other external environmental interferences in all directions, effectively preventing oxidation, erosion or contamination of the surface and sidewalls of the first dielectric layer 5 and the gate 4, and significantly reducing interface defects and gate leakage current; at the same time, SiN has good mechanical stability and dielectric properties, which can not only strengthen the gate structure and prevent the gate from being physically damaged in subsequent processes, but also optimize the insulation compatibility of the overall stacked structure, ensuring the electrical performance stability and reliability of the transistor during long-term operation.

[0046] Optionally, the enhancement-mode transistor also includes a source 10 and a drain 20, which are located on opposite sides of the gate 4. The source 10 and drain 20 require lateral electrical isolation via mesa isolation or ion implantation, and ohmic contact is achieved with the barrier layer 2 through openings in the barrier layer 2 to efficiently inject and collect current. The gate 4 needs to extend to the lower surface of the channel layer 1, ensuring no two-dimensional electron flow passes beneath it.

[0047] Optionally, the material of gate 4 is TiN, TaN, or W. The thickness of gate 4 (the thickness deposited on the surface of the first value layer) is 200nm-400nm. In this embodiment, the gate 4 is made of TiN. The thickness of the gate 4 is 300 nm. TiN has a very low resistivity, which can reduce the series resistance of the gate itself and reduce the gate signal transmission delay, making it particularly suitable for high-frequency and high-speed devices.

[0048] In this embodiment, the thickness of gate 4 is 300 nm. A thickness of 300 nm allows the gate to provide sufficient conductive cross-sectional area, further reducing series resistance. At the same time, it does not increase the manufacturing complexity due to excessive thickness.

[0049] Optionally, the gate dielectric layer 3 is a SiO2 or SiN layer.

[0050] SiO2 or SiN layers are excellent insulators with extremely high resistivity. They form a large conduction band and valence band offset with common semiconductor materials (such as GaN, GaAs, and Si). This large band difference acts like a high barrier above the channel layer, effectively preventing gate electrons from tunneling into the channel layer, thereby significantly reducing the gate leakage current of the device.

[0051] This disclosure also provides a method for fabricating an enhancement-mode transistor, such as... Figure 4 As shown, the manufacturing method includes: S401: The channel layer, barrier layer and gate dielectric layer are formed sequentially.

[0052] S402: Multiple gates are formed on the gate dielectric layer.

[0053] Multiple gates are located on the side of the gate dielectric layer away from the channel layer and are arranged in a row. The gate spacing between two adjacent gates is less than 200nm. Each gate applies an electric field to the channel layer through the gate dielectric layer so that the depletion regions under adjacent gates can overlap each other.

[0054] The above manufacturing methods have the same beneficial effects as the aforementioned enhanced transistors, and will not be repeated here.

[0055] This disclosure also provides another method for fabricating an enhancement transistor, such as... Figure 5 As shown, the manufacturing method includes: S501: A channel layer, a barrier layer, and a first dielectric layer are formed sequentially on a substrate.

[0056] Optionally, step S501 includes the following steps: Step 1: Form a stacked channel layer 1 and barrier layer 2 on the substrate.

[0057] Figure 6 See the schematic diagram of the extensional structure. Figure 6 Before forming the channel layer 1 on the substrate, a buffer layer 8 is first formed on the surface of the substrate 100 using a metal-organic chemical vapor deposition (MOCVD) process to alleviate the lattice mismatch between the channel layer 1 and the substrate 100. Then, the channel layer 1 and the barrier layer 2 are formed on the buffer layer 8 using MOCVD.

[0058] In this embodiment, the channel layer 1 is a GaN layer and the barrier layer 2 is an AlGaN layer.

[0059] Step 2: Form a first passivation layer and a stop layer stacked on barrier layer 2.

[0060] After forming the channel layer 1 and the barrier layer 2, the first passivation layer 6 and the stop layer 7 are grown in situ on the barrier layer 2 within the MOCVD reaction chamber.

[0061] In this embodiment, the first passivation layer 6 is a SiN layer, and the stop layer 7 is an AlN layer.

[0062] Step 3: Form the first dielectric layer on the stop layer.

[0063] The first dielectric layer 5 is also formed by MOCVD.

[0064] The first dielectric layer 5 can be a SiO2 layer.

[0065] S502: Perform wet etching on the first dielectric layer to form a pre-groove in the first dielectric layer for defining the first groove.

[0066] The spacing d1 between two adjacent pre-grooves 201 and the width d2 of each pre-groove are both less than 450nm and greater than 200nm.

[0067] In this embodiment, the spacing d1 between two adjacent pre-grooves 201 and the width d2 of the pre-grooves 201 are both 400nm.

[0068] Figure 7See the schematic diagram of the extensional structure with pre-grooved grooves. Figure 7 After the first dielectric layer 5 is formed on the stop layer 7, a first photoresist mask is first formed on the surface of the first dielectric layer 5 by photolithography. Then, the structure is dry etched using the first photoresist mask as a mask until the interface between the stop layer 7 and the first dielectric layer 5 is formed, thereby forming a plurality of pre-grooves 201 in the first dielectric layer 5.

[0069] After the pre-groove 201 is formed, the first photoresist mask is removed.

[0070] S503: Etch the stop layer and the first passivation layer so that the pre-groove extends from the first dielectric layer to the surface of the barrier layer.

[0071] Optionally, step S503 includes the following steps: Step 1: Remove the exposed stop layer 7 below the pre-groove 201.

[0072] Wet etching was used to remove the exposed stop layer 7 below the pre-groove 201.

[0073] In this embodiment, 85% hot phosphoric acid is used for wet etching of the stop layer 7, and the etching temperature is 160°C-180°C. This etching process will not affect the first dielectric layer 5.

[0074] Step 2: Remove the first passivation layer within the pre-groove.

[0075] A second photolithography process is performed. A second photoresist mask 300 is formed on the surface of the first dielectric layer 5. Then, using the second photoresist mask 300 as a mask, dry etching is performed on the structure obtained in the first step to remove the first passivation layer 6 in the pre-groove 201, so that the pre-groove 201 extends from the first dielectric layer 5 to the surface of the barrier layer 2.

[0076] In the above process, the first photolithography and dry etching form a pre-groove 201 with a stop layer as the bottom in the first dielectric layer. The contour of the pre-groove 201 determines the coverage of the gate field plate. Then, the stop layer 7 is selectively removed by wet etching to provide a step interface for separating the gate field plate and the gate area.

[0077] like Figure 1 As shown, the second photolithography step involves selectively etching the underlying first passivation layer 6 within the defined pre-groove 201, extending the pre-groove 201 to the channel layer 1. Simultaneously, a third step 603 and a fourth step 604 are formed between the first passivation layer 6 and the stop layer 7. The third step 603 and the fourth step 604 are located on opposite sides of the pre-groove 201. This allows the finally filled gate to simultaneously form the bottom gate electrode and the gate field plate covering the third step 603 and the fourth step 604.

[0078] The first photolithography etching stops at the interface between the first dielectric layer 5 and the stop layer 7, forming a pre-groove 201 in the first dielectric layer 5 (that is,...). Figure 1 (The location of the first groove 101). Next, wet etching is used to remove the stop layer 7. Then, a second photolithography is performed. Because the masks used in the two photolithography processes are different, along the direction perpendicular to the first direction (i.e., the arrangement direction of the source 10 and drain 20), the window defined by the second photolithography is smaller than the pre-groove 201 (that is, the opening of the first groove in the first passivation layer 6 is smaller than the opening size of the first groove in the upper stop layer 7). Therefore, a third step 603 and a fourth step 604 can be formed between the first passivation layer 6 and the stop layer 7. Along the first direction, the window size defined by the second photolithography is the same as the opening size of the pre-groove 201.

[0079] In other examples, if it is not necessary to form a gate field plate, the first dielectric layer can be formed directly on the barrier layer, and pre-grooves can be formed directly in the first dielectric layer by photolithography.

[0080] S504: Etching of the first dielectric layer, channel layer, and barrier layer.

[0081] The pre-groove 201 is enlarged along the first direction to become a first groove 101, and a plurality of second grooves 102 are formed in the barrier layer and channel layer below the first groove. The second grooves 102 correspond one-to-one with the first grooves 101 and are connected to form gate grooves. The first groove extends from the upper surface of the first dielectric layer to the surface of the barrier layer facing the first dielectric layer. The opening size of the first groove is larger than the opening size of the second groove. The opening size of both the first groove and the second groove is the length of the opening along the first direction, and the spacing between two adjacent first grooves is less than 200 nm.

[0082] Optionally, step S504 includes: Step 1: Remove the second photoresist mask 300 after the second photolithography.

[0083] Step 2: Form a metal mask layer 105 on the surface of the first dielectric layer 5.

[0084] Figure 8 This is a schematic diagram of the structure of the metal mask layer deposited on the epitaxial structure, as shown below. Figure 8 As shown, Figure 7 The second photoresist mask 300 is removed, and a metal mask layer 105 is deposited over the entire surface. The metal mask layer 105 completely fills the pre-groove 201 and covers the surface of the first dielectric layer 5.

[0085] For example, the metal mask layer 105 is a TiN, Ti, or Al layer.

[0086] In this embodiment, the metal mask layer 105 is a TiN layer. TiN has excellent chemical inertness and can exhibit a very high etching selectivity during subsequent epitaxial etching, ensuring that the metal mask layer has stable shape and controllable loss during the etching process.

[0087] The thickness of the metal mask layer 105 is 400nm-600nm. In this embodiment, the thickness of the metal mask layer 105 is 500nm.

[0088] Step 3: Form a dielectric mask layer 106 on the metal mask layer 105. The dielectric mask layer 106 has dielectric grooves 301 that are aligned one-to-one with a plurality of pre-grooves 201.

[0089] Figure 9 This is a schematic diagram of the structure of the deposition medium mask layer on top of the metal mask layer, as shown below. Figure 9 As shown, a dielectric mask layer 106 is deposited over the entire surface of the metal mask layer 105, and multiple dielectric grooves 301 are formed in the dielectric mask layer 106 by photolithography and dielectric etching. The multiple dielectric grooves 301 are aligned one-to-one with the multiple pre-grooves 201.

[0090] The one-to-one alignment of the dielectric groove 301 and the pre-groove 201 means that their orthogonal projections on the surface of the substrate 100 completely overlap.

[0091] The dielectric mask layer 106 is made of SiO2, Al2O3 or Si x N y .

[0092] In this embodiment, the dielectric mask layer 106 is a SiO2 layer. The material selection for the dielectric mask layer is mainly based on the etching selectivity and the wet etching rate.

[0093] Since the dielectric groove 301 is created by dry etching in the dielectric mask layer, the etching gas may over-etch and reach the underlying metal mask layer 105. In this case, under the process conditions for etching the dielectric mask layer 106, the etching selectivity ratio between the etching rate of the dielectric mask layer 106 and the metal mask layer 105 needs to be very high to ensure that the surface of the metal mask layer 105 remains intact after the dielectric mask layer 106 is etched, providing a smooth starting surface for subsequent wet etching. If the surface of the metal mask layer has been damaged by dry etching, the wet etching will become uneven. Simultaneously, when performing wet etching on the metal mask layer 105, the dielectric mask layer 106 is needed as a mask for wet etching. This requires the dielectric mask layer 106 to remain stable during the wet etching process, with an extremely slow etching rate, and a high wet selectivity ratio relative to the metal mask layer 105. Therefore, the material of the dielectric mask layer 106 must meet the above conditions.

[0094] The thickness of the dielectric mask layer 106 is 200nm-300nm. The spacing d4 between two adjacent dielectric grooves 301 and the width d3 of each dielectric groove 301 are both less than 450nm and greater than 200nm.

[0095] In this embodiment, the inclination angle formed between the sidewall of the opening from the top edge to the bottom edge in the dielectric groove 301 and the horizontal substrate surface is greater than 80 degrees and less than or equal to 90 degrees. If the angle is small (gentle sidewall slope), the bottom size of the opening will be significantly smaller than the top size. When using this opening as a mask to etch the underlying metal mask layer, the etched metal groove will be larger than the top size of the dielectric groove and difficult to predict. However, if the angle is large, the size of the formed metal groove is easier to control when wet etching the metal mask layer.

[0096] The opening width d3 of the dielectric groove 301 is 400nm, and the spacing d4 between adjacent dielectric grooves 301 is 400nm.

[0097] Step 4: Using the dielectric mask layer as a mask, wet etching is performed on the metal mask layer 105 to form multiple metal grooves 401 that connect the pre-grooves 201 and the dielectric grooves 301 that correspond to each other.

[0098] right Figure 9 The metal mask layer 105 in the pre-groove 201 is subjected to wet etching to completely remove the metal mask layer 105 in the pre-groove 201.

[0099] By utilizing the isotropic nature of wet corrosion, the metal mask layer 105 below the dielectric mask layer 106 is subjected to lateral corrosion to reduce the spacing d5 between adjacent metal grooves 401 in the metal mask layer 105.

[0100] Figure 10 This is a schematic diagram of the metal mask layer after wet etching, as shown. Figure 10 As shown, since wet etching is isotropic, while removing the metal mask layer 105 within the pre-groove 201 along a direction perpendicular to the first direction (direction b), the metal mask layer 105 is also etched laterally. This results in the width d6 of the metal groove 401 formed in the metal mask layer 105 being greater than the width d1 of the pre-groove 201. Correspondingly, the distance d5 between two adjacent metal grooves 401 is less than the distance d2 between two adjacent pre-grooves 201.

[0101] In this embodiment, d5 is no greater than 150nm. For example, d5 is 120nm.

[0102] Optionally, when etching the metal mask layer 105, the etching solution selected is a mixture of NH4OH, H2O2 and H2O, H2O2, aqua regia, or a mixture of HF acid and nitric acid.

[0103] In this embodiment, the etching solution used to etch the metal mask layer 105 is a mixture of NH4OH, H2O2 and H2O, with a volume ratio of NH4OH:H2O2:H2O=1:1:5, and the etching temperature is 60℃ to 80℃.

[0104] Step 5: Remove the dielectric mask layer and use the metal mask layer as a mask to etch the first dielectric layer, the channel layer, and the barrier layer.

[0105] For example, the dielectric mask layer is removed by wet etching, and the etching solution used is buffer oxide etch (BOE), diluted HF or high temperature H3PO4.

[0106] In this embodiment, the etchant used in the wet etching of the dielectric mask layer is BOE, which has a more stable etching rate and better controllability compared to other methods.

[0107] Figure 11 For a schematic diagram after removing the dielectric mask layer, see [link / reference]. Figure 11 After removing the dielectric mask layer, the entire structure is epitaxially etched using the metal mask layer as a mask, which increases the width of the pre-groove 201 to become the first groove 101. At the same time, a second groove 102 communicating with the first groove 101 is formed in the barrier layer and channel layer directly below each first groove 101.

[0108] When using a metal mask layer, dry etching with plasma BCl3 or Cl2 is employed to completely etch the channel layer 1 below the first groove 101, ultimately leaving it within the buffer layer 8. After etching, the spacing between adjacent first grooves 101 is less than 150 nanometers.

[0109] During etching, the etching gas can also perform lateral and vertical etching on the first dielectric layer 5, the first passivation layer 6, and the stop layer 7 while vertically etching the barrier layer and the channel layer. However, the lateral and vertical etching rate on the first dielectric layer 5, the first passivation layer 6, and the stop layer 7 is much lower than the vertical etching rate on the barrier layer and the channel layer. Therefore, a second step 602 is formed between the barrier layer 2 and the first passivation layer 6, and a first step 601 is formed on the top of the first dielectric layer 5.

[0110] S505: Remove the metal mask layer and form a gate dielectric layer in the gate recess and on the surface of the first dielectric layer.

[0111] The gate dielectric layer covers the bottom and sidewalls of the gate recess and the upper surface of the first dielectric layer.

[0112] See Figure 11Based on step S505, the remaining metal mask layer 105 on the surface of the first dielectric layer 5 is removed, and a gate dielectric layer 3 is deposited on the entire surface to obtain the desired result. Figure 3 The structure shown.

[0113] The etching solution used to remove the metal mask layer is the same as the etching solution used in step S504 above, and the etching conditions are also the same, so it will not be described again here.

[0114] Among them, the gate dielectric layer 3 is a SiO2 or SIN layer.

[0115] In this embodiment, the gate dielectric layer 3 is a SiO2 layer. Because SiO2 has an extremely low interface state density, it can effectively suppress carrier traps. At the same time, the process of forming the SiO2 film is relatively mature, making the SiO2 layer a uniform, dense, and high-quality thin film, thereby providing a reliable and repeatable insulating interface for the device.

[0116] S506: Multiple gates are formed on the gate dielectric layer, such that each gate is located in a corresponding gate recess.

[0117] See also Figure 3 A gate metal layer 40 is deposited on the gate dielectric layer, and the gate metal layer 40 is located in the gate recess, so that a gate 4 is formed in each gate recess, and the tops of the multiple gates 4 are interconnected through the gate metal layer 40.

[0118] After the gate is formed, a high-temperature rapid thermal annealing is performed to optimize the interface contact between the gate and the gate dielectric layer. The rapid annealing temperature is 500-600 degrees Celsius, preferably 550 degrees Celsius, and the annealing time is 60-100 seconds.

[0119] The gate metal layer is a TiN, TaN, or W layer.

[0120] In this embodiment, the gate metal layer is a TiN layer. TiN has a high melting point and a low diffusion coefficient, which can maintain morphological stability during subsequent high-temperature processes and prevent harmful reactions with the gate dielectric layer.

[0121] The thickness of the gate metal layer (the thickness deposited on the surface of the gate dielectric layer) is 200nm-400nm.

[0122] In this embodiment, the thickness of the gate metal layer is 300 nm. This thickness ensures that the gate has a sufficiently low sheet resistance, effectively reducing the parasitic resistance of the gate; at the same time, this thickness also provides good film density, avoiding problems such as discontinuity caused by being too thin or stress cracks caused by being too thick.

[0123] S507: A second passivation layer is formed on the surface of the gate metal layer.

[0124] See also Figure 3 A second passivation layer 9 is deposited on the gate metal layer. The second passivation layer can effectively isolate the gate from the subsequent interconnect layer to prevent short circuits; moreover, the second passivation layer can also block environmental factors such as moisture and impurity ions from intruding, protecting the sensitive gate and metal.

[0125] The second passivation layer 9 is a SiO2 or SiN layer.

[0126] In this embodiment, the second passivation layer 9 is a SiO2 layer. SiO2 has good insulating properties and can be used to obtain a dense film with excellent coverage and low internal stress through plasma-enhanced chemical vapor deposition, thereby achieving effective passivation and reliable isolation of the gate.

[0127] S508: The source and drain are fabricated on the second passivation layer.

[0128] The source 10 and drain 20 are located on opposite sides of the plurality of gates 4, and both the source 10 and drain 20 are electrically connected to the barrier layer 2.

[0129] The manufacturing method provided in this disclosure has the following significant technical effects: (1) Breaking through the limits of traditional photolithography: By utilizing the isotropic properties of wet etching of metal, the spacing between gates is reduced by lateral etching of the metal mask layer, achieving channel lines with resolution far superior to current photolithography processes (up to 150nm or less), effectively avoiding the disadvantages of high-cost and low-efficiency solutions such as electron beam lithography.

[0130] (2) Simple process and low cost: The whole process is based on mature semiconductor planar process, only adding a controllable wet etching step. It does not require the introduction of expensive equipment such as extreme ultraviolet lithography or electron beam lithography, which greatly reduces the preparation cost and process complexity, and is conducive to large-scale industrial production.

[0131] (3) Wide process window, good repeatability and consistency. The spacing between gates is mainly determined by the wet etching time and epitaxial etching conditions, rather than entirely by photolithography precision. This method has a large process window, strong controllability, good repeatability, and is easy to achieve consistent fabrication of narrow channels of different sizes.

[0132] (4) Enhanced electrostatic control capability of the gate over the channel layer. Due to the gate spacing of hundreds of nanometers that can be fabricated by the above methods, the depletion regions of the two gates can overlap efficiently at extremely low operating voltages, achieving perfect pinch-off of the two-dimensional electron gas channel. This superior electrostatic control capability enables the device to have lower off-state current, steeper subthreshold swing, and better switching characteristics.

[0133] In summary, the fabrication method provided by the embodiments of this disclosure not only overcomes the technological challenge of small gate spacing in the fabrication of multi-channel gallium nitride high electron mobility transistors, but also brings comprehensive improvements in performance, cost, reliability and manufacturability, and has extremely high industrial application value.

[0134] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0135] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. An enhancement transistor, characterized in that, The enhancement transistor includes a channel layer (1), a barrier layer (2), a gate dielectric layer (3), and multiple gates (4). The channel layer (1), the barrier layer (2), and the gate dielectric layer (3) are stacked sequentially; The plurality of gates (4) are located on the side of the gate dielectric layer (3) away from the channel layer (1) and are arranged at intervals along the first direction, with the gate spacing between two adjacent gates (4) being less than 200 nm.

2. The enhancement-mode transistor according to claim 1, characterized in that, The enhancement transistor further includes a first dielectric layer (5) stacked on the barrier layer (2), wherein the first dielectric layer (5) has a first groove (101) corresponding one-to-one with the plurality of gates (4). The barrier layer (2) and the channel layer (1) below the first groove (101) have a plurality of second grooves (102), and the second grooves (102) correspond one-to-one with the first grooves (101) and are connected to form a gate groove; Along the first direction, the spacing between two adjacent first grooves (101) is less than 200 nm.

3. The enhancement-mode transistor according to claim 2, characterized in that, The opening size of the first groove (101) is larger than the opening size of the second groove (102), and the opening size of both the first groove (101) and the second groove (102) is the length of the opening along the first direction.

4. The enhancement transistor according to claim 3, characterized in that, The opening size of the first groove (101) is greater than 500nm and less than 600nm, and the opening size of the second groove (102) is not less than 400nm.

5. The enhancement-mode transistor according to claim 2, characterized in that, The first dielectric layer (5) is a SiO2 layer, an Al2O3 layer, a SiN layer, or a Si x N y layer.

6. The enhancement-mode transistor according to claim 2, characterized in that, The enhancement transistor further includes a first passivation layer (6) and a stop layer (7) stacked sequentially on the barrier layer (2), wherein the stop layer (7) is located on the side of the first dielectric layer (5) facing the barrier layer (2); The first groove (101) penetrates the first passivation layer (6) and the stop layer (7), and the sidewall of the first groove (101) located at the interface between the first passivation layer (6) and the stop layer (7) has a third step (603) and a fourth step (604), the third step (603) and the fourth step (604) are located on both sides of the first groove (101) along a direction perpendicular to the first direction.

7. The enhancement-mode transistor according to claim 6, characterized in that, The first passivation layer (6) is a SiN layer, and the stop layer (7) is an AlN layer.

8. A method for fabricating an enhancement-mode transistor, characterized in that, The manufacturing method includes: The channel layer, barrier layer, and gate dielectric layer are sequentially formed; A plurality of gates are formed on the gate dielectric layer, the plurality of gates are arranged at intervals along a first direction, and the gate spacing between two adjacent gates is less than 200 nm.

9. The manufacturing method according to claim 8, characterized in that, The channel layer, barrier layer, and gate dielectric layer, which are sequentially stacked together, include: The channel layer, the barrier layer, and the first dielectric layer are formed sequentially on the substrate; The first dielectric layer is subjected to wet etching to form a pre-groove in the first dielectric layer for defining the first groove; The first dielectric layer, the channel layer, and the barrier layer are etched to make the pre-groove become the first groove, and a plurality of second grooves are formed in the barrier layer and the channel layer below the first groove. The second grooves correspond one-to-one with the first grooves and are connected to form a gate groove. The first groove extends from the upper surface of the first dielectric layer to the surface of the barrier layer facing the first dielectric layer. The opening size of the first groove is larger than the opening size of the second groove. The opening size of both the first groove and the second groove is the length of the opening along the first direction, and the distance between two adjacent first grooves is less than 200nm. The gate dielectric layer is formed, which covers the bottom and sidewalls of the gate recess and the upper surface of the first dielectric layer.

10. The manufacturing method according to claim 9, characterized in that, The wet etching of the first dielectric layer, the channel layer, and the barrier layer includes: A metal mask layer is formed on the first dielectric layer, the metal mask layer filling the pre-groove and covering the upper surface of the first dielectric layer; A dielectric mask layer is formed on the metal mask layer, the dielectric mask layer having dielectric grooves that are aligned one-to-one with the plurality of pre-grooves; Using the dielectric mask layer as a mask, the metal mask layer is wet-etched to form a plurality of metal grooves that connect the pre-grooves and the dielectric grooves that correspond to each other. The opening size of the metal grooves along the first direction is larger than the opening size of the pre-grooves. Remove the dielectric mask layer, and using the metal mask layer as a mask, etch the first dielectric layer, the channel layer, and the barrier layer, so that the pre-groove becomes the first groove, and a corresponding second groove is formed in the barrier layer and the channel layer directly below each first groove.

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