Power device resistant to single event burnout and method of manufacturing the same, chip
By introducing a P-type polysilicon source and a hardening layer into the Trench MOSFET, the electric field distribution was adjusted, the single-event burn-out problem was solved, the radiation resistance and electrical performance of the device were improved, and the reliability of the device was enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN SIRIUS SEMICON CO LTD
- Filing Date
- 2026-04-02
- Publication Date
- 2026-07-03
AI Technical Summary
In the prior art, trench metal-oxide semiconductors (Trench MOSFETs) are susceptible to single-event burn-out (SEB) under single-event irradiation, which can lead to permanent damage to the device. Furthermore, existing SEB protection technologies cannot balance radiation resistance with device electrical performance, and thus cannot meet the application requirements of radiation environments.
By forming an N-type drift region and a P-type well region on a silicon carbide substrate, and forming first and second gate oxide layers on both sides respectively, N-type and P-type polysilicon layers and N-type and P-type heavily doped regions are introduced to cover a P-type polysilicon source, the surface electric field is adjusted to avoid hole accumulation on the gate, and a reinforcement layer is introduced to adjust the electric field distribution.
This effectively avoids single-event burn-out, improves the device's radiation resistance and electrical performance, enhances device reliability, and reduces the risk of gate breakdown and thermal runaway.
Smart Images
Figure CN122002863B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power device technology, and in particular relates to a power device resistant to single-event burn-out, its preparation method, and chip. Background Technology
[0002] Trench MOSFETs, with their advantages of low specific on-resistance, high current density, and excellent high-frequency characteristics, have become core power devices in high-power power electronic systems in radiation environments such as aerospace, aviation, and nuclear industries, and are a key foundation for achieving equipment miniaturization and high efficiency. Under extreme conditions such as high-energy heavy ion and proton irradiation in space, power devices are susceptible to single-event effects. Single-event burn-out (SEB) is the main form of sudden failure of trench MOSFETs, causing permanent damage and directly leading to system paralysis, seriously threatening equipment operational safety. Compared to planar gate structures, the trench corners of trench MOSFETs exhibit significant electric field concentration, making them more prone to triggering the SEB effect under high-energy particle irradiation.
[0003] However, among related technologies, anti-SEB technologies are mostly based on planar gate device designs, which have poor adaptability. Moreover, hardening methods often come at the cost of sacrificing the device's conduction and switching characteristics, making it difficult to balance radiation resistance performance with the core electrical performance of the device. This fails to meet the application requirements of Trench MOSFETs in radiation environments. Therefore, it is crucial to develop efficient anti-SEB technologies that are adapted to their structural characteristics. Summary of the Invention
[0004] To address the aforementioned technical problems, this application provides a power device resistant to single-event burn-out, its fabrication method, and a chip, aiming to optimize the device's threshold voltage and improve its reliability.
[0005] The first aspect of this application provides a power device resistant to single-event burn-out, the power device comprising:
[0006] A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate;
[0007] A first gate oxide layer and a second gate oxide layer are formed on the N-type drift region;
[0008] An N-type polysilicon layer formed within the first gate oxide layer;
[0009] A P-type polysilicon layer formed within the second gate oxide layer;
[0010] A P-type well region is formed on the N-type drift region, wherein the first gate oxide layer and the second gate oxide layer are located on both sides of the P-type well region, respectively;
[0011] The N-type heavily doped region and the P-type heavily doped region are in contact with the P-type well region; wherein the P-type heavily doped region is in contact with the second gate oxide layer, and the N-type heavily doped region is in contact with the first gate oxide layer;
[0012] A first electrode layer in contact with the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region, and the P-type heavily doped region;
[0013] A second electrode layer is formed on the back side of the silicon carbide substrate.
[0014] In some embodiments, the N-type heavily doped region and the P-type heavily doped region are formed on the P-type well region.
[0015] In some embodiments, the two sides of the P-type well region are in contact with the first gate oxide layer and the second gate oxide layer, respectively.
[0016] In some embodiments, the P-type heavily doped region is formed between the N-type heavily doped region and the second gate oxide layer, and the P-type heavily doped region is also formed between the P-type well region and the second gate oxide layer.
[0017] In some embodiments, the P-type heavily doped region further extends to the bottom of the second gate oxide layer.
[0018] In some embodiments, the depth of the second gate oxide layer is greater than the depth of the first gate oxide layer.
[0019] In some embodiments, the power device further includes:
[0020] A reinforcement layer is formed within the second gate oxide layer; wherein the reinforcement layer includes a plurality of reinforcement dielectric regions stacked together, and the width of the plurality of reinforcement dielectric regions gradually decreases from the second electrode layer toward the first electrode layer.
[0021] In some embodiments, the widths of the plurality of reinforced medium regions form an arithmetic sequence; or,
[0022] The dielectric constant of the plurality of reinforced dielectric regions gradually decreases from the second electrode layer toward the first electrode layer.
[0023] A second aspect of this application also provides a method for fabricating a power device as described in any of the foregoing embodiments, the method comprising:
[0024] An N-type drift region is formed on the front side of the silicon carbide substrate;
[0025] The two sides of the N-type drift region are etched, and a first gate oxide layer and a second gate oxide layer are formed on the two sides of the N-type drift region, respectively.
[0026] An N-type polysilicon layer is formed on the first gate oxide layer, and a P-type polysilicon layer is formed on the second gate oxide layer;
[0027] The P-type well region and the heavily doped N-type and P-type regions in contact with the P-type well region are formed by ion implantation; wherein the first gate oxide layer and the second gate oxide layer are located on both sides of the P-type well region, respectively.
[0028] A first gate oxide layer is formed by depositing silicon oxide material to encapsulate the N-type polycrystalline silicon layer, and a second gate oxide layer is formed to encapsulate the P-type polycrystalline silicon layer;
[0029] A first electrode layer is formed covering the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region, and the P-type heavily doped region, and a second electrode layer is formed on the back side of the silicon carbide substrate.
[0030] A third aspect of this application also provides a chip including the power device as described in any of the above embodiments.
[0031] The beneficial effects of the embodiments of this application are as follows: A P-type well region is formed on the N-type drift region, and a first gate oxide layer and a second gate oxide layer are formed on both sides of the P-type well region, respectively. An N-type polysilicon layer is formed in the first gate oxide layer, and a P-type polysilicon layer is formed in the second gate oxide layer. The N-type heavily doped region and the P-type heavily doped region are in contact with the P-type well region. A first electrode layer covers the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region, and the P-type heavily doped region. By introducing a P-type polysilicon source, a metal-insulator-semiconductor (MIS) barrier is applied to the device surface, and the surface electric field is adjusted so that more electric field lines point to the trench source. This causes most of the holes to drift to the surface of the trench source and flow to the P-type heavily doped region, avoiding the accumulation of holes on the gate and inducing gate breakdown, thus solving the problem of single-event failure in the device. Attached Figure Description
[0032] Figure 1 This is a schematic diagram of a power device provided in an embodiment of this application;
[0033] Figure 2 This is a schematic diagram of the hole current density distribution of the power device provided in the embodiments of this application;
[0034] Figure 3 This is a simulation diagram of the power device provided in the embodiments of this application;
[0035] Figure 4 This is another schematic diagram of the power device provided in the embodiments of this application;
[0036] Figure 5This is another schematic diagram of the power device provided in the embodiments of this application;
[0037] Figure 6 This is another schematic diagram of the power device provided in the embodiments of this application;
[0038] Figure 7 This is a schematic flowchart of the method for fabricating the power device provided in the embodiments of this application;
[0039] Figure 8 This is a partial cross-sectional schematic diagram of the power device provided in the embodiments of this application;
[0040] Figure 9 This is a partial cross-sectional schematic diagram of the power device provided in the embodiments of this application;
[0041] Figure 10 This is a partial cross-sectional schematic diagram of the power device provided in the embodiments of this application;
[0042] Figure 11 This is a partial cross-sectional schematic diagram of the power device provided in the embodiments of this application. Detailed Implementation
[0043] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0044] Among related technologies, single-event burn-out (SEB) protection technologies are mostly based on planar gate device designs, which have poor adaptability. Moreover, hardening methods often come at the cost of sacrificing the device's conduction and switching characteristics, making it difficult to balance radiation resistance and the core electrical performance of the device. This fails to meet the application requirements of trench MOSFETs in radiation environments. Therefore, it is crucial to develop efficient SEB protection technologies that are adapted to their structural characteristics.
[0045] To address the aforementioned technical problems, embodiments of this application provide a power device resistant to single-event burn-out, see [link to relevant documentation]. Figure 1 As shown, the power device in this embodiment includes: a silicon carbide substrate 110, an N-type drift region 120, a first gate oxide layer 310, a second gate oxide layer 210, an N-type polysilicon layer 320, a P-type polysilicon layer 220, a P-type well region 410, an N-type heavily doped region 420, a P-type heavily doped region 430, a first electrode layer 510, and a second electrode layer 520.
[0046] An N-type drift region 120 is formed on the front side of a silicon carbide substrate 110. A first gate oxide layer 310 and a second gate oxide layer 210 are formed on the N-type drift region 120. The first gate oxide layer 310 and the second gate oxide layer 210 are not in contact with each other.
[0047] An N-type polysilicon layer 320 is formed within a first gate oxide layer 310, a P-type polysilicon layer 220 is formed within a second gate oxide layer 210, and a P-type well region 410 is formed on an N-type drift region 120. The first gate oxide layer 310 and the second gate oxide layer 210 are located on opposite sides of the P-type well region 410, respectively.
[0048] The N-type heavily doped region 420 and the P-type heavily doped region 430 are in contact with the P-type well region 410. The P-type heavily doped region 430 is in contact with the second gate oxide layer 210. The N-type heavily doped region 420 is in contact with the first gate oxide layer 310. The first electrode layer 510 is in contact with the first gate oxide layer 310, the second gate oxide layer 210, the N-type heavily doped region 420, and the P-type heavily doped region 430. The N-type heavily doped region 420 and the P-type heavily doped region 430 are located between the first electrode layer 510 and the P-type well region 410. The second electrode layer 520 is formed on the back side of the silicon carbide substrate 110.
[0049] In this embodiment, a P-type well region 410 is formed on the N-type drift region 120. A first gate oxide layer 310 and a second gate oxide layer 210 are formed on both sides of the P-type well region 410, respectively. An N-type polysilicon layer 320 is formed within the first gate oxide layer 310, and a P-type polysilicon layer 220 is formed within the second gate oxide layer 210. The heavily doped N-type region 420 and the heavily doped P-type region 430 are in contact with the P-type well region 410. A first electrode layer 510 covers the first gate oxide layer 310, the second gate oxide layer 210, the heavily doped N-type region 420, and the heavily doped P-type region 430. By introducing a P-type polysilicon source, a metal-insulator-semiconductor (MIS) layer is applied to the device surface. MIS) adjusts the surface electric field, directing more electric field lines toward the trench source, thereby diverting most holes to the trench source surface and flowing to the P-type heavily doped region 430, avoiding hole accumulation on the gate and inducing gate breakdown, thus solving the problem of single-event failure in the device.
[0050] In some embodiments, combined with Figure 1 As shown, the N-type heavily doped region 420 and the P-type heavily doped region 430 are formed on the P-type well region 410.
[0051] In this embodiment, the N-type heavily doped region 420 is located between the P-type well region 410 and the first electrode layer 510, and the P-type heavily doped region 430 is located between the P-type well region 410 and the first electrode layer 510. The P-type heavily doped region 430 is close to the P-type polysilicon layer 220. By introducing a P-type trench source, the source-side electric field is adjusted. When triggered by heavy ion irradiation, some holes are driven to the surface of the source trench by the electric field, which avoids accumulation in the gate trench, disperses the hole current, and improves the SEB resistance.
[0052] In some embodiments, combined with Figure 1 As shown, the two sides of the P-type well region 410 are in contact with the first gate oxide layer 310 and the second gate oxide layer 210, respectively.
[0053] In traditional trench MOSFETs, when triggered by heavy ion irradiation, holes drift along the direction of the electric field at the corner of the trench gate and accumulate at the corner, forming a local positive charge region and further distorting the corner electric field. This causes the electric field in this region to rise a second time, which not only exacerbates the risk of tunneling leakage of the gate oxide layer, but also eventually induces single-event failures such as gate breakdown and thermal runaway. In this embodiment, a P-type polysilicon source is introduced. A MIS barrier is applied to the surface of the P-type polysilicon. For Si MOSFETs, an approximately 0.5 eV barrier is applied to the surface of N-type polysilicon, while an approximately -0.5 eV barrier is applied to P-type polysilicon. Therefore, the electric field lines are more directed towards the P-type polysilicon. This MIS barrier modulates the surface electric field, causing more electric field lines to point towards the trench source. Most holes will drift to the surface of the trench source and flow directly to the heavily doped P-type region 430. This avoids hole accumulation at the gate that induces gate breakdown, as well as parasitic BJT turn-on and thermal runaway, among other single-event failure problems. Simulation verification shows that... Figure 2 The schematic structure (a) shows the hole current density distribution of the 220 device without a P-type polysilicon layer at 0.1 ns after irradiation. Figure 2 The schematic structure (b) in this embodiment shows the hole current density distribution of the device with the P-type polysilicon layer 220 introduced at 0.1 ns after irradiation. It can be observed that some holes in the schematic structure (b) are diverted to the trench source, avoiding accumulation at the trench gate.
[0054] Figure 3 The figures show the current-time waveforms of the conventional structure and the schematic structure of this application under different linear energy transfer conditions, where curve S11 is... Figure 2 The schematic structure (a) in the figure shows the current-time relationship curve when the linear energy transfer is 0.01 pC / um. Curve S12 is... Figure 2 The schematic structure (a) in the figure shows the current-time relationship curve when the linear energy transfer is 0.015 pC / um. Curve S21 is... Figure 2 The schematic structure (b) in the diagram shows the current-time relationship curve when the linear energy transfer is 0.025 pC / um. Curve S22 is... Figure 2 The schematic diagram of the current-time relationship of the schematic structure (b) in the figure shows that when the linear energy transfer is 0.03 pC / um, it can be observed that... Figure 2 The radiation energy that the schematic structure (b) can withstand is Figure 2 It is 2.5 times the schematic structure (a) in the diagram.
[0055] In some embodiments, combined with Figure 4 As shown, the P-type heavily doped region 430 is formed between the N-type heavily doped region 420 and the second gate oxide layer 210, and the P-type heavily doped region 430 is also formed between the P-type well region 410 and the second gate oxide layer 210.
[0056] In this embodiment, the P-type heavily doped region 430 extends below the second gate oxide layer 210 and is attached to the second gate oxide layer 210. The P-type polysilicon layer 220 has a shallow trench structure. The depth of the second gate oxide layer 210 is less than the depth of the first gate oxide layer 310, and the depth of the P-type heavily doped region 430 is less than the depth of the N-type polysilicon layer 320.
[0057] In some embodiments, the lower surface of the heavily doped P-type region 430 is flush with the lower surface of the P-type well region 410.
[0058] In some embodiments, the source trench (second gate oxide layer 210, P-type polysilicon layer 220) can be fabricated under the same conditions as the gate trench (first gate oxide layer 310, N-type polysilicon layer 320).
[0059] In some embodiments, the source trench (second gate oxide layer 210, P-type polysilicon layer 220) can be a shallow trench structure, and the gate trench (first gate oxide layer 310, N-type polysilicon layer 320) can be a deep trench structure.
[0060] In some embodiments, the doping concentration of the P-type polysilicon layer 220 is greater than the doping concentration of the P-type well region 410.
[0061] In some embodiments, the thickness of the second gate oxide layer 210 is the same as the thickness of the first gate oxide layer 310.
[0062] In some embodiments, the difference between the thickness of the second gate oxide layer 210 and the thickness of the first gate oxide layer 310 is less than one-fifth of the thickness of the second gate oxide layer 210, and the thickness of the first gate oxide layer 310 and the thickness of the second gate oxide layer 210 are 10nm-500nm.
[0063] In some embodiments, a P-type heavily doped region 430 is formed between an N-type heavily doped region 420 and a second gate oxide layer 210, and the P-type heavily doped region 430 is also formed between a P-type well region 410 and a second gate oxide layer 210.
[0064] In some embodiments, combined with Figure 5 As shown, the P-type heavily doped region 430 also extends to the bottom of the second gate oxide layer 210.
[0065] In some embodiments, combined with Figure 5 As shown, the depth of the second gate oxide layer 210 is greater than the depth of the first gate oxide layer 310.
[0066] In this embodiment, the P-type polysilicon layer 220 is a deep trench structure. The source trench structure is located in the active semiconductor region between the P-type well regions 410. When a single-event event is triggered, the potential barrier formed by the P-type polysilicon layer 220 on the surface of the source trench structure can modulate the surface electric field distribution and guide some hole current to flow to the surface of the source trench structure, thereby preventing holes from accumulating at the corner of the gate trench and improving the device's resistance to single-event burn-out.
[0067] In some embodiments, the first electrode layer 510 can be a source metal layer and the second electrode layer 520 can be a drain metal layer. In this case, the power device is a MOSFET.
[0068] In some embodiments, the first electrode layer 510 can be the emitter and the second electrode layer 520 can be the collector. In this case, the power device is an IGBT.
[0069] In traditional trench IGBTs, single-event irradiation can induce hole accumulation at the gate trench corner, leading to parasitic thyristor latch-up and causing single-event latch-up failure. This embodiment introduces a P-type trench collector, forming a local hole "drainage channel" inside the device (below the P-type body region). When a single-event event generates a large number of electron-hole pairs, some holes are attracted to the surface of the P-type trench collector and recombine under the influence of an electric field, effectively reducing the hole concentration at the gate corner and in the parasitic NPN transistor base region (P-type body region). This suppresses the turn-on conditions of the parasitic thyristor (NPN-PNP), mechanistically improving the device's resistance to single-event latch-up while maintaining the low on-state voltage drop advantage of IGBTs.
[0070] In some embodiments, combined with Figure 6 As shown, the power device further includes a reinforcement layer 211, which is formed within the second gate oxide layer 210; wherein the reinforcement layer 211 includes a plurality of reinforcement dielectric regions stacked together, and the width of the plurality of reinforcement dielectric regions gradually decreases from the second electrode layer 520 toward the first electrode layer 510.
[0071] In some embodiments, the reinforcing layer 211 may be made of a high-K insulating dielectric material, which may be any insulating material including but not limited to oxides, nitrides, composite materials, etc.
[0072] In some embodiments, under high-frequency applications, the gate oxide / semiconductor interface of SiC MOSFETs in related technologies has a large number of defects. Due to the high electric field of the gate, charge carriers in the channel are continuously adsorbed to the gate oxide layer, and the charge carriers tunnel. During tunneling, defects trap charge carriers, leaving fixed charges, causing threshold voltage (Vth) drift. Figure 6As shown, by introducing a reinforcing layer 211, the electric field strength of the gate oxide is adjusted by using a stepped insulating layer (high-K materials can significantly reduce the tunneling probability, and increasing the thickness of the insulating layer can also significantly reduce the tunneling probability) to prevent tunneling of channel carriers.
[0073] In some embodiments, combined with Figure 6 As shown, the reinforcing layer 211 includes multiple reinforcing medium regions stacked together, and the width of the multiple reinforcing medium regions gradually decreases from the second electrode layer 520 toward the first electrode layer 510.
[0074] In this embodiment, the reinforcement layer 211 includes multiple reinforcement dielectric regions stacked together. The width of the multiple reinforcement dielectric regions gradually decreases from the second electrode layer 520 to the first electrode layer 510. This design can better adjust the gate oxide electric field distribution and avoid electron tunneling caused by high electric field peaks at corners.
[0075] In some embodiments, the widths of the plurality of reinforced medium regions are arranged in an arithmetic sequence.
[0076] In this embodiment, by setting the widths of multiple hardening dielectric regions to be in an arithmetic sequence, the electric field distribution on the surface of the second gate oxide layer 210 can be adjusted evenly, reducing the electric field spikes at its corners and thus reducing the probability of electron tunneling.
[0077] In some embodiments, the dielectric constant of the plurality of reinforced dielectric regions gradually decreases from the second electrode layer 520 toward the first electrode layer 510.
[0078] In this embodiment, the P-type polysilicon layer 220 is heavily P-type doped. The closer to the channel, the greater the dielectric constant of the hardening dielectric region. Furthermore, the thickness of the hardening layer 211 gradually increases from the P-type well region 410 to the channel, which can increase the difficulty of carriers tunneling into the P-type polysilicon layer 220 in the channel and avoid the high concentration of doping in the channel being captured by gate oxide defects, thereby reducing the tunneling probability of carriers in the device.
[0079] In some embodiments, the reinforcing layer 211 is a stepped structure, which may be multiple steps, each step being a reinforcing medium area.
[0080] In some embodiments, the hardening layer 211 includes multiple hardening dielectric regions that form a stepped structure. The thickness of the hardening dielectric regions near the channel is larger, and the thickness of the multiple hardening dielectric regions gradually decreases from the second electrode layer 520 to the first electrode layer 510. This increases the difficulty for carriers in the channel to tunnel into the P-type polysilicon layer 220, avoids the high concentration of doping in the channel being captured by gate oxide defects, and thus reduces the tunneling probability of carriers in the device.
[0081] In some embodiments, the reinforcing layer 211 includes a plurality of reinforcing medium regions, and the thickness of a single layer of the reinforcing medium region is 10-200 nm.
[0082] In some embodiments, the reinforcing layer 211 can be a stepless reinforcing layer 211 structure, which is simple to process. However, a high electric field spike is easily caused at the interface between the reinforcing layer 211 and the P-type polysilicon layer 220, which increases the probability of electron tunneling at this location. Therefore, by setting the interface between the reinforcing layer 211 and the P-type polysilicon layer 220 as a concave-convex structure, the interface area between the reinforcing layer 211 and the P-type polysilicon layer 220 can be increased, and the probability of a high electric field spike being caused at the interface can be reduced.
[0083] In some embodiments, the hardening layer 211 includes a plurality of hardening dielectric regions, at least a portion of which is located above the vertical portion of the P-type well region 410, and at least a portion of the P-type polysilicon layer 220 and at least a portion of the second gate oxide layer 210 are disposed between the hardening dielectric region and the vertical portion of the P-type well region 410. In this way, the thickness of the P-type polysilicon layer 220 can be adjusted to avoid the thickness of the P-type polysilicon layer 220 above the vertical portion of the P-type well region 410 being too large, which would affect the threshold voltage of the device.
[0084] In this embodiment, the reinforcement layer 211 includes multiple reinforcement dielectric regions stacked together. The width of the multiple reinforcement dielectric regions gradually decreases from the second electrode layer 520 to the first electrode layer 510. This design can better adjust the gate oxide electric field distribution and avoid electron tunneling caused by high electric field peaks at corners.
[0085] This application also provides a method for fabricating a power device as described in any of the above embodiments, see [link to relevant documentation]. Figure 7 As shown, the preparation method in this embodiment includes steps S100 to S600.
[0086] In step S100, an N-type drift region 120 is formed on the front side of the silicon carbide substrate 110.
[0087] In this embodiment, combined with Figure 8 As shown, the silicon carbide substrate 110 can be an N-type silicon carbide substrate 110, and an N-type drift region 120 is formed on the front side of the silicon carbide substrate 110 by epitaxial process.
[0088] In step S200, the two sides of the N-type drift region 120 are etched, and a first gate oxide layer 310 and a second gate oxide layer 210 are formed on the two sides of the N-type drift region 120, respectively.
[0089] In this embodiment, combined with Figure 9As shown, the two sides of the N-type drift region 120 are etched, a gate trench is formed on the first side of the N-type drift region 120, and a source trench is formed on the second side. A first gate oxide layer 310 and a second gate oxide layer 210 are formed on the two sides of the N-type drift region 120 respectively by an oxidation process.
[0090] In step S300, an N-type polysilicon layer 320 is formed on the first gate oxide layer 310, and a P-type polysilicon layer 220 is formed on the second gate oxide layer 210.
[0091] In this embodiment, combined with Figure 9 As shown, an N-type polysilicon layer 320 is formed by depositing N-type polysilicon material in the gate trench, and a P-type polysilicon layer 220 is formed by depositing P-type polysilicon material in the source trench.
[0092] In step S400, an N-type heavily doped region 420 and a P-type heavily doped region 430 in contact with the P-type well region 410 are formed by an ion implantation process.
[0093] In this embodiment, combined with Figure 10 As shown, a P-type well region 410 is formed by implanting P-type dopant ions into the front side of the N-type drift region 120, and an N-type heavily doped region 420 and a P-type heavily doped region 430 are formed by sequentially implanting P-type dopant ions and N-type dopant ions into a portion of the P-type well region 410.
[0094] In some embodiments, the concentration of N-type dopant ions in the N-type heavily doped region 420 is greater than the concentration of P-type dopant ions in the P-type well region 410, and the concentration of P-type dopant ions in the P-type heavily doped region 430 is greater than the concentration of P-type dopant ions in the P-type well region 410.
[0095] In step S500, silicon oxide material is deposited to form a first gate oxide layer 310 encapsulating an N-type polysilicon layer 320 and a second gate oxide layer 210 encapsulating a P-type polysilicon layer 220.
[0096] In this embodiment, combined with Figure 11 As shown, a first gate oxide layer 310 comprising an N-type polysilicon layer 320 and a second gate oxide layer 210 encapsulating a P-type polysilicon layer 220 can be formed by depositing silicon oxide material and a gate oxide material.
[0097] In step S600, a first electrode layer 510 is formed covering the first gate oxide layer 310, the second gate oxide layer 210, the N-type heavily doped region 420 and the P-type heavily doped region 430, and a second electrode layer 520 is formed on the back side of the silicon carbide substrate 110.
[0098] In this embodiment, combined with Figure 11As shown, a field oxide material is deposited to form a first gate oxide layer 310 covering the N-type polysilicon layer 320, such that the first gate oxide layer 310 encapsulates the N-type polysilicon layer 320. A second gate oxide layer 210 is also deposited to cover the P-type polysilicon layer 220, such that the second gate oxide layer 210 encapsulates the P-type polysilicon layer 220. Combined with... Figure 11 As shown, a first electrode layer 510 is formed on the front side of the device, which is in contact with the first gate oxide layer 310, the second gate oxide layer 210, the N-type heavily doped region 420 and the P-type heavily doped region 430, and a second electrode layer 520 is located on the back side of the silicon carbide substrate 110.
[0099] In some embodiments, the second gate oxide layer 210 is silicon dioxide, and the first electrode layer 510 covers the P-type heavily doped region 430 and at least a portion of the N-type heavily doped region 420.
[0100] This application also provides a chip, including the power device as described in any of the above embodiments.
[0101] In this embodiment, a P-type well region 410 is formed on the N-type drift region 120. A first gate oxide layer 310 and a second gate oxide layer 210 are formed on both sides of the P-type well region 410, respectively. An N-type polysilicon layer 320 is formed in the first gate oxide layer 310, and a P-type polysilicon layer 220 is formed in the second gate oxide layer 210. The N-type heavily doped region 420 and the P-type heavily doped region 430 are in contact with the P-type well region 410. A first electrode layer 510 covers the first gate oxide layer 310, the second gate oxide layer 210, the N-type heavily doped region 420, and the P-type heavily doped region 430. By introducing a P-type polysilicon source, a MIS barrier is applied to the device surface, and the surface electric field is adjusted so that more electric field lines point to the trench source. This causes most holes to drift to the surface of the trench source and flow to the P-type heavily doped region 430, avoiding the accumulation of holes on the gate and inducing gate breakdown, thus solving the problem of single-event failure in the device.
[0102] In some embodiments, other related semiconductor devices, as well as MOSFETs, may be integrated on the chip substrate to form an integrated circuit.
[0103] In one specific application embodiment, the chip can be a switch chip or a driver chip.
[0104] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0105] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.
[0106] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0107] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0108] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A power device resistant to single-event burn-out, characterized in that, The power device includes: A silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate; A first gate oxide layer and a second gate oxide layer are formed on the N-type drift region; An N-type polysilicon layer formed within the first gate oxide layer; A P-type polysilicon layer formed within the second gate oxide layer; A P-type well region is formed on the N-type drift region, wherein the first gate oxide layer and the second gate oxide layer are located on both sides of the P-type well region, respectively; The N-type heavily doped region and the P-type heavily doped region are in contact with the P-type well region; wherein the P-type heavily doped region is in contact with the second gate oxide layer, and the N-type heavily doped region is in contact with the first gate oxide layer; A first electrode layer in contact with the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region, and the P-type heavily doped region; A second electrode layer is formed on the back side of the silicon carbide substrate.
2. The power device as described in claim 1, characterized in that, The N-type heavily doped region and the P-type heavily doped region are formed on the P-type well region.
3. The power device as described in claim 2, characterized in that, The two sides of the P-type well region are in contact with the first gate oxide layer and the second gate oxide layer, respectively.
4. The power device as described in claim 1, characterized in that, The P-type heavily doped region is formed between the N-type heavily doped region and the second gate oxide layer, and the P-type heavily doped region is also formed between the P-type well region and the second gate oxide layer.
5. The power device as described in claim 4, characterized in that, The P-type heavily doped region also extends to the bottom of the second gate oxide layer.
6. The power device as described in claim 4, characterized in that, The depth of the second gate oxide layer is greater than the depth of the first gate oxide layer.
7. The power device according to any one of claims 1-6, characterized in that, The power device further includes: A reinforcement layer is formed within the second gate oxide layer; wherein the reinforcement layer includes a plurality of reinforced dielectric regions stacked together, and the width of the plurality of reinforced dielectric regions gradually decreases from the second electrode layer toward the first electrode layer.
8. The power device as described in claim 7, characterized in that, The widths of the multiple reinforced medium regions form an arithmetic sequence; or, The dielectric constant of the plurality of reinforced dielectric regions gradually decreases from the second electrode layer toward the first electrode layer.
9. A method for fabricating a power device as described in any one of claims 1-8, characterized in that, The preparation method includes: An N-type drift region is formed on the front side of the silicon carbide substrate; The two sides of the N-type drift region are etched, and a first gate oxide layer and a second gate oxide layer are formed on the two sides of the N-type drift region, respectively. An N-type polysilicon layer is formed on the first gate oxide layer, and a P-type polysilicon layer is formed on the second gate oxide layer; A P-type well region, along with an N-type heavily doped region and a P-type heavily doped region in contact with the P-type well region, are formed by an ion implantation process; wherein the first gate oxide layer and the second gate oxide layer are located on opposite sides of the P-type well region, respectively. A first gate oxide layer is formed by depositing silicon oxide material to encapsulate the N-type polycrystalline silicon layer, and a second gate oxide layer is formed to encapsulate the P-type polycrystalline silicon layer; A first electrode layer is formed covering the first gate oxide layer, the second gate oxide layer, the N-type heavily doped region, and the P-type heavily doped region, and a second electrode layer is formed on the back side of the silicon carbide substrate.
10. A chip, characterized in that, Includes the power device as described in any one of claims 1-8.