Optoelectronic spiking neuron based on field effect positive feedback transistor and preparation method thereof
By integrating semiconductor field-effect positive feedback transistors and two-dimensional optoelectronic devices into photoelectric pulse neurons, the problems of high hardware overhead and high energy consumption in traditional CMOS circuits are solved. This results in a high-integration-density and low-power pulse neural network with light-controlled pulse frequency characteristics, making it suitable for machine vision technology.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2023-05-18
- Publication Date
- 2026-07-03
AI Technical Summary
Traditional CMOS circuits used to construct spiking neurons suffer from high hardware overhead and high energy consumption, and limited research on neuron function makes it difficult to achieve high integration density and low power consumption spiking neural networks.
The optoelectronic pulse neuron, which integrates a semiconductor field-effect positive feedback transistor and a two-dimensional optoelectronic device, controls the output pulse frequency of the neuron by modulating the incident light, converting the optical signal into an electrical signal. The accumulation and release function of the pulse neuron is realized by utilizing the extremely low subthreshold swing and huge hysteresis characteristics of the field-effect positive feedback transistor.
It achieves high integration density and low power consumption spiking neurons, significantly reducing the hardware overhead of neuromorphic chips, and has light-controlled pulse frequency characteristics, making it suitable for machine vision technology.
Smart Images
Figure CN116613179B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of pulsed neural network technology, specifically relating to an optoelectronic pulsed neuron and its preparation method. Background Technology
[0002] The human brain is a supercomputing system composed of interconnected synapses and neurons, capable of processing complex activities such as language, movement, and computation with very low energy consumption. In order to overcome the memory wall bottleneck in the traditional von Neumann computing architecture, improve computational efficiency, and reduce energy consumption, researchers have proposed artificial neural networks by mimicking the structure of the human brain. Among them, the spiking neural network (SNN) transmits information in the form of pulses and has the characteristics of event-driven, low energy consumption, and high efficiency [1,2].
[0003] Spiking neurons are the basic computational units in SNNs. Their behavior is often described using the integrated-and-fire model, which involves the following process: when the membrane potential is below the threshold voltage, the neuron accumulates input pulses and raises the membrane potential; when the membrane potential exceeds the threshold voltage, the neuron fires a pulse signal and resets the membrane potential. Traditional IF neurons are built from complex CMOS circuits, using multiple transistors to realize the function of a single neuron, resulting in high hardware overhead and high power consumption [3,4]. In recent years, the demand for high integration and low power consumption has promoted the development of novel neuromorphic devices [5,6]. Furthermore, current research on many functions of neurons, such as visual perception, is relatively limited. Therefore, further research on spiking neurons based on novel devices is still needed to realize neuromorphic chips with high integration density and rich functionality. Summary of the Invention
[0004] The purpose of this invention is to provide an optoelectronic pulse neuron in a high-density, low-power, and multifunctional spiking neural network and its fabrication method.
[0005] The structure of the photoelectric pulse neuron proposed in this invention is shown in [reference needed]. Figure 1 As shown, it is composed of a semiconductor field-effect positive feedback transistor and a two-dimensional optoelectronic device assembly, wherein the semiconductor field-effect positive feedback transistor and the two-dimensional optoelectronic device share the same substrate; wherein:
[0006] The semiconductor field-effect positive feedback transistor includes:
[0007] Substrate 1;
[0008] Buried oxide layer 2 on substrate 1;
[0009] A first channel region 3, a gate oxide layer 4, a positive gate 5, and a positive gate metal contact 10 are sequentially formed on the buried oxide layer 2.
[0010] The first source doped region 6 on the left side of the first channel region 3 on the buried oxide layer 2, and the first source metal contact 8 on the first source doped region 6;
[0011] The first drain doped region 7 on the right side of the first channel region 3 on the buried oxide layer 2, and the first drain metal contact 9 on the first drain doped region 7;
[0012] The two-dimensional optoelectronic device is located on the same substrate 1 and buried oxide layer 2, and includes:
[0013] The second channel region 12 on the buried oxide layer 2, and the second source metal contact 13 and the second drain metal contact 14;
[0014] The first end of the second source metal contact 13 is located above the first drain metal contact 9, that is, the integration of the two devices is achieved through the metal interconnection between the first drain of the semiconductor field-effect positive feedback transistor and the second source in the two-dimensional optoelectronic device; the second end of the second source metal contact 13 is located on one side of the second channel region 12.
[0015] In this invention, the photoelectric pulse neuron is based on a silicon substrate structure built on an insulating layer, comprising: a substrate; and a buried oxide layer on the substrate;
[0016] The substrate 1 is any one of semiconductor materials such as silicon, germanium, germanium silicon, gallium nitride, and indium gallium arsenide;
[0017] The oxide buried layer 2 is any one of insulating materials such as silicon dioxide, aluminum oxide, and hafnium oxide;
[0018] The first channel 3 is any one of semiconductor materials such as silicon, germanium, germanium silicon, gallium nitride, and indium gallium arsenide;
[0019] The substrate 1 is undoped or weakly doped; the first channel 3 is undoped or weakly doped;
[0020] The first source doped region 6 is N-type doped and the first drain doped region 7 is P-type doped; or, the first source doped region 6 is P-type doped and the first drain doped region 7 is N-type doped.
[0021] The first source doped region 6 is heavily doped with a doping concentration of 10. 19 -10 21 cm -3 The first drain doped region 7 is inversely heavily doped relative to the first source doped region 6, with a doping concentration of 10. 19 -10 21 cm -3 ;
[0022] The gate oxide layer is one or more insulating materials such as silicon dioxide, silicon nitride, aluminum oxide, and hafnium oxide;
[0023] The positive gate is polysilicon or metal, or a composite structure of polysilicon and metal;
[0024] The first source metal contact 8, the first drain metal contact 9, the positive gate metal contact, and the substrate metal contact are one or more materials selected from aluminum, nickel, titanium, metal silicide, etc.
[0025] The second source metal contact 13 and the second drain metal contact 14 are one or more of the following metal materials: aluminum, gold, titanium, silver, etc.
[0026] The second channel region 12 is one or more of two-dimensional materials such as molybdenum disulfide, molybdenum ditelluride, graphene, and black phosphorus.
[0027] This invention also provides a method for preparing the above-mentioned photoelectric pulse neuron, the specific steps of which are as follows:
[0028] (1) Prepare the initial insulating layer on silicon substrate;
[0029] (2) Photolithography and etching are performed to form the first channel region in the upper silicon layer;
[0030] (3) Deposit a gate oxide layer thereon and deposit a positive gate thereon;
[0031] (4) Photolithography and etching are performed to form a positive gate pattern above the first channel region;
[0032] (5) Photolithography and ion implantation are performed to form a heavily N-type doped first source doped region and a heavily P-type doped first drain doped region on both sides of the first channel region, and the implanted ions are activated by high-temperature annealing.
[0033] (6) Photolithography and deposition of metal contacts, followed by annealing, to form the metal contacts of the first source, the first drain, the positive gate and the substrate;
[0034] (7) A second channel region of two-dimensional material is formed on the oxide buried layer;
[0035] (8) Photolithography and deposition of metal contacts, followed by annealing, to form metal contacts between the second source and the second drain, and to form metal interconnect between the first drain and the second source.
[0036] More detailed process steps are described in Example 1.
[0037] The photoelectric pulse neuron based on a field-effect positive feedback transistor proposed in this invention can control the output pulse frequency of the neuron by modulating the incident light. It utilizes a two-dimensional optoelectronic device to convert optical signals into electrical signals, and leverages the extremely low subthreshold swing and large hysteresis characteristics of the field-effect positive feedback transistor to achieve the accumulation and release function of the pulse neuron. The specific implementation method is as follows:
[0038] (1) The source (i.e., the first source), the positive gate and the substrate of the field-effect positive feedback transistor are properly biased so that they are initially in the off state. The drain (i.e., the second drain) of the two-dimensional optoelectronic device is properly biased so that it provides a suitable source current (i.e., the second source current) and serves as the drain input current (i.e., the first drain current) of the field-effect positive feedback transistor.
[0039] (2) The capacitance between the drain metal (i.e. the first drain metal contact) of the field-effect positive feedback transistor and the substrate is used as the membrane capacitance of the neuron; the membrane capacitance integrates the first drain input current and increases the first drain voltage (i.e. the membrane voltage of the neuron); until the membrane voltage rises to the threshold voltage, the field-effect positive feedback transistor is turned on sharply, causing the membrane capacitance to discharge rapidly and the membrane voltage to suddenly drop back to the turn-off voltage of the field-effect positive feedback transistor, thereby allowing the next integration and discharge, so a voltage pulse signal is output at the first drain and a current pulse signal is output at the first source.
[0040] (3) Illuminating the two-dimensional optoelectronic device and adjusting the wavelength and intensity of the incident light can change the photocurrent of the two-dimensional optoelectronic device, that is, change the drain input current of the field-effect positive feedback transistor, thereby changing the charging speed of the film capacitor and further regulating the output pulse frequency of the neuron.
[0041] The beneficial effects of this invention are as follows:
[0042] This invention utilizes a single field-effect positive feedback transistor to realize the basic characteristics of a spiking neuron, which is beneficial for high integration density and low power consumption applications, significantly reducing the hardware overhead of neuromorphic chips. Two-dimensional materials are considered highly attractive next-generation optoelectronic materials due to their tunable bandgap, wide absorption spectrum, and nanoscale characteristics. This invention integrates a two-dimensional optoelectronic device with a field-effect positive feedback transistor to realize a novel optoelectronic spiking neuron with light-controlled pulse frequency characteristics. This can be used in machine vision technology, thus having wide applications in medical, military, aerospace, and agricultural fields. This invention provides a new approach to realizing high integration density, low power consumption, and feature-rich neuromorphic chips. Attached Figure Description
[0043] Figure 1 This is a structural diagram of the photoelectric pulse neuron based on a field-effect positive feedback transistor according to the present invention.
[0044] Figure 2This is a flowchart illustrating the fabrication process of the photoelectric pulse neuron based on a field-effect positive feedback transistor according to the present invention.
[0045] Figure 3 The diagrams show the structures of embodiments 2, 3, and 4 of the photoelectric pulse neuron based on the field-effect positive feedback transistor of the present invention. Detailed Implementation
[0046] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Specific implementation methods may vary depending on the embodiment:
[0047] Example 1 (corresponding) Figure 1 Device structure and Figure 2 (The process flow).
[0048] (1) As Figure 2 As shown in (a), a silicon-on-insulator (SCI) wafer is prepared for initiation, including a substrate, a buried oxide layer, and a first channel. The substrate is typically weakly p-type doped with a doping concentration of 10%. 15 cm -2 Up to 10 17 cm -2 The layers between the top and bottom layers are typically made of semiconductor materials such as silicon, germanium, germanium-silicon, gallium nitride, or indium gallium arsenide. The buried oxide layer is typically made of insulating materials such as silicon dioxide, aluminum oxide, or hafnium oxide, with a thickness between 10 nm and 1000 nm. The upper channel is typically made of semiconductor materials such as silicon, germanium, germanium-silicon, gallium nitride, or indium gallium arsenide, with a thickness between 5 nm and 500 nm.
[0049] (2) Figure 2 As shown in (b), a window for the active region of the field-effect positive feedback transistor is photolithographically created. Then, the first channel of the upper layer is etched using photoresist as a mask to form the active region pattern and provide a reserved area above the buried oxide layer for the two-dimensional optoelectronic device. Etching can be performed using either dry or wet etching. Dry etching typically uses fluorine-based or halogen gases, such as SF6, CHF3, HBr, or Cl2. Wet etching typically uses solutions such as TMAH or KOH.
[0050] (3) Figure 2 As shown in (c), a gate oxide layer is deposited, and a positive gate material is deposited on top of it. The gate oxide layer can be deposited by methods such as atomic layer deposition, thermal oxidation, or chemical vapor deposition, and is generally an insulating material such as silicon dioxide, aluminum oxide, or hafnium oxide, with a thickness typically between 1 nm and 30 nm. The positive gate is generally a polycrystalline silicon, metal, or a composite structure of polycrystalline silicon and metal, with a thickness typically between 10 nm and 500 nm.
[0051] (4) Figure 2 As shown in (d), the positive gate pattern of the field-effect positive feedback transistor is formed by photolithography and etching.
[0052] (5) Figure 2 As shown in (e), photolithography opens the ion implantation window of the first source region and performs ion implantation to form the N-type heavily doped region of the first source region; arsenic or phosphorus is generally used for ion implantation, with a dose of 10. 13 cm -2 Up to 10 16 cm -2 The energy ranges from 1 keV to 100 keV. Afterwards, photolithography is used again to open the ion implantation window of the first drain region and ion implantation is performed to form the heavily p-type doped region of the first drain region; boron or BF2 is typically used for ion implantation, with a dose of 10... 13 cm -2 Up to 10 16 cm -2 The energy ranges from 1 keV to 100 keV. After removing the photoresist, high-temperature annealing is performed to activate impurities; the activation annealing temperature is generally between 900 degrees and 1200 degrees, and the time is between 1 microsecond and 10 seconds.
[0053] (6) Figure 2 As shown in (f), photolithography is used to open windows for the first source, first drain, positive gate, and substrate. Metal is then deposited and annealed to form metal contacts between the first source, first drain, positive gate, and substrate. Materials such as aluminum, nickel, titanium, or metal silicides are typically used. The annealing temperature is generally between 300 and 900 degrees Celsius.
[0054] (7) Figure 2 As shown in (g), a two-dimensional material layer is formed in the second channel region above the buried oxide layer. The two-dimensional material layer can be formed using thin-film vacuum transfer or chemical vapor deposition. After forming the two-dimensional material layer, photolithography and etching are performed to define the pattern of the second channel region. The two-dimensional material layer is typically molybdenum disulfide, molybdenum ditelluride, graphene, black phosphorus, etc.
[0055] (8) Figure 2 As shown in (h), photolithography is used to open the windows of the second source and the second drain, metal is deposited and annealed to form the metal contact between the second source and the second drain, and to form the interconnect metal between the second source and the first drain. Metal materials such as aluminum, gold, titanium, and silver are generally used. The annealing temperature is generally between 300 and 900 degrees Celsius.
[0056] Example 2 (corresponding) Figure 3 (a) Device structure diagram.
[0057] Example 2 is similar to Example 1, except that the field-effect positive feedback transistor is P-type instead of N-type. The first source doping region is heavily P-type doped, while the first drain doping region is heavily N-type doped. Therefore, the process flow of this example is similar to that of Example 1, only the ion implantation type in step (5) above needs to be reversed.
[0058] Example 3 (corresponding) Figure 3 (b) Device structure diagram.
[0059] Example 3 is similar to Example 1, except that the two-dimensional phototransistor has a top-gate structure. The top-gate structure enhances the electrical control of the second channel. To avoid hindering light absorption, a transparent top-gate structure needs to be formed above the second channel region. Specifically, after step (8), the following steps are added: depositing the gate oxide layer of the two-dimensional phototransistor, which can be made of materials such as aluminum oxide, with a thickness generally between 1 nm and 30 nm; depositing a positive gate material on the gate oxide layer of the two-dimensional phototransistor, photolithographically etching to form the second gate pattern, removing the photoresist, and then annealing. The second gate is generally made of transparent conductive materials such as AZO, ITO, or IZO, with a thickness generally between 10 nm and 500 nm. The annealing temperature is generally between 300 degrees and 900 degrees.
[0060] Example 4 (corresponding) Figure 3 (c) Device structure diagram).
[0061] Example 4 is similar to Example 1, except that the two-dimensional phototransistor has a back gate structure. Transparent electrode materials are difficult to reconcile with high transparency and high conductivity. Using a back gate structure avoids the limitations of transparent electrode materials, enhancing the electrical control of the second channel without hindering light absorption. To achieve Example 4, a back gate structure needs to be fabricated before forming the second channel region of the two-dimensional material. The fabrication method of this example is similar to Example 1, specifically adding the following steps between steps (6) and (7): depositing a back gate material, photolithographically etching to form a second gate pattern; the back gate is generally polysilicon or a metal or a composite structure of polysilicon and metal, with a thickness generally between 10 nm and 500 nm; depositing a gate oxide layer, which can be deposited by atomic layer deposition, thermal oxidation, or chemical vapor deposition, generally using insulating materials such as silicon dioxide, aluminum oxide, or hafnium oxide, with a thickness generally between 1 nm and 30 nm; photolithographically etching to create a via above the first drain metal, preparing for the subsequent connection between the first drain and the second source.
[0062] References
[0063] [1]W.Maass,"Networks of spiking neurons:the third generation ofneural network models,"Neural Netw.,vol.10,no.9,pp.1659-1671,1997.
[0064] [2]P.A.Merolla et al.,"A million spiking-neuron integrated circuitwith a scalable communication network and interface,"Science,vol.345,no.6197,pp.668-673,2014.
[0065] [3]J.H.B.Wijekoon and P.Dudek,"Compact silicon neuron circuit withspiking and bursting behaviour,"Neural Netw.,vol.21,no.2-3,pp.524-534,2008.
[0066] [4]M.Akbari,S.M.Hussein,T.I.Chou,and K.T.Tang,"A 0.3-V Conductance-Based Silicon Neuron in 0.18μm CMOS Process,"IEEE Transactions on Circuitsand Systems II:Express Briefs,vol.68,no.10,pp.3209-3213,2021.
[0067] [5]Y.Chen et al.,"Realization of Artificial Neuron Using MXene Bi-Directional Threshold Switching Memristors,"IEEE Electron Device Letters,vol.40,no.10,pp.1686-1689,2019.
[0068] [6]Y.F.Lu et al.,"Low-Power Artificial Neurons Based on Ag / TiN / HfAlOx / Pt Threshold Switching Memristor for Neuromorphic Computing,"IEEEElectron Device Letters,vol.41,no.8,pp.1245-1248,2020。
Claims
1. A photoelectric pulse neuron based on a field-effect positive feedback transistor, characterized in that, It consists of a semiconductor field-effect positive feedback transistor and a two-dimensional optoelectronic device, wherein the semiconductor field-effect positive feedback transistor and the two-dimensional optoelectronic device share the same substrate; wherein: The semiconductor field-effect positive feedback transistor includes: Substrate (1); Buried oxide layer (2) on substrate (1); A first channel region (3), a gate oxide layer (4), a positive gate (5), and a positive gate metal contact (10) are sequentially formed on the buried oxide layer (2); On the buried oxide layer (2), on the left side of the first channel region (3), there is a first source doped region (6) and a first source metal contact (8) on the first source doped region (6); The first drain doped region (7) on the right side of the first channel region (3) on the buried oxide layer (2), and the first drain metal contact (9) on the first drain doped region (7); The two-dimensional optoelectronic device is located on the same substrate (1) and buried oxide layer (2), comprising: The second channel region (12) on the buried oxide layer (2), and the second source metal contact (13) and the second drain metal contact (14); The first end of the second source metal contact (13) is located above the first drain metal contact (9), that is, the integration of the two devices is achieved through the metal interconnection between the first drain of the semiconductor field-effect positive feedback transistor and the second source in the two-dimensional optoelectronic device; the second end of the second source metal contact (13) is located on one side of the second channel region (12).
2. The photoelectric pulse neuron according to claim 1, characterized in that: The substrate (1) is any one of the semiconductor materials silicon, germanium, germanium silicon, gallium nitride, and indium gallium arsenide; The buried oxide layer (2) is any one of the two insulating materials: silicon oxide, aluminum oxide, and hafnium oxide; The first channel (3) is any one of the semiconductor materials silicon, germanium, germanium silicon, gallium nitride, and indium gallium arsenide.
3. The photoelectric pulse neuron according to claim 1, characterized in that: The substrate (1) is undoped or weakly doped; the first channel (3) is undoped or weakly doped; The first source doped region (6) is N-type doped and the first drain doped region (7) is P-type doped; or, the first source doped region (6) is P-type doped and the first drain doped region (7) is N-type doped.
4. The photoelectric pulse neuron according to claim 3, characterized in that: The first source doped region (6) is heavily doped with a doping concentration of 10. 19 -10 21 cm -3 The first drain doped region (7) is inversely heavily doped relative to the first source doped region (6), with a doping concentration of 10. 19 -10 21 cm -3 .
5. The photoelectric pulse neuron according to claim 3, characterized in that, The gate oxide layer (4) is one or more of the insulating materials silicon dioxide, silicon nitride, aluminum oxide, and hafnium oxide; The positive gate (5) is polysilicon or metal, or a composite structure of polysilicon and metal.
6. The photoelectric pulse neuron according to claim 3, characterized in that: The first source metal contact (8), the first drain metal contact (9), and the positive gate metal contact (10) are one or more of aluminum, nickel, titanium, and metal silicide materials; The second source metal contact (13) and the second drain metal contact (14) are one or more of aluminum, gold, titanium and silver metal materials.
7. The photoelectric pulse neuron according to claim 3, characterized in that, The second channel region (12) is one or more of the two-dimensional materials molybdenum disulfide, molybdenum ditelluride, graphene, and black phosphorus.
8. A method for preparing a photoelectric pulse neuron as described in any one of claims 1-7, characterized in that, The specific steps are as follows: (1) Prepare the initial insulating layer on silicon substrate; (2) Photolithography and etching are performed to form the first channel region in the upper silicon layer; (3) Deposit a gate oxide layer thereon and deposit a positive gate thereon; (4) Photolithography and etching are performed to form a positive gate pattern above the first channel region; (5) Photolithography and ion implantation are performed to form a heavily N-type doped first source doped region and a heavily P-type doped first drain doped region on both sides of the first channel region, and the implanted ions are activated by high-temperature annealing. (6) Photolithography and deposition of metal contacts, followed by annealing, to form the metal contacts of the first source, the first drain, the positive gate and the substrate; (7) A second channel region of two-dimensional material is formed on the oxide buried layer; (8) Photolithography and deposition of metal contacts, followed by annealing, to form metal contacts between the second source and the second drain, and to form metal interconnect between the first drain and the second source.
9. A method for regulating photoelectric pulse neurons as described in any one of claims 1-7, characterized in that, The output pulse frequency of neurons is controlled by modulating the incident light. Two-dimensional optoelectronic devices are used to convert the optical signal into an electrical signal. The accumulation and release function of the spiking neuron is achieved by utilizing the extremely low subthreshold swing and large hysteresis characteristics of the field-effect positive feedback transistor. Specifically: (1) The source, positive gate and substrate of the field-effect positive feedback transistor are appropriately biased so that they are initially in the off state. The drain of the two-dimensional optoelectronic device is appropriately biased so that it provides a suitable source current and serves as the drain input current of the field-effect positive feedback transistor. (2) The capacitance between the drain metal of the field-effect positive feedback transistor and the substrate is used as the membrane capacitance of the neuron. The film capacitor integrates the first drain input current and increases the first drain voltage; Until the membrane voltage rises to the threshold voltage, the field-effect positive feedback transistor is turned on sharply, causing the membrane capacitor to discharge rapidly and the membrane voltage to suddenly drop back to the turn-off voltage of the field-effect positive feedback transistor, thus allowing the next integration and discharge. As a result, a voltage pulse signal is output at the first drain and a current pulse signal is output at the first source. (3) Illuminate the two-dimensional optoelectronic device, adjust the wavelength and intensity of the incident light, change the photocurrent of the two-dimensional optoelectronic device, that is, change the drain input current of the field-effect positive feedback transistor, thereby changing the charging speed of the film capacitor and further regulating the output pulse frequency of the neuron.