Semiconductor devices and their fabrication methods

Abstract

This application provides a semiconductor device and its fabrication method, belonging to the field of semiconductor technology. The semiconductor device includes: a substrate having an active region and a trench with inclined sidewalls within the active region; a gate structure including a gate oxide layer and a gate conductive layer, the gate oxide layer covering two opposing inclined sidewalls of the trench and exposing at least a portion of the bottom wall of the trench, the gate conductive layer being located on the gate oxide layer; a channel region located in the active region below the gate oxide layer; a drift region; a source region and a drain region, the drain region being located in the drift region, and the source region being located in the active region at the edge of the trench; a first sidewall structure and a second sidewall structure, the first sidewall structure being located on the side of the gate structure near the source region and protruding from the surface of the source region and the gate structure, the second sidewall structure being located on the drift region and covering the sidewall of the gate structure on the drain region side. This application reduces the device area while maintaining the length / width of the channel, thereby improving chip integration.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a semiconductor device and its fabrication method. Background Technology

[0002] With the continuous development of new energy technologies, the demand for power chips used in high-voltage, high-frequency and high-power scenarios is constantly increasing. It is becoming increasingly important to fit more transistors into a limited chip area, so it is necessary to further reduce the area of ​​transistors.

[0003] For chips used in specific applications, long / wide channel transistors are used for driving. These transistors occupy most of the chip area, which poses a challenge to chip integration. How to reduce the area of ​​the transistor while ensuring the length / width of the channel is an urgent problem to be solved. Summary of the Invention

[0004] In view of this, the embodiments of this application aim to provide a semiconductor device and a method for fabricating the same, so as to solve the problem in the prior art that it is impossible to reduce the area of ​​the transistor while ensuring the length / width of the channel.

[0005] This application provides a semiconductor device, including:

[0006] A substrate having an active region thereon, wherein the active region has a trench with inclined sidewalls;

[0007] A gate structure includes a gate oxide layer and a gate conductive layer, the gate oxide layer covering two opposing inclined sidewalls of the trench and exposing at least a portion of the bottom wall of the trench, the gate conductive layer being located on the gate oxide layer, and the gate oxide layer enclosing the sidewalls and bottom surface of the gate conductive layer;

[0008] The channel region is located in the active region beneath the gate oxide layer;

[0009] The drift region is located in the active region of the bottom wall of the trench and is in contact with the channel region;

[0010] The source region and the drain region, wherein the drain region is located in the drift region and the source region is located in the active region at the edge of the trench;

[0011] A first sidewall structure and a second sidewall structure, wherein the first sidewall structure is located on the side of the gate structure near the source region and protrudes from the surface of the source region and the gate structure, and the second sidewall structure is located on the drift region and covers the sidewall of the gate structure near the drain region.

[0012] In some embodiments, the trench is part of a sigma trench, and the width of the trench gradually decreases in the direction close to the substrate so that the sidewalls of the trench are inclined.

[0013] In some embodiments, the surface of the gate oxide layer away from the channel region includes a step, and the thickness of the gate oxide layer near the drain region is greater than the thickness of the gate oxide layer near the source region.

[0014] In some embodiments, the gate conductive layer is wedge-shaped, with a thickness near the source region that is less than the thickness near the drain region.

[0015] In some embodiments, the gate structure further extends to cover a portion of the active region at the bottom of the trench, making the gate structure L-shaped.

[0016] This application also provides a method for fabricating a semiconductor device, comprising:

[0017] A substrate is provided, the surface of which has an active region, and a trench with inclined sidewalls is formed in the active region;

[0018] A gate structure is formed in the trench. The gate structure includes a gate oxide layer and a gate conductive layer. The gate oxide layer covers two opposite inclined sidewalls of the trench and exposes at least a portion of the bottom wall of the trench. The gate conductive layer is located on the gate oxide layer and wraps around the sidewalls and bottom surface of the gate conductive layer. The active region under the gate oxide layer serves as the channel region.

[0019] A drift region is formed in the active region exposed on the bottom wall of the trench, and the drift region is in contact with the channel region;

[0020] A drain region is formed in the drift region, and a source region is formed in the active region at the edge of the trench.

[0021] In some embodiments, the step of forming a trench with inclined sidewalls within the active region further includes:

[0022] The active region is etched using a dry process and a wet process including TMAH to form a sigma trench within the active region;

[0023] A first sacrificial layer is filled into the sigma groove;

[0024] The first sacrificial layer is etched back until the top surface of the first sacrificial layer is flush with the inflection point of the sidewall of the sigma groove;

[0025] A planarization process is performed until the top surface of the active region is flush with the top surface of the first sacrificial layer, and the remaining portion of the sigma groove forms the trench.

[0026] Remove the first sacrificial layer.

[0027] In some embodiments, the step of forming the gate structure further includes:

[0028] A gate oxide material is formed to cover the surface of the active region and the bottom and sidewalls of the trench;

[0029] A gate conductive material is formed to cover the surface of the gate oxide material and fill the trench;

[0030] The gate conductive material and the gate oxide material on the surface of the active region outside the trench and on the bottom wall of the trench are removed by etching, exposing the surface of the active region on the bottom wall of the trench and the surface of the active region outside the trench. The remaining gate oxide material serves as the gate oxide layer, and the remaining gate conductive material serves as the gate conductive layer.

[0031] In some embodiments, the step of forming a gate oxide material covering the surface of the active region and the bottom and sidewalls of the trench further includes:

[0032] The gate oxide material is formed to conformally cover the surface of the active region and the bottom and sidewalls of the trench;

[0033] A second sacrificial layer is formed to cover the surface of the gate oxide material and fill the trench;

[0034] The second sacrificial layer on the gate oxide material is removed by grinding, exposing the gate oxide material outside the trench;

[0035] Etching back removes a portion of the thickness of the second sacrificial layer, exposing a portion of the gate oxide material on the trench sidewalls;

[0036] Etching removes a portion of the thickness of the exposed gate oxide material;

[0037] Remove the remaining second sacrificial layer.

[0038] In some embodiments, the step of forming the source region and the drain region further includes:

[0039] The sidewall material conformally covers the surfaces of the active region, the gate structure, and the drift region;

[0040] The sidewall material is patterned, and the remaining sidewall material is used as the first sidewall structure and the second sidewall structure. The first sidewall structure is located on the side of the gate structure near the source region and protrudes from the surface of the source region and the gate structure. The second sidewall structure is located on the drift region and covers the sidewall of the gate structure near the drain region.

[0041] A patterned mask layer is formed to cover the gate structure, at least a portion of the first sidewall structure and the second sidewall structure. The active regions on both sides of the first sidewall structure and the second sidewall structure are then heavily doped with ions to form the source region and the drain region.

[0042] In summary, this embodiment provides a semiconductor device and a method for fabricating the same, comprising: a substrate having an active region thereon, the active region having a trench with inclined sidewalls; a gate structure including a gate oxide layer and a gate conductive layer, the gate oxide layer covering two opposite inclined sidewalls of the trench and exposing at least a portion of the bottom wall of the trench, the gate conductive layer being located on the gate oxide layer, the gate oxide layer enclosing the sidewalls and bottom surface of the gate conductive layer; a channel region located in the active region below the gate oxide layer; a drift region located in the active region on the bottom wall of the trench and in contact with the channel region; a source region and a drain region, the drain region being located in the drift region, the source region being located in the active region at the edge of the trench; a first sidewall structure and a second sidewall structure, the first sidewall structure being located on the side of the gate structure near the source region and protruding from the surface of the source region and the gate structure, the second sidewall structure being located on the drift region and covering the sidewall of the gate structure near the drain region. An unexpected effect of this application is that by placing the gate structure on the sidewall of the trench and using the active region of the trench sidewall as the channel region, the device area is reduced while maintaining the length / width of the channel, thereby improving chip integration. Furthermore, a protruding first sidewall structure is provided on the side of the gate structure near the source region (outside the trench), and a second sidewall structure covering the sidewall of the gate structure is provided on the sidewall of the drain region (inside the trench). On the one hand, the first and second sidewall structures can protect the gate oxide layer, preventing direct bombardment of the gate oxide layer during source / drain ion implantation. On the other hand, the first and second sidewall structures can increase the distance between the source / drain regions and the gate conductive layer, thereby reducing parasitic capacitance. Attached Figure Description

[0043] Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application.

[0044] Figure 2 This is a schematic diagram of a structure for etching an active region to form a sigma groove in the active region, according to an embodiment of this application.

[0045] Figure 3 This is a schematic diagram of a structure in which a first sacrificial layer is filled in a sigma groove, according to an embodiment of this application.

[0046] Figure 4This is a schematic diagram of a structure for removing a portion of the thickness of the first sacrificial layer through grinding, according to an embodiment of this application.

[0047] Figure 5 This is a schematic diagram of the structure of the first sacrificial layer etched back according to an embodiment of this application.

[0048] Figure 6 This is a schematic diagram of a structure provided in an embodiment of the present application, showing the grinding of the top surface of the active region until the top surface of the active region is flush with the top surface of the first sacrificial layer.

[0049] Figure 7 This is a schematic diagram of the structure after removing the first sacrificial layer, provided in an embodiment of this application.

[0050] Figure 8 This is a schematic diagram of a structure in which a gate oxide material and a second sacrificial layer are sequentially formed on an active region, according to an embodiment of this application.

[0051] Figure 9 This is a schematic diagram of a structure provided in an embodiment of the present application for grinding a second sacrificial layer to remove a portion of the thickness of the second sacrificial layer.

[0052] Figure 10 This is a schematic diagram of the structure after etching back the second sacrificial layer to remove the second sacrificial layer of a preset thickness, according to an embodiment of this application.

[0053] Figure 11 This is a schematic diagram of the structure for etching away the gate oxide material in the trench portion according to an embodiment of this application.

[0054] Figure 12 This is a schematic diagram of the structure after removing the second sacrificial layer, provided in an embodiment of this application.

[0055] Figure 13 This is a schematic diagram of the structure after the active region is covered and the trench is filled with gate conductive material, according to an embodiment of this application.

[0056] Figure 14 This is a schematic diagram of the structure after etching away part of the gate conductive material and gate oxide material, according to an embodiment of this application.

[0057] Figure 15 This is a schematic diagram of a structure in which a drift region is formed in the active region exposed on the bottom wall of a trench, according to an embodiment of this application.

[0058] Figure 16 This is a schematic diagram of a sidewall material conformally covering the outer wall of the active region, gate structure, and drift region, according to an embodiment of this application.

[0059] Figure 17This is a schematic diagram of a graphic sidewall material provided in an embodiment of the present application to form a first sidewall structure and a second sidewall structure.

[0060] Figure 18 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0061] The attached figures are labeled as follows:

[0062] 100 - Substrate; 110 - Active region; 120a - Sigma trench; 120 - Trench; 200 - Mask layer; 210 - First sacrificial layer; 220a - Gate oxide material; 230 - Second sacrificial layer; 231 - Step; 240a - Gate conductive material; 241 - First portion; 242 - Second portion; 243 - Third portion; 240 - Gate conductive layer; 220 - Gate oxide layer; 250 - Gate structure; 310 - Drift region; 320a - First dielectric layer; 320b - Second dielectric layer; 321 - First sidewall structure; 322 - Second sidewall structure; 330 - Drain region; 340 - Source region. Detailed Implementation

[0063] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0064] This application provides a semiconductor device.

[0065] Figure 18 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application, as shown below. Figure 18 As shown, the semiconductor device includes a substrate 100, an active region 110, a gate structure 250, a drift region 310, a source region 340, and a drain region 330.

[0066] Specifically, the substrate 100 can be made of silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon on insulator (SOI), germanium on insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), or it can be an organic semiconductor material or other semiconductor materials known in the art.

[0067] Trench isolation structures can be formed on substrate 100. Figure 18(Not shown in the diagram) A trench isolation structure extends from the substrate 100 into the substrate 100 to define an active region 110 within the substrate 100, such that adjacent active regions 110 are isolated from each other by the trench isolation structure. The top of the trench isolation structure may be higher than or flush with the surface of the substrate 100. The material of the trench isolation structure is silicon oxide, but it is not limited thereto. In other embodiments, the trench isolation structure may also be other dielectric materials, such as high-k dielectrics like metal oxides. The active region 110 may be formed by doping the surface of the substrate 100 (e.g., ion implantation), i.e., the active region 110 is a surface portion of the substrate 100, or an epitaxial layer may be formed on the substrate 100 as the active region 110.

[0068] Please continue to refer to Figure 18 A trench 120 is provided in the active region 110 of the substrate 100, extending from the surface of the active region 110 into the active region 110. The gate structure 250 includes a gate oxide layer 220 and a gate conductive layer 240. The gate conductive layer 240 is located on the gate oxide layer 220. The gate oxide layer 220 covers the sidewalls and bottom surface of the gate conductive layer 240. The gate oxide layer 220 covers two opposite inclined sidewalls of the trench 120 and may extend to cover part of the bottom of the trench 120, but exposes at least part of the bottom wall of the trench 120. That is, each of the two gate oxide layers 220 covers one sidewall of the trench 120. It is understood that the active region 110 covered by the gate oxide layer 220 serves as the channel region, i.e., the channel region is sloped or includes a slope. Compared to planar channels, the channel region including a slope (or slope-shaped) in this application can significantly reduce the area occupied by the channel region on the substrate 100 while ensuring the length / width of the channel, thereby reducing the device area and improving chip integration. Moreover, using the solution of this application, the length of the channel region can be adjusted relatively easily by changing the length and depth of the trench 120 sidewalls while ensuring the substrate area occupied, making the device design and integration more flexible. It should be noted that the gate oxide layer 220 covers the sidewalls and part of the bottom wall of the trench 120 in an L-shape. In other embodiments of this application, it is also feasible for the gate oxide layer 220 to only cover the sidewalls of the trench 120.

[0069] Furthermore, the surface of the gate oxide layer 220 away from the channel region (slope surface) has a step 231. Using the step 231 as a boundary, the gate oxide layer 220 can be divided into a first region (located below the step 231) near the drain region 330 (drift region 310) and a second region (located above the step 231) near the source region 340. The thickness of the first region of the gate oxide layer 220 is greater than the thickness of the second region. The position of the step 231 and the thickness difference between the first and second regions in the gate oxide layer 220 can be set according to actual needs. If the length of the second region is too short or the thickness difference between the first and second regions is too small, the gate control capability of the gate structure 250 on the side near the source region 340 may decrease. On the other hand, if the length of the second region is too long or the thickness difference between the first and second regions is too large, the breakdown voltage of the gate structure 250 on the side near the drain region 330 may decrease, or the leakage current of the gate structure 250 on the side near the source region 340 may increase.

[0070] Furthermore, the gate conductive layer 240 conformally covers the surface of the gate oxide layer 220 away from the channel region (including the step 231) and can be wedge-shaped, meaning that the thickness of the region of the gate conductive layer 240 near the source region 340 is less than the thickness of the region near the drain region 330, and the thickness of the gate conductive layer 240 gradually increases from the source region 340 to the drain region 330. Therefore, the gate control capability can also gradually increase from the source region 340 to the drain region 330, which is more in line with actual application scenarios.

[0071] Please continue reading. Figure 18The semiconductor device also includes a first sidewall structure 321 and a second sidewall structure 322. The first sidewall structure 321 is located on the side of the gate structure 250 near the source region 340, while the source region 340 is located in the active region 110 at the edge of the trench 120, more specifically in the active region 110 on the side of the first sidewall structure 321 away from the gate structure 250. The first sidewall structure 321 covers the edge of the gate oxide layer 220 near the source region 340 and protrudes from the surfaces of the source region 340 and the gate structure 250. A drift region 310 is located in the active region 110 on the bottom wall of the trench 120, and a drain region 330 is located in the drift region 310, with the drift region 310 in contact with the drain region 330. The second sidewall structure 322 is located on the side of the gate structure 250 near the drain region 330, and covers the sidewall of the gate structure 250 near the drain region 330. In other words, the second sidewall structure 322 covers the edge of the gate oxide layer 220 near the drain region 330 and the sidewall of the gate conductive layer 240 above it. Understandably, the first sidewall structure 321 and the second sidewall structure 322 cover the edges of both sides of the gate oxide layer 220, respectively. During the process of heavy doping ion implantation to form the source region 340 and the drain region 330, the first sidewall structure 321 and the second sidewall structure 322 can protect the gate oxide layer 220 and prevent the source and drain ions from directly bombarding the gate oxide layer 220 during implantation. At the same time, with the blocking effect of the first sidewall structure 321 and the second sidewall structure 322, the source and drain doping ions will not be implanted into the active region 110 below the first sidewall structure 321 and the second sidewall structure 322. The formed source region 340 and drain region 330 can be further away from the gate structure 250. Therefore, the first sidewall structure 321 and the second sidewall structure 322 can increase the distance between the source region 340 and the drain region 330 and the gate conductive layer 240, thereby reducing parasitic capacitance.

[0072] In some embodiments, the material of the gate oxide layer 220 may be a dielectric material such as silicon oxide or silicon oxynitride, but should not be limited thereto; the material of the gate conductive layer 240 may be a gate conductive material such as polysilicon or metal, but should not be limited thereto.

[0073] In some embodiments, the first sidewall structure 321 and the second sidewall structure 322 may include a first dielectric layer 320a and a second dielectric layer 320b formed sequentially. In the first sidewall structure 321, the first dielectric layer 320a covers the edge of the gate oxide layer 220 near the source region 340, and the second dielectric layer 320b is located on the first dielectric layer 320a; in the second sidewall structure 322, the first dielectric layer 320a covers the edge of the gate oxide layer 220 near the drain region 330 and the sidewall of the gate conductive layer 240 near the drain region 330, and the second dielectric layer 320b covers the sidewall of the first dielectric layer 320a. The material of the first dielectric layer 320a may be a dielectric material such as silicon oxide, silicon oxynitride, or silicon oxycarbide, and its thickness may be 50 angstroms to 100 angstroms; the material of the second dielectric layer 320b may be a dielectric material such as silicon nitride, and its thickness may be 100 angstroms to 150 angstroms.

[0074] In some embodiments, the type of dopant ions in the source region 340, drain region 330, and drift region 310 can be consistent with the type of transistor to be formed. For example, when the semiconductor device includes an N-type power device, the dopant ions in the source region 340, drain region 330, and drift region 310 can be one or more N-type ions selected from P, As, or Sb; when the semiconductor device is a P-type power device, the dopant ions in the source region 340, drain region 330, and drift region 310 can be one or more P-type ions selected from B, Ga, or In.

[0075] In some embodiments, the trench 120 may also be a part of a sigma trench (specifically, the part below the inflection point of the sidewall of the sigma trench). The width of the trench 120 gradually decreases along the direction close to the substrate 100 so that the sidewall of the trench 120 is inclined, that is, the trench 120 has an inverted trapezoidal structure that is wider at the top and narrower at the bottom. The inclination angle α of the sidewall of the trench 120 may be 45° to 52°, the length of the bottom surface of the trench 120 may be 400nm to 500nm, the length of the sidewall of the trench 120 may be 40nm to 50nm, and the depth of the trench 120 may be 300nm to 500nm, but should not be limited thereto.

[0076] Based on this, one embodiment of this application also provides a method for fabricating a semiconductor device. Figure 1 A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application is shown below. Figure 1 As shown, the method for fabricating a semiconductor device includes:

[0077] Step S100: Provide a substrate with an active region on its surface, and form a trench with inclined sidewalls in the active region;

[0078] Step S200: A gate structure is formed in the trench. The gate structure includes a gate oxide layer and a gate conductive layer. The gate oxide layer covers two opposite inclined sidewalls of the trench and exposes at least part of the bottom wall of the trench. The gate conductive layer is located on the gate oxide layer and the gate oxide layer wraps around the sidewalls and bottom surface of the gate conductive layer. The active region under the gate oxide layer is used as the channel region.

[0079] Step S300: A drift region is formed in the active area exposed on the bottom wall of the trench, and the drift region is in contact with the channel area;

[0080] Step S400: A drain region is formed in the drift region, and a source region is formed in the active region at the edge of the trench.

[0081] Figures 2-18 This is a schematic diagram of the structure corresponding to the respective steps of the method for fabricating a semiconductor device according to an embodiment of this application. Next, we will combine... Figures 2-18 The method for fabricating the semiconductor device provided in this application is described in detail.

[0082] like Figure 2 As shown, step S100 is first performed to provide a substrate 100. The material of the substrate 100 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), silicon carbide (SiC), gallium nitride (GaN), indium phosphide (InP), zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc., or it can be an organic semiconductor material or other semiconductor materials known in the art. The active region 110 can be formed by doping the surface of the substrate 100 (e.g., ion implantation), or by forming an epitaxial layer on the substrate 100 as the active region 110.

[0083] like Figures 2-7 As shown, a trench 120 is formed in the active region 110 on the substrate 100.

[0084] Specifically, such as Figure 2 As shown, a mask layer 200 is formed on the active region 110, and the mask layer 200 is patterned using photolithography and etching processes. The material of the mask layer 200 may include silicon oxide and silicon nitride, wherein the thickness of the silicon nitride may be 200 angstroms to 500 angstroms.

[0085] Next, the active region 110 is etched using the patterned mask layer 200 as a mask to form a sigma groove 120a in the active region 110. The sigma groove 120a extends downward from the surface of the active region 110 into the active region 110. Specifically, the active region 110 can be etched first using a dry etching process to form the initial shape of the sigma groove 120a. The initial shape of the sigma groove 120a can be U-shaped, bowl-shaped, saucer-shaped, rectangular, or inverted trapezoidal, etc. Then, a wet etching process is used to continue etching along the sidewalls and bottom of the sigma groove 120a. The etchant of the wet etching process flows into the sigma groove 120a and continues to etch the active region 110 within the sigma groove 120a. Since the etchant of the wet etching process is selective for crystal orientation, the shape and size of the sigma groove 120a will change after etching, forming the final shape of the sigma groove 120a. The final shape of the sigma groove 120a is sigma-shaped (also known as Σ-shaped or diamond-shaped). In some embodiments, the etchant used in the wet etching process of the active region 110 can be tetramethylammonium hydroxide (TMAH) or potassium hydroxide (KOH). <111> The etching rate of the crystal orientation is lower than that of other crystal orientations. After etching is completed, the sigma groove 120a forms its final shape.

[0086] Please continue reading. Figure 2 After forming the sigma groove 120a, the length of the bottom of the sigma groove 120a can be 400nm~600nm, the depth of the sigma groove 120a can be 500angstroms~700angstroms, the sidewall of the sigma groove 120a has an inflection point at the height position H1, and the part of the sidewall of the sigma groove 120a below the inflection point is inclined, and the inclination angle α is 45°~52°.

[0087] like Figure 3 As shown, a first sacrificial layer 210 is filled within the sigma trench 120a. Specifically, the first sacrificial layer 210 is deposited within the mask layer 200 and the sigma trench 120a. At this time, the first sacrificial layer 210 covers the mask layer 200 and fills the sigma trench 120a. It should be noted that the first sacrificial layer 210 needs to serve as a grinding stop layer in subsequent processes. Therefore, the material of the first sacrificial layer 210 can be a material with high hardness, such as silicon nitride. Furthermore, the deposition thickness of the first sacrificial layer 210 can be greater than the depth of the sigma trench 120a. Therefore, after the formation of the first sacrificial layer 210, it can completely fill the sigma trench 120a, facilitating subsequent processes. The thickness of the first sacrificial layer 210 can be, for example, 900 angstroms to 1200 angstroms.

[0088] like Figure 4As shown, a polishing process is performed using the surface of the active region 110 (e.g., silicon) as a polishing stop layer to remove the first sacrificial layer 210 and the mask layer 200 on the surface of the active region 110, exposing the surface of the active region 110. From Figure 4 As can be seen, after the polishing process, the surface of the active region 110 and the top surface of the first sacrificial layer 210 are flush, and both the top surfaces of the active region 110 and the first sacrificial layer 210 are higher than the height position H1. It is understood that this step removes a portion of the thickness of the first sacrificial layer 210, which can reduce the subsequent etching amount of the first sacrificial layer 210, thereby reducing the process difficulty. In some embodiments, the step of performing the polishing process to remove a portion of the thickness of the active region 110 and the first sacrificial layer 210 can be omitted.

[0089] like Figure 5 As shown, the first sacrificial layer 210 is removed by etching back until the top surface of the first sacrificial layer 210 in the sigma trench 120a is flush with the inflection point of the sidewall of the sigma trench 120a. In some embodiments, a wet process can be used to control the removal of a portion of the thickness of the first sacrificial layer 210 by controlling the etching time, so that the top surface of the first sacrificial layer 210 is flush with the inflection point of the sidewall of the sigma trench 120a. In other embodiments, it is also feasible for the top surface of the first sacrificial layer 210 to be slightly lower than the inflection point of the sidewall of the sigma trench 120a.

[0090] Understandably, compared to directly using a grinding process to grind the top surface of the first sacrificial layer 210 to be flush with the inflection point of the sidewall of the sigma groove 120a (which is difficult to set as a reference grinding stop layer), the wet etching process can precisely etch the first sacrificial layer 210 to be flush with the inflection point of the sidewall of the sigma groove 120a, and the process is easier to control.

[0091] It should be noted that when etching back the first sacrificial layer 210, the etching amount can be precisely controlled to avoid abnormal morphology of the sidewalls of the subsequently formed trench 120 due to insufficient etching amount. At the same time, excessive etching amount should be avoided to prevent the sidewalls of the subsequently formed trench 120 from becoming shorter.

[0092] like Figure 6 As shown, the grinding process is performed with the first sacrificial layer 210 as the grinding stop layer to remove part of the active region 110 until the surface of the active region 110 is flush with the surface of the first sacrificial layer 210. At this time, the surface of the active region 110 and the top surface of the first sacrificial layer 210 are both located at the height position H1. The remaining part of the sigma groove 120a can form the trench 120. At this time, the trench 120 is still filled by the first sacrificial layer 210.

[0093] Understandably, the trench 120, as part of the sigma trench 120a, has inclined sidewalls. Compared to directly etching the active region 110 (substrate 100) to form the trench 120 with inclined sidewalls, forming the trench 120 by means of the sigma trench 120a can automatically form the trench 120 with inclined sidewalls. The inclination angle α of the sidewalls of the trench 120 can be automatically controlled between 45° and 52°. The angle α of the sidewalls of the trench 120 is easier to control, the process is simple, and no additional photomask is required, thus saving costs.

[0094] like Figure 7 As shown, the first sacrificial layer 210 is removed using a process such as wet etching.

[0095] like Figures 8-14 As shown, step S200 is performed to form a gate structure 250 within the trench 120.

[0096] Specifically, such as Figure 8 As shown, a gate oxide material 220a and a second sacrificial layer 230 are sequentially formed on the active region 110. The gate oxide material 220a and the second sacrificial layer 230 sequentially cover the surface of the active region 110 and together fill the trench 120. For example, the gate oxide material 220a can conformally cover the surface of the active region 110 and the bottom and sidewalls of the trench 120, and the second sacrificial layer 230 can cover the surface of the gate oxide material 220a and completely fill the trench 120. The sum of the thicknesses of the gate oxide material 220a and the second sacrificial layer 230 needs to be greater than the depth of the trench 120, such that the top surface of the second sacrificial layer 230 is higher than the top surface of the trench 120. In some embodiments, the thickness of the gate oxide material 220a can be set according to the voltage withstand range of the semiconductor device; for example, the thickness of the gate oxide material 220a can be 400 angstroms to 600 angstroms. The material of the second sacrificial layer 230 can be selected from materials that have a larger etching selectivity and polishing selectivity than the gate oxide material 220a. For example, if the material of the gate oxide material 220a can include silicon oxide, the material of the second sacrificial layer 230 can include silicon nitride.

[0097] like Figure 9 As shown, a polishing process is performed using the gate oxide material 220a as the polishing stop layer, polishing the second sacrificial layer 230 to remove a portion of its thickness until a portion of the surface of the gate oxide material 220a is exposed. From Figure 9 As can be seen, the gate oxide material 220a at this time has a planar portion and a recessed portion. The planar portion covers the active region 110 outside the trench 120 and is exposed. The recessed portion covers the surface of the active region 110 inside the trench 120 and is covered by the second sacrificial layer 230. The surface of the planar portion of the gate oxide material 220a is flush with the top surface of the second sacrificial layer 230.

[0098] like Figure 10 As shown, the second sacrificial layer 230 of a predetermined thickness D is removed by back etching, reducing the thickness of the remaining second sacrificial layer 230 in the trench 120 and exposing a portion of the recessed gate oxide material 220a from the second sacrificial layer 230. Similarly, a wet process (high selectivity) can be used, combined with etching time, to precisely control the predetermined thickness D. In some embodiments, D can be 1 / 4 to 1 / 2 of the trench 120 depth.

[0099] It should be noted that when etching back to remove the second sacrificial layer 230, the etching amount can be precisely controlled to avoid insufficient etching amount, which would result in insufficient exposed ramp gate oxide length on the side (near the source region) and reduce the gate control capability on that side. At the same time, excessive etching amount should be avoided, which would result in insufficient gate oxide length on the other side (near the drain region) and reduce the breakdown voltage.

[0100] like Figure 11 As shown, the exposed gate oxide 220a is etched so that the thickness of the gate oxide 220a above the second sacrificial layer 230 in the trench 120 is less than the thickness of the gate oxide 220a below the second sacrificial layer 230 in the trench 120. In other words, the thickness of the gate oxide 220a protected by the second sacrificial layer 230 is greater than the thickness of the gate oxide 220a exposed by the second sacrificial layer 230. That is, the gate oxide 220a located on the sidewall of the trench 120 has a step 231 (step structure). In some embodiments, a wet etching process can be used to etch the gate oxide 220a to remove part of the thickness of the exposed gate oxide 220a. Of course, it is feasible to completely or partially remove the planar portion of the gate oxide 220a.

[0101] It should be noted that the etching amount can be precisely controlled when etching away the gate oxide material 220a. This avoids the gate oxide material 220a step 231 being indistinct due to insufficient etching, which would reduce the control of the channel by the gate on that side. At the same time, excessive etching should be avoided, which would result in the gate oxide material 220a on the sidewall of the trench 120 being too thin and causing leakage.

[0102] like Figure 12 As shown, the second sacrificial layer 230 is removed using a process such as wet etching.

[0103] like Figure 13As shown, a gate conductive material 240a is formed to cover the surface of the gate oxide material 220a and fill the trench 120. In some embodiments, the gate conductive material 240a may be made of, for example, polycrystalline silicon or doped polycrystalline silicon, and may be formed using a CVD process or a furnace tube process. The thickness of the formed gate conductive material 240a may be greater than the depth of the trench 120, so that the gate conductive material 240a completely fills the trench 120. Figure 13 As can be seen, the gate conductive material 240a at this time includes a first part 241 located on the active region 110 outside the trench 120, a second part 242 located on the sidewall of the trench 120, and a third part 243 located on the bottom wall of the trench 120. The first part 241 and the third part 243 are planar, and the second part 242 is sloping.

[0104] like Figure 14 As shown, an anisotropic etching process is performed to etch the gate conductive material 240a and the gate oxide material 220a, exposing the surface of the active region 110 outside the trench 120 and the bottom wall of the trench 120, while retaining the gate oxide material 220a and part of the gate conductive material 240a on the sidewall of the trench 120. In other words, the gate conductive material 240a of the first part 241 and the third part 243 is etched away, while part of the gate conductive material 240a of the second part 242 is retained. The remaining gate conductive material 240a serves as the gate conductive layer 240, and the remaining gate oxide material 220a located below the gate conductive layer 240 serves as the gate oxide layer 220. The gate oxide layer 220 and the gate conductive layer 240 constitute the gate structure 250, and the active region 110 below the gate structure 250 serves as the channel region. In some embodiments, the anisotropic etching process described above can be a dry etching process. When etching ions are perpendicularly directed towards the first portion 241, the second portion 242, and the third portion 243, the etching rate of the second portion 242 is lower than that of the first portion 241 and the third portion 243 because the surface of the second portion 242 is sloped. This results in the second portion 242 being exposed when the first portion 241 and the third portion 243 are removed. In other embodiments, after etching away the gate conductive material 240a of the first portion 241 and the third portion 243, the remaining gate oxide material 220a below them can be etched to expose the surface of the active region 110.

[0105] Please continue to refer to Figure 14After the etching process described above, a gate structure 250 is formed on each of the two sidewalls of the trench 120. In each gate structure 250, the gate conductive layer 240 can be irregularly wedge-shaped. The thickness of the gate conductive layer 240 near the opening of the trench 120 is less than the thickness near the center of the trench 120. The surface of the gate oxide layer 220 has a step 231, and the thickness of the gate oxide layer 220 near the opening of the trench 120 is less than the thickness near the center of the trench 120. In addition, the two gate structures 250 can extend to cover part of the bottom wall of the trench 120, in addition to covering the sidewalls of the trench 120. It can be seen that compared with forming the gate structure 250 by photolithography and etching processes, this application uses the inclined sidewalls of the trench 120 to directly etch the gate structure 250, which is not only simple in process but also eliminates the need for a photomask, saving costs. In addition, this application forms an inclined (slope-shaped) gate structure 250 on the sidewall of the trench 120, and uses the active region 110 of the sidewall of the trench 120 as the channel region to form a slope-shaped channel region (or a channel region including a slope). This can significantly reduce the area of ​​the substrate 100 occupied by the channel region while ensuring the length / width of the channel, thereby reducing the area of ​​the device and improving the chip integration.

[0106] like Figure 15 As shown, step S300 is performed to form a drift region 310 in the active region 110 exposed on the bottom wall of trench 120. Specifically, a patterned mask layer can first be formed to cover the active region 110 and gate structure 250 outside trench 120. The patterned mask layer has an opening that exposes the active region 110 at the bottom of trench 120. Then, ion implantation of drift region 310 is performed to form drift region 310 in the exposed active region 110. In some embodiments, the semiconductor device formed in active region 110 can be an NLDMOS device, and the ion implantation of drift region 310 can be lightly doped N-type ion implantation.

[0107] like Figures 16-18 As shown, step S400 is performed to form a drain region 330 in the drift region 310 and a source region 340 in the active region 110 at the edge of the trench 120.

[0108] Specifically, such as Figure 16 As shown, a sidewall material conformally covers the outer walls of the active region 110, the gate structure 250, and the drift region 310. The sidewall material may include a first dielectric layer 320a and a second dielectric layer 320b formed sequentially. The first dielectric layer 320a may include silicon oxide, and the second dielectric layer 320b may include silicon nitride. Both may be formed using a CVD process. The first dielectric layer 320a and the second dielectric layer 320b cover the surface of the active region 110, the surface of the drift region 310, the surface of the gate structure 250, and the sidewalls.

[0109] like Figure 17 As shown, the sidewall material is patterned, and the remaining sidewall material is used as the first sidewall structure 321 and the second sidewall structure 322. At this time, the first sidewall structure 321 is located at the opening of the trench 120 and covers the edge of the gate oxide layer 220 on that side. The first sidewall structure 321 protrudes from the surface of the active region 110 and the gate structure 250. The second sidewall structure 322 is located in the trench 120 and covers the sidewall of the gate structure 250. In some embodiments, a patterned mask layer formed on the sidewall material, the patterned mask layer being strip-shaped, covers the edge region of the gate structure 250 facing the outside of the trench 120. The sidewall material in this region is retained after dry etching and serves as a first sidewall structure 321 to protect the edge of the gate structure 250 on this side. Meanwhile, the sidewall material covering the other side of the gate structure 250 (facing the bottom wall of the trench 120) is retained as a second sidewall structure 322 because it is thicker in the etching direction (even if it does not cover the mask layer), to protect the sidewall of the gate structure 250. The sidewall material in the remaining areas not covered by the mask layer is removed after dry etching, exposing the surface of the active region 110 and the surface of the drift region 310 outside the trench 120, and then the patterned mask layer is removed.

[0110] like Figure 18 As shown, a patterned mask layer is formed to cover the gate structure 250, at least part of the first sidewall structure 321 and the second sidewall structure 322, and the active regions 110 on both sides of the first sidewall structure 321 and the second sidewall structure 322 are heavily doped with ions to form the source region 340 and the drain region 330.

[0111] from Figure 18 As can be seen, the first sidewall structure 321 and the second sidewall structure 322 respectively cover the edges of both sides of the gate oxide layer 220. During the heavy doping ion implantation process, the first sidewall structure 321 and the second sidewall structure 322 can protect the gate oxide layer 220 and prevent the source and drain ions from directly bombarding the gate oxide layer 220. At the same time, with the blocking effect of the first sidewall structure 321 and the second sidewall structure 322, the source and drain doping ions will not be implanted into the active region 110 below the first sidewall structure 321 and the second sidewall structure 322. The formed source region 340 and drain region 330 can be further away from the gate structure 250. Therefore, the first sidewall structure 321 and the second sidewall structure 322 can increase the distance between the source region 340 and drain region 330 and the gate conductive layer 240, thereby reducing parasitic capacitance.

[0112] In summary, this embodiment provides a semiconductor device and its fabrication method, comprising: a substrate having an active region on the substrate, and a trench with inclined sidewalls within the active region; a gate structure including a gate oxide layer and a gate conductive layer, the gate oxide layer covering two opposing inclined sidewalls of the trench and exposing at least a portion of the bottom wall of the trench, the gate conductive layer being located on the gate oxide layer, the gate oxide layer enclosing the sidewalls and bottom surface of the gate conductive layer; a channel region located in the active region below the gate oxide layer; a drift region located in the active region on the bottom wall of the trench and in contact with the channel region; a source region and a drain region, the drain region being located in the drift region, and the source region being located in the active region at the edge of the trench; a first sidewall structure and a second sidewall structure, the first sidewall structure being located on the side of the gate structure near the source region and protruding from the surface of the source region and the gate structure, and the second sidewall structure being located on the drift region and covering the sidewall of the gate structure near the drain region. An unexpected effect of this application is that by placing the gate structure on the sidewall of the trench and using the active region of the trench sidewall as the channel region, the device area is reduced while maintaining the length / width of the channel, thereby improving chip integration. Furthermore, a protruding first sidewall structure is provided on the side of the gate structure near the source region (outside the trench), and a second sidewall structure is provided on the side of the gate structure near the drain region (inside the trench), covering the sidewall of the gate structure. On the one hand, the first and second sidewall structures can protect the gate oxide layer, preventing direct bombardment of the gate oxide layer during source / drain ion implantation. On the other hand, the first and second sidewall structures can increase the distance between the source / drain regions and the gate conductive layer, thereby reducing parasitic capacitance.

[0113] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0114] It should also be noted that although preferred embodiments have been disclosed above, these embodiments are not intended to limit this application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application, or modify them into equivalent embodiments, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application, without departing from the content of the technical solutions of this application, shall still fall within the scope of protection of the technical solutions of this application.

[0115] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0116] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of this application. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates the opposite. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood as having the definition of logical “or”, not logical “exclusive OR”, unless the context clearly indicates the opposite. Furthermore, implementations of the methods and / or devices in the embodiments of this application may include performing selected tasks manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that, include: A substrate having an active region thereon, wherein the active region has a trench with inclined sidewalls; A gate structure includes a gate oxide layer and a gate conductive layer, the gate oxide layer covering two opposing inclined sidewalls of the trench and exposing at least a portion of the bottom wall of the trench, the gate conductive layer being located on the gate oxide layer, and the gate oxide layer enclosing the sidewalls and bottom surface of the gate conductive layer; The channel region is located in the active region beneath the gate oxide layer; The drift region is located in the active region of the bottom wall of the trench and is in contact with the channel region; The source region and the drain region, wherein the drain region is located in the drift region and the source region is located in the active region at the edge of the trench; A first sidewall structure and a second sidewall structure, wherein the first sidewall structure is located on the side of the gate structure near the source region and protrudes from the surface of the source region and the gate structure, and the second sidewall structure is located on the drift region and covers the sidewall of the gate structure near the drain region. The surface of the gate oxide layer away from the channel region includes a step, and the thickness of the gate oxide layer near the drain region is greater than the thickness of the gate oxide layer near the source region.

2. The semiconductor device according to claim 1, characterized in that, The trench is part of a sigma trench, and the width of the trench gradually decreases in the direction close to the substrate so that the sidewalls of the trench are inclined.

3. The semiconductor device according to claim 1, characterized in that, The gate conductive layer is wedge-shaped, with a thickness near the source region that is less than the thickness near the drain region.

4. The semiconductor device according to claim 1, characterized in that, The gate structure also extends to cover a portion of the active region at the bottom of the trench, making the gate structure L-shaped.

5. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, the surface of which has an active region, and a trench with inclined sidewalls is formed in the active region; A gate structure is formed within the trench. The gate structure includes a gate oxide layer and a gate conductive layer. The gate oxide layer covers two opposing inclined sidewalls of the trench and exposes at least a portion of the bottom wall of the trench. The gate conductive layer is located on the gate oxide layer and encloses the sidewalls and bottom surface of the gate conductive layer. The active region under the gate oxide layer serves as the channel region. The surface of the gate oxide layer away from the channel region includes steps. The thickness of the gate oxide layer near the drain region is greater than the thickness of the gate oxide layer near the source region. A drift region is formed in the active region exposed on the bottom wall of the trench, and the drift region is in contact with the channel region; A drain region is formed in the drift region, and a source region is formed in the active region at the edge of the trench.

6. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The step of forming a trench with inclined sidewalls within the active region further includes: The active region is etched using a dry process and a wet process including TMAH to form a sigma trench within the active region; A first sacrificial layer is filled into the sigma groove; The first sacrificial layer is etched back until the top surface of the first sacrificial layer is flush with the inflection point of the sidewall of the sigma groove; A planarization process is performed until the top surface of the active region is flush with the top surface of the first sacrificial layer, and the remaining portion of the sigma groove forms the trench. Remove the first sacrificial layer.

7. The method for fabricating a semiconductor device as described in claim 6, characterized in that, The step of forming the gate structure further includes: A gate oxide material is formed to cover the surface of the active region and the bottom and sidewalls of the trench; A gate conductive material is formed to cover the surface of the gate oxide material and fill the trench; The gate conductive material and the gate oxide material on the surface of the active region outside the trench and on the bottom wall of the trench are removed by etching, exposing the surface of the active region on the bottom wall of the trench and the surface of the active region outside the trench. The remaining gate oxide material serves as the gate oxide layer, and the remaining gate conductive material serves as the gate conductive layer.

8. The method for fabricating a semiconductor device as described in claim 7, characterized in that, The step of forming a gate oxide material covering the surface of the active region and the bottom and sidewalls of the trench further includes: The gate oxide material is formed to conformally cover the surface of the active region and the bottom and sidewalls of the trench; A second sacrificial layer is formed to cover the surface of the gate oxide material and fill the trench; The second sacrificial layer on the gate oxide material is removed by grinding, exposing the gate oxide material outside the trench; Etching back removes a portion of the thickness of the second sacrificial layer, exposing a portion of the gate oxide material on the trench sidewalls; Etching removes a portion of the thickness of the exposed gate oxide material; Remove the remaining second sacrificial layer.

9. The method for fabricating a semiconductor device as described in claim 5, characterized in that, The steps of forming the source region and the drain region further include: The sidewall material conformally covers the surfaces of the active region, the gate structure, and the drift region; The sidewall material is patterned, and the remaining sidewall material is used as the first sidewall structure and the second sidewall structure. The first sidewall structure is located on the side of the gate structure near the source region and protrudes from the surface of the source region and the gate structure. The second sidewall structure is located on the drift region and covers the sidewall of the gate structure near the drain region. A patterned mask layer is formed to cover the gate structure, at least a portion of the first sidewall structure and the second sidewall structure. The active regions on both sides of the first sidewall structure and the second sidewall structure are then heavily doped with ions to form the source region and the drain region.

Images