Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device including a high integration memory cell and a method for manufacturing the same are provided. The semiconductor device includes nanosheets arranged in a vertical arrangement and a horizontal arrangement and spaced apart from a surface of a substrate, horizontal wires horizontally oriented and disposed to surround the nanosheets arranged in the horizontal arrangement, vertical wires commonly coupled to the nanosheets arranged in the vertical arrangement and respectively coupled to the nanosheets arranged in the horizontal arrangement, supports disposed between the vertical wires to support the vertical wires, and an array isolation layer including a bridge prevention portion disposed between a bottom portion of the vertical wires and the surface of the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Application No. 10-2024-0191107, filed on December 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of this disclosure relate to a semiconductor device, and more specifically, to a semiconductor device including a three-dimensional (3D) memory cell and a method for manufacturing the semiconductor device. Background Technology

[0004] Recently, there has been an increasing demand for larger capacity and smaller size of storage devices. To address these demands, three-dimensional (3D) storage devices, including stacked memory cells, have been proposed. Summary of the Invention

[0005] Embodiments of this disclosure relate to a semiconductor device including highly integrated memory cells and a method for manufacturing the semiconductor device.

[0006] According to embodiments of the present disclosure, a semiconductor device may include: nanosheets arranged in a vertical and horizontal configuration and spaced apart from the surface of a substrate; horizontal wires horizontally oriented and configured to surround the horizontally arranged nanosheets; vertical wires commonly coupled to the vertically arranged nanosheets and individually coupled to the horizontally arranged nanosheets; supports disposed between the vertical wires to support the vertical wires; and an array isolation layer including bridging prevention portions disposed between the bottom portions of the vertical wires and the surface of the substrate.

[0007] According to embodiments of the present disclosure, a method for manufacturing a semiconductor device may include: forming a mold stack including mold layers vertically stacked on a substrate; forming a sacrificial isolation layer in the mold stack; forming a linear opening penetrating the mold stack and extending into the substrate; replacing a portion of the sacrificial isolation layer with a support through the linear opening; trimming a first portion of the mold layers of the mold stack to form a sliver; forming a sacrificial pouch layer on one side of the sliver; forming a sacrificial protection layer on the bottom surface of the linear opening; removing the sacrificial pouch layer; forming vertical conductors commonly coupled to one side of the sliver; selectively removing the sacrificial protection layer; and forming an array isolation layer including bridging prevention portions filling the linear opening and disposed between the bottom portion of the vertical conductor and the surface of the substrate.

[0008] According to embodiments of the present disclosure, a semiconductor device may include: a first vertical wire spaced apart from the surface of a substrate; a second vertical wire horizontally spaced apart from the first vertical wire; first nanosheets arranged vertically and co-coupled to the first vertical wire; second nanosheets arranged vertically and co-coupled to the second vertical wire; a first horizontal wire horizontally oriented and configured to surround the first nanosheet; a second horizontal wire horizontally oriented and configured to surround the second nanosheet; supports configured to support the first and second vertical wires; and an array isolation layer disposed between the first and second vertical wires, the array isolation layer including bridging prevention portions disposed between the bottom portions of the first and second vertical wires and the surface of the substrate.

[0009] According to embodiments of the present disclosure, a method for manufacturing a semiconductor device may include: forming a mold stack including mold layers vertically stacked on a substrate; forming a sacrificial isolation layer in the mold stack; forming a linear opening penetrating the mold stack and extending into the substrate; replacing a portion of the sacrificial isolation layer with a support through the linear opening; trimming a first portion of the mold layers of the mold stack to form a vesicle; forming a sacrificial pouch layer on one side of the vesicle; forming a sacrificial protection layer on the bottom surface of the linear opening; removing the sacrificial pouch layer; forming a dummy ohmic contact layer on the sacrificial protection layer; forming a vertical conductor commonly coupled to one side of the vesicle; forming a vertical spacer on the vertical conductor; using the vertical spacer as a barrier layer to cut the dummy ohmic contact layer and the sacrificial protection layer; selectively removing the sacrificial protection layer and forming a bottom trench; trimming the bottom surface of the bottom trench; and forming an array isolation layer including a bridging prevention portion filling the linear opening and the bottom trench and disposed between the bottom portion of the vertical conductor and the surface of the substrate. Attached Figure Description

[0010] Figure 1A This is a schematic perspective view illustrating a storage unit according to an embodiment of the present disclosure.

[0011] Figure 1B yes Figure 1A The diagram shows a schematic cross-sectional view of the storage cell.

[0012] Figure 2A This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 2B It is shown Figure 2A A partial perspective view of the first spacer shown.

[0014] Figure 2C It is shown Figure 2A A partial perspective view of the second spacer shown.

[0015] Figure 3 This is a schematic perspective view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0016] Figure 4A This is a schematic plan view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0017] Figure 4B It is along Figure 4A The diagram shows a schematic cross-sectional view of a semiconductor device taken by line AA′.

[0018] Figure 4C It is along Figure 4A The diagram shows a schematic cross-sectional view of a semiconductor device taken by line A1-A1′.

[0019] Figure 4D It is along Figure 4A The diagram shows a schematic cross-sectional view of a semiconductor device taken by line BB′.

[0020] Figures 5A to 28B Various views of a semiconductor device formed using a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown.

[0021] Figure 29 This is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0022] Figures 30 to 34 It shows the use of manufacturing Figure 29 Various views of the semiconductor device formed by the method shown.

[0023] Figure 35A and Figure 35B This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present disclosure.

[0024] Figure 36A and Figure 36B Various views of a stacked assembly according to embodiments of the present disclosure are shown. Detailed Implementation

[0025] The various embodiments of this disclosure described herein can be described with reference to cross-sectional views, plan views, and block diagrams, which are ideal schematic diagrams of semiconductor devices. It should be noted that the structures in the drawings can be modified by manufacturing techniques and / or tolerances. Embodiments of this disclosure are not limited to the described embodiments and the specific structures shown in the drawings, but may include other embodiments or modifications to the described embodiments, including any changes in structure that may arise as required by the manufacturing process. Therefore, the areas shown in the drawings are schematic in nature, and the shapes of the areas shown in the drawings are intended to illustrate specific structures of areas of elements and are not intended to limit the scope of this disclosure.

[0026] The following embodiments provide a three-dimensional storage cell, wherein the storage cells are stacked vertically to increase the storage cell density and reduce parasitic capacitance.

[0027] Figure 1A This is a schematic perspective view illustrating a storage unit MC according to an embodiment of the present disclosure. Figure 1B yes Figure 1A The diagram shows a schematic cross-sectional view of the storage cell MC.

[0028] refer to Figure 1A and Figure 1B The storage unit MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0029] The first conductor BL may be oriented perpendicularly to a first direction D1. The first conductor BL may include a bit line. The first conductor BL may be referred to as a "vertical conductor," "vertically oriented bit line," "vertically extending bit line," or "pillar bit line." The first conductor BL may include a conductive material. The first conductor BL may include a silicon-based material, a metal-based material, or a combination thereof. The first conductor BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductor BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductor BL may include a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked.

[0030] A switching element TR has the function of controlling the voltage or current supplied to the data storage element CAP during data write and data read operations. The switching element TR may include a nanosheet HL, a nanosheet dielectric layer GD, and a second conductor WL. The second conductor WL may include a horizontal conductor or a horizontal word line, and the nanosheet HL may include an active layer. The switching element TR may include a transistor, and in this case, the second conductor WL may serve as a gate electrode. The switching element TR may also be referred to as a "nanosheet transistor," a "cell transistor," an "access element," or a "select element." The second conductor WL may be referred to as a "horizontal gate electrode" or a "horizontal word line."

[0031] The nanosheet HL can extend along a second direction D2 intersecting the first direction D1. The second conductor WL can extend along a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The nanosheet HL can extend along the first horizontal direction (i.e., the second direction D2), and the second conductor WL can extend along the second horizontal direction (i.e., the third direction D3). The nanosheet HL can be referred to as a "horizontal layer".

[0032] The nanosheet HL may include a channel CH, a first doped region SR between the channel CH and a first conductive line BL, and a second doped region DR between the channel CH and a data storage element CAP. The first doped region SR may be electrically coupled to the first conductive line BL, and the second doped region DR may be electrically coupled to the data storage element CAP. The height of the second doped region DR along a first direction D1 may be greater than the height of the channel CH along the first direction D1. The length of the second doped region DR along a second direction D2 may be less than the length of the channel CH along the second direction D2. The lengths of the first doped region SR, the channel CH, and the second doped region DR along a third direction D3 may be equal to each other.

[0033] The nanosheet HL may include a first region NS and a second region WS horizontally disposed along a second direction D2. The second region WS may extend from the first region NS. The thickness of the second region WS may gradually increase from the first region NS toward the data storage element CAP along the second direction D2 between the first region NS and the data storage element CAP. The average vertical height or thickness of the second region WS along the first direction D1 may be greater than the average vertical height or thickness of the first region NS. In the following, the first region NS is referred to as a "narrow wafer", and the second region WS is referred to as a "wide wafer".

[0034] The narrow strip NS can have a flat plate shape. The wide strip WS can have a fan-like shape. The wide strip WS can have a thickness that gradually increases along the second direction D2. The narrow strip NS can be referred to as a "flat strip", while the wide strip WS can be referred to as a "fan-shaped strip". The boundary between the narrow strip NS and the wide strip WS can have curvature.

[0035] The first doped region SR and the channel CH can be disposed in a narrow wafer NS, while the second doped region DR can be disposed in a wide wafer WS. The channel CH formed in the narrow wafer NS can be referred to as a "narrow channel" or a "flat channel". A portion of the second doped region DR can extend to be disposed in the narrow wafer NS. The second doped region DR can include a thick portion disposed in the wide wafer WS and a thin portion disposed in the narrow wafer NS. One side of the wide wafer WS and one side of the second doped region DR (which contact the data storage element CAP) can each have a flat side surface shape.

[0036] The horizontal length of the wide slice WS along the second direction D2 can be less than the horizontal length of the narrow slice NS. The narrow slice NS can be called a "long slice", while the wide slice WS can be called a "short slice".

[0037] Nanosheets HL can include semiconducting materials. For example, nanosheets HL can include polycrystalline silicon, monocrystalline silicon, germanium, or silicon-germanium. In some embodiments, nanosheets HL can include oxide semiconductor materials. For example, oxide semiconductor materials can include indium gallium zinc oxide (IGZO), InSnZnO, ZnSnO, or combinations thereof. In some embodiments, nanosheets HL can include conductive metal oxides. In some embodiments, nanosheets HL can include two-dimensional materials such as MoS2, WS2, or MoSe2.

[0038] When the nanosheet HL is formed from an oxide semiconductor material, the channel CH can also be formed from an oxide semiconductor material, and the first doped region SR and the second doped region DR can be omitted. The nanosheet HL can also be referred to as an active layer or a thin body.

[0039] The first doped region SR and the second doped region DR may be doped with impurities having the same conductivity type. Each doped region in the first doped region SR and the second doped region DR may be doped with an N-type conductive impurity or a P-type conductive impurity. The first doped region SR and the second doped region DR may each include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be coupled to a first conductive line BL, and the second doped region DR may be coupled to a data storage element CAP. The first doped region SR and the second doped region DR may be referred to as the "first source / drain region and the second source / drain region".

[0040] The nanosheet HL can be horizontally oriented from the first wire BL along the second direction D2.

[0041] The second conductor WL can have a gate-all-around (GAA) structure. For example, the second conductor WL can surround the nanosheet HL and extend along the third direction D3. A nanosheet dielectric layer GD can be formed between the nanosheet HL and the second conductor WL. The nanosheet dielectric layer GD can surround the nanosheet HL. The second conductor WL can surround the nanosheet HL on the nanosheet dielectric layer GD.

[0042] The second conductor WL may comprise a metal-based material, a semiconducting material, or a combination thereof. The second conductor WL may comprise molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polycrystalline silicon, or a combination thereof. For example, the second conductor WL may comprise a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second conductor WL may comprise an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, while the P-type work function material may have a high work function of approximately 4.5 eV or greater. The second conductor WL may comprise a stack of low work function materials or high work function materials.

[0043] A nanosheet dielectric layer GD can be disposed between the nanosheet HL and the second conductive line WL. The nanosheet dielectric layer GD can be referred to as a "gate dielectric layer" or a "channel-side dielectric layer". The nanosheet dielectric layer GD can include silicon oxide, silicon nitride, metal oxides, metal oxynitrides, metal silicates, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. The nanosheet dielectric layer GD can include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or combinations thereof. The nanosheet dielectric layer GD can be formed by a thermal oxidation process of a semiconducting material. In some embodiments, the nanosheet dielectric layer GD can be formed by a deposition and oxidation process of the nanosheet dielectric material.

[0044] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally disposed from the switching element TR along a second direction D2. The data storage element CAP may include a first electrode SN, a second electrode PN on the first electrode SN, and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN may extend horizontally from the nanosheet HL along the second direction D2. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally disposed along the second direction D2. The first electrode SN may include an inner space and multiple outer surfaces, and the inner space of the first electrode SN may include multiple inner surfaces. The outer surfaces of the first electrode SN may include vertical outer surfaces and multiple horizontal outer surfaces. The vertical outer surface of the first electrode SN may extend vertically along a first direction D1, and the horizontal outer surfaces of the first electrode SN may extend horizontally along either the second direction D2 or a third direction D3. The inner space of the first electrode SN may be three-dimensional. The dielectric layer DE may conformally cover the inner surface of the first electrode SN. The second electrode PN may be disposed in the inner space of the first electrode SN on the dielectric layer DE. Some outer surfaces of the first electrode SN may be electrically coupled to a second doped region DR of the nanosheet HL. The second electrode PN of the data storage element CAP can be coupled to the common board PL.

[0045] The data storage element CAP can have a three-dimensional structure. The first electrode SN can also have a three-dimensional structure, which may be a horizontal three-dimensional structure oriented along a second direction D2. In an example of a three-dimensional structure, the first electrode SN can have a cylindrical shape. The cylindrical shape of the first electrode SN may include an inner cylindrical surface and an outer cylindrical surface. Some of the outer cylindrical surfaces of the first electrode SN can be electrically coupled to a second doped region DR of the nanosheet HL. A dielectric layer DE and a second electrode PN can be disposed on the inner and outer cylindrical surfaces of the first electrode SN.

[0046] In some embodiments, the first electrode SN may have a cylindrical or columnar shape. A cylindrical shape may refer to a structure in which a cylindrical and columnar shape are combined.

[0047] The first electrode SN and the second electrode PN can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN can include: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum nitride (MoN), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium nitride / titanium silicon nitride (TiN / TiSiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or combinations thereof. The second electrode PN can also include a combination of metal-based materials and silicon-based materials. For example, the second electrode PN can be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In the titanium nitride / germanium silicon / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be the interstitial filling material filling the interior of the first electrode SN, titanium nitride (TiN) can be used as the second electrode PN of the data storage element CAP, and tungsten nitride can be a low-resistance material.

[0048] The dielectric layer DE can be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer DE can include silicon oxide, silicon nitride, high-k materials, perovskite materials, or combinations thereof. High-k materials can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In some embodiments, the dielectric layer DE can be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0049] The dielectric layer DE can be formed of zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure comprising zirconium oxide (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. A ZA stack can have a structure in which alumina (Al2O3) is stacked on zirconium oxide (ZrO2). A ZAZ stack can have a structure in which zirconium oxide (ZrO2), alumina (Al2O3), and zirconium oxide (ZrO2) are sequentially stacked. Each of the ZA and ZAZ stacks can be referred to as a "zirconia (ZrO2) substrate." In some embodiments, the dielectric layer DE can be formed of hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure comprising hafnium oxide (HfO2). The dielectric layer DE can include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. HA stacks can have a structure in which alumina (Al₂O₃) is stacked on hafnium oxide (HfO₂). HAH stacks can have a structure in which hafnium oxide (HfO₂), alumina (Al₂O₃), and hafnium oxide (HfO₂) are stacked sequentially. Each of the HA and HAH stacks can be referred to as a "hafnium oxide (HfO₂) substrate." In ZA, ZAZ, HA, and HAH stacks, alumina (Al₂O₃) can have a larger band gap energy than zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). Alumina (Al₂O₃) can have a lower dielectric constant than zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). Therefore, the dielectric layer DE can comprise a stack of high-k materials and high-bandgap materials, where the high-bandgap material has a larger band gap energy than the high-k materials. The dielectric layer DE may include silicon oxide (SiO2) as a high bandgap material other than aluminum oxide (Al2O3). Because the dielectric layer DE includes a high bandgap material, leakage current can be suppressed. The high bandgap material can be thinner than the high-k material. In some embodiments, the dielectric layer DE may include a stacked structure in which high-k material and high bandgap material are alternately stacked.For example, the dielectric layer DE can include ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack, HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stack, ZHZAZHZ (ZrO2 / HfO2 / ZrO2 / Al2O3 / ) stack, and ZHZAZHZ (ZrO2 / HfO2 / ZrO2 / Al2O3 / ) stack. The stacked structures can be ZrO2 / HfO2 / ZrO2, ZHZAZHZA (ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3), ZHZAZHZAT (ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2), HZHZ (HfO2 / ZrO2 / HfO2 / ZrO2), or AHZAZHA (Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3). In these stacked structures, alumina (Al2O3) can be thinner than zirconium oxide (ZrO2) and hafnium oxide (HfO2).

[0050] In some embodiments, the dielectric layer DE may include a high-k material and a high-bandgap material. The dielectric layer DE may have a stacked structure in which multiple high-k materials and multiple high-bandgap materials are stacked, or a hybrid structure in which high-k materials and high-bandgap materials are mixed.

[0051] In some embodiments, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0052] In some embodiments, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, or a combination of a high-k material or a ferroelectric material and an antiferroelectric material.

[0053] In some embodiments, the data storage element CAP may further include multiple interface control layers to mitigate leakage current. Each interface control layer may comprise titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or a combination thereof. A first interface control layer may be formed between the first electrode SN and the dielectric layer DE, and a second interface control layer may be formed between the dielectric layer DE and the second electrode PN. The first and second interface control layers may be made of the same material or different materials.

[0054] For example, a structure in which the first interface control layer, the dielectric layer DE, and the second interface control layer are stacked sequentially may include an NZHZAZHZATN (Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0055] Data storage element CAP can include a three-dimensional capacitor. Data storage element CAP can include a metal-insulator-metal (MIM) capacitor. Data storage element CAP can be replaced with another data storage material. For example, the data storage material can be a thyristor, phase change material, magnetic tunnel junction (MTJ), or variable resistance material.

[0056] The memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may be disposed between the first conductive line BL and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconducting material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node BLC may include doped polycrystalline silicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconducting material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC may include doped silicon, and the second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC along the first direction D1 may be less than the height of the second contact node SNC along the first direction D1. The height of the first contact node BLC along the first direction D1 may be greater than the height of the channel CH along the first direction D1. The first contact node BLC and the second contact node SNC may each comprise polysilicon doped with N-type impurities, such as phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0057] In some embodiments, the second contact node SNC can be selectively grown from a wide sheet WS of the nanosheet HL. The second contact node SNC can be formed by selective epitaxial growth (SEG). For example, the second contact node SNC can be a silicon epitaxial layer formed by SEG. The second contact node SNC can be a doped silicon epitaxial layer, for example, a silicon epitaxial layer doped with N-type impurities.

[0058] In some embodiments, the first contact node BLC can also be selectively grown from the narrow NS of the nanosheet HL. The first contact node BLC can be formed by selective epitaxial growth (SEG). For example, the first contact node BLC can be a silicon epitaxial layer formed by SEG. The first contact node BLC can be a doped silicon epitaxial layer, for example, a silicon epitaxial layer doped with N-type impurities.

[0059] The first contact node BLC can be a narrow-side contact node, while the second contact node SNC can be a wide-side contact node.

[0060] The nanosheet HL may include a first edge and a second edge. The first edge may refer to a portion of a first doped region SR electrically coupled to a first wire BL, and the second edge may refer to a portion of a second doped region DR electrically coupled to a first electrode SN of a data storage element CAP.

[0061] The memory cell MC may also include an ohmic contact layer BLO between the first contact node BLC and the first conductor BL. The ohmic contact layer BLO may include a metal silicide such as titanium silicide or molybdenum silicide.

[0062] The memory cell MC may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second conductor WL and the second doped region DR. The second spacer SP2 may be disposed between the first conductor BL and the second conductor WL. The second spacer SP2 may include a stack of a first liner L1 and a second liner L2. The first spacer SP1 and the second spacer SP2 may each comprise a dielectric material. The first spacer SP1 and the second spacer SP2 may each comprise silicon oxide, silicon nitride, or a combination thereof. The first spacer SP1 may comprise silicon nitride. The first liner L1 of the second spacer SP2 may be silicon nitride, while the second liner L2 of the second spacer SP2 may be silicon oxide. The second liner L2 may partially fill the internal space of the first liner L1.

[0063] The first conductor BL may include multiple horizontal extensions BLE1, BLE2, and BLE3. The horizontal extensions BLE1, BLE2, and BLE3 may extend along a second direction D2. The horizontal extensions may include an inner horizontal extension BLE2 and outer horizontal extensions BLE1 and BLE3. The inner horizontal extension BLE2 of the first conductor BL may extend to be disposed in the gap between first liner L1s that are perpendicularly adjacent to each other. Therefore, the inner horizontal extension BLE2 of the first conductor BL can be electrically coupled to the ohmic contact layer BLO.

[0064] The outer horizontal extensions BLE1 and BLE3 of the first conductor BL can extend to be disposed on one side of the second spacer SP2. Therefore, the outer horizontal extensions BLE1 and BLE3 of the first conductor BL can contact the second liner L2 of the second spacer SP2.

[0065] From another perspective, a memory cell MC can have a 1T-1C structure, where 1T can refer to a switching element TR and 1C can refer to a data storage element CAP. When the memory cell MC is a DRAM cell with a 1T-1C structure, 1T can refer to a cell transistor and 1C can refer to a capacitor. Therefore, the gate of the cell transistor can be a word line, the first source / drain region of the cell transistor can be coupled to a bit line, and the second source / drain region of the cell transistor can be coupled to a capacitor. In this paper, a bit line can correspond to... Figure 1A and Figure 1B The first conductor BL shown can correspond to the word line. Figure 1A and Figure 1B The second conductor WL shown, and the capacitor, can correspond to Figure 1A and Figure 1B The data storage element CAP is shown in the diagram. Furthermore, the first source / drain region can correspond to... Figure 1A and Figure 1B The first doped region SR is shown, and the second source / drain region can correspond to... Figure 1A and Figure 1B The second doped region DR is shown in the figure.

[0066] Figure 2A This is a schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 2B It is to further demonstrate Figure 2A A partial perspective view of the first spacer SP1 shown. Figure 2C It is to further demonstrate Figure 2A A partial perspective view of the second spacer SP2 shown.

[0067] Figure 2A The diagram shows a horizontal array HMCA in which multiple memory cells (MCs) are arranged horizontally. Figure 2A Each storage unit shown can be the reference above. Figure 1A and Figure 1B The described storage unit MC.

[0068] refer to Figure 1A , Figure 1B and Figures 2A to 2CA horizontal array HMCA may include horizontally arranged memory cells MC. The memory cells MC of the horizontal array HMCA may be horizontally spaced along a third direction D3. Each memory cell MC of the horizontal array HMCA may be coupled to a different first conductor BL. The horizontal array HMCA may include multiple horizontally arranged first conductors BL. The memory cells MC of the horizontal array HMCA may share a second conductor WL. Each memory cell MC may include a first conductor BL, a nanosheet HL, and a data storage element CAP. The nanosheet HL may include a first doped region SR, a channel CH, and a second doped region DR. A first contact node BLC and an ohmic contact layer BLO may be formed between the first doped region SR and the first conductor BL of the nanosheet HL. A second contact node SNC may be formed between the second doped region DR of the nanosheet HL and the data storage element CAP. The nanosheet HL may be surrounded by a nanosheet dielectric layer GD. The second conductor WL may extend along a third direction D3, while surrounding the channel CH of the nanosheet HL disposed at the same horizontal level on the nanosheet dielectric layer GD.

[0069] Horizontal array HMCA may also include the above references Figure 1B The first spacer SP1 and the second spacer SP2.

[0070] Return to reference Figure 1B and Figure 2B The first spacer SP1 may extend along a third direction D3, while surrounding a portion of the nanosheet HL disposed at the same horizontal level, namely, the second doped region DR. The first spacer SP1 may include a protruding portion surrounding the second doped region DR of the nanosheet HL. The protruding portions of the first spacer SP1 may be joined together and extend along a third direction D3. The first spacer SP1 may have an integral structure extending along a first direction D1. The protruding portions of the first spacer SP1 may each have a cup shape, and the cross-section of the protruding portions may each have an open shape (e.g., a "C" shape, a "U" shape, or a shape with right angle brackets "[").

[0071] Return to reference Figure 1B and Figure 2C The second spacer SP2 can extend along the third direction D3, while surrounding a portion of the nanosheet HL, i.e., the first doped region SR. A portion of the second spacer SP2 can partially overlap with the channel CH.

[0072] Figure 3 This is a schematic perspective view illustrating a semiconductor device 100V according to an embodiment of the present disclosure. Figure 3 The semiconductor device 100V shown may include therein. Figure 2A The structure shown is a horizontal array that is stacked vertically along the first direction D1. (See above reference.) Figures 1A to 2C A detailed description of the stacked components is provided.

[0073] refer to Figure 3 Semiconductor device 100V may include a vertically stacked horizontal array HMCA. Semiconductor device 100V may include a plurality of horizontally arranged first conductors BL and a plurality of vertically arranged second conductors WL. Vertically arranged memory cells MC stacked along a first direction D1 may share a first conductor BL. Horizontally arranged memory cells MC arranged along a third direction D3 may be coupled to different first conductors BL.

[0074] Horizontally arranged memory cells MC along the third direction D3 can share a second conductor WL. Vertically arranged memory cells MC stacked along the first direction D1 can be coupled to different second conductors WL.

[0075] Each support element BLS can be disposed between adjacent first conductors BL. The first conductors BL can be supported by the support elements BLS. The support elements BLS can extend perpendicularly along a first direction. Each support element BLS can comprise a dielectric material.

[0076] Figure 4A This is a schematic plan view illustrating a semiconductor device 200 according to an embodiment of the present disclosure. Figure 4B It is along Figure 4A The diagram shows a schematic cross-sectional view of the semiconductor device 200 taken by line AA′. Figure 4C It is along Figure 4A The diagram shows a schematic cross-sectional view of the semiconductor device 200 taken by line A1-A1′. Figure 4D It is along Figure 4A The diagram shows a schematic cross-sectional view of semiconductor device 200 taken by line BB′. (See above for reference.) Figures 1A to 3 A detailed description of the stacked components is provided.

[0077] refer to Figures 4A to 4D The semiconductor device 200 may include a memory cell array (MCA). The memory cell array (MCA) may include a three-dimensional array of memory cells (MC). The memory cell array (MCA) may be formed on the underlying structure (LS).

[0078] The underlying semiconductor substrate (LS) can be a material suitable for semiconductor processing. The underlying semiconductor substrate (LS) can include a semiconductor substrate, a conductive material, a dielectric material, a semiconducting material, or a combination thereof. The underlying semiconductor substrate (LS) can include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, epitaxial silicon, combinations thereof, or multilayers thereof. The underlying semiconductor substrate (LS) can also include another semiconductor material, such as germanium. The underlying semiconductor substrate (LS) can also include a group III-V semiconductor substrate, such as a compound semiconductor substrate, such as GaAs.

[0079] Each memory cell MC may include a first conductive line BL, a switching element TR, and a data storage element CAP. The switching element TR may include a second conductive line WL, a nanosheet dielectric layer GD, and a nanosheet HL. The nanosheet HL may include a first doped region SR, a channel CH, and a second doped region DR.

[0080] A memory cell array (MCA) may include a column array of memory cells (MCs) and a row array of memory cells (MCs). The column array may include multiple memory cells (MCs) stacked vertically along a first direction D1. The memory cells (MCs) in the column array may share a first conductor BL. The row array may include multiple memory cells (MCs) arranged horizontally along a third direction D3. The memory cells (MCs) in the row array may share a second conductor WL. The first direction D1 may be vertical, while the third direction D3 may be horizontal.

[0081] A memory cell array (MCA) may include a first sub-cell array (MCA1) and a second sub-cell array (MCA2). Each of the first and second sub-cell arrays (MCA1 and MCA2) may comprise a three-dimensional array of memory cells (MC). The first and second sub-cell arrays (MCA1 and MCA2) may share a first conductor (BL). The first conductor (BL) may include a first vertical conductor (BLA) and a second vertical conductor (BLB). The bottom portions of the first vertical conductor (BLA) and the second vertical conductor (BLB) may be merged together. The first conductor (BL) may have a U-shape formed by merging the first vertical conductor (BLA) and the second vertical conductor (BLB). The memory cells (MC) of the first sub-cell array (MCA1) may share the first vertical conductor (BLA), and the memory cells (MC) of the second sub-cell array (MCA2) may share the second vertical conductor (BLB). Thus, adjacent first and second sub-cell arrays (MCA1 and MCA2) may have a mirror structure sharing the first conductor (BL). From a top view perspective, the first vertical conductor (BLA) and the second vertical conductor (BLB) may each have a rectangular shape.

[0082] Each memory cell MC in the first sub-cell array MCA1 may include a first vertical conductor BLA, a switching element TR, and a data storage element CAP. The switching element TR may include a second conductor WL and a nanosheet HL. Each memory cell MC in the second sub-cell array MCA2 may include a second vertical conductor BLB, a switching element TR, and a data storage element CAP. The switching element TR may include a second conductor WL, a nanosheet dielectric layer GD, and a nanosheet HL. The switching element TR of the memory cell MC may be a nanosheet transistor.

[0083] The first conductor BL can extend perpendicularly along the first direction D1. The nanosheet HL can extend along the second direction D2. The second conductor WL can extend horizontally along the third direction D3.

[0084] The first inter-cell dielectric layer IL1 can be disposed between data storage elements CAP arranged adjacent to each other along the third direction D3. The second inter-cell dielectric layer IL2 can be disposed between second conductors WL stacked perpendicularly along the first direction D1. The third inter-cell dielectric layer IL3 can be disposed between the first electrodes SN of the data storage elements CAP stacked perpendicularly along the first direction D1. The first to third inter-cell dielectric layers IL1, IL2 and IL3 can each comprise silicon oxide, silicon carbon oxide (SiCO), silicon nitride or a combination thereof. The first inter-cell dielectric layer IL1 can be referred to as a "device isolation layer".

[0085] Each memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may be disposed between the first conductor BL and the nanosheet HL. The first contact node BLC may include a metal-based material or a semiconducting material. For example, the first contact node BLC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the first contact node BLC may include doped polysilicon, and the first doped region SR may include impurities diffused from the first contact node BLC. The second contact node SNC may be disposed between the nanosheet HL and the first electrode SN. The second contact node SNC may include a metal-based material or a semiconducting material. For example, the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. Furthermore, the second contact node SNC may include doped polysilicon, and the second doped region DR may include impurities diffused from the second contact node SNC. The height of the first contact node BLC along the first direction D1 may be less than the height of the second contact node SNC along the first direction D1. The height of the first contact node BLC along the first direction D1 may be greater than the height of the channel CH along the first direction D1. The first contact node BLC and the second contact node SNC may each comprise polysilicon doped with N-type impurities, such as phosphorus-doped polysilicon or arsenic-doped polysilicon.

[0086] The memory cell MC may also include an ohmic contact layer BLO between the first contact node BLC and the first conductor BL. The ohmic contact layer BLO may include a metal silicide such as titanium silicide or molybdenum silicide.

[0087] The memory cell MC may further include a first spacer SP1 and a second spacer SP2. The first spacer SP1 may be disposed between the second conductor WL and the second doped region DR. The second spacer SP2 may be disposed between the first conductor BL and the second conductor WL. The first spacer SP1 and the second spacer SP2 may each comprise a dielectric material. The first spacer SP1 and the second spacer SP2 may each comprise silicon oxide, silicon nitride, or a combination thereof. The second spacer SP2 may include materials as described above. Figure 1B The first liner L1 and the second liner L2 are described above. (Refer to the above.) Figure 2B The first spacer SP1 can extend along a third direction D3, while surrounding a portion of the nanosheet HL disposed at the same horizontal level. (Refer to the above) Figure 2C The second spacer SP2 can extend along the third direction D3, while surrounding a portion of the nanosheet HL disposed at the same horizontal level.

[0088] The memory cell array MCA may include a plurality of second conductors WL stacked perpendicularly along a first direction D1. The memory cell array MCA may include a plurality of nanosheets HL stacked perpendicularly along the first direction D1. The memory cell array MCA may include a plurality of data storage elements CAP stacked perpendicularly along the first direction D1. The memory cell array MCA may include a plurality of first conductors BL spaced apart along a third direction D3. The memory cell array MCA may include dummy second conductors WLU and WLL positioned at a level higher than the uppermost second conductor WL and a dummy second conductor WLL positioned at a level lower than the lowermost second conductor WL, respectively. The dummy second conductors WLU and WLL may each have a horizontally extending linear shape.

[0089] The memory cell array MCA may include a stack of multiple hard mask layers HM1 and HM2 positioned at a level higher than the topmost second conductor WL.

[0090] A memory cell array (MCA) may include multiple bottom protective layers (BTs). The bottom protective layers (BTs) prevent the data storage elements (CAPs) and the underlying structure (LS) from making electrical contact with each other. Each bottom protective layer (BT) may contain a dielectric material.

[0091] An array isolation layer BLF can be disposed between a first vertical conductor BLA and a second vertical conductor BLB of a first conductor BL. The array isolation layer BLF may include a dielectric material. The array isolation layer BLF may include an air gap FG and a bridging prevention portion BP. The air gap FG can reduce the parasitic capacitance between adjacent first vertical conductors BLA and BLB. The bridging prevention portion BP of the array isolation layer BLF can prevent bridging between the bottom portions of the first vertical conductor BLA and the bottom portions of the second vertical conductor BLB and the lower structure LS. Although the bottom portions of the first vertical conductor BLA and the second vertical conductor BLB are close to the lower structure LS, the bridging prevention portion BP of the array isolation layer BLF can prevent bridging between the bottom portions of the first vertical conductor BLA and the bottom portions of the second vertical conductor BLB and the lower structure LS. Because the height of the bridging prevention portion BP is low, the bottom portions of the first vertical conductor BLA and the bottom portions of the second vertical conductor BLB can be formed close to the lower structure LS.

[0092] In this embodiment, because the bottom portions of the first vertical conductor BLA and the second vertical conductor BLB are formed close to the lower structure LS, dummy memory cells can be avoided. Since dummy memory cells are absent, the memory cell density can be increased.

[0093] Return to reference Figure 4A and Figure 4D The first vertical conductor BLA and the second vertical conductor BLB can be supported by a support member BLS. The support member BLS can extend perpendicularly along a first direction D1. Each support member BLS can include a dielectric material. The first vertical conductor BLA and the second vertical conductor BLB can be formed to be self-aligned using the support member BLS. The first vertical conductor BLA adjacent to each other along a third direction D3 can be isolated from each other by the support member BLS. The second vertical conductor BLA adjacent to each other along a third direction D3 can be isolated from each other by the support member BLS. The first vertical conductor BLA and the second vertical conductor BLB adjacent to each other along a second direction D2 can be isolated from each other by an array of isolation layers BLF.

[0094] Nanosheets HL of a switching element TR arranged horizontally along the third direction D3 can share a second conductor WL. Nanosheets HL of a switching element TR arranged horizontally along the third direction D3 can be coupled to different first conductors BL. Switching elements TR stacked along the first direction D1 can share a first conductor BL. Switching elements TR arranged horizontally along the third direction D3 can share a second conductor WL.

[0095] The second electrode PN of the data storage element CAP can be coupled to the common board PL.

[0096] Figures 5A to 28B Various views of a semiconductor device formed using a method for manufacturing a semiconductor device according to embodiments of the present disclosure are shown.

[0097] Figure 5A This is a plan view showing the structure at the second module level used to describe the method of forming a module stack SB. Figure 5B It is along Figure 5A The cross-sectional view of the structure intercepted by line AA′ is shown. Figure 5C It is along Figure 5A The cross-sectional view of the structure cut by line BB′ is shown.

[0098] refer to Figures 5A to 5C A mode stack SB can be formed on substrate 11. Substrate 11 can be a material suitable for semiconductor processing. Substrate 11 can include a semiconductor substrate, a conductive material, a dielectric material, a semiconducting material, or a combination thereof. Substrate 11 can include silicon, monocrystalline silicon, polycrystalline silicon, amorphous silicon, silicon-germanium, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, epitaxial silicon, a combination thereof, or multiple layers thereof. Substrate 11 can also include another semiconductor material, such as germanium. Substrate 11 can also include a III-V group semiconductor substrate, for example, a compound semiconductor substrate such as GaAs. The mode stack SB can include an alternating stack of a first mode layer 12 and a second mode layer 13.

[0099] In order to form a module stack SB, the first module layer 12 can be stacked alternately with the second module layer 13, and the first module layer 12 and the second module layer 13 can be epitaxially grown multiple times.

[0100] The first template layer 12 and the second template layer 13 can be made of different semiconducting materials. The first template layer 12 can all comprise silicon-germanium or monocrystalline silicon-germanium. The second template layer 13 can all comprise monocrystalline silicon. The first template layer 12 and the second template layer 13 can be formed by an epitaxial growth process. The bottommost first template layer 12 can be used as a seed layer during the epitaxial growth process. Each first template layer 12 can be thinner than each second template layer 13. The first template layer 12 can include a first epitaxial growth layer, and the second template layer 13 can include a second epitaxial growth layer.

[0101] In this embodiment, multiple single-crystal silicon-germanium layers can be stacked alternately with multiple single-crystal silicon layers in the mode stack SB. For example, the first mode layer 12 can be a single-crystal silicon-germanium layer, and the second mode layer 13 can be a single-crystal silicon layer. The stack of single-crystal silicon-germanium layers and single-crystal silicon layers (SiGe / Si stack) can be stacked multiple times. The first mode layer 12 can be referred to as a "sacrificial layer," and the second mode layer 13 can be referred to as a "nanosheet target layer" or a "recessed target layer."

[0102] Modular stacked (SB) can be referred to as "vertical stacking". Modular stacked SB can be formed by alternately stacking multiple sacrificial layers and multiple nanosheet target layers. The sacrificial layer can be a single-crystal silicon-germanium layer, and the nanosheet target layer can be a single-crystal silicon layer.

[0103] The thickness ratio of the first module layer 12 and the thickness ratio of the second module layer 13 in the module stack SB can be modified in various ways. For example, the thickness of the first module layer 12 can be 5 to 20 nm, and the thickness of the second module layer 13 can be 50 to 80 nm. The number of first module layers 12 and the number of second module layers 13 in the module stack SB can be modified in various ways. In some embodiments, a triple stack including the first module layer 12, the second module layer 13, and the first module layer 12 can be defined in the bottommost and / or topmost portion of the module stack SB. In some embodiments, a triple stack including the first module layer 12, the second module layer 13, and the first module layer 12 can be formed in the topmost portion of the module stack SB. The second module layer 13 of the triple stack can have a smaller thickness than the other second module layers 13 in the module stack SB.

[0104] A first hard mask layer 14 may be formed on the die stack SB. The first hard mask layer 14 may include a dielectric material, such as an oxide-based material, a nitride-based material, a carbon-based material, or a combination thereof. For example, the first hard mask layer 14 may include SiO2, Si3N4, amorphous carbon, or a combination thereof.

[0105] Return to reference Figure 5A and Figure 5C A first hard mask layer 14 can be used as a barrier layer to etch portions of the die stack SB, and multiple sacrificial isolation openings 15 can be formed. The sacrificial isolation openings 15 can be initial openings for cell isolation. From a top view perspective, the cross-section of each sacrificial isolation opening 15 can be rectangular. In some embodiments, the cross-section of each sacrificial isolation opening 15 can be circular or elliptical. In some embodiments, the sacrificial isolation opening 15 can be referred to as a "sacrificial isolation trench". The sacrificial isolation openings 15 can extend vertically along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation openings 15 can be arranged at predetermined intervals along a third direction D3. The bottom surface of each sacrificial isolation opening 15 can extend inside the substrate 11.

[0106] Figure 6A This is a plan view showing the structure at the second module level used to describe the method of forming the sacrificial linear openings 18 and 19. Figure 6B It is along Figure 6A The cross-sectional view of the structure intercepted by line AA′ is shown. Figure 6C It is along Figure 6A The cross-sectional view of the structure cut by line BB′ is shown.

[0107] refer to Figures 6A to 6C The sacrificial isolation layer 16 can be formed to fill the sacrificial isolation opening 15. The sacrificial isolation layer 16 may comprise the same material. The sacrificial isolation layers 16 may each be formed from a dielectric material. The sacrificial isolation layer 16 may have etching selectivity relative to the mold stack SB. For example, the sacrificial isolation layers 16 may all comprise silicon oxide, silicon nitride, silicon oxide carbon, silicon nitride carbon, or combinations thereof. Forming the sacrificial isolation layer 16 may include forming a sacrificial isolation material on the mold stack SB to fill the sacrificial isolation opening 15 and planarizing the sacrificial isolation material to expose the surface of the first hard mask layer 14.

[0108] The sacrificial isolation layer 16 may extend vertically along a first direction D1 and longitudinally along a second direction D2. The sacrificial isolation layers 16 may be arranged at predetermined intervals along a third direction D3. Each sacrificial isolation layer 16 may include a stack of a first sacrificial inner liner layer and a first sacrificial gap fill layer. The first sacrificial inner liner layer may be silicon nitride, and the first sacrificial gap fill layer may be silicon oxide. The sacrificial isolation layers 16 may penetrate the mold stack SB along the first direction D1.

[0109] Subsequently, a second hard mask layer 17 can be formed on the die stack SB and the sacrificial isolation layer 16. The second hard mask layer 17 may include silicon nitride. The second hard mask layer 17 can be formed by etching the second hard mask material using a mask layer such as photoresist. The second hard mask layer 17 may have a plurality of linear openings defined therein.

[0110] A second hard mask layer 17 can be used as an etching barrier layer to etch portions of the mold stack SB. Therefore, a plurality of sacrificial linear openings 18 and 19 can be formed between the sacrificial isolation layers 16. The sacrificial linear openings may include a first sacrificial linear opening 18 and a second sacrificial linear opening 19. From a top view perspective, the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be linear openings extending along a third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may extend perpendicularly along a first direction D1. The sacrificial isolation layer 16 may be disposed between the first sacrificial linear opening 18 and the second sacrificial linear opening 19 along a second direction D2. From a top view perspective, the cross-sections of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may each have a rectangular shape. In some embodiments, the cross-sections of the first sacrificial linear opening 18 and the second sacrificial linear opening 19 may each have a circular or elliptical shape. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may each have a width along the second direction D2, which is smaller than the width along the third direction D3. The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may be referred to as "sacrificial linear trenches". The first sacrificial linear opening 18 and the second sacrificial linear opening 19 may have different horizontal lengths along the third direction D3. The sacrificial isolation layer 16 may not be in contact with the first sacrificial linear opening 18 and the second sacrificial linear opening 19.

[0111] Figure 7A This is a plan view showing the structure at the second module level used to describe the method of forming linear sacrificial layers 18L and 19, and Figure 7B It is along Figure 7A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0112] refer to Figure 7A and Figure 7BLinear sacrificial layers 18L and 19L can be formed to fill the first sacrificial linear opening 18 and the second sacrificial linear opening 19. The linear sacrificial layers may include the first linear sacrificial layer 18L and the second linear sacrificial layer 19L. From a top view perspective, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may have a linear shape extending along a third direction D3. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may extend perpendicularly along a first direction D1. The sacrificial isolation layer 16 may be disposed between the first linear sacrificial layer 18L and the second linear sacrificial layer 19L along a second direction D2. From a top view perspective, the cross-sections of the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may each have a rectangular shape. In some embodiments, the cross-sections of the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may each have a circular or elliptical shape. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may comprise the same material. The first linear sacrificial layer 18L and the second linear sacrificial layer 19L may each be formed from a dielectric material. For example, the first linear sacrificial layer 18L and the second linear sacrificial layer 19L may each comprise silicon oxide, silicon nitride, silicon oxide carbon, silicon nitride carbon, or combinations thereof. The sacrificial isolation layer 16 may not be in contact with the first linear sacrificial layer 18L and the second linear sacrificial layer 19L.

[0113] Figure 8A This is a plan view showing the structure at the mold level used to describe the method of forming the support hole 16R, and Figure 8B It is along Figure 8A The cross-sectional view of the structure cut by line BB′ is shown.

[0114] refer to Figure 8A and Figure 8B Between the first linear sacrificial layer 18L and the second linear sacrificial layer 19L, the first linear sacrificial layer 18L can be selectively removed. Therefore, a first linear opening 20 can be formed. From a top view perspective, the first linear opening 20 can be horizontally spaced from the second linear sacrificial layer 19L along the second direction D2.

[0115] One edge of each sacrificial isolation layer 16 can be exposed through the first linear opening 20.

[0116] Subsequently, the first mold layer 12 and the second mold layer 13 of the mold stack SB can be partially recessed along the second direction D2 through the first linear opening 20.

[0117] Subsequently, a portion of the sacrificial isolation layer 16 can be recessed through the first linear opening 20 along the second direction D2. Thus, a support hole 16R can be formed.

[0118] Figure 9AThis is a plan view showing the structure at the second mold level used to describe the method of forming the support member 16S, and Figure 9B It is along Figure 9A The cross-sectional view of the structure cut by line BB′ is shown.

[0119] refer to Figure 9A and Figure 9B The support member 16S can be formed to fill the support member hole 16R. The support member 16S can all comprise a dielectric material. In an embodiment, the support member 16S can all comprise silicon nitride. The support member 16S can have etching selectivity relative to the sacrificial isolation layer 16.

[0120] Support member 16S can correspond to Figures 4A to 4D The support component BLS is shown.

[0121] Figure 10A This is a plan view showing the structure at the second mold layer level used to describe the method of recessing the first mold layer 12 and the second mold layer 13. Figure 10B It is along Figure 10A The cross-sectional view of the structure intercepted by line AA′ is shown. Figure 10C It is along Figure 10A The cross-sectional view of the structure intercepted by line A-A1′ is shown.

[0122] refer to Figures 10A to 10C The first mold layer 12 can be selectively recessed through the first linear opening 20.

[0123] The difference in etching selectivity between the first template layer 12 and the second template layer 13 can be used to selectively recess the first template layer 12. The first template layer 12 can be removed using either a wet etching process or a dry etching process. For example, when the first template layer 12 comprises a silicon-germanium layer and the second template layer 13 comprises a monocrystalline silicon layer, the silicon-germanium layer can be etched using an etchant or etching gas that is selective relative to the monocrystalline silicon layer. The first template layers, each with its original thickness, can be retained, as indicated by reference numeral "12A".

[0124] Subsequently, a portion (first portion) of each second mold layer 13 can be recessed to form a narrow wafer 13N. The second mold layer 13 can be recessed using either a wet etching process or a dry etching process. The original body portion 13A and the narrow wafer 13N can be formed by recessing each portion of the second mold layer 13. The original body portion 13A can maintain its original thickness T1, while the narrow wafer 13N can have a thickness T2 less than the original thickness T1. The horizontal length of the original body portion 13A along the second direction D2 can be equal to or different from the horizontal length of the narrow wafer 13N along the second direction D2. The combination of the original body portion 13A and the narrow wafer 13N can be referred to as a "primary active layer." The narrow wafer 13N can be referred to as a "flat wafer" or a "protruding narrow wafer."

[0125] The recessed process used to form the narrow wafer 13N can be referred to as a "thinning process" or "trimming process" for the second module layer 13. To form the narrow wafer 13N, the upper surface, lower surface, and side surfaces of the second module layer 13 can be recessed. The narrow wafer 13N can be referred to as a "thin active layer." The narrow wafer 13N may include a monocrystalline silicon layer. The recessed process used to form the narrow wafer 13N can use, for example, Hot SC-1 (HSC1). HSC1 may include a solution in which ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) are mixed in a ratio of 1:4:20. Using HSC1, the second module layer 13 can be selectively etched.

[0126] Narrow sheets 13N can be formed using the partial recessing process for the second template layer 13 as described above. Each nanosheet recess 21 can be formed between vertically arranged narrow sheets 13N. The upper and lower surfaces of each narrow sheet 13N can each include a flat surface. The boundary between the original body portion 13A and the narrow sheet 13N can be vertical or curved. Each first template layer 12A can be disposed between vertically stacked original body portions 13A.

[0127] Each support 16S can be positioned between narrow strips 13N that are adjacent to each other along the third direction D3.

[0128] Figure 11A This is a plan view illustrating a lamella-level structure used to describe the method of forming the sacrificial isolation level opening 22. Figure 11B It is along Figure 11A The cross-sectional view of the structure intercepted by line B1-B1′ is shown.

[0129] refer to Figure 11A and Figure 11B The sacrificial isolation layer 16 can be selectively peeled off through the recesses 21 between the nanosheets. Therefore, each sacrificial isolation layer level opening 22 can be formed between the original body portions 13A along the third direction D3. Each support 16S can be disposed between adjacent narrow sheets 13N along the third direction D3. The support 16S can be left unremoved when removing the sacrificial isolation layer 16.

[0130] The side surfaces of the first module layer 12A, the original main body portion 13A, and the narrow strip 13N can be exposed along the third direction D3 through the sacrificial isolation layer opening 22.

[0131] When the sacrificial isolation layer 16 is removed, the support 16S can prevent the narrow strip 13N from collapsing.

[0132] Figure 12AThis is a plan view showing a veneer-level structure used to describe the method of forming the first inter-cell dielectric layer 23. Figure 12B It is along Figure 12A The cross-sectional view of the structure intercepted by line AA′ is shown. Figure 12C It is along Figure 12A The cross-sectional view of the structure intercepted by line A1-A1′ is shown. Figure 12D It is along Figure 12A The cross-sectional view of the structure intercepted by line B1-B1′ is shown.

[0133] refer to Figures 12A to 12D A first inter-cell dielectric layer 23 can be formed in the sacrificial isolation level opening 22. The first inter-cell dielectric layer 23 may all comprise a dielectric material. The first inter-cell dielectric layer 23 may all comprise silicon oxide, silicon nitride, silicon carbon oxide, or a combination thereof. Forming the first inter-cell dielectric layer 23 may include forming a dielectric material that fills the sacrificial isolation level opening 22 and performing an etch-back process on the dielectric material.

[0134] The first inter-cell dielectric layer 23 may fill a portion of the sacrificial isolation layer opening 22. The side surfaces of the first module layer 12A and the original body portion 13A may be covered by the first inter-cell dielectric layer 23 along the third direction D3. The first inter-cell dielectric layer 23 may expose the side surfaces of the narrow sheet 13N. Other portions of the sacrificial isolation layer opening 22 (i.e., the non-gap fill portion 23A) may expose the side surfaces of the narrow sheet 13N. The non-gap fill portion 23A may be defined between the narrow sheets 13N along the third direction D3.

[0135] After forming the first inter-unit dielectric layer 23, a fully open nanosheet recess 24 that opens all the narrow strips 13N can be formed. The fully open nanosheet recess 24 can refer to a combination of the inter-nanosheet recess 21 and the non-gap-filling portion 23A of the first inter-unit dielectric layer 23. The fully open nanosheet recess 24 exposes the plurality of narrow strips 13N along the third direction D3.

[0136] The fully open recessed nanosheet 24 exposes all the first portions of the narrow sheet 13N, and one edge (i.e., the second portion) of each narrow sheet 13N can be supported by the support member 16S. From a top view perspective, the fully open recessed nanosheet 24 can be defined between the inter-cell dielectric layer 23 and the support member 16S.

[0137] Figure 13A This is a plan view showing a slab-level structure used to describe the method of forming the first spacer layer 26A. Figure 13B It is along Figure 13A The cross-sectional view of the structure intercepted by line AA′ is shown. Figure 13C It is along Figure 13AThe cross-sectional view of the structure intercepted by line A1-A1′ is shown.

[0138] refer to Figures 13A to 13C A nanosheet dielectric layer 25 can be formed on the exposed portion of the narrow strip 13N. The nanosheet dielectric layer 25 can be referred to as the "gate dielectric layer".

[0139] The nanosheet dielectric layer 25 can be formed by oxidizing the surface of the narrow wafer 13N. In some embodiments, the nanosheet dielectric layer 25 can be formed by a silicon oxide deposition and oxidation process. The nanosheet dielectric layer 25 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The nanosheet dielectric layer 25 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof. The nanosheet dielectric layer 25 can be formed on all surfaces of the narrow wafer 13N.

[0140] A first spacer layer 26A may be formed on the nanosheet dielectric layer 25. The first spacer layer 26A may include silicon nitride. The first spacer layer 26A may surround and cover the narrow strip 13N on the nanosheet dielectric layer 25. The first spacer layer 26A may be thicker than the nanosheet dielectric layer 25. From a top view perspective, the first spacer layer 26A may fill the space between the first inter-unit dielectric layer 23 and the support member 16S, i.e., the fully open recessed portion 24 of the nanosheet.

[0141] A second inter-unit dielectric layer 27A can be formed on the first spacer layer 26A. The second inter-unit dielectric layer 27A may all comprise silicon oxide. The first spacer layer 26A and the second inter-unit dielectric layer 27A may partially fill the first linear opening 20. The stacking of the first spacer layer 26A and the second inter-unit dielectric layer 27A may fill the fully open recess 24 of the nanosheet.

[0142] Alternatively, a nanosheet dielectric layer 25 and a first spacer layer 26A can be formed on the surface of the substrate 11.

[0143] As described above, the first spacer layer 26A can be disposed between the narrow strips 13N along the third direction D3.

[0144] Figure 14A This is a plan view showing a structure at the narrow plate level used to describe the method of forming the first spacer 26. Figure 14B It is along Figure 14A The cross-sectional view of the structure intercepted by line AA′ is shown. Figure 14C It is along Figure 14A The cross-sectional view of the structure intercepted by line A1-A1′ is shown.

[0145] refer to Figures 14A to 14C The second inter-unit dielectric layer 27A can be cut through the first linear opening 20. Subsequently, the first spacer layer 26A can be selectively recessed. The remaining first spacer layer can become the first spacer 26, while the second inter-unit dielectric layer can be retained, as indicated by reference numeral "27". From the top view, the first spacer 26 can be disposed between the first inter-unit dielectric layer 23 and the support member 16S.

[0146] When the first spacer 26 is formed, a linear surrounding recess 28 surrounding the narrow strip 13N can be formed on the nanosheet dielectric layer 25. Each second inter-unit dielectric layer 27 can be disposed between the vertically positioned linear surrounding recesses 28. Dummy recesses 28U and 28L can be formed at levels higher and lower than the linear surrounding recesses 28. From a top view perspective, the linear surrounding recesses 28 can be defined between the first spacer 26 and the support member 16S.

[0147] The first spacer 26 can correspond to Figures 4A to 4C The first spacer SP1 is shown.

[0148] Figure 15A This is a plan view showing a narrow-slice-level structure used to describe the method of forming the horizontal conductor 29. Figure 15B It is along Figure 15A The cross-sectional view of the structure intercepted by line AA′ is shown. Figure 15C It is along Figure 15A The cross-sectional view of the structure intercepted by line A1-A1′ is shown.

[0149] refer to Figures 15A to 15C The horizontal guide wire 29 can be formed to fill the linearly surrounding recess 28. The horizontal guide wire 29 can extend horizontally along the third direction D3. The horizontal guide wire 29 can correspond to... Figures 4A to 4C The second conductor WL is shown in the diagram.

[0150] Forming the horizontal conductors 29 may include depositing a conductive material that fills the linearly surrounding recess 28 on the nanosheet dielectric layer 25 and performing a horizontal etch-back process on the conductive material. Each horizontal conductor 29 may simultaneously surround a narrow strip 13N at the same level. The horizontal conductors 29 may all comprise a metal-based material, a semiconducting material, or a combination thereof. The horizontal conductors 29 may all comprise molybdenum, molybdenum nitride, ruthenium, titanium nitride, tungsten, polycrystalline silicon, or a combination thereof. For example, the horizontal conductors 29 may all comprise a titanium nitride and tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The horizontal conductors 29 may all comprise an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of approximately 4.5 eV or less, while the P-type work function material may have a high work function of approximately 4.5 eV or greater. Each second inter-unit dielectric layer 27 may be disposed between the plurality of horizontal conductors 29 along the first direction D1. The horizontal conductors 29 may surround the narrow strip 13N at the same level along the third direction D3. The horizontal conductor 29 can be referred to as a “gate all-around (GAA) electrode”. The narrow strip 13N can be referred to as a “nanopie channel”, “nanowire”, or “nanowire channel”.

[0151] A lower-level dummy horizontal electrode 29L can be formed on the surface of the substrate 11. An upper-level dummy horizontal electrode 29U can be formed above the uppermost horizontal conductor 29. The dummy horizontal electrodes 29L and 29U can each have a non-enclosed shape.

[0152] The horizontal guide 29 may include a surrounding portion that surrounds the narrow strip 13N and a gap-filling portion disposed between the narrow strips 13N. From a top view perspective, the gap-filling portion of the horizontal guide 29 may be disposed between the first spacer 26 and the support 16S.

[0153] Figure 16A This is a plan view showing a structure at the narrow plate level used to describe the method of forming the second spacer 30. Figure 16B It is along Figure 16A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0154] refer to Figure 16A and Figure 16B Each second spacer 30 can be formed on one side of each horizontal conductor 29. The second spacer 30 may comprise silicon oxide, silicon nitride, silicon oxide carbon, intercalated air gaps, or a combination thereof. A deposition and etch-back process of the spacer material can be performed to form the second spacer 30. The second spacer 30 may comprise a stack of silicon oxide liners and silicon nitride liners. The second spacer 30 may correspond to... Figures 4A to 4C The second spacer SP2 shown.

[0155] After the second spacer 30 is formed, a portion of the nanosheet dielectric layer 25 can be cut to expose one side of each narrow strip 13N.

[0156] Each second spacer 30 can be disposed on one side of each horizontal conductor 29 and surround the narrow strip 13N at the same horizontal level along the third direction D3.

[0157] Figure 17A This is a plan view showing a structure at the narrow-slice level used to describe the method of forming the narrow-slice cut 13R. Figure 17B It is along Figure 17A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0158] refer to Figure 17A and Figure 17B One side surface E1 of the narrow strip 13N can be cut. Therefore, a narrow strip cutout 13R that is horizontally recessed from the edge of the first spacer 26 can be formed. When forming the narrow strip cutout 13R, the surface of the substrate 11 can be recessed, and then a substrate recess 13R′ can be formed.

[0159] Figure 18A This is a plan view showing a slab-level structure used to describe the method of forming the sacrificial protective layer 32. Figure 18B It is along Figure 18A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0160] refer to Figure 18A and Figure 18B The sacrificial pouch layer 31 can be formed to fill the narrow notch 13R. The sacrificial pouch layer 31 can be formed by silicon oxide deposition and etching processes. During the formation of the sacrificial pouch layer 31, a portion of the second spacer 30 can be recessed.

[0161] Subsequently, the sacrificial protective layer 32 can be grown on the surface of the substrate recess 13R′. The sacrificial protective layer 32 can be selectively grown from the surface of the substrate recess 13R′. The sacrificial protective layer 32 may include a silicon-germanium layer. Due to the sacrificial pouch layer 31, the sacrificial protective layer 32 may not need to be grown on the surface of the narrow strip 13N.

[0162] Figure 19A This is a plan view of a narrow-plate-level structure used to describe the method of forming a vertical opening VL. Figure 19B It is along Figure 19A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0163] refer to Figure 19A and Figure 19BThe sacrificial bag layer 31 can be selectively removed. Therefore, the vertical opening VL can be formed to expose the edge E2 of the narrow strip 13N. From a top view perspective, the vertical opening VL can be formed to be self-aligned by the supports 16S, thereby defining the vertical opening VL between the supports 16S. The sacrificial protective layer 32 can be retained beneath the vertical opening VL.

[0164] Figure 20A This is a plan view showing a slab-level structure used to describe the method of forming the first contact node 33. Figure 20B It is along Figure 20A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0165] refer to Figure 20A and Figure 20B The first contact node 33 can be selectively formed from the edge E2 of the narrow wafer 13N. The first contact node 33 can be formed by selective epitaxial growth (SEG). The first contact node 33 can be an epitaxial layer of silicon. The first contact node 33 can be a doped silicon epitaxial layer. The first contact node 33 can be a silicon epitaxial layer doped with N-type impurities. The first contact node 33 can correspond to... Figures 4A to 4C The first contact node BLC is shown in the diagram.

[0166] A first doped region 34 can be formed within one side of the narrow strip 13N. A thermal processing step can be performed to form the first doped region 34, and thus the dopant can diffuse from the first contact node 33.

[0167] When forming the first contact node 33, a dummy contact node 33T can be formed on the sacrificial protective layer 32. The dummy contact node 33T can be formed by a SEG (Self-Enhancing Gland). The dummy contact node 33T can be an epitaxial layer of silicon. The dummy contact node 33T can be a doped silicon epitaxial layer.

[0168] Figure 21A This is a plan view illustrating a nanosheet-level structure used to describe the method of forming the first vertical conductor 36A and the second vertical conductor 36B. Figure 21B It is along Figure 21A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0169] refer to Figure 21A and Figure 21B A first vertical conductor 36A and a second vertical conductor 36B can be formed on the first contact node 33. Before forming the first vertical conductor 36A and the second vertical conductor 36B, an ohmic contact layer 35 can be formed on the first contact node 33. The ohmic contact layer 35 can all comprise a metal silicide such as titanium silicide or molybdenum silicide. When forming the ohmic contact layer 35, a dummy ohmic contact layer 35T can be formed on the dummy contact node 33T.

[0170] Forming the first vertical conductor 36A and the second vertical conductor 36B may include depositing a metallic material and etching the metallic material. Etching the metallic material may include a re-etching process. For example, a re-etching process can be performed without a mask, and the first vertical conductor 36A and the second vertical conductor 36B, which are isolated from each other, can be formed. The first vertical conductor 36A and the second vertical conductor 36B, which are adjacent to each other along the third direction D3, can be self-aligned using a support 16S. Because the support 16S acts as an etch barrier layer, the first vertical conductor 36A and the second vertical conductor 36B can be formed solely by the re-etching process. The bottom portions of the first vertical conductor 36A and the second vertical conductor 36B, which are adjacent to each other along the second direction D2, can be isolated from each other.

[0171] The first vertical conductor 36A and the second vertical conductor 36B may be vertically oriented along a first direction D1. The first vertical conductor 36A and the second vertical conductor 36B may each include a bit line. The first vertical conductor 36A and the second vertical conductor 36B may each include a metal, a metal-based material, or a combination thereof. The first vertical conductor 36A and the second vertical conductor 36B may each include a metal, a metal nitride, a metal silicide, or a combination thereof. The first vertical conductor 36A and the second vertical conductor 36B may each include titanium nitride, tungsten, or a combination thereof. For example, the first vertical conductor 36A and the second vertical conductor 36B may include a titanium nitride / tungsten (TiN / W) stack in which titanium nitride and tungsten are sequentially stacked. The first vertical conductor 36A and the second vertical conductor 36B may correspond to... Figures 4A to 4D The first conductor BL is shown in the figure.

[0172] Figure 22A This is a plan view showing a nanosheet-scale structure used to describe the method of forming the array isolation layer 37. Figure 22B and Figure 22C It is along Figure 22A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0173] refer to Figure 22A and Figure 22BThe sacrificial protective layer 32, dummy contact nodes 33T, and dummy ohmic contact layer 35T can be selectively removed. Therefore, a bottom trench 36T can be formed between the bottom portions of the first vertical conductor 36A and the bottom portions of the second vertical conductor 36B and the substrate 11. The bottom trench 36T may include a bridging prevention space 36L. The size of the bridging prevention space 36L may be equal to the total thickness of the sacrificial protective layer 32, the dummy contact nodes 33T, and the dummy ohmic contact layer 35T. The bottom portions of the first vertical conductor 36A and the second vertical conductor 36B can be spaced apart from the surface of the substrate 11 by the bridging prevention space 36L. That is, the bridging prevention space 36L can prevent bridging between the bottom portions of the first vertical conductor 36A and the bottom portions of the second vertical conductor 36B and the substrate 11. Although the bottom portions of the first vertical conductor 36A and the bottom portions of the second vertical conductor 36B are close to the substrate 11, the bridging prevention space 36L can prevent bridging between the bottom portions of the first vertical conductor 36A and the bottom portions of the second vertical conductor 36B and the substrate 11. Because the bridging prevention space 36L has a small height, the bottom portion of the first vertical conductor 36A and the bottom portion of the second vertical conductor 36B can be formed close to the substrate 11.

[0174] refer to Figure 22C An array isolation layer 37 can be formed between the first vertical conductor 36A and the second vertical conductor 36B. The array isolation layer 37 may include a dielectric material. The array isolation layer 37 may include an air gap 37G and a bridging prevention portion 37B. The array isolation layer 37 may fill the space between horizontally adjacent first vertical conductors 36A and between horizontally adjacent second vertical conductors 36B. The array isolation layer 37 may fill the bottom trench 36T. The bridging prevention portion 37B may fill the bridging prevention space 36L. The array isolation layer 37 may include a dielectric material. The array isolation layer 37 may include spin-on dielectric (SOD), silicon oxide, silicon nitride, or combinations thereof.

[0175] Forming the array isolation layer 37 may include depositing a dielectric material and planarizing the dielectric material. An air gap 37G may be formed during the deposition of the dielectric material.

[0176] As described above, the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B can be spaced apart from the surface of the substrate 11 by the total thickness of the sacrificial protective layer 32, the dummy contact node 33T, and the dummy ohmic contact layer 35T. That is, bridging between the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B and the substrate 11 can be prevented by the bridging prevention portion 37B of the array isolation layer 37. Although the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B are close to the substrate 11, the bridging prevention portion 37B of the array isolation layer 37 can prevent bridging between the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B and the substrate 11. Because the height of the bridging prevention portion 37B is small, the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B can be formed close to the substrate 11.

[0177] In this embodiment, because the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B are formed close to the substrate 11, dummy memory cells can be avoided. Since dummy memory cells are absent, the memory cell density can be increased.

[0178] In the comparative example, an oxide gap filling process and an oxide etch-back process can be performed before the formation of the first vertical conductor 36A and the second vertical conductor 36B. After the oxide etch-back process, the remaining oxide can block the bridge path between the first vertical conductor 36A and the second vertical conductor 36B and the substrate 11.

[0179] However, the problem with the comparative example is that, due to significant variations in the oxide etch-back process, the endpoint of the etch-back process must be set much higher than the surface of substrate 11. Therefore, in the comparative example, multiple dummy memory cells in which the first and second vertical conductors are not formed can be created, and thus the memory cell density can be reduced.

[0180] In an embodiment, the growth and removal process of the sacrificial protective layer 32 can suppress dummy memory cells and (e.g., easily or controllably) isolate the first vertical conductor 36A and the second vertical conductor 36B.

[0181] Figure 23A This is a plan view of a slab-level structure used to describe the method of forming the second linear opening 38. Figure 23B It is along Figure 23A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0182] refer to Figure 23A and Figure 23B The second linear sacrificial layer 19L can be selectively removed. Therefore, a second linear opening 38 can be formed.

[0183] After the second linear opening 38 is formed, the first mold layer 12A can be selectively recessed through the second linear opening 38. To selectively recess the first mold layer 12A, the difference in etching selectivity between the first mold layer 12A and the original body portion 13A can be used. The first mold layer 12A can be removed using a wet etching process or a dry etching process. For example, when the first mold layer 12A comprises a silicon-germanium layer and the original body portion 13A comprises a monocrystalline silicon layer, the silicon-germanium layer can be etched using an etchant or etching gas that is selective relative to the monocrystalline silicon layer.

[0184] Subsequently, the original body portion 13A can be recessed. To recess the original body portion 13A, a wet etching process or a dry etching process can be used. The vertical thickness of the original body portion 13A can be reduced, as indicated by the reference numeral "13S" in the attached figure. In the following text, the original body portion with the reduced vertical thickness is referred to as "recessed body portion 13S".

[0185] Each recessed portion 39 can be formed between the vertically arranged recessed main body portions 13S.

[0186] Figure 24A This is a planar view illustrating a sheet-like structure used to describe the method for forming nanosheets HL. Figure 24B It is along Figure 24A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0187] refer to Figure 24A and Figure 24B A third inter-unit dielectric layer 40 can be formed to fill the recess 39 between the main bodies. The third inter-unit dielectric layer 40 may all comprise silicon oxide.

[0188] After forming the third inter-cell dielectric layer 40, a bottom protective layer 41T may be formed on the bottom portion of the second linear opening 38. The bottom protective layer 41T may uniformly comprise a material with etching selectivity relative to the substrate 11. The bottom protective layer 41T may uniformly comprise a dielectric material. The bottom protective layer 41T may uniformly comprise silicon oxide, silicon nitride, silicon carbon oxide, or combinations thereof.

[0189] After forming the bottom protective layer 41T, a storage opening 41 can be formed by horizontally recessing the recessed body portion 13S. The storage opening 41 can be referred to as a "capacitor opening". Nanosheets HL can be formed by horizontally recessing the recessed body portion 13S. Each nanosheet HL can include a narrow sheet 13N and a wide sheet 13W. The narrow sheet 13N can include a first doped region 34. The wide sheet 13W of the nanosheet HL can refer to the recessed body portion 13S retained after the recess. The average vertical height of the wide sheet 13W of the nanosheet HL along the first direction D1 can be greater than the average vertical height of the narrow sheet 13N. The thickness of the wide sheet 13W of the nanosheet HL can gradually increase along the second direction D2. The horizontal length of the wide sheet 13W along the second direction D2 can be less than the horizontal length of the narrow sheet 13N. The wide sheet 13W of the nanosheet HL can have a fan-like shape. The wide sheet 13W can be referred to as a "fan-shaped sheet," while the narrow sheet 13N can be referred to as a "flat sheet."

[0190] To form nanosheets HL (each nanosheet comprising a wide sheet 13W), the recessed body portion 13S can be etched isotropically or anisotropically. One side of the wide sheet 13W (i.e., the side exposed by each storage opening 41) can have a flat shape. One side of the wide sheet 13W can have various shapes.

[0191] One side of the wide plate 13W can have various shapes. For example, one side of the wide plate 13W can have a rounded concave shape, a rounded convex shape, an angled concave shape, or an angled convex shape.

[0192] The bottom protective layer 41T and the bottommost third inter-unit dielectric layer 40 can prevent the substrate 11 from being lost during the recess process of the recessed body portion 13S.

[0193] Each storage opening 41 can be disposed between the third inter-cell dielectric layers 40 along the first direction D1.

[0194] In some embodiments, the horizontal recess of the recessed main body portion 13S used to form the wide piece 13W can stop at the boundary region between the narrow piece 13N and the wide piece 13W.

[0195] The first spacer 26 can surround the wide strip 13W, which is positioned at the same horizontal level along the third direction D3. The second spacer 30 can surround the narrow strip 13N, which is positioned at the same horizontal level along the third direction D3.

[0196] Figure 25A This is a planar diagram illustrating a nanosheet-level structure used to describe the method for forming nanosheets HL. Figure 25B It shows along Figure 25A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0197] refer to Figure 25A and Figure 25B It can perform a pre-cleaning process on the surface of a 13W wide sheet.

[0198] A second contact node 42 can be formed on the wafer 13W. Forming the second contact node 42 can include selective epitaxial growth (SEG). For example, a semiconductive material can be grown from the side surface of the wafer 13W via SEG. The second contact node 42 can all comprise SEG Si. Because the wafer 13W comprises monocrystalline silicon, the silicon layer can be epitaxially grown along the crystal surface of the side surface of the wafer 13W.

[0199] The second contact nodes 42 may all include dopants. When a silicon layer is grown using SEG, dopants can be doped in situ. Therefore, the second contact nodes 42 may all be doped epitaxial layers. The second contact nodes 42 may all include N-type dopants as dopants. N-type dopants may include phosphorus, arsenic, antimony, or combinations thereof. The second contact nodes 42 may all include phosphorus-doped silicon epitaxial layers formed by SEG, i.e., doped SEG SiP. In some embodiments, the second contact nodes 42 may be formed by a deposition process and an etch-back process of doped polysilicon.

[0200] Each second contact node 42 can be disposed between the vertically stacked third inter-cell dielectric layers 40. The second contact node 42 can correspond to... Figures 4A to 4C The second contact node SNC is shown.

[0201] A second doped region 43 can be formed in the wide wafer 13W. A thermal processing step can be performed to form the second doped region 43, and thus the dopant can diffuse from the second contact node 42.

[0202] A channel 44 can be defined between the first doped region 34 and the second doped region 43. The horizontally arranged first doped region 34, channel 44 and second doped region 43 can form each nanosheet HL.

[0203] Each nanosheet HL may include a first doped region 34, a second doped region 43, and a channel 44. The first doped region 34 and the channel 44 may be formed in a narrow wafer 13N. The second doped region 43 may be formed in a wide wafer 13W. A portion of each second doped region 43 may extend into the narrow wafer 13N. One side of each second doped region 43 of the nanosheet HL may be coupled to the channel 44. The other side of each second doped region 43 of the nanosheet HL may be coupled to a second contact node 42. The first doped region 34, the second doped region 43, and the channel 44 may respectively correspond to Figures 4A to 4CThe first doped region SR, the second doped region DR, and the channel CH are shown. The nanosheet HL, the nanosheet dielectric layer 25, and the horizontal wire 29 can be switching elements.

[0204] The first spacer 26 may surround a second doped region 43 disposed along the third direction D3 and at the same horizontal level. The second spacer 30 may surround a first doped region 34 disposed along the third direction D3 and at the same horizontal level. The horizontal conductor 29 may surround a channel 44 disposed along the third direction D3 and at the same horizontal level.

[0205] In some embodiments, an ohmic contact layer comprising metal silicide may be further formed after the formation of the second contact node 42.

[0206] As described above, nanosheets HL can be formed by performing a subsequent selective recessing process on the second mold layer 13 of the mold stack SB, and each nanosheet HL may include a narrow wafer 13N and a wide wafer 13W. A first doped region 34 and a channel 44 can be formed in the narrow wafer 13N, and a second doped region 43 can be formed in the wide wafer 13W.

[0207] Figure 26A This is a plan view showing a veneer-level structure used to describe the method of forming the first electrode 45. Figure 26B It shows along Figure 26A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0208] refer to Figure 26A and Figure 26B A first electrode 45 of a data storage element can be formed on the second contact node 42. The first electrode 45 can all be horizontally oriented cylindrical. Each first electrode 45 can be disposed in a different storage opening 41. First electrodes 45 disposed adjacent to each other along the second direction D2 can be spaced apart from each other through a second linear opening 38. First electrodes 45 disposed adjacent to each other along the first direction D1 can be spaced apart from each other through a third inter-cell dielectric layer 40. Forming the first electrode 45 may include depositing a metallic material along a vertical / horizontal direction, filling gaps with a sacrificial material, and isolating a metallic material. The sacrificial material may include oxide or polysilicon.

[0209] Each first electrode 45 may include an inner space and multiple outer surfaces. The inner space of the first electrode 45 may include multiple inner surfaces. The outer surfaces of the first electrode 45 may include a vertical outer surface and multiple horizontal outer surfaces. The vertical outer surface of the first electrode 45 may extend vertically along a first direction D1. The horizontal outer surfaces of the first electrode 45 may extend horizontally along a second direction D2 or a third direction D3. The inner space of the first electrode 45 may be three-dimensional. The first electrode 45 may be cylindrical.

[0210] Within the outer surface of the first electrode 45, the vertical outer surface can be electrically coupled to the nanosheet HL and the second contact node 42.

[0211] The first electrode 45 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 45 may include: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, or a combination thereof.

[0212] Figure 27A This is a plan view of a narrow-plate structure illustrating a method for describing the method of partially recessing the dielectric layer 40 between the third units. Figure 27B It is along Figure 27A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0213] refer to Figure 27A and Figure 27B The first inter-unit dielectric layer 23 and the third inter-unit dielectric layer 40 can be partially horizontally recessed (refer to reference numeral "40R" in the accompanying drawings). Therefore, the outer wall of the first electrode 45 can be partially exposed. Each of the first electrodes 45 can have a semi-cylindrical shape. The horizontal recess depth of the third inter-unit dielectric layer 40 can be a depth that does not expose the second contact node 42. The semi-cylindrical shape of each first electrode 45 can include a cylindrical inner surface and a semi-cylindrical outer surface.

[0214] Figure 28A This is a plan view showing a veneer-level structure used to describe the method of forming the second electrode 47. Figure 28B It is along Figure 28A The cross-sectional view of the structure intercepted by line AA′ is shown.

[0215] refer to Figure 28A and Figure 28B A dielectric layer 46 and a second electrode 47 can be sequentially formed on the first electrode 45. The first electrode 45, the dielectric layer 46, and the second electrode 47 can be data storage elements (CAPs). The second electrodes 47 of the data storage elements (CAPs) can be joined together to form a common plate (PL).

[0216] The dielectric layer 46 and the second electrode 47 may be disposed on the cylindrical inner surface of the first electrode 45. A portion of the dielectric layer 46 and a portion of the second electrode 47 may extend to be disposed on the semi-cylindrical outer surface of the first electrode 45. The second electrode 47 may extend perpendicularly along the first direction D1.

[0217] The dielectric layer 46 may be referred to as a "capacitor dielectric layer" or a "storage layer". The dielectric layer 46 may comprise silicon oxide, silicon nitride, high-k materials, ferroelectric materials, antiferroelectric materials, perovskite materials, or combinations thereof. The dielectric layer 46 may comprise hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). The dielectric layer 46 may include ZA (ZrO2 / Al2O3) stacks, ZAZ (ZrO2 / Al2O3 / ZrO2) stacks, ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stacks, ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stacks, HAH (HfO2 / Al2O3 / HfO2) stacks, HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stacks, HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stacks, and HZAZH (HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2) stacks. Stacked ZHZAZHZ(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2), stacked ZHZAZHZA(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3), stacked ZHZAZHZAT(ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2), stacked HZHZ(HfO2 / ZrO2 / HfO2 / ZrO2), or stacked AHZAZHA(Al2O3 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / Al2O3).

[0218] The second electrode 47 may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the second electrode 47 may include: titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stacks, tungsten nitride / tungsten (WN / W) stacks, titanium silicon nitride / titanium nitride (TiSiN / TiN) stacks, titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stacks, or combinations thereof. A titanium silicon nitride / titanium nitride / tungsten (TiSiN / TiN / W) stack can refer to a structure in which titanium silicon nitride, titanium nitride, and tungsten are sequentially stacked. The second electrode 47 may also comprise a combination of metal-based and silicon-based materials. For example, titanium nitride, tungsten, and polycrystalline silicon may be sequentially stacked in the second electrode 47.

[0219] In some embodiments, the data storage element CAP may further include multiple interface control layers to mitigate leakage current. Each interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), niobium oxynitride (NbON), or combinations thereof. A first interface control layer may be formed between the first electrode 45 and the dielectric layer 46, and a second interface control layer may be formed between the dielectric layer 46 and the second electrode 47. For example, a structure in which the first interface control layer, the dielectric layer 46, and the second interface control layer are sequentially stacked may include an NZHZAZHZATN (Nb2O5 / ZrO2 / HfO2 / ZrO2 / Al2O3 / ZrO2 / HfO2 / ZrO2 / Al2O3 / TiO2 / Nb2O5) stack.

[0220] In some embodiments, this can be omitted. Figure 27B The recesses in the third inter-cell dielectric layer 40 and the first inter-cell dielectric layer 23 are shown. Thereafter, as... Figure 28B As shown, a dielectric layer 46 and a second electrode 47 can be formed. Therefore, a data storage element CAP including a concave first electrode 45 can be formed.

[0221] Figure 29 This is a schematic cross-sectional view showing a semiconductor device 200M according to an embodiment of the present disclosure. Figure 29 It can be along Figure 4A The diagram shows a schematic cross-sectional view of semiconductor device 100 taken by line AA′. Semiconductor device 200M can be similar to... Figures 4A to 4D The semiconductor device 100 shown above. (Reference above) Figures 4A to 4D A detailed description of the stacked components is provided.

[0222] refer to Figure 29 The semiconductor device 200M may include a first vertical conductor BLA and a second vertical conductor BLB. An array isolation layer BLF may be disposed between the first vertical conductor BLA and the second vertical conductor BLB. The array isolation layer BLF may include a dielectric material. The first vertical conductor BLA and the second vertical conductor BLB, which are adjacent to each other along the second direction D2, may be isolated from each other by the array isolation layer BLF.

[0223] A vertical spacer BLL can be disposed between the array isolation layer BLF and the first vertical conductor BLA and the second vertical conductor BLB. A dummy ohmic contact layer BLT can be coupled to the bottom portion of the first vertical conductor BLA and the bottom portion of the second vertical conductor BLB. The bottom portion of the vertical spacer BLL can extend downward to cover the dummy ohmic contact layer BLT.

[0224] The array isolation layer BLF may include an air gap FG and a bridging prevention portion BP. The air gap FG reduces the parasitic capacitance between adjacent first vertical conductors BLA and second vertical conductors BLB. The bridging prevention portion BP of the array isolation layer BLF prevents bridging between the bottom portions of the first vertical conductor BLA and the bottom portions of the second vertical conductor BLB and the lower structure LS. Although the bottom portions of the first vertical conductor BLA and the second vertical conductor BLB are close to the lower structure LS, the bridging prevention portion BP of the array isolation layer BLF prevents bridging between the bottom portions of the first vertical conductor BLA and the bottom portions of the second vertical conductor BLB and the lower structure LS. Because the height of the bridging prevention portion BP is small, the bottom portions of the first vertical conductor BLA and the bottom portions of the second vertical conductor BLB can be formed close to the lower structure LS.

[0225] In this embodiment, because the bottom portions of the first vertical conductor BLA and the second vertical conductor BLB are formed close to the lower structure LS, dummy memory cells can be avoided. Since dummy memory cells are absent, the memory cell density can be increased.

[0226] Figures 30 to 34 It shows the use of manufacturing Figure 29 Various views of the semiconductor device 200M formed by the method shown.

[0227] For reference Figures 5A to 21B As described above, a sacrificial protective layer 32, a dummy contact node 33T, a dummy ohmic contact layer 35T, and a first vertical conductor 36A and a second vertical conductor 36B can be formed.

[0228] Subsequently, reference Figure 30 A vertical inner liner 51A can be formed. The vertical inner liner 51A can be conformally formed on the first vertical conductor 36A and the second vertical conductor 36B. The vertical inner liner 51A may include silicon oxide.

[0229] refer to Figure 31 The vertical inner liner 51A can be etched to form the vertical spacer 51. The dummy ohmic contact layer 35T can be exposed beneath the bottom portion of the vertical spacer 51.

[0230] The dummy ohmic contact layer 35T, the dummy contact node 33T, and the sacrificial protective layer 32 can be sequentially cut using the vertical spacer 51 as an etching barrier layer. Therefore, a bottom isolation trench 52 can be formed.

[0231] refer to Figure 32 The dummy contact node 33T and the sacrificial protective layer 32 can be removed sequentially through the bottom isolation trench 52. When removing the dummy contact node 33T and the sacrificial protective layer 32, the dummy ohmic contact layer 35T and the vertical spacer 51 can be used as etching barrier layers.

[0232] A bottom trench 53 can be formed in the spacer where the dummy contact node 33T and the sacrificial protective layer 32 are removed. The bottom trench 53 can expose the surface of the substrate 11. The bottom trench 53 can be U-shaped.

[0233] refer to Figure 33 The surface of the substrate 11 exposed by the bottom trench 53 can be adjusted. Therefore, a substrate adjustment portion 54 can be formed. The substrate adjustment portion 54 can be U-shaped.

[0234] As described above, the bottom trench 53 and the substrate trimming portion 54 can be formed between the bottom portion of the first vertical conductor 36A and the bottom portion of the second vertical conductor 36B and the substrate 11.

[0235] The bottom portions of the first vertical conductor 36A and the second vertical conductor 36B are spaced apart from the surface of the substrate 11 by the bottom trench 53 and the substrate trimming portion 54. That is, the bottom trench 53 and the substrate trimming portion 54 prevent bridging between the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B and the substrate 11. Although the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B are close to the substrate 11, bridging between them and the substrate 11 can be prevented by the bottom trench 53 and the substrate trimming portion 54. Because the height of the bottom trench 53 and the height of the substrate trimming portion 54 are small, the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B can be formed close to the substrate 11.

[0236] refer to Figure 34 An array isolation layer 37 can be formed between the first vertical conductor 36A and the second vertical conductor 36B. The array isolation layer 37 may include a dielectric material. The array isolation layer 37 may include an air gap 37G and a bridging prevention portion 37B. The array isolation layer 37 may fill the space between the first vertical conductor 36A and the second vertical conductor 36B. The array isolation layer 37 may fill the first linear opening 20, the bottom trench 53, and the substrate trimming portion 54. The bridging prevention portion 37B may fill the bottom trench 53 and the substrate trimming portion 54. The array isolation layer 37 may include silicon oxide.

[0237] A vertical spacer 51 may be disposed between the array isolation layer 37 and the first vertical conductor 36A and the second vertical conductor 36B. A dummy ohmic contact layer 35T may be coupled to the bottom portion of the first vertical conductor 36A and the bottom portion of the second vertical conductor 36B. The bottom portion of the vertical spacer 51 may extend downward to cover the dummy ohmic contact layer 35T.

[0238] Forming the array isolation layer 37 may include depositing a dielectric material and planarizing the dielectric material. An air gap 37G may be formed during the deposition of the dielectric material.

[0239] As described above, the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B can be spaced apart from the surface of the substrate 11 by the total thickness of the bottom trench 53 and the substrate trimming portion 54. That is, the bridging prevention portion 37B of the array isolation layer 37 can prevent bridging between the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B and the substrate 11. Although the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B are close to the substrate 11, the bridging prevention portion 37B of the array isolation layer 37 can prevent bridging between the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B and the substrate 11. Because the height of the bridging prevention portion 37B is small, the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B can be formed close to the substrate 11.

[0240] In this embodiment, because the bottom portions of the first vertical conductor 36A and the second vertical conductor 36B are formed close to the substrate 11, dummy memory cells can be avoided. The absence of dummy memory cells provides the ability to increase memory cell density.

[0241] Subsequently, it can be done through reference as follows Figures 23A to 28B The aforementioned series of processes form wide sheets, second contact nodes, nanosheets, and data storage elements.

[0242] Figure 35A and Figure 35B These are schematic cross-sectional views of semiconductor devices 300 and 301 according to embodiments of the present disclosure.

[0243] refer to Figure 35A Semiconductor device 300 may include a memory cell array MCA, a peripheral circuit portion PERI, and a bonding interface BS. The bonding interface BS may be disposed between the memory cell array MCA and the peripheral circuit portion PERI. In semiconductor device 300, the memory cell array MCA may be disposed at a level higher than the peripheral circuit portion PERI. Semiconductor device 300 may be referred to as a "peri-under-cell array (PUC) structure". The memory cell array MCA may include a substrate to which back-grinding has been performed and an array of memory cells. For example, as referenced... Figure 34 After forming the data storage element CAP, the substrate 11 can be flipped by wafer flipping, and then the back side of the substrate 11 can be partially grounded.

[0244] refer to Figure 35BSemiconductor device 301 may include a memory cell array (MCA), a peripheral circuit portion (PERI), and a bonding interface (BS). The bonding interface (BS) may be disposed between the memory cell array (MCA) and the peripheral circuit portion (PERI). In semiconductor device 301, the memory cell array (MCA) may be disposed at a level below the peripheral circuit portion (PERI). Semiconductor device 301 may be referred to as a "cell array under peripheral (CUP) structure." Forming the peripheral circuit portion (PERI) may include forming multiple control circuits on the peripheral circuit substrate and forming multi-level interconnects on the control circuits.

[0245] exist Figure 35A and Figure 35B In this context, the bonding interface BS can include pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or combinations thereof. Hybrid bonding can refer to a combination of pad bonding and oxide-to-oxide bonding. Pad bonding can include: forming cell bonding pads for a memory cell array (MCA); forming peripheral circuit bonding pads for a peripheral circuit section (PERI); performing wafer flipping so that the cell bonding pads and peripheral circuit bonding pads face each other; and performing wafer bonding.

[0246] After forming the cell bonding pads and the peripheral circuit bonding pads Figure 35A The semiconductor device 300 shown can perform wafer flipping on the substrate on which a memory cell array is formed, such that the cell bonding pads and the peripheral circuit bonding pads face each other. After forming the cell bonding pads and the peripheral circuit bonding pads... Figure 35B The semiconductor device 301 shown can perform wafer flipping on the substrate on which the peripheral circuit portion is formed, so that the cell bonding pads and the peripheral circuit bonding pads face each other.

[0247] Figure 36A and Figure 36B Various views of stacked components 400 and 500 according to embodiments of the present disclosure are shown.

[0248] refer to Figure 36A The stacked assembly 400 may include a component of semiconductor dies. For example, the stacked assembly 400 may include a first semiconductor die BSD and a plurality of second semiconductor dies 401. The first semiconductor die BSD may include logic circuitry. Each second semiconductor die 401 may include a memory cell array according to the above embodiments.

[0249] Each second semiconductor die 401 may include a structure in which a memory cell array stack and peripheral circuitry portions are stacked, for example, Figure 35A The semiconductor device 300 shown Figure 35BThe semiconductor device 301 is shown. The logic circuitry of the first semiconductor die BSD may differ from the peripheral circuitry of the second semiconductor die 401. The second semiconductor die 401 may be located at the chip level or the wafer level.

[0250] The second semiconductor die 401 can be electrically coupled to each other through multiple through-silicon vias (TSVs) and bonding interfaces (CBSs). The first semiconductor die (BSD) and the bottommost second semiconductor die 401 can be electrically coupled to each other through bonding interfaces (CBSs). The second semiconductor die 401 can be referred to as a "core die," a "semiconductor chip," or a "memory chip."

[0251] The bonding interface CBS can include microbumps, pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or combinations thereof.

[0252] refer to Figure 36B The stacked assembly 500 may include a component of semiconductor dies. For example, the stacked assembly 500 may include a first semiconductor die BSD, a plurality of second semiconductor dies 501, and a plurality of third semiconductor dies 502. The first semiconductor die BSD may include logic circuitry. Each second semiconductor die 501 and each third semiconductor die 502 may include a stack of memory cell arrays according to the above embodiments. The second semiconductor dies 501 and the third semiconductor dies 502 may have different structures.

[0253] Each second semiconductor die 501 may include Figure 35A The semiconductor device 300 shown includes a memory cell array stacked on top of a peripheral circuitry portion. Each third semiconductor die 502 may include... Figure 35B The semiconductor device 301 shown has a peripheral circuit portion stacked on top of the memory cell array.

[0254] In some embodiments, each second semiconductor die 501 may include Figure 35B The semiconductor device 301 shown includes peripheral circuitry stacked on top of a memory cell array, and each third semiconductor die 502 may include... Figure 35A The semiconductor device 300 shown has a memory cell array stacked on top of a peripheral circuit portion.

[0255] The logic circuitry of the first semiconductor die BSD may differ from the peripheral circuitry of the second semiconductor die 501 and the third semiconductor die 502. The second semiconductor die 501 and the third semiconductor die 502 may be located at the chip level or the wafer level.

[0256] The second semiconductor die 501 and the third semiconductor die 502 can be electrically coupled to each other through multiple through-silicon vias (TSVs) and bonding interfaces (CBSs). The first semiconductor die BSD and the bottommost second semiconductor die 501 can be electrically coupled to each other through bonding interfaces (CBSs). The second semiconductor die 501 and the third semiconductor die 502 can be referred to as "core dies," "semiconductor chips," or "memory chips."

[0257] The bonding interface CBS can include microbumps, pad bonding, hybrid bonding, oxide-to-oxide bonding, metal-to-metal bonding, or combinations thereof.

[0258] refer to Figure 36A and Figure 36B The stacking components 400 and 500 may be high-bandwidth memories.

[0259] According to various embodiments of this disclosure, the bridging prevention portion can prevent bridging between the bottom portion of the vertical conductor and the surface of the substrate.

[0260] According to various embodiments of this disclosure, because the bottom portion of the vertical conductor is formed as a surface close to the substrate, the formation of dummy memory cells can be prevented, which allows for an increase in memory cell density.

[0261] According to various embodiments of this disclosure, parasitic capacitance between vertical conductors can be reduced because an air gap is formed between adjacent vertical conductors.

[0262] According to various embodiments of this disclosure, the reliability of 3D storage devices can be improved.

[0263] While embodiments of the present disclosure have been shown and described with reference to specific examples and accompanying drawings, the disclosed embodiments are not intended to be limiting. Furthermore, it should be noted that those skilled in the art will recognize from this disclosure that these embodiments can be implemented in various ways through substitutions, changes, and modifications without departing from the spirit and / or scope of this disclosure and the appended claims. Moreover, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: Nanosheets, which are arranged in a vertical and horizontal manner and spaced apart from the surface of a substrate; A horizontal conductor, the horizontal conductor being horizontally oriented and configured to surround the nanosheets arranged in a horizontal manner; Vertical wires, which are collectively coupled to the nanosheets arranged in the vertical arrangement and are also individually coupled to the nanosheets arranged in the horizontal arrangement; A support member is disposed between the vertical conductors to support the vertical conductors; as well as An array isolation layer, the array isolation layer including a bridging prevention portion disposed between the bottom portion of the vertical conductor and the surface of the substrate.

2. The semiconductor device as claimed in claim 1, wherein, All bridging prevention components include dielectric materials.

3. The semiconductor device as claimed in claim 1, wherein, The array isolation layer also includes an air gap.

4. The semiconductor device as claimed in claim 1, wherein, The vertical guide wire is configured to be aligned between the supports.

5. The semiconductor device as claimed in claim 1, wherein, All of the support components include dielectric materials.

6. The semiconductor device of claim 1, further comprising: A contact node is disposed between the nanosheet and the vertical wire; as well as An ohmic contact layer is disposed between the contact node and the vertical conductor.

7. The semiconductor device of claim 6, wherein, The contact node includes a doped silicon layer.

8. The semiconductor device of claim 1, further comprising: Data storage elements, each data storage element being coupled to the nanosheets arranged in the vertical and horizontal configurations.

9. The semiconductor device of claim 1, further comprising: A dummy ohmic contact layer is configured to extend from the bottom portion of the vertical conductor; as well as A vertical spacer is configured to cover the dummy ohmic contact layer and the vertical conductor.

10. A semiconductor device, comprising: A first vertical conductor, spaced apart from the surface of the substrate; The second vertical conductor is horizontally spaced from the first vertical conductor; The first nanosheet is arranged in a vertical manner and is coupled together to the first vertical wire; The second nanosheet is arranged in a vertical manner and is coupled together to the second vertical wire; A first horizontal wire, the first horizontal wire being horizontally oriented and configured to surround the first nanosheet; A second horizontal wire, the second horizontal wire being horizontally oriented and configured to surround the second nanosheet; A support member configured to support the first vertical conductor and the second vertical conductor; as well as An array isolation layer is disposed between a first vertical conductor and a second vertical conductor, the array isolation layer including a bridging prevention portion disposed between the bottom portions of the first vertical conductor and the bottom portions of the second vertical conductor and the surface of the substrate.

11. The semiconductor device of claim 10, wherein, All bridging prevention components include dielectric materials.

12. The semiconductor device of claim 10, wherein, The array isolation layer also includes an air gap disposed between the first vertical conductor and the second vertical conductor.

13. The semiconductor device of claim 10, wherein, The first vertical guide and the second vertical guide are configured to be aligned using the support.

14. The semiconductor device of claim 10, wherein, All of the support components include dielectric materials.

15. The semiconductor device of claim 10, further comprising: The first contact node is disposed between the first nanosheet and the first vertical wire, and is also disposed between the second nanosheet and the second vertical wire; as well as An ohmic contact layer is disposed between the contact node and the first vertical conductor and the second vertical conductor.

16. The semiconductor device of claim 15, wherein, The first contact node includes a doped silicon layer.

17. The semiconductor device of claim 10, further comprising: Data storage elements, each data storage element being coupled to the first nanosheet and the second nanosheet; as well as The second contact node is disposed between the first nanosheet and the second nanosheet and the data storage element.

18. The semiconductor device of claim 17, wherein, Each of the first nanosheet and the second nanosheet includes a flat sheet that contacts the first vertical conductor and the second vertical conductor, and a fan-shaped sheet that contacts the data storage element.

19. The semiconductor device of claim 10, further comprising: A dummy ohmic contact layer is configured to extend from the bottom portion of the first vertical conductor and the bottom portion of the second vertical conductor; as well as A vertical spacer is configured to cover the dummy ohmic contact layer as well as the first vertical conductor and the second vertical conductor.

20. A method for manufacturing a semiconductor device, the method comprising: Forming a mold stack, the mold stack comprising mold layers vertically stacked on a substrate; A sacrificial isolation layer is formed in the module stack; A linear opening is formed that penetrates the mold stack and extends into the substrate; A portion of the sacrificial isolation layer is replaced by a support through the linear opening; The first portion of the mold layer of the mold stack is adjusted to form a narrow sheet; A sacrificial bag layer is formed on one side of the narrow strip; A sacrificial protective layer is formed on the bottom surface of the linear opening; Remove the sacrificial bag layer; A vertical conductor is formed that is coupled to one side of the narrow strip; The sacrificial protective layer is selectively removed; as well as An array isolation layer is formed, the array isolation layer including a bridging prevention portion that fills the linear opening and is disposed between the bottom portion of the vertical conductor and the surface of the substrate.

21. The method of claim 20, wherein, The sacrificial protective layer includes a selective epitaxial growth layer.

22. The method of claim 20, wherein, Forming the sacrificial protective layer involves selectively and epitaxially growing a silicon-germanium layer on the bottom surface of the linear opening.

23. The method of claim 20, wherein, The vertical guide is formed to be self-aligned using the support member.

24. The method of claim 20, wherein, The array isolation layer also includes an air gap adjacent to the vertical conductor.

25. The method of claim 20, further comprising: After the array isolation layer is formed: The second portion of the mold layer is horizontally recessed to form a fan-shaped sheet; as well as Data storage elements are formed, and each data storage element is coupled to the sector.

26. The method of claim 20, further comprising: After the narrow strip is formed: Remove the sacrificial isolation layer to expose the narrow strip; A first spacer is formed, which extends horizontally to surround a portion of the exposed narrow strip; A horizontal guide is formed, which is adjacent to the first spacer and extends horizontally to surround the narrow strip; as well as A second spacer is formed, which is adjacent to the horizontal conductor and extends horizontally to surround the narrow strip.

27. The method of claim 20, further comprising: Before forming the vertical conductor: Contact nodes are selectively grown on one side of the narrow strip; as well as An ohmic contact layer is formed on the contact node.

28. The method of claim 27, wherein, The contact node includes a selectively epitaxial growth layer.

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