Semiconductor device

Abstract

The semiconductor device includes a withstand voltage holding layer of a first conductivity type, and a super junction layer disposed in contact with an upper surface of the withstand voltage holding layer. In the super junction layer, first regions of a first conductivity type and second regions of a second conductivity type are alternately and repeatedly arranged along a first direction. The second region includes a lower-side second region in contact with the withstand voltage holding layer and an upper-side second region disposed in contact with an upper surface of the lower-side second region. The lower-side second region has a lower-side maximum width, which is the maximum width in the first direction. The upper-side second region has an upper-side maximum width, which is the maximum width in the first direction. The lower maximum width is larger than the upper maximum width. The lower-side second region is higher than the upper-side second region with respect to the density of the fixed charge at the time of depletion.

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices. Background Technology

[0002] A semiconductor device is known to have a structure in which a superjunction layer is stacked on a breakdown voltage holding layer (also called a drift layer) that shares the breakdown voltage. The superjunction layer is essentially completely depleted, thus forming a depletion layer over a large area, thereby ensuring sufficient breakdown voltage. An example of a semiconductor device having such a structure is disclosed in Patent Document 1.

[0003] Existing technical documents Patent documents Patent Document 1: U.S. Patent Application Publication No. 2023-282705 Summary of the Invention

[0004] There are cases where the depletion layer has difficulty progressing from the superjunction layer into the interior of the drift layer. In such cases, due to the low electric field inside the drift layer, it may not be possible to adequately ensure the withstand voltage of the drift layer.

[0005] In one embodiment of the semiconductor device disclosed in this specification, the semiconductor device includes a voltage holding layer of a first conductivity type and a superjunction layer disposed grounded to the upper surface of the voltage holding layer. In the superjunction layer, a first region of the first conductivity type and a second region of the second conductivity type are alternately arranged along a first direction. The second region includes a lower second region disposed grounded to the voltage holding layer and an upper second region disposed grounded to the upper surface of the lower second region. The lower second region has a maximum width in the first direction, i.e., a lower maximum width. The upper second region also has a maximum width in the first direction, i.e., an upper maximum width. The lower maximum width is larger than the upper maximum width. Regarding the density of the fixed charge at depletion, the lower second region is higher than the upper second region.

[0006] Based on the above structure, the density of fixed charge at depletion is higher in the lower second region than in the upper second region. Therefore, the increased density of fixed charge in the lower second region promotes the progression of the depletion layer toward the voltage holding layer adjacent to the lower second region. Since the electric field shared by the voltage holding layer can be increased, the voltage withstand capability of the voltage holding layer can be improved. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view of the main parts of a semiconductor device.

[0008] Figure 2 This is a magnified view of a local area near the SJ layer.

[0009] Figure 3 This is a magnified view of a portion of the area near the SJ layer in a comparative example semiconductor device.

[0010] Figure 4 This is a magnified view of a portion of the area near the SJ layer in the semiconductor device of this embodiment.

[0011] Figure 5 This is a diagram illustrating the process of forming the SJ layer.

[0012] Figure 6 This is a diagram illustrating the process of forming the SJ layer.

[0013] Figure 7 This is a diagram illustrating the process of forming the SJ layer.

[0014] Figure 8 This is a cross-sectional view of the main part of the semiconductor device according to the second embodiment.

[0015] Figure 9 This is a diagram illustrating the effects of the second embodiment.

[0016] Figure 10 This is a diagram illustrating the process of forming the SJ layer.

[0017] Figure 11 This is a cross-sectional view of the main part of the semiconductor device according to the third embodiment.

[0018] Figure 12 This is a diagram showing examples of various cross-sectional shapes in the lower second region. Detailed Implementation

[0019] [First Implementation Method] The semiconductor device disclosed in this specification will now be described with reference to the accompanying drawings. Furthermore, for the purpose of clarity, for components that are repeatedly arranged, sometimes only one of them is labeled with a reference numeral.

[0020] like Figure 1 As shown, semiconductor device 1 is a power semiconductor device of the type known as MOSFET. Semiconductor device 1 includes a semiconductor substrate 10, a drain 22 covering the lower surface of the semiconductor substrate 10, a source 24 covering the upper surface of the semiconductor substrate 10, and a plurality of trench gates 30 disposed on the upper part of the semiconductor substrate 10.

[0021] The material of the semiconductor substrate 10 is not particularly limited. In this embodiment, it is silicon carbide. Additionally, the n-type impurity is nitrogen, and the p-type impurity is aluminum. The semiconductor substrate 10 has n... + Type 11, n - The drift region 12, superjunction layer 14, bulk region 15, source region 16, and bulk contact region 17 are defined. Furthermore, the superjunction layer will sometimes be abbreviated as "SJ layer" below.

[0022] Drain region 11 is located at the exposed lower surface of semiconductor substrate 10. Drain region 11 contains a high concentration of n-type impurities and has an ohmic contact with drain electrode 22. Drift region 12 is located between drain region 11 and SJ layer 14, and is connected to both drain region 11 and SJ layer 14. The concentration of n-type impurities in drift region 12 is lower than that in drain region 11.

[0023] An SJ layer 14 is disposed on the upper surface of the drift region 12. The SJ layer 14 has a plurality of n-type first regions 31 and a plurality of p-type second regions 32. The first regions 31 and the second regions 32 are alternately repeated along the x-direction. Although not particularly limited, the plurality of first regions 31 and the plurality of second regions 32 may be arranged in a strip shape, for example, when viewed from a direction orthogonal to the upper surface 10s of the semiconductor substrate 10 (+z direction).

[0024] The second region 32 comprises a lower second region 32b and an upper second region 32a. The lower second region 32b is a region where the concentration of p-type impurities is higher than that of the upper second region 32a. The lower second region 32b is connected to the drift region 12. The upper second region 32a is connected to the upper surface of the lower second region 32b.

[0025] use Figure 2 The lower second region 32b and the upper second region 32a are described. Figure 2 (A) is a magnified view of a portion near layer 14 of SJ. Additionally, in Figure 2 In (A), the description of the groove grid 30 is omitted. Figure 2 (B) is a depth-direction distribution map of the negative fixed charge when the second region 32 is depleted. The distribution of the negative fixed charge can be obtained, for example, by subtracting the donor impurity concentration distribution from the acceptor impurity concentration distribution.

[0026] The concentration of p-type impurities in the lower second region 32b is higher than the concentration of p-type impurities in the upper second region 32a. Therefore, as Figure 2 As shown in (B), when the second region 32 is depleted, the lower second region 32b has a higher density of negative fixed charge than the upper second region 32a. Furthermore, there is a boundary BL1 between the lower second region 32b and the upper second region 32a where the amount of negative fixed charge changes drastically.

[0027] The lower second region 32b has a maximum width in the x-direction, i.e., a lower maximum width W2b. In this embodiment, the width of the lower second region 32b in the x-direction is constant in the depth direction (z-direction). Therefore, the width of the lower second region 32b is the lower maximum width W2b throughout the depth direction. That is, the width of the lower second region 32b at the interface IF between the lower second region 32b and the drift region 12 is the lower maximum width W2b. Additionally, the upper second region 32a has a maximum width in the x-direction, i.e., an upper maximum width W2a. In this embodiment, the width of the upper second region 32a in the x-direction is constant in the depth direction (z-direction). Therefore, the width of the upper second region 32a is the upper maximum width W2a throughout the depth direction. Furthermore, the lower maximum width W2b is larger than the upper maximum width W2a.

[0028] Furthermore, the maximum widths W2a and W2b on the upper and lower sides, and the z-direction heights of the lower second region 32b and the upper second region 32a can be various values. Additionally, the distribution of negative fixed charge (refer to...) Figure 2 (B) is not limited to the manner described in this embodiment and can be of various kinds.

[0029] like Figure 1 As shown, body region 15 is disposed on SJ layer 14. Body region 15 is located between SJ layer 14 and source region 16, and is connected to both SJ layer 14 and source region 16, separating SJ layer 14 and source region 16. The concentration of p-type impurities in body region 15 is adjusted according to the required gate threshold voltage.

[0030] Source region 16 is disposed on body region 15 and is located at a position exposed on the upper surface 10s of semiconductor substrate 10. Source region 16 is connected to the upper side of trench gate 30. Source region 16 contains n-type impurities at a high concentration and has an ohmic contact with source electrode 24.

[0031] A body contact region 17 is disposed on the body region 15, located on the upper layer of the semiconductor substrate 10, and positioned at a location exposed on the upper surface 10s of the semiconductor substrate 10. The body contact region 17 makes a 24-ohm contact with the source electrode covering the upper surface 10s.

[0032] Multiple trenches TR extend from the surface of the source region 16 through the body region 15 to the first region 31. A trench gate 30 is disposed within each of the multiple trenches TR. Each trench gate 30 has a gate 33 and a gate insulating film 34. The gate insulating film 34 is formed of silicon oxide and covers the inner wall of the trench. The gate 33 is formed of polysilicon containing impurities. The multiple trench gates 30 extend along the y-direction within the cross-section of the semiconductor substrate 10. Furthermore, the multiple trench gates 30 are arranged at intervals along a direction orthogonal to their length direction (x-direction). That is, when the semiconductor substrate 10 is viewed from above (viewed from the z-direction), the trench gates 30 are located within the region of the first region 31.

[0033] (Operation of semiconductor device 1) When the potential of the drain 22 is positive compared to the potential of the source 24, and the potential of the gate 33 of the trench gate 30 is positive compared to the source 24 and is controlled to be higher than a threshold, the semiconductor device 1 turns on. At this time, an inversion layer is formed in the body region 15, which separates the source region 16 from the first region 31 of the SJ layer 14. Electrons supplied from the source region 16 reach the first region 31 of the SJ layer 14 through the inversion layer channel. Electrons that reach the first region 31 flow through the first region 31 to the drift region 12 and the drain region 11. Because the concentration of n-type impurities in the first region 31 is high, the semiconductor device 1 can have the characteristic of low on-resistance.

[0034] When the potential of the gate 33 of the trench gate 30 is controlled to be the same as the potential of the source 24, the inversion layer channel disappears, and the semiconductor device 1 is turned off. In the SJ layer 14, the configuration is such that, in the repeating direction (x-direction), the density of positive fixed charge when the plurality of first regions 31 are depleted is balanced with the density of negative fixed charge when the plurality of second regions 32 are depleted. Therefore, the plurality of first regions 31 and the plurality of second regions 32 are substantially completely depleted, resulting in a large-scale depletion of the SJ layer 14. Furthermore, the electric field distribution of the SJ layer 14 is uniform in the depth direction. Therefore, the SJ layer 14 can withstand a large potential difference, thus enabling the semiconductor device 1 to possess high withstand voltage characteristics.

[0035] (Topic and Results) Figure 3 Semiconductor device 101 is shown as a comparative example. Additionally... Figure 4 This refers to the semiconductor device 1 in this embodiment. Figure 3 (A) and Figure 4 (A) is a magnified view of a local area near the SJ layer. Figure 3 (A) and Figure 4In (A), the description of the trench gate 30 is omitted, and the depletion layer during depletion is represented by the area indicated by the dashed line. In addition, among the fixed charges present near the interface IF between the SJ layer and the drift region 12, positive fixed charges are simulated by circles with a + sign and negative fixed charges are simulated by circles with a - sign. Figure 3 (B) and Figure 4 (B) is the electric field distribution within the second region when the second region is depleted.

[0036] use Figure 3 The comparative example illustrates the topic. The comparative example uses SJ layer 140 (… Figure 3 ) and SJ layer 14 of this embodiment ( Figure 4 In contrast, the second region 132 has a different structure. The concentration of p-type impurities in the second region 132 is constant throughout the entire depth direction (z-direction). Therefore, the second region 132 is not divided into an upper region and a lower region. Furthermore, the second region 132 has a constant width W 102 throughout the entire depth direction. Similarly, the first region 131 has a constant width W 101 throughout the entire depth direction.

[0037] When a voltage is applied to the semiconductor device 101, a negative fixed charge is generated in the second region 132 near the interface IF, and a positive fixed charge is generated in the first region 131 and the drift region 12 (see reference). Figure 3 (A)). Furthermore, in semiconductor device 101, at any depth, the fixed charge amount of the second region 132 is set to be approximately the same as that of the first region 131. Therefore, the SJ layer 140 is substantially completely depleted, thereby forming a depletion layer DL0 throughout the SJ layer 140. The electric field distribution in the SJ layer 140 is approximately constant (see [reference]). Figure 3 (B) thus ensures sufficient withstand voltage. However, in this case, due to the balance of positive and negative fixed charges within the SJ layer 140, the depletion layer DL0 has difficulty advancing into the interior of the drift region 12. Because the electric field inside the drift region 12 is low, it may not be possible to sufficiently ensure the withstand voltage of the drift region 12 (see reference). Figure 3 (A), region R0). In other words, in Figure 3 In the electric field distribution ED0 of (B), the shaded area represents the withstand voltage, which is the state with a small area in the drift region 12.

[0038] use Figure 4 This embodiment will explain the effects. In this embodiment, semiconductor device 1 (… Figure 4In the second region 32b, as mentioned above, the concentration of p-type impurities is higher than that of the second region 32a. That is, for the negative fixed charge density at depletion, the lower second region 32b is higher than that of the upper second region 32a. Furthermore, the maximum lower width W2b of the lower second region 32b is larger than the maximum upper width W2a of the upper second region 32a. That is, for the amount of negative fixed charge at depletion, the lower second region 32b is greater than that of the upper second region 32a. Through these effects, compared to the comparative example, the amount of negative fixed charge near the interface IF can be increased (see reference). Figure 4 (Region R1). Near the interface IF of the lower second region 32b, the amount of negative fixed charge can be increased, which can correspondingly promote the progress of the depletion layer DL1 towards the drift region 12 connected to the lower second region 32b (refer to arrow Y1).

[0039] Figure 4 (B) represents the electric field distribution ED1 (solid line) in this embodiment and the electric field distribution ED0 (dashed line) in the comparative example. In the electric field distribution ED1 of this embodiment, the electric field shared by the drift region 12 can be increased compared with the electric field distribution ED0 of the comparative example. In other words, the area within the drift region 12 can make the electric field distribution ED1 larger than the electric field distribution ED0 (reference region R2). Therefore, in the semiconductor device 1 of this embodiment, the withstand voltage of the drift region 12 can be improved.

[0040] Furthermore, in this embodiment, the electric field near the interface IF of the lower second region 32b increases (reference region R3). Therefore, for the electric field inside the SJ layer 14, the electric field distribution ED1 of this embodiment is lower than that of the comparative example (reference region R4). However, in the technology of this embodiment, since it has a structure that only expands the width of the lower second region 32b, the influence on the electric field shared by the upper second region 32a can be reduced. Therefore, the amount of reduction in the electric field inside the SJ layer 14 can be reduced (region R4). Thus, by maintaining a high electric field inside the SJ layer 14 while increasing the electric field shared by the drift region 12, the total area of ​​the electric field distribution ED1 can be further expanded. This increases the withstand voltage of the semiconductor device 1.

[0041] (Manufacturing method of semiconductor device 1) Next, refer to Figures 5-7 The process of forming the SJ layer 14 in the manufacturing method of semiconductor device 1 will be described. Other processes used in manufacturing semiconductor device 1 can utilize known manufacturing techniques.

[0042] First, prepare as n +The drain region 11 is formed on a silicon carbide substrate. Next, using epitaxial growth techniques, an n-type drift region 12 and an epitaxial layer 114 of silicon carbide are grown from the surface of the drain region 11. This completes the process. Figure 5 The structure is shown. Regarding the concentration of n-type impurities, the drift region 12 is lower than that of the epitaxial layer 114. Furthermore, the concentration distribution of n-type impurities along the depth direction (z-direction) is constant in both the drift region 12 and the epitaxial layer 114. This distribution of n-type impurity concentration can be adjusted during the epitaxial growth of the drift region 12 and the epitaxial layer 114, or it can be adjusted using ion implantation technology after epitaxial growth, or it can be adjusted through a combination of these methods.

[0043] Next, as Figure 6 As shown, a mask 42 is formed on the epitaxial layer 114 using known photolithography techniques. The mask 42 is a strip-shaped mask with an opening corresponding to the upper second region 32a. The mask 42 can be a photoresist mask formed of a photoresist, or a hard mask formed of a silicon oxide film, etc.

[0044] Next, as Figure 6 As shown, an ion implantation process is performed. Specifically, p-type impurities are implanted in a multi-stage manner along the depth direction of the epitaxial layer 114 through mask 42. At this time, ion implantation is controlled so that the implantation amount on the lower side of the epitaxial layer 114 is greater than the implantation amount on the upper side. Thus, as... Figure 7 As shown, an SJ layer 14 with multiple lower second regions 32b and multiple upper second regions 32a can be formed.

[0045] Here, a method for forming the width W2b of the lower second region 32b to be larger than the width W2a of the upper second region 32a will be described. Implanted impurity ions have the property of diffusing laterally (in a direction perpendicular to the implantation direction) within the semiconductor substrate. There is a tendency that the greater the amount of impurity ions implanted, the greater this lateral diffusion. Therefore, by making the implantation amount on the lower side of the epitaxial layer 114 greater than the implantation amount on the upper side, the ion diffusion amount on the lower side can be increased. Furthermore, there is a tendency that the longer the range of the impurity ions, the greater the lateral diffusion. Therefore, by performing ion implantation from the same substrate surface, the ion diffusion amount of the lower second region 32b can be increased compared to the ion diffusion amount of the upper second region 32a. Thus, the width W2b can be made larger than the width W2a.

[0046] In the manufacturing method of this embodiment, a single mask 42 can be used to form a lower second region 32b and an upper second region 32a with mutually different widths. Compared to using multiple masks to perform multiple ion implantations according to the width of the regions, this reduces the number of steps and thus lowers manufacturing costs.

[0047] [Second Implementation] (Structure of semiconductor device 201) Figure 8 The semiconductor device 201 represents the second embodiment. Figure 8 It is the same as the first embodiment. Figure 2 The accompanying drawings show the same location. The semiconductor device 201 includes an SJ layer 214. The SJ layer 214 of the second embodiment differs in its first region 31 structure from the SJ layer 14 of the first embodiment. Common reference numerals are used for the same parts in both the first and second embodiments, thus omitting descriptions.

[0048] The first region 31 of the second embodiment includes a lower first region 31b and an upper first region 31a. The lower first region 31b is a region with a lower n-type impurity concentration than the upper first region 31a. The lower first region 31b is in contact with the drift region 12. The upper first region 31a is disposed in contact with the upper surfaces of the lower first region 31b. The lower first region 31b is disposed between lower second regions 32b that are adjacent to each other in the x-direction. The upper first region 31a is disposed between upper second regions 32a that are adjacent to each other in the x-direction.

[0049] The lower first region 31b has a maximum width in the x-direction, i.e., a lower maximum width W1b. In this embodiment, the x-direction width of the lower first region 31b is constant in the depth direction (z-direction). Additionally, the upper first region 31a has a maximum width in the x-direction, i.e., an upper maximum width W1a. In this embodiment, the x-direction width of the upper first region 31a is constant in the depth direction (z-direction). Furthermore, the lower maximum width W1b is smaller than the upper maximum width W1a.

[0050] Figure 8 (B) is a depth-direction distribution diagram of the positive fixed charge when the first region 31 is depleted. The distribution of the positive fixed charge can be obtained, for example, by subtracting the acceptor impurity concentration distribution from the donor impurity concentration distribution. The concentration of n-type impurities in the lower first region 31b is lower than the concentration of n-type impurities in the upper first region 31a. Therefore, as Figure 8 As shown in (B), when the first region 31 is depleted, the density of positive fixed charge in the lower first region 31b is lower than that in the upper first region 31a. Furthermore, there is a boundary BL2 between the lower first region 31b and the upper first region 31a where the amount of positive fixed charge changes drastically.

[0051] (Effect) use Figure 9 The effects of the second embodiment will be explained. Figure 9 It is the same as the first embodiment. Figure 4Same figures. As described above, regarding the positive fixed charge density at depletion, the lower first region 31b is lower than the upper first region 31a. Therefore, compared to the first embodiment, the amount of positive fixed charge near the interface IF can be reduced. (Refer to...) Figure 9 (Region R11).

[0052] Near the interface IF, the amount of positive fixed charge in the lower first region 31b (region R11) can be reduced, and correspondingly, the effect of extending the depletion layer into the drift region 12 can be enhanced by the amount of negative fixed charge in the lower second region 32b (region R1). In other words, the amount of positive fixed charge that balances the amount of negative fixed charge in the lower second region 32b can be increased in the drift region 12 in accordance with the amount reduced in the lower first region 31b. As a result, the extension of the depletion layer into the drift region 12, which is connected to the lower second region 32b, can be further promoted from the depletion layer DL1 to the depletion layer DL2 (refer to arrow Y2).

[0053] (Manufacturing method of SJ layer 214) The manufacturing method of the SJ layer 214 in the second embodiment will be described. Only the differences from the manufacturing method in the first embodiment will be explained. Using epitaxial growth technology, the n-type drift region 12 of silicon carbide and the epitaxial layer 114 are grown from the surface of the drain region 11. At this time, as Figure 10 As shown, the epitaxial layer 114 is formed as a lower epitaxial layer 114b with a relatively low concentration of n-type impurities and an upper epitaxial layer 114a with a relatively high concentration of n-type impurities. The thickness T2 of the lower epitaxial layer 114b is the same as the thickness of the lower first region 31b.

[0054] After that, as Figure 6 As explained, p-type impurities are injected through a mask in 42 stages. This completes the process. Figure 8 The SJ layer 214 of the second embodiment shown.

[0055] [Third Implementation Method] (Structure of semiconductor device 301) Figure 11 Semiconductor device 301, representing the third embodiment. Figure 11 It is the same as the second embodiment. Figure 9 The accompanying drawings are in the same locations. Common parts in both the second and third embodiments are labeled with the same reference numerals, thus omitting descriptions.

[0056] SJ layer 214 has repeating units RU in the x-direction. Each repeating unit RU is defined by a pair of lower first regions 31b and lower second regions 32b. Additionally, drift region 12 has a repeating region 12o contained within the repeating units RU. The repeating region 12o is the region that overlaps with the repeating units RU when SJ layer 214 is viewed vertically upwards (in the +z direction).

[0057] Here, the total amount of positive fixed charge when the repeating region 12o is depleted is defined as the total charge of the repeating region COp. The total amount of positive fixed charge when the lower first region 31b is depleted is defined as the total charge of the first region C1p. The total amount of negative fixed charge when the lower second region 32b is depleted is defined as the total charge of the second region C2n. Thus, the semiconductor device 301 of the third embodiment has the relationship that "the total charge of the second region C2n is the sum of the total charge of the first region C1p and the total charge of the repeating region COp or more".

[0058] (Effect) When a depletion layer is formed, since electrons and holes recombine in a 1:1 ratio, the amount of fixed charge inside the depletion layer is the same on both the positive and negative sides. Therefore, in the third embodiment, the relationship "C2n ≥ C1p + COp" exists. In other words, the amount of negative fixed charge in the lower second region 32b is sufficient to recombine with the positive fixed charge in the lower first region 31b and the overlapping region 12o. Thus, the depletion layer DL3 can be advanced to the interface between the drift region 12 and the drain region 11 (see reference). Figure 11 Since the drift region 12 can be completely depleted, its withstand pressure can be maximized.

[0059] The specific examples of the present invention have been described in detail above, but these are merely illustrative and do not limit the scope of the claims. The technology described in the claims includes technologies obtained by various modifications and alterations to the specific examples described above. Furthermore, the technical elements illustrated in this specification or drawings exert their technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

[0060] (Variation example) The lower second region 32b can have various cross-sectional shapes as long as it has a lower maximum width W2b that is larger than the upper maximum width W2a. Figure 12Examples of various cross-sectional shapes for the lower second region 32b are shown below. As shown in lower second region 32b_1, the cross-sectional shape can be such that the width in the x-direction increases as the depth increases, reaching its maximum width W2b at the bottom surface. As shown in lower second region 32b_2, the cross-sectional shape can be such that the width in the x-direction increases as the depth increases, reaching its maximum width W2b at the top surface. As shown in lower second region 32b_3, the width in the x-direction can increase linearly from the top surface towards the middle point, reaching its maximum width W2b at the middle point, and then decrease linearly from the middle point towards the bottom surface. Alternatively, as shown in lower second region 32b_4, the width in the x-direction can increase curvilinearly from the top surface towards the middle point, reaching its maximum width W2b at the middle point, and then decrease curvilinearly from the middle point towards the bottom surface.

[0061] The SJ layer 14 in this specification is not limited to MOSFETs, but can be applied to various device structures such as diodes. Furthermore, the SJ layer 14 in this specification is not limited to trench gate structures, but can be applied to various gate structures such as planar gate structures.

[0062] In the manufacturing method of SJ layer 14 in this specification, the implantation steps of donor impurities and acceptor impurities can also be reversed. That is, n-type impurities can be ion implanted into the p-type epitaxial layer 114 via a mask.

[0063] This specification describes the case where the first conductivity type is n-type and the second conductivity type is p-type, but the reverse is also possible. That is, in Figure 1 In the semiconductor device 1, the n and p components can also be interchanged.

[0064] The SJ structure described in this specification is not limited to a strip shape and various shapes can be used. For example, when viewed from above the semiconductor substrate 10, multiple n-type columns and multiple p-type columns can be arranged in a lattice pattern.

[0065] The material of the semiconductor substrate 10 is not limited to silicon carbide, and various materials can be used. For example, it can also be silicon, various wide-bandgap semiconductors (e.g., gallium nitride, gallium oxide, etc.).

[0066] The following describes the methods of this technology.

[0067] [Method 1] A semiconductor device, have: The first conductivity type of voltage-resistant retaining layer; and The superjunction layer is grounded to the upper surface of the withstand voltage layer, and alternately and repeatedly arranged along a first direction with a first region of a first conductivity type and a second region of a second conductivity type. The second region includes a lower second region in contact with the pressure-resistant retaining layer and an upper second region disposed in contact with the upper surface of the lower second region. The lower second region has the maximum width in the first direction, i.e., the maximum width on the lower side. The upper second region has the maximum width in the first direction, i.e., the maximum width on the upper side. The maximum width of the lower side is greater than the maximum width of the upper side. The lower second region has a higher density of fixed charge at depletion than the upper second region.

[0068] [Method 2] The semiconductor device according to method 1 The concentration of the second conductive impurity contained in the lower second region is higher than the concentration of the second conductive impurity contained in the upper second region.

[0069] [Method 3] The semiconductor device according to method 1 or 2 The width of the first direction at the interface between the lower second region and the pressure-resistant retaining layer is the maximum width of the lower side.

[0070] [Method 4] The semiconductor device according to any one of methods 1 to 3, The first region includes a lower first region that is in contact with the pressure-resistant retaining layer and an upper first region that is grounded to the upper surface of the lower first region. The lower first region is disposed between the lower second regions that are adjacent to each other in the first direction. The upper first region is disposed between the upper second regions that are adjacent to each other in the first direction. The lower first region has a lower density of fixed charge at depletion than the upper first region.

[0071] [Method 5] The semiconductor device according to method 4 When viewed from a vertically upward perspective, the pressure-resistant retaining layer has an overlapping region that overlaps with the lower first region and the lower second region. The total amount of fixed charge when the overlapping region is depleted is set as the total charge of the overlapping region. The total amount of fixed charge when the lower first region is depleted is set as the total charge of the first region. When the total fixed charge at the point of depletion of the lower second region is set as the total charge of the second region, The total charge in the second region is greater than or equal to the sum of the total charge in the first region and the total charge in the overlapping region.

[0072] [Method 6] The semiconductor device according to any one of methods 1 to 5, The first conductivity type is n-type, and the second conductivity type is p-type.

[0073] [Method 7] A semiconductor device, have: The first conductivity type of voltage-resistant retaining layer; and The superjunction layer is grounded to the upper surface of the withstand voltage layer, and alternately and repeatedly arranged along a first direction with a first region of a first conductivity type and a second region of a second conductivity type. The second region includes a lower second region in contact with the pressure-resistant retaining layer and an upper second region disposed in contact with the upper surface of the lower second region. The lower second region has the maximum width in the first direction, i.e., the maximum width on the lower side. The upper second region has the maximum width in the first direction, i.e., the maximum width on the upper side. The maximum width of the lower side is greater than the maximum width of the upper side. The concentration of the second conductive impurity contained in the lower second region is higher than the concentration of the second conductive impurity contained in the upper second region.

[0074] According to the structure of Method 2, corresponding to the increase in the concentration of the second type of conductive impurity in the lower second region, the progress of the depletion layer toward the voltage-holding layer connected to the lower second region can be promoted. This can improve the voltage withstand capability of the voltage-holding layer.

[0075] According to the structure of method 3, at the pn junction interface between the lower second region and the voltage-resistant retaining layer, the density of the fixed charge at depletion can be made higher in the lower second region than in the upper second region.

[0076] According to the structure of method 4, the amount of fixed charge in the lower first region can be reduced, and correspondingly, the effect of extending the depletion layer to the pressure-resistant retention layer can be improved by increasing the amount of fixed charge in the lower second region.

[0077] According to the structure of method 5, the fixed charge amount in the lower second region can be set to a sufficient amount to combine with the fixed charge amounts in the lower first region and the repeating region. Thus, the depletion layer can extend to the entire voltage-holding layer. By completely depleting the voltage-holding layer, the voltage resistance of the voltage-holding layer can be maximized.

Claims

1. A semiconductor device, characterized in that, have: The first conductivity type of voltage-resistant retaining layer; and The superjunction layer is grounded to the upper surface of the withstand voltage layer, and alternately and repeatedly arranged along a first direction with a first region of a first conductivity type and a second region of a second conductivity type. The second region includes a lower second region in contact with the pressure-resistant retaining layer and an upper second region disposed in contact with the upper surface of the lower second region. The lower second region has the maximum width in the first direction, i.e., the maximum width on the lower side. The upper second region has the maximum width in the first direction, i.e., the maximum width on the upper side. The maximum width of the lower side is greater than the maximum width of the upper side. The lower second region has a higher density of fixed charge at depletion than the upper second region.

2. The semiconductor device according to claim 1, characterized in that, The concentration of the second conductive impurity contained in the lower second region is higher than the concentration of the second conductive impurity contained in the upper second region.

3. The semiconductor device according to claim 1, characterized in that, The width of the first direction at the interface between the lower second region and the pressure-resistant retaining layer is the maximum width of the lower side.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first region includes a lower first region that is in contact with the pressure-resistant retaining layer and an upper first region that is grounded to the upper surface of the lower first region. The lower first region is disposed between the lower second regions that are adjacent to each other in the first direction. The upper first region is disposed between the upper second regions that are adjacent to each other in the first direction. The lower first region has a lower density of fixed charge at depletion than the upper first region.

5. The semiconductor device according to claim 4, characterized in that, When viewed from a vertically upward perspective, the pressure-resistant retaining layer has an overlapping region that overlaps with the lower first region and the lower second region. The total amount of fixed charge when the overlapping region is depleted is set as the total charge of the overlapping region. The total amount of fixed charge when the lower first region is depleted is set as the total charge of the first region. When the total fixed charge at the point of depletion of the lower second region is set as the total charge of the second region, The total charge in the second region is greater than or equal to the sum of the total charge in the first region and the total charge in the overlapping region.

6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first conductivity type is n-type, and the second conductivity type is p-type.

7. A semiconductor device, characterized in that, have: The first conductivity type of voltage-resistant retaining layer; and The superjunction layer is grounded to the upper surface of the withstand voltage layer, and alternately and repeatedly arranged along a first direction with a first region of a first conductivity type and a second region of a second conductivity type. The second region includes a lower second region in contact with the pressure-resistant retaining layer and an upper second region disposed in contact with the upper surface of the lower second region. The lower second region has the maximum width in the first direction, i.e., the maximum width on the lower side. The upper second region has the maximum width in the first direction, i.e., the maximum width on the upper side. The maximum width of the lower side is greater than the maximum width of the upper side. The concentration of the second conductive impurity contained in the lower second region is higher than the concentration of the second conductive impurity contained in the upper second region.

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