Gate-all-around field effect transistor and manufacturing method thereof

Abstract

The invention relates to a gate-all-around field effect transistor and a manufacturing method thereof.The gate-all-around field effect transistor comprises a substrate, a gate and a gate oxide layer, the substrate comprises a body and a silicon column which are connected with each other, and the silicon column protrudes out of the body; the silicon column comprises a conducting channel region, a source region and a drain region, the source region and the drain region are formed on the two sides of the conducting channel region respectively, the conducting channel region is arranged between the source region and the drain region, a conducting channel is formed in the conducting channel region, a recess or a protrusion is formed in the outer surface of the conducting channel region, and the grid electrode is arranged in the circumferential direction of the conducting channel region. And the gate oxide layer is arranged between the gate electrode and the conductive channel region in a surrounding manner, and the shape of the gate oxide layer is matched with that of the outer surface of the conductive channel region. By increasing the contact area between the grid electrode and the conducting channel region, the current driving capability of the device can be improved, the contact resistance can be reduced, the voltage drop can be reduced, and the purposes of improving the switching speed and the working efficiency of the transistor can be achieved.

Description

Technical Field

[0001] This disclosure relates to the field of field-effect transistor technology, and more specifically, to a fully all-around gate field-effect transistor and a method for fabricating the same. Background Technology

[0002] With the continuous advancement of semiconductor process technology, planar transistors have gradually been upgraded to Gate all around (GAA) field-effect transistors, which improve the control capability of conductive channels by completely surrounding the conductive channel under the gate.

[0003] However, traditional all-around gate field-effect transistors still have shortcomings in gate control, which limits device performance. Summary of the Invention

[0004] The purpose of this disclosure is to provide a fully all-around gate field-effect transistor and a method for fabricating the same, in order to solve the technical problems existing in the related art.

[0005] To achieve the above objectives, a first aspect of this disclosure provides a fully all-around gate field-effect transistor, including a substrate, a gate, and a gate oxide layer, wherein the substrate includes an interconnected body and silicon pillars, the silicon pillars being disposed protruding from the body; The silicon pillar includes a conductive channel region and a source region and a drain region formed on both sides of the conductive channel region, respectively. The conductive channel region is disposed between the source region and the drain region, and a conductive channel is disposed within the conductive channel region. The outer surface of the conductive channel region has depressions or protrusions; The gate is arranged circumferentially around the conductive channel region and is attached to the outer wall of the conductive channel region; The gate oxide layer is disposed around the gate and the conductive channel region, and the shape of the gate oxide layer matches the outer surface of the conductive channel region.

[0006] Optionally, the conductive channel region includes a columnar portion and an annular portion, wherein the annular portion is circumferentially arranged around the columnar portion.

[0007] Optionally, there are multiple annular portions, and the multiple annular portions are spaced apart along the length direction of the silicon pillar.

[0008] Optionally, the columnar portion and the annular portion are integrally formed.

[0009] Optionally, the all-around gate field-effect transistor further includes a first silicon dioxide layer and a second silicon dioxide layer, wherein the first silicon dioxide layer is deposited on the side of the gate close to the body, and the second silicon dioxide layer is deposited on the side of the gate away from the body.

[0010] A second aspect of this disclosure provides a method for fabricating a fully all-around gate field-effect transistor as described above, comprising: The silicon pillar is deposited on the body, the silicon pillar including a conductive channel region and a source region and a drain region respectively formed on both sides of the conductive channel region, and the outer surface of the conductive channel region is formed with a depression or a protrusion. The gate oxide layer is deposited on the outer surface of the conductive channel region; Along the length of the silicon pillar, a first silicon dioxide layer, a gate, and a second silicon dioxide layer are deposited sequentially.

[0011] Optionally, before depositing the silicon pillar on the body, a first layer of silicon dioxide, a silicon nitride layer, and a second layer of silicon dioxide are deposited sequentially on the body; Photolithography and / or photoetching are performed to form vias that sequentially penetrate the first silicon dioxide layer, the silicon nitride layer, and the second silicon dioxide layer, with the silicon pillars deposited within the vias.

[0012] Optionally, forming a depression or protrusion on the outer surface of the conductive channel region includes: The silicon nitride layer is etched back inside the via so that the inner diameter of the via formed on the silicon nitride layer is larger than the inner diameter of the via formed in the first silicon dioxide layer and the second silicon dioxide layer. Silicon seed crystals are deposited in the through-holes, and then silicon is epitaxially grown to form the silicon pillars.

[0013] Optionally, the first silicon dioxide layer, the silicon nitride layer, and the second silicon dioxide layer are removed, and a replacement gate oxide is deposited on the periphery of the conductive channel region and the source region, and doping is performed on the drain region. After doping is completed, the replacement gate oxide is removed.

[0014] Optionally, after depositing the first silicon dioxide layer along the length direction of the silicon pillar, the gate oxide layer is deposited on the outer surface of the silicon pillar located above the first silicon dioxide layer; After depositing the gate over the first silicon dioxide layer along the length direction of the silicon pillar, the gate oxide layer above the gate is removed and doped. A second silicon dioxide layer is deposited over the gate along the length of the silicon pillar.

[0015] Through the above technical solution, since the outer surface of the conductive channel region has depressions or protrusions, the contact area between the gate and the outer surface of the conductive channel region can be increased when the gate is in contact with the outer surface of the conductive channel region. On the one hand, a larger contact area means that more charge carriers can flow from the source region (source) to the drain region (drain), thereby improving the device's drive current capability. On the other hand, contact resistance is one of the important factors affecting transistor performance. Increasing the contact area can effectively reduce contact resistance, reduce voltage drop, and improve the switching speed and operating efficiency of the transistor. In addition, with the advancement of semiconductor technology, device size is constantly shrinking. It is precisely because of the increased contact area between the gate and the conductive channel region that the problem of increased contact resistance caused by size reduction can be overcome, which is conducive to further improving the chip integration.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a cross-sectional schematic diagram of a fully all-around gate field-effect transistor provided in an exemplary embodiment of this disclosure; meanwhile, Figure 1 This is also a cross-sectional diagram after step S208 is completed in the manufacturing method; Figure 2 This is a cross-sectional schematic diagram of a fully all-around gate field-effect transistor provided in another exemplary embodiment of this disclosure; meanwhile, Figure 2 This is also a cross-sectional diagram after step S208 is completed in the manufacturing method; Figure 3 This is a schematic flowchart of a method for fabricating a fully all-around gate field-effect transistor according to an exemplary embodiment of the present disclosure; Figure 4 This is a schematic flowchart of a method for fabricating a fully all-around gate field-effect transistor according to another exemplary embodiment of this disclosure; Figure 5 This is a cross-sectional schematic diagram after step S201 is completed in the fabrication method of a fully all-around gate field-effect transistor provided in an exemplary embodiment of this disclosure; Figure 6 This is a cross-sectional schematic diagram after step S202 is completed in the fabrication method of a fully all-around gate field-effect transistor provided in an exemplary embodiment of this disclosure; Figure 7This is a cross-sectional schematic diagram after step S203 is completed in the fabrication method of a fully all-around gate field-effect transistor provided in an exemplary embodiment of this disclosure; Figure 8 This is a cross-sectional schematic diagram after step S204 is completed in the fabrication method of a fully all-around gate field-effect transistor provided in an exemplary embodiment of this disclosure; Figure 9 , Figure 10 This is a cross-sectional schematic diagram after step S205 is completed in the fabrication method of a fully all-around gate field-effect transistor provided in an exemplary embodiment of this disclosure. Figure 11 This is a cross-sectional schematic diagram after step S206 is completed in the fabrication method of a fully all-around gate field-effect transistor provided in an exemplary embodiment of this disclosure. Figure 12 This is a cross-sectional schematic diagram after step S207 is completed in the fabrication method of a fully all-around gate field-effect transistor provided in an exemplary embodiment of this disclosure.

[0018] Explanation of reference numerals in the attached figures 10-Substrate; 11-Body; 12-Silicon pillar; 120-Conductive channel region; 121-Conductive channel; 122-Pillar portion; 123-Annular portion; 124-Source region; 125-Drain region; 20-Gate; 30-Gate oxide layer; 40-First silicon dioxide layer; 50-Second silicon dioxide layer; 60-Through hole; 70-First silicon dioxide layer; 80-Silicon nitride layer; 90-Second silicon dioxide layer; 100-Replacement gate oxide. Detailed Implementation

[0019] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0020] In this disclosure, unless otherwise stated, directional terms such as "up," "down," "left," and "right" are used to indicate orientation or positional relationships only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or a specific orientation structure and operation, and therefore should not be construed as a limitation of this disclosure. The terms "inner" and "outer" refer to the inner and outer contours of the corresponding structures.

[0021] Additionally, it should be noted that the terms used, such as "first" and "second," are used to distinguish one element from another and do not indicate sequence or importance. Furthermore, in the description referring to the accompanying drawings, the same reference numerals in different drawings denote the same element.

[0022] In the description of this disclosure, it should also be noted that, unless otherwise expressly specified and limited, the terms "set up," "connect," "link," and "install" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0023] refer to Figure 1 , Figure 2 As shown, the first aspect of this disclosure provides a fully all-around gate field-effect transistor, including a substrate 10, a gate 20, and a gate oxide layer 30. The substrate 10 includes a body 11 and a silicon pillar 12 interconnected. The silicon pillar 12 protrudes from the body 11 and includes a conductive channel region 120 and a source region 124 and a drain region 125 formed on both sides of the conductive channel region 120, respectively. The conductive channel region 120 is disposed between the source region 124 and the drain region 125. A conductive channel 121 is disposed within the conductive channel region 120. A depression or protrusion is formed on the outer surface of the conductive channel region 120. The gate 20 is disposed circumferentially around the conductive channel region 120 and is attached to the outer wall of the conductive channel region 120. The gate oxide layer 30 is disposed around the gate 20 and the conductive channel region 120, and the shape of the gate oxide layer 30 matches the outer surface of the conductive channel region 120.

[0024] Through the above technical solution, since the outer surface of the conductive channel region 120 has depressions or protrusions, when the gate 20 is in contact with the outer surface of the conductive channel region 120, the contact area between the gate 20 and the outer surface of the conductive channel region 120 can be increased. On the one hand, a larger contact area means that more charge carriers can flow from the source region 124 (source) to the drain region 125 (drain), thereby improving the driving current capability of the device. On the other hand, contact resistance is one of the important factors affecting transistor performance. Increasing the contact area can effectively reduce contact resistance, reduce voltage drop, and improve the switching speed and operating efficiency of the transistor. In addition, with the advancement of semiconductor technology, device size is constantly shrinking. It is precisely because of the increased contact area between the gate 20 and the conductive channel region 120 that the problem of increased contact resistance caused by size reduction can also be overcome, which is conducive to further improving the integration of the chip.

[0025] This disclosure does not limit the specific shape or form of the depressions or protrusions formed on the outer surface of the conductive channel region 120, as long as they can increase the area of ​​the outer surface of the conductive channel region 120, thereby increasing the contact area between the conductive channel region 120 and the gate 20. For example, in an exemplary embodiment provided in this disclosure, such as... Figure 1 , Figure 2As shown, the conductive channel region 120 may include a columnar portion 122 and an annular portion 123, with the annular portion 123 circumferentially surrounding the columnar portion 122. That is, the annular portion protrudes from the outer surface of the conductive channel region 120. Thus, when bonded to the gate 20 / gate 20 oxide layer, the annular portion 123 protruding from the columnar portion 122 has a front facing the gate 20 / gate 20 oxide layer and two opposite sides arranged on either side of the front, thereby increasing the contact area with the gate 20 and improving the switching speed and operating efficiency of the transistor.

[0026] In order to further increase the outer surface area of ​​the aforementioned conductive channel region 120, in this disclosure, such as Figure 2 As shown, there are multiple annular portions 123, which are spaced apart along the length of the silicon pillar 12. Thus, when the gate 20 surrounds and adheres to the outer wall of the conductive channel region 120, the multiple annular portions 123 protruding from the pillar portions 122 make the structure of the outer wall of the conductive channel region 120 more complex, thereby further increasing the external area of ​​the conductive channel region 120 and further increasing the corresponding adhesion area between the conductive channel region 120 and the gate 20.

[0027] The cross-sectional shape of the aforementioned annular portion 123 can be rectangular, triangular, or arc-shaped, and this disclosure does not impose any restrictions on it.

[0028] Alternatively, in other embodiments provided in this disclosure, the conductive channel region 120 may also include a columnar portion 122 and a plurality of protrusions, one end of each protrusion being connected to the columnar portion 122, and the other end of each protrusion extending in a direction away from the columnar portion 122 and protruding out of the columnar portion 122, thereby also achieving the purpose of increasing the contact area between the two.

[0029] Optionally, such as Figure 1 , Figure 2 As shown, the columnar portion 122 and the annular portion 123 can be integrally formed. On the one hand, the integral forming arrangement reduces the interface between different materials, thereby reducing parasitic capacitance and resistance, and improving the response speed and frequency characteristics of the device. On the other hand, the integral forming arrangement also reduces multiple independent manufacturing steps, simplifies the process steps and material handling, can improve manufacturing efficiency, shorten the production cycle, and moreover, can more evenly distribute heat, reduce local hot spots, and improve the stability and reliability of the device.

[0030] It should be noted that the aforementioned conductive channels 121 are formed in both the columnar portion 122 and the annular portion 123, thereby increasing the number of conductive channels 121 in the conductive channel region 120. More channels can provide more current paths, thereby improving the current carrying capacity of the device. At the same time, more parallel channels can reduce the current density of a single channel, thereby reducing power consumption and improving the efficiency of the transistor.

[0031] Optionally, such as Figure 1 , Figure 2 As shown, the all-around gate field-effect transistor may further include a first silicon dioxide layer 40 and a second silicon dioxide layer 50. The first silicon dioxide layer 40 is deposited on the side of the gate 20 closest to the body 11, and the second silicon dioxide layer 50 is deposited on the side of the gate 20 away from the body 11. The first silicon dioxide layer 40 on the side of the gate 20 closest to the body 11 can serve as a physical barrier between the gate 20 and the drain region 125 (drain), and the second silicon dioxide layer 50 on the side of the gate 20 away from the body 11 can serve as a physical barrier between the gate 20 and the source region 124 (source), preventing direct current flow when no voltage is applied to the gate 20, i.e., preventing the occurrence of a "short circuit," which helps protect the normal operation of the transistor or other devices.

[0032] Thus, when a voltage is applied to the gate 20, an electric field is generated between the first silicon dioxide layer 40 and the second silicon dioxide layer 50. This electric field affects the semiconductor region (conductive channel region 120) near the gate 20, changing the conductivity of the region and thereby controlling the current flow from the source to the drain.

[0033] like Figure 3 As shown, a second aspect of this disclosure provides a method for fabricating the above-described all-around gate field-effect transistor, comprising: S101. Deposit silicon pillars 12 on the body 11. The silicon pillars 12 include a conductive channel region 120 and a source region 124 and a drain region 125 formed on both sides of the conductive channel region 120, and make the outer surface of the conductive channel region 120 form a depression or a protrusion. S102. Deposit the gate oxide layer 30 on the outer surface of the conductive channel region 120; S103. Along the length of the silicon pillar 12, a first silicon dioxide layer 40, a gate 20, and a second silicon dioxide layer 50 are deposited sequentially.

[0034] Through the above technical solution, since the outer surface of the conductive channel region 120 has depressions or protrusions, when the gate 20 is in contact with the outer surface of the conductive channel region 120, the contact area between the gate 20 and the outer surface of the conductive channel region 120 can be increased. On the one hand, a larger contact area means that more charge carriers can flow from the source region 124 (source) to the drain region 125 (drain), thereby improving the driving current capability of the device. On the other hand, contact resistance is one of the important factors affecting transistor performance. Increasing the contact area can effectively reduce contact resistance, reduce voltage drop, and improve the switching speed and operating efficiency of the transistor. In addition, with the advancement of semiconductor technology, device size is constantly shrinking. It is precisely because of the increased contact area between the gate 20 and the conductive channel region 120 that the problem of increased contact resistance caused by size reduction can also be overcome, which is conducive to further improving the integration of the chip.

[0035] like Figures 4 to 12 As shown, according to an embodiment of this disclosure, another method for fabricating a metal layer capacitor is also provided, including: like Figure 5 As shown, in S201, a first layer of silicon dioxide 70, a silicon nitride layer 80, and a second layer of silicon dioxide 90 are sequentially deposited on the body 11. like Figure 6 As shown, in S202, photolithography and / or photoetching operations are performed to form a through-hole 60 that sequentially penetrates the first silicon dioxide layer 70, the silicon nitride layer 80, and the second silicon dioxide layer 90, with silicon pillars 12 deposited in the through-hole 60. like Figure 7 As shown, S203, forming a depression or protrusion on the outer surface of the conductive channel region 120 includes: The silicon nitride layer 80 is etched back inside the via 60 so that the inner diameter of the via 60 formed on the silicon nitride layer 80 is larger than the inner diameter of the via 60 formed on the first silicon dioxide layer 70 and the second silicon dioxide layer 90. In other words, the inner diameter of the via 60 located on the silicon nitride layer 80 can be enlarged by the back etching method, so that when the silicon pillar 12 is subsequently deposited to fill the via 60, a silicon pillar 12 with small size at both ends and large size in the middle can be obtained, thereby increasing the contact area between the silicon pillar 12 and the gate 20.

[0036] S204. A silicon seed crystal is deposited inside the through-hole 60, and then silicon is epitaxially grown to form a silicon pillar 12, as detailed below. Figure 8 As shown.

[0037] S205, remove the first silicon dioxide layer 70, the silicon nitride layer 80, and the second silicon dioxide layer 90, and deposit a replacement gate oxide 100 on the outer periphery of the conductive channel region 120 and the source region 124, and perform doping on the drain region 125. After doping, remove the replacement gate oxide 100; specifically as follows... Figure 9 , Figure 10 As shown, since a substitute gate oxide 100 is deposited on the outer periphery of the conductive channel region 120 and the source region 124, it is equivalent to performing a doping process on the drain region 125. By replacing the gate oxide 100, the drain is isolated from the source and gate 20, preventing the dopant from diffusing to the source and gate 20. The doping process is precisely controlled to prevent the dopant from depositing in areas where doping is not required, thereby ensuring the manufacturing quality and performance of the transistor.

[0038] S206. After depositing a first silicon dioxide layer 40 along the length of the silicon pillar 12, a gate oxide layer 30 is deposited on the outer surface of the silicon pillar 12 above the first silicon dioxide layer 40. That is, the gate oxide layer 30 is deposited on the outer surface of the conductive channel region 120 and the source region 124, and then the gate oxide layer 30 is deposited on the outer periphery of the gate oxide layer 30. (Reference) Figure 11 As shown, the gate oxide layer 30 deposited on the outer periphery of the conductive channel region 120 can isolate the gate 20 from the conductive channel 121, preventing direct conduction between the gate 20 and the conductive channel 121. This helps improve the insulation performance of the device and reduce leakage current. Furthermore, the gate oxide layer 30, together with the gate 20 and the conductive channel 121, forms a capacitor (gate capacitor). When a voltage is applied to the gate 20, this capacitor can store charge, thereby affecting the charge distribution in the conductive channel 121 and thus controlling the conductivity state of the transistor.

[0039] S207. After depositing the gate 20 above the first silicon dioxide layer 40 along the length direction of the silicon pillar 12, the gate oxide layer 30 located above the gate 20 is removed and doped; Reference Figure 12 As shown, after the gate 20 is deposited on the first silicon dioxide layer 40, the gate 20 can wrap around and cover part of the gate oxide layer 30 located inside the gate 20, that is, cover the gate oxide layer 30 wrapped around the outer periphery of the conductive channel region 120. Then, the gate oxide layer 30 located above the gate 20 is removed and doped. The gate 20 can achieve isolation between the conductive channel region 120 and the source, avoiding the problem that the dopant material diffuses into the gate 20 during the doping process of the source, which would affect the manufacturing quality and performance of the transistor.

[0040] In this disclosure, silicon gate 20 material can be grown or deposited directly on substrate 10 using in-situ silicon gate technology.

[0041] In one exemplary embodiment provided in this supply, the gate oxide layer 30 may be made of an HK metal gate (high dielectric constant metal gate, such as HfO2), a work function metal layer (such as TiAlN), and a metal gate (such as tungsten). Alternatively, in other embodiments provided in this disclosure, the gate oxide layer may also be made of a polysilicon gate (SiON as gate oxide + polysilicon as gate).

[0042] S208. A second silicon dioxide layer 50 is deposited above the gate 20 along the length direction of the silicon pillar 12. (Reference) Figure 1 , Figure 2 As shown, at this time, the second silicon dioxide layer 50 can protect and insulate the source located above the gate 20, thereby effectively isolating the source from other regions (such as the drain and gate 20) and preventing leakage current and short circuit. In addition, the second silicon dioxide layer 50 can also serve as a diffusion barrier to prevent impurities or dopants in the source material from diffusing to other regions during high-temperature processing, thus maintaining the electrical characteristics of the source.

[0043] It should be noted that the replacement gate oxide 100 can be removed by wet etching, dry etching or chemical mechanical polishing, and this disclosure does not limit this process.

[0044] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0045] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0046] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A fully all-around gate field-effect transistor, characterized in that, The device includes a substrate, a gate, and a gate oxide layer. The substrate includes an interconnected body and silicon pillars, with the silicon pillars protruding from the body. The silicon pillar includes a conductive channel region and a source region and a drain region formed on both sides of the conductive channel region, respectively. The conductive channel region is disposed between the source region and the drain region, and a conductive channel is disposed within the conductive channel region. The outer surface of the conductive channel region has depressions or protrusions; The gate is arranged circumferentially around the conductive channel region and is attached to the outer wall of the conductive channel region; The gate oxide layer is disposed around the gate and the conductive channel region, and the shape of the gate oxide layer matches the outer surface of the conductive channel region.

2. The all-around gate field-effect transistor according to claim 1, characterized in that, The conductive channel region includes a columnar portion and an annular portion, wherein the annular portion is arranged circumferentially around the columnar portion.

3. The all-around gate field-effect transistor according to claim 2, characterized in that, The annular portion is multiple, and the multiple annular portions are spaced apart along the length direction of the silicon pillar.

4. The all-around gate field-effect transistor according to claim 2, characterized in that, The columnar portion and the annular portion are integrally formed.

5. The all-around gate field-effect transistor according to any one of claims 1-4, characterized in that, The all-around gate field-effect transistor further includes a first silicon dioxide layer and a second silicon dioxide layer, wherein the first silicon dioxide layer is deposited on the side of the gate close to the body, and the second silicon dioxide layer is deposited on the side of the gate away from the body.

6. A method for fabricating a fully all-around gate field-effect transistor according to any one of claims 1-5, characterized in that, include: The silicon pillar is deposited on the body, the silicon pillar including a conductive channel region and a source region and a drain region respectively formed on both sides of the conductive channel region, and the outer surface of the conductive channel region is formed with a depression or a protrusion. The gate oxide layer is deposited on the outer surface of the conductive channel region; Along the length of the silicon pillar, a first silicon dioxide layer, a gate, and a second silicon dioxide layer are deposited sequentially.

7. The method according to claim 6, characterized in that, Before depositing the silicon pillar on the substrate, a first layer of silicon dioxide, a silicon nitride layer, and a second layer of silicon dioxide are sequentially deposited on the substrate; Photolithography and / or photoetching are performed to form vias that sequentially penetrate the first silicon dioxide layer, the silicon nitride layer, and the second silicon dioxide layer, with the silicon pillars deposited within the vias.

8. The method according to claim 7, characterized in that, The method of forming a depression or protrusion on the outer surface of the conductive channel region includes: The silicon nitride layer is etched back inside the via so that the inner diameter of the via formed on the silicon nitride layer is larger than the inner diameter of the via formed on the first silicon dioxide layer and the second silicon dioxide layer. Silicon seed crystals are deposited in the through-holes, and then silicon is epitaxially grown to form the silicon pillars.

9. The method according to claim 8, characterized in that, The first silicon dioxide layer, the silicon nitride layer, and the second silicon dioxide layer are removed, and a replacement gate oxide is deposited on the periphery of the conductive channel region and the source region. The drain region is then doped. After doping is completed, the replacement gate oxide is removed.

10. The method according to claim 6, characterized in that, After depositing the first silicon dioxide layer along the length direction of the silicon pillar, the gate oxide layer is deposited on the outer surface of the silicon pillar located above the first silicon dioxide layer; After depositing the gate over the first silicon dioxide layer along the length direction of the silicon pillar, the gate oxide layer above the gate is removed and doped. A second silicon dioxide layer is deposited over the gate along the length of the silicon pillar.

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