Novel ScAlN semiconductor material with extremely high hole mobility and preparation method and application thereof

Abstract

The invention relates to a novel ScAlN semiconductor material with extremely high hole mobility and a preparation method and application thereof, the material has an ScAlN digital alloy structure and is formed by periodically and alternately stacking basic repetitive units (ScN) m / (AlN) n along an epitaxial growth direction; wherein (ScN) m represents ScN of m atomic layers, and (AlN) n represents AlN of n atomic layers; the value of m is 3 or 5, and the value of n is 1; the number of repetition cycles of the basic repetition units is x, and x is a natural number larger than or equal to 1. According to the structure, the unique octahedral coordination tendency of Sc atoms is utilized, the number of ScN layers and sorting are periodically introduced and limited in AlN crystal lattices, local symmetric breaking and hybrid orbit reconstruction are induced to occur in the crystal lattices, valence band top electron state distribution is remodeled while a wide band gap is kept, and the hole mobility is improved; the structure can be applied to an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device with an enhanced p-channel vertical trench gate structure and a p-type GaN power diode device based on an AlN substrate through a pulse growth mode of a periodic switch specific MO source of an MOCVD (Metal-Organic Chemical Vapor Deposition) process.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor material preparation technology, and particularly relates to a novel ScAlN semiconductor material with extremely high hole mobility, its preparation method and application. Background Technology

[0002] As a representative of third-generation semiconductor materials, nitride semiconductors play a decisive supporting and driving role in optoelectronics, radio frequency, and power electronics fields due to their excellent properties such as wide bandgap, high breakdown electric field, high thermal conductivity, and high electron saturation drift velocity. Carrier mobility is a very important physical parameter in nitride semiconductor materials, which directly affects the performance of the material in electronic devices. For example, in high-frequency and radio frequency devices, improving carrier mobility can significantly increase the operating frequency of the device, thereby meeting the needs of the modern integrated circuit industry for high-frequency signal processing; in power devices, high mobility helps to reduce conduction losses and switching losses, thereby improving the overall device performance.

[0003] Typically, nitride semiconductors exhibit excellent electron mobility, but their hole mobility is significantly low. For example, the electron mobility of GaN bulk materials at room temperature is usually between 1000 and 1200 cm⁻¹. 2 / Vs, while the hole mobility at room temperature is only 10-20 cm. 2 / Vs; InN materials, possessing the highest electron mobility among nitrides, achieve an electron mobility of up to 3200 cm⁻¹ at room temperature. 2 / Vs or more, but its hole mobility is less than 30 cm. 2 / Vs, while for the currently popular semiconductor AlN, its hole mobility is less than 10 cm⁻¹. 2 The / Vs ratio results in generally poor performance for p-type channel nitride electronic devices that use holes as charge carriers, significantly lower than that of n-type channel devices that use electrons. Driven by the strong demand for pn-complementary power electronics and digital logic applications, improving p-type carrier mobility and conductivity has become a core challenge in the research and development of nitride semiconductor materials. In particular, maintaining high hole mobility while ensuring wide bandgap semiconductor characteristics is a highly competitive area for patents in both industry and academia.

[0004] For nitride semiconductors such as GaN and AlN, the fundamental reason for the low hole mobility mainly stems from the fact that the highly electronegative nitrogen element under sp3 hybridization tends to localize holes, resulting in a very high effective hole mass near the valence band apex and a very low hole mobility. Therefore, the fundamental solution to the low hole mobility of nitride semiconductors lies in changing the crystal structure and thus altering the tetrahedral sp3 hybridization, thereby reducing the effective hole mass near the valence band apex. To address the low hole mobility problem in nitride semiconductors, current mainstream technical solutions mainly fall into two categories: (1) Two-dimensional hole gas (2DHG) is generated at the interface of GaN / AlGaN (SHAO P, FAN X, LI S, et al. High density polarization-induced 2D hole gas enabled by elevating Al composition in GaN / AlGaN heterostructures[J / OL]. Applied Physics Letters, 2023, 122(14):142102.) or GaN / AlN (Chaudhuri R, Bader SJ, Chen Z, et al. A polarization-induced 2D hole gas in undoped gallium nitride quantum wells[J]. Science,2019, 365(6460): 1454-1457.). Group III nitride materials exhibit spontaneous polarization and piezoelectric polarization effects. At the GaN / AlGaN or GaN / AlN heterojunction interface, due to polarization discontinuity, a negatively charged fixed charge is generated. To maintain charge neutrality, holes in the valence band are attracted to the interface potential well, forming a 2DHG. Since it still belongs to the AlN / GaN nitride system, this approach does not solve the problem of low mobility due to the large effective mass of holes at the valence band top. Furthermore, due to interface scattering introduced by the GaN / AlGaN or GaN / AlN heterojunction, the hole mobility of the 2DHG at room temperature (300 K) is less than 20 cm⁻¹. 2 / Vs did not significantly improve the hole mobility of nitride semiconductors.

[0005] (2) Modulation doping technology based on GaN / AlGaN superlattice structure (KRISHNA A, RAJ A, HATUI N, et al. Investigation of nitrogen polar p-type doped GaN / AlxGa(1-x)Nsuperlattices for applications in wide-bandgap p-type field effect transistors[J / OL]. Applied Physics Letters, 2019, 115(17): 172105.). The periodic arrangement of atoms in this superlattice structure greatly eliminates alloy scattering in traditional disordered alloys, but does not change the problem of large effective hole mass caused by sp3 hybridization of traditional nitride semiconductors. The hole mobility of the material at room temperature (300K) is only 18 cm⁻¹. 2 / Vs. Summary of the Invention

[0006] To overcome the shortcomings of the prior art, the present invention aims to provide a novel ScAlN semiconductor material with extremely high hole mobility, its preparation method, and its applications. Specifically, addressing the inherent contradiction between wide bandgap and high hole mobility in traditional nitride semiconductors due to the sp3 hybridization mechanism, the present invention innovatively constructs a ScAlN digital alloy structure with a specific atomic layer arrangement. This structure utilizes the unique octahedral coordination tendency of Sc atoms to induce local symmetry breaking and hybrid orbital reconstruction within the AlN lattice by periodically introducing and restricting the number and order of ScN layers. This fundamentally reshapes the valence band top electron state distribution while maintaining a wide bandgap, significantly improving hole mobility. The present invention not only solves the mobility bottleneck at room temperature but also provides a superior material approach for fabricating highly reliable high-temperature p-type nitride devices.

[0007] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A novel ScAlN semiconductor material with extremely high hole mobility, possessing a ScAlN digital alloy structure whose crystal structure consists of basic repeating units (ScN). m / (AlN) n It is formed by periodically and alternately stacking elements along the epitaxial growth direction; among them, (ScN) m ScN and (AlN) represent m atomic layers. n AlN represents n atomic layers; m takes the value of 3 or 5, and n takes the value of 1; the number of repetition cycles of the basic repeating unit is x, and x is a natural number greater than or equal to 1.

[0008] The ScAlN semiconductor material is prepared by MOCVD process. The specific process is as follows: In the pulse growth mode of periodically switching a specific MO source, ammonia gas is continuously introduced. (1) ScN sublayer growth stage: turn on the Sc source, turn off the Al source, and grow 3 or 5 mL of ScN; (2) AlN sublayer growth stage: turn off the Sc source, turn on the Al source, and grow 1 mL of AlN; repeat steps (1) and (2) until the preset total thickness is reached.

[0009] An enhanced p-channel vertical trench gate MOSFET device includes, from bottom to top, a drain electrode 8, a p-type GaN substrate 1, and a p-type GaN drift layer 2 stacked together; an n-type channel layer 3, a p-type GaN heavily doped layer 4, and a source electrode 7 are stacked sequentially on both sides of the top of the p-type GaN drift layer 2; a vertical trench structure is formed in the p-type GaN drift layer 2, the n-type channel layer 3, and the p-type GaN heavily doped layer 4, and the sidewalls and bottom of the vertical trench structure are covered with an Al2O3 gate dielectric layer 5, and a gate electrode 6 is disposed inside the vertical trench structure and located inside the Al2O3 gate dielectric layer 5; wherein, the material of the n-type channel layer 3 is the aforementioned ScAlN semiconductor material, namely (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1.

[0010] The doping concentration of the p-type GaN drift layer 2 is 1×10⁻⁶. 16 -5×10 16 cm -3 The thickness is 300-800 nm; the doping concentration of the n-type channel layer 3 is 1×10⁻⁶. 15 -5×10 15 cm -3 The thickness is 100-200 nm; the doping concentration of the p-type GaN heavily doped layer 4 is 1×10⁻⁶. 19 -5×10 19 cm -3 The thickness of the Al2O3 gate dielectric layer 5 is 200-300 nm; the material of the Al2O3 gate dielectric layer 5 is Al2O3, and the thickness is 20-30 nm; the material of the gate electrode 6 is metal W, and the thickness is 280-470 nm.

[0011] A method for fabricating an enhanced p-channel vertical trench gate MOSFET device includes the following steps: Step 1: Use MOCVD process to grow a 300-800 nm thick lightly doped p-type GaN drift layer 2 on a heavily doped p-type GaN substrate 1; Step 2: Use MOCVD process to grow a lightly doped n-type channel layer 3 on the p-type GaN drift layer 2; adopt a pulse growth mode of periodically switching a specific MO source and keeping ammonia gas continuously introduced, (1) ScN sublayer growth stage: turn on the Sc source, turn off the Al source, and grow 3 or 5 mL of ScN; (2) AlN sublayer growth stage: turn off the Sc source, turn on the Al source, and grow 1 mL of AlN; repeat steps (1) and (2) until the total thickness of the n-type channel layer 3 reaches 100-200 nm; Step 3: Use MOCVD process to grow a 200-300 nm thick p-type GaN heavily doped layer 4 on the n-type channel layer 3; Step 4: Use photolithography to define the gate trench planar pattern on the p-type GaN heavily doped layer 4, and use plasma reactive ion etching to etch until the p-type GaN drift layer 2 is exposed to form the gate trench. Step 5: Use atomic layer deposition technology to uniformly deposit a 20-30 nm thick Al2O3 dielectric layer on the inner wall of the gate trench; Step 6: Use CVD process to deposit metal W to completely fill the gate trench, forming a gate electrode 6 with a thickness of 280-470 nm; Step 7: Deposit a Ni / Au metal stack on the heavily doped p-type GaN layer 4 using electron beam evaporation to form the source electrode 7; deposit a Ni / Au metal stack on the back side of the p-type GaN substrate 1 using electron beam evaporation to form the drain electrode 8.

[0012] A p-type GaN power diode device based on an AlN substrate, comprising, from bottom to top, an n-region electrode 14, an n-type AlN substrate 9, an n-type AlGaN drift layer 10, a p-type hole transport layer 11, a p-type AlGaN hole injection layer 12, and a p-region electrode 13 stacked together; wherein the p-type hole transport layer 11 is made of the aforementioned ScAlN semiconductor material, namely (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1.

[0013] The doping concentration of the n-type AlGaN drift layer 10 is 1×10⁻⁶. 16 -5×10 16 cm -3 The thickness is 5-10 μm; the doping concentration of the p-type hole transport layer 11 is 1×10⁻⁶. 15 -5×10 15 cm -3 The thickness is 100-200 nm; the doping concentration of the p-type AlGaN hole injection layer 12 is 1×10⁻⁶. 19 -5×10 19 cm -3 The thickness is 200-300 nm.

[0014] A method for fabricating a p-type GaN power diode device based on an AlN substrate includes the following steps: Step 1: Use MOCVD process to grow a 5-10 μm thick lightly doped p-type AlGaN drift layer 10 on a heavily doped n-type AlN substrate 9; Step 2: Use MOCVD process to grow a lightly doped p-type hole transport layer 11 on the p-type AlGaN drift layer 10; adopt a pulse growth mode of periodically switching a specific MO source, keep ammonia gas continuously flowing in, (1) ScN sublayer growth stage: turn on the Sc source, turn off the Al source, and grow 3 or 5 mL of ScN; (2) AlN sublayer growth stage: turn off the Sc source, turn on the Al source, and grow 1 mL of AlN; repeat steps (1) and (2) until the total thickness of the p-type hole transport layer 11 reaches 100-200 nm; Step 3: Use MOCVD process to grow a 200-300 nm thick heavily doped p-type AlGaN hole injection layer 12 on the p-type hole transport layer 11; Step 4: A Ni / Au metal stack is deposited on the p-type AlGaN hole injection layer 12 by electron beam evaporation, and the p-region electrode 13 is formed after annealing; a Ti / Al / Ni / Au metal stack is deposited on the back side of the n-type AlN substrate 9 by electron beam evaporation, and the n-region electrode 14 is formed after annealing.

[0015] This invention designs specific (ScN) m / (AlN) n Short-period superlattice (digital alloy) structures offer the following advantages compared to technologies such as 2DHG and superlattice modulation doping: 1. This invention proposes two specific AlN / ScN ratio ScAlN digital alloys, namely (ScN)5 / (AlN)1 and (ScN)3 / (AlN)1, which induce the formation of a novel hexagonal phase crystal intermediate between the tetrahedral coordination of traditional AlN nitrides and the octahedral coordination of transition metal group nitrides ScN. This structure inherits the excellent thermodynamic stability of traditional group III nitride semiconductors and possesses the excellent hole transport potential of ScN. The room temperature out-of-plane hole mobility of the ScAlN digital alloy structure proposed in this invention reaches over 177 cm² / Vs, far exceeding the hole mobility results of all current mainstream nitride semiconductor technologies; and at a high temperature of 500K, the out-of-plane hole mobility remains above 117 cm² / Vs, exceeding the reported values ​​of existing nitrides by more than two orders of magnitude, meeting the reliability requirements of high-temperature power devices.

[0016] 2. This invention uses ScAlN digital alloy as a p-type channel to fabricate a vertical trench gate MOSFET device. The high hole mobility of ScAlN digital alloy helps to reduce channel resistance and significantly improve the switching speed and transconductance performance of the device.

[0017] 3. This invention uses ScAlN digital alloy as a hole transport layer to fabricate a p-type GaN power diode device on an AlN substrate. The high hole mobility of ScAlN digital alloy is beneficial to improving the injection and transport efficiency of holes from the anode to the n-type AlGaN drift layer, thereby reducing the on-state voltage drop and on-resistance of the device.

[0018] 4. This invention employs a pulsed source supply in the MOCVD process, which rapidly switches between Sc and Al sources and precisely controls the injection time and flow rate to achieve alternating growth of 3 or 5 mL ScN and 1 mL AlN single crystals.

[0019] This invention, through in-depth electronic structure research and verification, reveals a critical window for the atomic layer thickness ratio of ScN and AlN. Only when the ScAlN digital alloy adopts a specific (ScN)5 / (AlN)1 or (ScN)3 / (AlN)1 periodic structure will an atypical phase transition occur within the lattice, forming a novel hexagonal crystal structure with an anomalous coexistence of in-plane sp2 hybridization (providing a wide bandgap) and out-of-plane octahedral coordination (providing a low effective mass). This special electronic state induced by a specific layer sequence enables the ScAlN digital alloys of the above two structures to achieve a significant increase in hole mobility while maintaining the wide bandgap semiconductor properties. The results show that its out-of-plane hole mobility at room temperature reaches as high as 177 cm⁻¹. 2 / Vs or more; more importantly, this structure exhibits extremely strong high-temperature resistance, with the external hole mobility remaining at 117 cm⁻¹ below 500K. 2 / Vs and above. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the local atomic coordination of a (ScN)3 / (AlN)1 digital alloy; where, Figure 1 (a) in the text represents Al-N. Figure 1 In (b), Sc-N is used.

[0021] Figure 2 The configuration diagram of the (ScN)3 / (AlN)1 digital alloy is shown; where, Figure 2 (a) in the diagram is a schematic of sp2 hybridization in the in-plane direction. Figure 2 (b) is a schematic diagram of out-of-plane octahedral coordination.

[0022] Figure 3 (ScN)m / (AlN) n The mobility of digital alloys varies with temperature; among which, Figure 3 In the figure, (a) represents the in-plane electron mobility; Figure 3 (b) represents the out-of-plane electron mobility; Figure 3 (c) represents the in-plane hole mobility. Figure 3 In the figure, (d) represents the out-of-plane hole mobility.

[0023] Figure 4 This is a ScN band structure diagram for cubic rock salt deposits.

[0024] Figure 5 This is a band structure diagram of AlN in hexagonal wurtzite.

[0025] Figure 6 Band structure diagram of (ScN)3 / (AlN)1 digital alloy.

[0026] Figure 7 Band diagram of (ScN)5 / (AlN)1 digital alloy.

[0027] Figure 8 This is a schematic diagram of an enhancement-mode p-channel vertical trench gate MOSFET device.

[0028] In the figure: p-type GaN substrate 1, p-type GaN drift layer 2, n-type channel layer 3, p-type GaN heavily doped layer 4, Al2O3 dielectric layer 5, gate electrode 6, source electrode 7, drain electrode 8.

[0029] Figure 9 This is a flowchart illustrating the fabrication process of an enhancement-mode p-channel vertical trench gate MOSFET device.

[0030] Figure 10 This is a schematic diagram of a p-type GaN power diode device based on an AlN substrate.

[0031] In the figure: n-type AlN substrate 9, n-type AlGaN drift layer 10, p-type hole transport layer 11, p-type AlGaN hole injection layer 12, p-region electrode 13, n-region electrode 14.

[0032] Figure 11 This is a flowchart illustrating the fabrication process of a p-type GaN power diode device based on an AlN substrate. Detailed Implementation

[0033] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0034] A novel ScAlN semiconductor material with extremely high hole mobility, possessing a ScAlN digital alloy structure whose crystal structure consists of basic repeating units (ScN).m / (AlN) n It is formed by periodically and alternately stacking elements along the epitaxial growth direction; among them, (ScN) m ScN and (AlN) represent m atomic layers. n AlN representing n atomic layers; m takes the value of 3 or 5, and n takes the value of 1; the number of repetition periods of the basic repeating unit is x, and x is a natural number greater than or equal to 1. This invention conducts a high-throughput first-principles study of ScAlN digital alloys based on density functional theory. The carrier mobility as a function of temperature is shown in the figure below. Figure 3 As shown in the figure, Sc m Al n The superlattice is composed of alternating m layers of ScN and n layers of AlN. The out-of-plane direction refers to the direction along the superlattice growth axis, i.e., the c-axis; the in-plane direction is perpendicular to the growth direction and parallel to the heterointerface direction. The results are given using density functional theory (DFT) in first-principles calculations. The systematic mobility was studied using the EPW tool in the internationally renowned Quantum Espresso software package, and calculations were performed within the framework of electro-acoustic coupling. Figure 3 The migration results have high theoretical guiding significance and experimental preparation value. The results show that the two digital alloy structures, (ScN)5 / (AlN)1 and (ScN)3 / (AlN)1, possess extremely high out-of-plane hole mobility, with room-temperature hole mobility in the out-of-plane direction ≥177 cm⁻¹. 2 / Vs, ≥50 cm in all in-plane directions 2 / Vs. Although the in-plane hole mobility is slightly lower than that in the out-of-plane direction, it is significantly better than that of conventional GaN and AlN nitride semiconductors. Furthermore, both of these digital alloy structures exhibit excellent temperature stability, with out-of-plane hole mobility ≥117 cm⁻¹ for both structures at 500 K. 2 / Vs, with in-plane dimensions ≥33 cm² / Vs. The following analysis delves into the crystal structure, band structure, and hole transport mechanism: First, taking the (ScN)3 / (AlN)1 digital alloy structure given in this invention as an example, such as Figure 1 As shown, the Sc atom forms a novel coordination structure with its five nearest N atoms, combining the sp3 hybrid coordination of traditional AlN nitrides with the octahedral coordination of transition metal group nitrides ScN. Specifically, as... Figure 2As shown, from a crystal structure perspective, in the in-plane direction, Sc atoms form a honeycomb-like sp2 hybrid configuration with the three surrounding N atoms; similarly, Al atoms also form a honeycomb-like sp2 hybrid configuration with the three surrounding N atoms. In the out-of-plane direction, Sc atoms form an octahedral coordination with the two N atoms above and below them, similar to the structure of rock salt. The overall crystal structure exhibits a novel hexagonal crystal system with a mixture of tetrahedral and octahedral coordination. This unique structural feature allows the (ScN)3 / (AlN)1 digital alloy structure to inherit the thermodynamic stability of traditional group III nitride semiconductors while possessing the extremely small effective hole mass of ScN crystals.

[0035] Furthermore, analyzing from the perspective of band structure, Figures 4-7 These are the band structures of ScN and AlN from the Materials Project database, and the band structures of the two digital alloys proposed in this invention. Figure 4 In ScN crystals, the valence band top energy structure is steep (small effective hole mass and strong high mobility potential), but the band gap is 0 eV, and it does not have semiconductor characteristics. Figure 5 In AlN crystals, the band gap is as wide as 4.05 eV, but the top band structure of the valence band is flat (the effective hole mass is extremely large and the mobility is low). Figures 6-7 In this system, the 0 eV position is the Fermi level, typically located at the center of the band gap. The nearest high-energy band and low-energy band are called the conduction band and valence band, respectively, and the energy difference between them is the band gap. The band gap of the (ScN)3 / (AlN)1 digital alloy is 3.08 eV, and that of the (ScN)5 / (AlN)1 digital alloy is 2.70 eV. In comparison, the band structures of the two digital alloys in this invention combine the advantages of both, retaining the wide band gap that nitrides are most advantageous for while preserving a steep valence band top structure, thus ensuring high hole mobility.

[0036] On the other hand, from the perspective of hole transport mechanism, observing the band diagram of digital alloys ( Figures 6-7 As can be seen, there is only one energy band near the top of its valence band, which is significantly different from the typical three-band structure of the valence band of nitrides (spin-orbit splitting band, heavy hole band, and light hole band). This means that the scattering process of holes only occurs within the band, and there is no inter-band scattering process, which is beneficial to improving the hole mobility.

[0037] In summary, the ScAlN digital alloy structure with specific ratios and atomic layer arrangements proposed in this invention effectively solves the core technical problem of low hole mobility in traditional nitride semiconductors, providing a highly advantageous technical solution for high-performance nitride semiconductor p-type channel devices.

[0038] like Figure 8As shown, based on the above material and structural characteristics, this invention constructs an enhanced p-channel vertical trench gate MOSFET device. Its core lies in using the proposed (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1 digital alloy as the n-type channel layer 3 between the p-type GaN drift layer 2 and the p-type GaN heavily doped layer 4. Figure 8 The device comprises, from bottom to top, a drain electrode 8, a p-type GaN substrate 1, and a p-type GaN drift layer 2 stacked together; a lightly doped n-type channel layer 3, a heavily doped p-type GaN layer 4, and a source electrode 7 are stacked sequentially on both sides of the top of the p-type GaN drift layer 2; a vertical trench structure is formed in the p-type GaN drift layer 2, the n-type channel layer 3, and the heavily doped p-type GaN layer 4; an Al2O3 gate dielectric layer 5 covers the sidewalls and bottom of the vertical trench structure; and a gate electrode 6 located inside the Al2O3 gate dielectric layer 5 is disposed inside the vertical trench structure.

[0039] The drain electrode 8 is a Ni / Au multilayer metal, located on the back side of the p-type GaN substrate 1, forming an ohmic contact with the substrate, and its thickness is 20-100 / 20-100 nm; the p-type GaN substrate 1 is heavily doped p-type GaN, providing mechanical support and vertical conductive paths for the device, and its doping concentration is 1×10⁻⁶. 19 -5×10 19 cm -3 The thickness is 300-500 nm; the p-type GaN drift layer 2 is a lightly doped p-type GaN layer, mainly responsible for the breakdown voltage function of the device, and its doping concentration is 1×10⁻⁶. 16 -5×10 16 cm -3 The thickness is 300-800 nm; the n-type channel layer 3 is a (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1 digital alloy structure proposed in this invention, which is periodically grown and has a doping concentration of 1×10⁻⁶. 15 -5×10 15 cm -3 The thickness is 100-200 nm; the heavily doped p-type GaN layer 4 is heavily doped p-type GaN, forming an ohmic contact with the source electrode 7 to provide hole carrier injection for the channel layer, and its doping concentration is 1×10⁻⁶. 19 -5×10 19 cm -3The thickness of the Al2O3 gate dielectric layer 5 is 200-300 nm; the material of the Al2O3 gate dielectric layer 5 is Al2O3 with a high dielectric constant and a thickness of 20-30 nm; the gate electrode 6 uses metal W as the gate material to fill the trench and has a thickness of 280-470 nm; the source electrode 7 is a Ni / Au stacked metal, located on the p-type GaN heavily doped layer 4, forming an ohmic contact with the heavily doped layer, and its thickness is 20-100 / 20-100 nm.

[0040] like Figure 9 As shown, a method for fabricating an enhanced p-channel vertical trench gate MOSFET device includes the following specific process steps: Step 1: A 500 nm lightly doped p-type GaN drift layer 2 is homoepitaxially grown on a heavily doped p-type GaN substrate 1 using MOCVD technology; the process conditions are: temperature 1000℃, pressure 300 Torr, gallium source flow rate 100 sccm, ammonia flow rate 20000 sccm, hydrogen flow rate 40000 sccm, and magnesia pyrocene (Cp2Mg) doping source flow rate 20 sccm. Step 2: Use MOCVD process to grow a 100 nm lightly doped n-type (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1 digital alloy channel layer 3 on the p-type GaN drift layer 2; adopt a pulse growth mode of periodically switching specific MO sources, the specific pulse growth sequence is as follows: keep ammonia gas continuously flowing in, and realize digital alloy growth by periodically switching the group III metal source gas path: (1) ScN sublayer growth stage: turn on the scandium source (Sc source), turn off the aluminum source (Al source), maintain the growth time for 5-10 s, and grow 3 or 5 mL (atomic monolayer) of ScN; (2) AlN sublayer growth stage: quickly switch the gas path, turn off the Sc source, turn on the Al source, maintain the growth time for 2-4 s, and grow 1 mL of AlN; (3) repeat the above steps (1) and (2) until the total thickness of the n-type channel layer 3 reaches 100 nm; its growth process and doping conditions: temperature 1300℃, pressure 50 Torr, Sc source flow rate 15 The flow rate of Al source was 40 sccm, the flow rate of ammonia was 20000 sccm, the flow rate of hydrogen was 30000 sccm, and the flow rate of n-type doped source silane was introduced during the growth process, with its flow rate controlled at 5 sccm. Step 3: A 200 nm p-type GaN heavily doped layer 4 is grown on the n-type channel layer 3 using MOCVD process; the process conditions are: temperature 1050℃, pressure 50 Torr, gallium source flow rate 100 sccm, ammonia flow rate 20000 sccm, hydrogen flow rate 30000 sccm, and magnesia pyrocene (Cp2Mg) doping source flow rate 50 sccm. Step 4: Define the gate trench planar pattern on the p-type GaN heavily doped layer 4 using photolithography. Then, use plasma reactive ion etching (RIE) to etch until the p-type GaN drift layer 2 is exposed, forming a gate trench with a thickness of 300 nm. RIE process parameters: 30 sccm Cl2, 10 sccm BCl3, 5 sccm Ar gas; RF power of 50 W, bias power of 100 W; cavity pressure controlled at 5-10 mTorr; the entire etching process lasts 450 seconds, with the etching depth strictly controlled to 300 nm and stopped when reaching the interface of the p-type GaN drift layer 2 to ensure the surface flatness of the bottom of the gate trench. Step 5: A high dielectric constant Al2O3 dielectric layer 5 with a thickness of 20 nm is uniformly deposited on the inner wall of the gate trench using atomic layer deposition (ALD) technology; the process parameters are: trimethylaluminum (TMAl) and H2O as sources, deposition temperature of 250-300℃; pulse / purge time of 0.1 s / 10 s to ensure that residual gas inside the high aspect ratio trench is completely removed, so as to ensure the compactness and thickness uniformity of the dielectric layer; Step 6: Use CVD process to deposit metal W to completely fill the gate trench, forming a gate electrode 6 with a thickness of 280 nm; the process parameters are: WF6 and H2 are used as reaction gases, the deposition temperature is 400-450℃, and the pressure is 10-50 Torr. Step 7: Deposit a Ni / Au metal stack with a thickness of 20 / 100 nm on the p-type GaN heavily doped layer 4 using electron beam evaporation to form the source electrode 7; the process parameters are: vacuum degree less than 3.5 × 10⁻⁶. -4 The process involves evaporation at 500 W per 1 Å / s, followed by rapid thermal annealing in a mixed O2 and N2 atmosphere at 500-550 °C for 1-3 minutes. A 20 / 100 nm thick Ni / Au metal stack is deposited on the back side of the p-type GaN substrate 1 using electron beam evaporation to form the drain electrode 8. The process parameters include a vacuum level of less than 3.5 × 10⁻⁶. -4 Pa, power 500 W, evaporation rate 1 Å / s, followed by rapid thermal annealing in a mixed atmosphere of O2 and N2 at annealing temperature 500-550℃ for 1-3 minutes.

[0041] like Figure 10As shown, based on the above material and structural characteristics, this invention constructs a p-type GaN power diode device based on an AlN substrate. This device has a vertical structure, and its core lies in using the (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1 digital alloy of this invention as the hole transport layer between the n-type AlGaN drift layer 10 and the ohmic contact metal. From bottom to top, the diode includes a stacked n-region electrode 14, an n-type AlN substrate 9, an n-type AlGaN drift layer 10, a p-type hole transport layer 11, a p-type AlGaN hole injection layer 12, and a p-region electrode 13.

[0042] The n-region electrode 14 is a Ti / Al / Ni / Au multilayer metal, located on the back side of the n-type AlN substrate 9, forming an ohmic contact with the substrate, and has a thickness of 20 / 100 / 40 / 50 nm; the n-type AlN substrate 9 is heavily doped n-type AlN, providing mechanical support and a growth plane for the device, and its doping concentration is 1×10⁻⁶. 19 -5×10 19 cm -3 The thickness is 300-500 nm; the n-type AlGaN drift layer 10 is a lightly doped n-type AlGaN layer, mainly responsible for the breakdown voltage function of the device, and its doping concentration is 1×10⁻⁶. 16 -5×10 16 cm -3 The thickness is 5-10 μm; the p-type hole transport layer 11 is a lightly doped p-type (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1 digital alloy layer, periodically epitaxially grown, with a doping concentration of 1×10⁻⁶. 15 -5×10 15 cm -3 The thickness is 100-200 nm; the p-type AlGaN hole injection layer 12 is heavily doped p-type AlGaN, forming an ohmic contact with the p-region electrode 13 to provide hole carrier injection for the channel layer, and its doping concentration is 1×10⁻⁶. 19 -5×10 19 cm -3 The thickness is 200-300 nm; the p-region electrode 13 is a Ni / Au multilayer metal, located on the p-type AlGaN hole injection layer 12, forming an ohmic contact with the hole injection layer, and its thickness is 20-100 / 20-100 nm.

[0043] like Figure 11 As shown, a method for fabricating a vertical structure power diode device based on an AlN substrate is described, and the specific process steps are as follows: Step 1: Homoepitaxially grow a 10 μm thick lightly doped p-type AlGaN drift layer 10 on an n-type AlN substrate 9 using MOCVD process; the process conditions are: temperature 1000℃, pressure 300 Torr, Al source flow rate 40 sccm, Ga source flow rate 100 sccm, ammonia flow rate 20000 sccm, hydrogen flow rate 40000 sccm, and magnesia pyrocene (Cp2Mg) doping source flow rate 20 sccm. Step 2: Use MOCVD process to grow a 200 nm thick lightly doped p-type hole transport layer 11 on the p-type AlGaN drift layer 10; adopt a pulse growth mode of periodically switching a specific MO source, and the specific pulse growth sequence is as follows: keep ammonia gas continuously flowing in, and realize digital alloy growth by periodically switching the gas path of the group III metal source: (1) ScN sublayer growth stage: turn on the Sc source, turn off the Al source, maintain the growth time for 5-10 s, and grow 3 or 5 ML (atomic monolayer) of ScN; (2) AlN sublayer growth stage: quickly switch the gas path, turn off the Sc source, turn on the Al source, maintain the growth time for 2-4 s, and grow 1 ML of AlN; (3) repeat the above steps (1) and (2) until the total thickness of the p-type hole transport layer 11 reaches 200 nm. The growth process and doping conditions are as follows: temperature 1300℃, pressure 50 Torr, Sc source flow rate 15 sccm, Al source flow rate 40 sccm, ammonia flow rate 20000 sccm, hydrogen flow rate 30000 sccm, and magnesia (Cp2Mg) doping source flow rate 20 sccm. Step 3: A 300 nm thick heavily doped p-type AlGaN hole injection layer 12 is grown on the p-type hole transport layer 11 using MOCVD technology. The process conditions are: temperature 1050℃, pressure 50 Torr, Al source flow rate 40 sccm, Ga source flow rate 100 sccm, ammonia flow rate 20000 sccm, hydrogen flow rate 30000 sccm, and magnesia pyrocene (Cp2Mg) doped source flow rate 50 sccm. Step 4: Deposit a Ni / Au metal stack with a thickness of 20 / 100 nm on the p-type AlGaN hole injection layer 12 using electron beam evaporation to form the p-region electrode 13; the process parameters are: vacuum degree less than 3.5 × 10⁻⁶. -4 Pa, power 500 W, evaporation rate 1 Å / s, followed by rapid thermal annealing in a mixed atmosphere of O2 and N2 at a temperature of 500-550℃ for 1-3 minutes; Step 5: Deposit a Ti / Al / Ni / Au metal stack with a thickness of 20 / 100 / 40 / 50 nm on the back side of the n-type AlN substrate 9 using electron beam evaporation to form the n-region electrode 14; the process parameters are: vacuum degree less than 3.5 × 10⁻⁶. -4Pa, power 500 W, evaporation rate 1 Å / s, followed by rapid thermal annealing (RTA) in a N2 protective atmosphere at a temperature of 900-1000 °C for 30-60 seconds.

Claims

1. A novel ScAlN semiconductor material with extremely high hole mobility, characterized in that: This material has a ScAlN digital alloy structure, whose crystal structure consists of basic repeating units (ScN). m / (AlN) n It is formed by periodically and alternately stacking elements along the epitaxial growth direction; among them, (ScN) m ScN and (AlN) represent m atomic layers. n AlN represents n atomic layers; m takes the value of 3 or 5, and n takes the value of 1; the number of repetition cycles of the basic repeating unit is x, and x is a natural number greater than or equal to 1.

2. The novel ScAlN semiconductor material according to claim 1, characterized in that, The ScAlN semiconductor material is prepared by MOCVD process. The specific process is as follows: In the pulse growth mode of periodically switching a specific MO source, ammonia gas is continuously introduced. (1) ScN sublayer growth stage: turn on the Sc source, turn off the Al source, and grow 3 or 5 mL of ScN; (2) AlN sublayer growth stage: turn off the Sc source, turn on the Al source, and grow 1 mL of AlN; repeat steps (1) and (2) until the preset total thickness is reached.

3. A MOSFET device with an enhanced p-channel vertical trench gate structure, characterized in that: The device comprises, from bottom to top, a drain electrode (8), a p-type GaN substrate (1), and a p-type GaN drift layer (2) stacked together; an n-type channel layer (3), a p-type GaN heavily doped layer (4), and a source electrode (7) are stacked sequentially on the top sides of the p-type GaN drift layer (2); a vertical trench structure is formed in the p-type GaN drift layer (2), the n-type channel layer (3), and the p-type GaN heavily doped layer (4); the sidewalls and bottom of the vertical trench structure are covered with an Al2O3 gate dielectric layer (5); and a gate electrode (6) is disposed inside the vertical trench structure located inside the Al2O3 gate dielectric layer (5); wherein, the material of the n-type channel layer (3) is the ScAlN semiconductor material as described in claim 1 or 2, namely (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1.

4. The MOSFET device according to claim 3, characterized in that: The doping concentration of the p-type GaN drift layer (2) is 1×10⁻⁶. 16 -5×10 16 cm -3 The thickness is 300-800 nm; the doping concentration of the n-type channel layer (3) is 1×10⁻⁶. 15 -5×10 15 cm -3 The thickness is 100-200 nm; the doping concentration of the p-type GaN heavily doped layer (4) is 1×10⁻⁶. 19 -5×10 19 cm -3 The thickness is 200-300 nm; the Al2O3 gate dielectric layer (5) is made of Al2O3 and has a thickness of 20-30 nm; the gate electrode (6) is made of metal W and has a thickness of 280-470 nm.

5. A method for fabricating a MOSFET device with an enhanced p-channel vertical trench gate structure, characterized in that, Includes the following steps: Step 1: Use MOCVD process to grow a 300-800 nm thick lightly doped p-type GaN drift layer (2) on a heavily doped p-type GaN substrate (1). Step 2: Use MOCVD process to grow a lightly doped n-type channel layer (3) on the p-type GaN drift layer (2); adopt a pulse growth mode of periodically switching a specific MO source and keeping ammonia gas continuously introduced, (1) ScN sublayer growth stage: turn on the Sc source, turn off the Al source, and grow 3 or 5 mL of ScN; (2) AlN sublayer growth stage: turn off the Sc source, turn on the Al source, and grow 1 mL of AlN; repeat steps (1) and (2) until the total thickness of the n-type channel layer (3) reaches 100-200 nm; Step 3: Use MOCVD process to grow a 200-300 nm thick p-type GaN heavily doped layer (4) on the n-type channel layer (3); Step 4: Use photolithography to define the gate trench planar pattern on the p-type GaN heavily doped layer (4), and use plasma reactive ion etching process to etch until the p-type GaN drift layer (2) is exposed to form the gate trench; Step 5: Use atomic layer deposition technology to uniformly deposit a 20-30 nm thick Al2O3 dielectric layer on the inner wall of the gate trench (5). Step 6: Use CVD process to deposit metal W to completely fill the gate trench, forming a gate electrode with a thickness of 280-470 nm (6). Step 7: Deposit a Ni / Au metal stack on the heavily doped p-type GaN layer (4) using electron beam evaporation to form a source electrode (7); deposit a Ni / Au metal stack on the back side of the p-type GaN substrate (1) using electron beam evaporation to form a drain electrode (8).

6. A p-type GaN power diode device based on an AlN substrate, characterized in that: The device comprises, from bottom to top, an n-region electrode (14), an n-type AlN substrate (9), an n-type AlGaN drift layer (10), a p-type hole transport layer (11), a p-type AlGaN hole injection layer (12), and a p-region electrode (13); wherein the p-type hole transport layer (11) is made of the ScAlN semiconductor material as described in claim 1 or 2, namely (ScN)3 / (AlN)1 or (ScN)5 / (AlN)1.

7. The p-type GaN power diode device according to claim 6, characterized in that: The doping concentration of the n-type AlGaN drift layer (10) is 1×10⁻⁶. 16 -5×10 16 cm -3 The thickness is 5-10 μm; the doping concentration of the p-type hole transport layer (11) is 1×10⁻⁶. 15 -5×10 15 cm -3 The thickness is 100-200 nm; the doping concentration of the p-type AlGaN hole injection layer (12) is 1×10⁻⁶. 19 -5×10 19 cm -3 The thickness is 200-300 nm.

8. A method for fabricating a p-type GaN power diode device based on an AlN substrate, characterized in that, Includes the following steps: Step 1: Use MOCVD process to grow a 5-10 μm thick lightly doped p-type AlGaN drift layer (10) on a heavily doped n-type AlN substrate (9). Step 2: Use MOCVD process to grow a lightly doped p-type hole transport layer (11) on the p-type AlGaN drift layer (10); adopt a pulse growth mode of periodically switching a specific MO source and keep ammonia gas continuously flowing in, (1) ScN sublayer growth stage: turn on the Sc source, turn off the Al source, and grow 3 or 5 mL of ScN; (2) AlN sublayer growth stage: turn off the Sc source, turn on the Al source, and grow 1 mL of AlN; repeat steps (1) and (2) until the total thickness of the p-type hole transport layer (11) reaches 100-200 nm; Step 3: Use MOCVD process to grow a 200-300 nm thick heavily doped p-type AlGaN hole injection layer (12) on the p-type hole transport layer (11). Step 4: Ni / Au metal stack is deposited on the p-type AlGaN hole injection layer (12) by electron beam evaporation, and p-region electrode (13) is formed after annealing; Ti / Al / Ni / Au metal stack is deposited on the back side of the n-type AlN substrate (9) by electron beam evaporation, and n-region electrode (14) is formed after annealing.

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