Silicon carbide mosfet integrated with a channel diode and method of fabrication

Abstract

This invention discloses a silicon carbide MOSFET with integrated channel diode, comprising, from bottom to top, a drain metal layer, a SiC-N substrate, a SiC-N epitaxial region, and a SiC-N current spreading layer. Source trenches (SiC-P+ regions) are respectively located on opposite sides of the N-type current spreading layer, and a source trench is located above each SiC-P+ region. A SiC-P pillar region is located at the center of the N-type current spreading layer, and a gate trench is located above the SiC-P pillar region. This invention also discloses a method for fabricating the silicon carbide MOSFET with integrated channel diode. This invention solves the problems of excessively high reverse turn-on voltage, poor reverse recovery characteristics, short short-circuit withstand time, and high peak short-circuit current in traditional silicon carbide MOSFET structures.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device technology, and relates to silicon carbide MOSFETs with integrated channel diodes. This invention also relates to a method for fabricating silicon carbide MOSFETs with integrated channel diodes. Background Technology

[0002] Silicon carbide MOSFETs are commonly used in bridge circuits such as inverters and choppers, where power switching devices need to provide a bidirectional path for the load current. When the main switch is turned off, the freewheeling current of the inductive load needs to be discharged through a complementary switching circuit. For silicon-based IGBTs, since they cannot conduct in reverse, a fast recovery diode (FRD) must usually be connected in anti-parallel externally to create a freewheeling path. However, silicon carbide MOSFETs (metal-oxide-semiconductor field-effect transistors), as bipolar devices, have an internal parasitic PN junction diode composed of a P-type body region and an N-drift region, i.e., a "body diode." Theoretically, this body diode can naturally assume the freewheeling function, potentially eliminating the need for an external anti-parallel diode. This is significant for simplifying system topology, reducing module size, and lowering manufacturing costs. However, in practical engineering applications, directly utilizing the body diode of a silicon carbide MOSFET for freewheeling faces a key technical challenge: the excessively high turn-on voltage of the silicon carbide body diode increases both static and dynamic losses and affects the device's reverse recovery characteristics. Therefore, despite the presence of a body diode, most current high-performance application solutions still tend to connect a low-turn-on voltage, fast-recovery SiC Schottky diode (SBD) in anti-parallel to the SiC MOSFET. This undoubtedly negates the advantage of SiC devices in reducing system size and increases cost and packaging complexity.

[0003] Furthermore, as the core power switch in power electronic systems, the reliability of silicon carbide MOSFETs directly affects the safe and stable operation of the entire system. Among various potential failure modes, short-circuit faults are one of the most severe challenges. In practical applications, if a motor stalls or control logic errors occur, a shoot-through short circuit can easily occur in the inverter bridge arm. At this time, a DC bus voltage of up to several hundred volts will be applied instantaneously across the device in the conducting state, triggering an extremely large transient short-circuit current and power surge. Due to the high critical electric field of silicon carbide material itself and the structural characteristics of the device, the short-circuit withstand time window of SiC MOSFETs is usually much shorter than that of traditional silicon-based IGBTs, generally only 2 to 5 microseconds. Within this extremely short time, the local junction temperature of the device chip can rise sharply to over 1000°C, bearing exceptionally severe electrical, thermal, and mechanical multi-physics field coupling stress. If the protection circuit fails to complete fault detection and shutdown within this narrow time window, the device will inevitably be damaged. Such failures not only cause a single path of functional interruption, but may also trigger the spread of the fault, leading to the complete paralysis of the entire drive system or critical power equipment, thereby causing significant safety hazards and high economic losses.

[0004] In summary, existing silicon carbide MOSFETs still need structural optimization to improve their issues of excessively high reverse turn-on voltage and poor reverse recovery characteristics in terms of freewheeling mode. Secondly, as silicon carbide MOSFETs are widely used in automotive-grade systems, their short-circuit reliability has become the most concerning reliability issue in the industry. The short short-circuit withstand time and easy damage of traditional structures have restricted their further promotion in high-end applications. Summary of the Invention

[0005] The purpose of this invention is to provide a silicon carbide MOSFET with an integrated channel diode, which solves the problems of excessive turn-on voltage, poor reverse recovery characteristics, short short-circuit withstand time, and high peak short-circuit current in traditional silicon carbide MOSFET structures.

[0006] Another object of the present invention is to provide a method for fabricating a silicon carbide MOSFET with an integrated channel diode.

[0007] The first technical solution adopted in this invention is a silicon carbide MOSFET with integrated channel diode, comprising, from bottom to top, a drain metal layer, a SiC-N type substrate, a SiC-N type epitaxial region, a SiC-N type current spreading layer, and a source metal layer. Source trench SiC-P+ regions are respectively provided on opposite sides of the N-type current spreading layer, and a source trench is provided above each source trench SiC-P+ region. A SiC-P type pillar region is provided at the center of the N-type current spreading layer, and a gate trench is provided above the SiC-P type pillar region.

[0008] The first technical solution of this invention is further characterized by:

[0009] The source trench includes a source trench gate oxide layer, and the source trench gate N-type polysilicon is disposed within the source trench gate oxide layer.

[0010] The gate trench includes a U-shaped trench gate oxide layer, and a trench gate N-type polysilicon is disposed above the trench gate oxide layer.

[0011] Above the SiC-N type current spread layer, there are sequentially arranged SiC-P type base regions and SiC-N type base regions. At the center of the SiC-N type base region, there is a SiC-P type source region. On the opposite sides of the SiC-P type source region, there are SiC-N type source regions respectively. The trench gate oxide layer is disposed through the center of the SiC-P type source region, the SiC-N type base region and the SiC-P type base region.

[0012] A source metal layer is provided above the source trench gate N-type polysilicon, SiC N-type source region, SiC-P-type source region, trench gate oxide layer, and trench gate N-type polysilicon.

[0013] An insulating dielectric layer is provided at the center of the source metal layer, and the gate metal layer is wrapped inside the insulating dielectric layer.

[0014] The second technical solution adopted in this invention is a method for fabricating a silicon carbide MOSFET with integrated channel diode, which specifically includes the following steps: Step 1: Sequentially form a SiC-N type epitaxial region and a SiC-N type current spreading layer on the SiC-N substrate; Step 2: Two source trench SiC-P+ regions and one SiC-P type pillar region are grown in the SiC-N type current spread layer, respectively. Step 3: Form SiC-P type base region, SiC-N type base region, SiC-P type source region and SiC N type source region on SiC-N type current spread layer respectively; Step 4: Etch source trenches and gate trenches on the SiC-N type base region and the SiC-P type base region, respectively.

[0015] The second technical solution of the present invention is further characterized by: A source metal layer is formed above the SiC-P type source region and the SiC-N type source region, and a drain metal layer is formed at the bottom of the SiC-N substrate.

[0016] The source trench includes a source trench gate oxide layer, and N-type polysilicon is deposited in the source trench gate oxide layer to generate source trench gate N-type polysilicon.

[0017] The gate trench includes a trench gate oxide layer, and N-type polysilicon is deposited in the trench gate oxide layer to form trench gate N-type polysilicon.

[0018] The beneficial effects of this invention are as follows: 1) This invention innovatively integrates a MOS channel diode with a low barrier height into the device cell structure. This structure provides a low-impedance path for charge carriers during reverse conduction, which is completely different from that of a traditional body diode, thereby significantly reducing the reverse turn-on voltage of the device from a physical mechanism perspective. V SD At the same time, this structure significantly reduces the stored charge of minority carriers extracted during turn-off, enabling reverse charge recovery (…). Q rr Excessively high and peak reverse recovery current ( I rr The problem of excessive size has been fundamentally improved. Based on this characteristic, systems using this device can completely eliminate the need for external anti-parallel freewheeling diodes. This not only directly reduces the package area and system size of the power module, but also effectively reduces material and assembly costs by reducing the number of core components, thereby improving system integration and reliability.

[0019] 2) Compared with existing devices, this invention has a longer short-circuit withstand time and a lower peak drain-source current under short-circuit conditions, providing valuable redundancy for system protection design. This improvement enables the drive circuit to accurately identify and safely shut off fault currents within a more relaxed time range, completely solving the problem of device damage caused by the failure of the protection "time race" in traditional solutions. Therefore, this invention not only improves the device's own resilience but also plays a decisive role in ensuring the functional safety and operational continuity of critical systems such as motor drives and aviation power supplies under extreme conditions.

[0020] 3) This invention employs a semi-superjunction structure design. This structure not only comprehensively optimizes the static characteristics of the device, including forward blocking capability, output characteristics, and transfer characteristics, but also significantly reduces the gate-drain capacitance (…). C GD ) and gate drain charge ( Q GD Thanks to this low gate charge characteristic, the device achieves faster switching speeds and lower switching losses. The dual reduction in static and dynamic losses directly translates into a decrease in overall device power consumption, thereby effectively improving system-level energy efficiency. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the silicon carbide MOSFET with integrated channel diode of the present invention; Figure 2 This is a process flow diagram of the silicon carbide MOSFET with integrated channel diode of the present invention; Figure 3This is a schematic diagram of the structure of the silicon carbide MOSFET with integrated channel diode of the present invention, in which a SiC-N type epitaxial region and a SiC-N type current spreading layer are formed on a silicon carbide substrate; Figure 4 This is a schematic diagram of the structure of the silicon carbide MOSFET with integrated channel diode of the present invention, which forms the source trench SiC-P+ region and the SiC-P type pillar region. Figure 5 This is a schematic diagram of the structure of the silicon carbide MOSFET with integrated channel diode of the present invention, which forms a SiC-P type base region, a SiC-N type base region, a SiC-N type source region and a SiC-P type source region; Figure 6 This is a schematic diagram of the silicon carbide MOSFET gate trench etching and source trench etching structure of the integrated channel diode of the present invention. Figure 7 This is a schematic diagram of the structure of the silicon carbide MOSFET integrated channel diode of the present invention, which grows a gate oxide layer and deposits polysilicon to form a gate metal and an insulating isolation dielectric layer. Figure 8 The silicon carbide MOSFET with integrated channel diode of the present invention forms the source metal and drain metal; Figure 9 The curves show a comparison of the forward blocking characteristics of a conventional structure (DT-MOSFET) and a silicon carbide MOSFET with an integrated channel diode as described in this invention. Figure 10 The curves show a comparison of the output characteristics of a silicon carbide MOSFET with a conventional structure and the integrated channel diode of this invention. Figure 11 The curves show a comparison of the transfer characteristics of the silicon carbide MOSFET with the traditional structure and the integrated channel diode of this invention. Figure 12 The curves show a comparison of the third quadrant IV characteristics of the silicon carbide MOSFET with a conventional structure and the integrated channel diode of this invention. Figure 13 The curves show a comparison of the gate charge characteristics of a silicon carbide MOSFET with a conventional structure and the integrated channel diode of this invention. Figure 14 The curves show a comparison of the gate capacitance characteristics of a silicon carbide MOSFET with a traditional structure and the integrated channel diode of this invention. Figure 15 The curves show a comparison of the reverse recovery characteristics of the silicon carbide MOSFET with the traditional structure and the integrated channel diode of this invention. Figure 16 The curves show the short-circuit characteristics of a silicon carbide MOSFET with a conventional structure and an integrated channel diode of the present invention at a bus voltage of 400V. Figure 17The curves show the short-circuit characteristics of a silicon carbide MOSFET with a conventional structure and an integrated channel diode of the present invention at a bus voltage of 600V. Figure 18 The curves show a comparison of the short-circuit characteristics of a silicon carbide MOSFET with a conventional structure and the integrated channel diode of this invention at a bus voltage of 800V.

[0022] In the figure, 1. SiC-N substrate, 2. SiC-N epitaxial region, 3. SiC-N current spreading layer, 4. Source trench SiC-P+ region, 5. SiC-P pillar region, 6. SiC-P base region, 7. SiC-N base region, 8. SiC-N source region, 9. SiC-P source region, 10. Source trench gate oxide layer, 11. Trench gate oxide layer, 12. Trench gate N-type polysilicon, 13. Source trench gate N-type polysilicon, 14. Gate metal layer, 15. Insulating dielectric layer, 16. Source metal layer, 17. Drain metal layer. Detailed Implementation

[0023] The following detailed description is provided in conjunction with specific implementation methods.

[0024] Example 1 This invention relates to a silicon carbide MOSFET with an integrated channel diode. This device features an additional N-type base region between the N+ source region and the P-type base region, giving it two key characteristics: 1) The P+ source region, the introduced N-type base region, and the original P-type base region form a JFET structure. By adjusting the drain-source voltage, the on-current can be controlled, thus regulating the channel resistance. When the drain-source voltage is low, the JFET's gate voltage is low, allowing for normal JFET operation, low channel resistance, and a large N-type base region conduction area. When the drain-source voltage is high, the JFET's gate voltage is high, resulting in high channel resistance and a small N-type base region conduction area. In this case, only a small number of electrons pass through the N-type base region after the silicon carbide MOSFET gate is turned on. However, when the device is in the forward conduction state, the drain-source voltage is only tens of volts. Therefore, the JFET control gate is at a low voltage, and the N-type base region of the device has a large conduction area. However, when the device is in an abnormal operating state such as a short circuit with a high drain-source voltage, the JFET control gate is at a high voltage, and the depletion of the N-type base region of the device is very obvious. At this time, the channel resistance when the device is turned on increases, thereby limiting the peak drain-source current of the device and allowing the device to withstand a longer short circuit withstand time. 2) Adjust the P+ region of the source trench downward so that a low-barrier MOS channel diode is introduced on the source gate of the device. When the device is working in the third quadrant, the current passes from the drain through the substrate, epitaxial region, through the P-base region channel, N-type base region and N+ source region and finally reaches the source.

[0025] However, the introduction of the N-type base region leads to an increase in the device's threshold voltage and channel resistance, as well as a decrease in its breakdown voltage. To improve the device's short-circuit reliability and third-quadrant performance without sacrificing other characteristics, we utilize the P+ region of the deep source trench and the current spread layer, along with a P-pillar region introduced at the bottom of the gate trench, to form a semi-superjunction structure. This allows the device to achieve a comprehensive improvement in static characteristics while maintaining high short-circuit reliability and superior third-quadrant performance. Furthermore, the introduction of the P-pillar region transforms the gate-drain capacitance below the gate into a drain-source capacitance, thus improving the device's dynamic characteristics. Therefore, this invention achieves an overall improvement in device performance.

[0026] like Figure 1 As shown, the silicon carbide MOSFET with integrated channel diode of the present invention includes, from bottom to top, a drain metal layer 17, a SiC-N substrate 1, a SiC-N epitaxial region 2, a SiC-N current spreading layer 3, a SiC-P pillar region 5, a SiC-P base region 6, a SiC-N base region 7, a SiC-P source region 9, a gate metal layer 14, an insulating dielectric layer 15, and a source metal layer 16; the SiC-N current spreading layer 3 has source trenches embedded on both sides, including a source trench P+ region 9, a source trench gate oxide layer 10, and a source trench gate N-type polysilicon 13; the N-type current spreading layer 3 has a source trench SiC-P+ region 4, a SiC-P pillar region 5, a gate trench, and a source trench; Example 2 The gate trench includes a trench gate oxide layer 11, a trench gate N-type polysilicon 12, and a gate metal layer 14; the source trench includes a source trench gate oxide layer 10, a source trench gate N-type polysilicon 13, and a source metal layer 16; a SiC-N type base region 7 is embedded with a SiC N-type source region 8; the SiC N-type source region 8 is surrounded by the source trench gate oxide layer 10, the SiC-N type base region 7, and the SiC-P type source region 9; the SiC-P type source region 9, the SiC N-type source region 8, and the source trench gate N-type polysilicon 13 are provided with a source metal layer 16; a gate metal layer 14 is provided on the trench gate N-type polysilicon 12; and a drain metal layer 17 is provided on the silicon carbide N-type substrate 1. An insulating dielectric layer 15 is disposed between the gate metal layer 14 and the source metal layer 16; the sidewall thickness of the source trench gate oxide layer 10 is between 20-40 nm; and the sidewall thickness of the trench gate oxide layer 11 is between 30-80 nm.

[0027] Example 3 The source trench includes a source trench gate oxide layer 10, which is adjacent to a SiC-N type base region 7, a SiC-P type source region 9, and a SiC-N type source region 8, respectively. The SiC-P type source region 9 is adjacent to a trench gate oxide layer 11, a SiC-N type source region 8, and a SiC-N type base region 7, respectively. The SiC-P type base region 6 is adjacent to a SiC-N type base region 7 and a SiC-N type current spread layer 3, respectively. The SiC-P type pillar region 5 is located in the middle of the SiC-N type current spread layer 3 and is adjacent to the trench gate oxide layer 11 above it. The source trench P+ region 9 is located at the left and right ends of the cell, adjacent to the source trench gate oxide layer 10, and has the same height as the SiC-P type pillar region 5. The cell of this device has a left-right symmetrical structure.

[0028] Example 4 The present invention discloses a method for fabricating a silicon carbide MOSFET with integrated channel diode, the process flow diagram of which is shown below. Figure 2 As shown, the specific steps include the following: Step 1: On an N-type doped 4H-SiC substrate with a diameter of 200.0 ± 0.25 mm, a crystal orientation of 4° <11-20> offset ± 0.25°, a substrate thickness of 350.0 ± 25.0 μm, a notch depth of 1 ~ 1.25 mm, and a doping concentration of 1 × 10⁻⁶ μm,... 19 cm -3 As SiC-N substrate 1, a SiC-N type epitaxial region 2 is epitaxially grown on SiC-N substrate 1, forming a doping concentration of 5×10⁻⁶. 15 ~1×10 16 cm -3 2. A SiC-N type epitaxial region with a drift region thickness of 5~11um.

[0029] On the surface of SiC-N epitaxial region 2, a layer with a thickness of 1.2~2.5 μm and a doping concentration of 2×10⁻⁶ was prepared by epitaxy. 16 ~1×10 17 cm -3 SiC-N type current-spreading layer 3, see Figure 3 .

[0030] Step 2: Using photolithography, two source trench SiC-P+ regions 4 are epitaxially grown on opposite sides of the SiC-N type current spreading layer 3, and a SiC-P type pillar region 5 is grown at the center of the SiC-N type current spreading layer 3. (See [link]). Figure 4 .

[0031] Step 3: Based on the previous step, grow an epitaxial layer with a thickness of 0.2~1.5µm and a doping concentration of 2×10⁻⁶. 16 ~1×10 17 cm -3The SiC-N type current spreading layer 3; a SiC-P type base region 6, a SiC-N type base region 7, a SiC-P type source region 9, and a SiC-N type source region 8 are formed on the SiC-N type current spreading layer 3, respectively. See [reference needed] Figure 5 .

[0032] Step 4: Trench etching is performed using inductively coupled plasma reactive ion etching (ICP-IR) with an etching gas mixture of SF6 / O2 / Ar (flow rate ratio: 30 / 60 / 170 sccm). Immediately after etching, passivation is performed using argon as the primary gas and SiH4 as a secondary gas to improve the interface condition of the trench sidewalls. See [link to relevant documentation]. Figure 6 .

[0033] Step 5: A gate dielectric layer is prepared using a dry oxidation process, comprising two source trench gate oxide layers 10 and one trench gate oxide layer 11, followed by high-temperature annealing in a nitrogen atmosphere at 1200-1300°C. Next, a polysilicon gate is deposited. N-type polysilicon is deposited within the source trench gate oxide layer 10 to form source trench gate N-type polysilicon 13, and N-type polysilicon is deposited within the trench gate oxide layer 11 to form trench gate N-type polysilicon 12. Specific steps include: growing polysilicon using low-pressure chemical vapor deposition (LPCVD), ion implantation of the polysilicon, planarization after annealing at 900°C, followed by polysilicon patterning, depositing metal above the trench gate N-type polysilicon 12, and etching to form a gate metal layer 14; an insulating dielectric layer 15 is then formed on this basis. See [link to relevant documentation]. Figure 7 .

[0034] Step 6: Deposit and etch metal to form source metal layer 16; form drain metal layer 17 on the lower surface of silicon carbide N-type doped substrate 1; wherein the metal uses Ti / Ni / Al alloy as ohmic contact material, and ohmic contact is achieved by annealing at an ambient temperature of 900~1100℃, see [link to relevant documentation]. Figure 8 .

[0035] Example 5 To verify the performance of the silicon carbide MOSFET with integrated channel diode of the present invention, a comparison was made between the conventional SiC DT-MOSFET and the silicon carbide MOSFET with integrated channel diode of the present invention. Figure 9 The curves show a comparison of the blocking characteristics of the conventional structure (DT-MOSFET) and the present invention (silicon carbide MOSFET with integrated channel diode). The breakdown voltage (BV) of the conventional structure is 1508V, while the breakdown voltage of the present invention is 1528V, representing a performance improvement of approximately 1.32%. Figure 10 This is a comparison curve of the output characteristics of the traditional structure and the present invention. The on-resistance (gate-source voltage) of the traditional structure is shown in the curve. V GS =15V, drain-source current (I DS (10A) is 70mΩ, and the on-resistance of the present invention is 62mΩ, a reduction of about 11.43%. Figure 11 This is a comparison curve of the transfer characteristics of the traditional structure and the present invention. The threshold voltage (drain-source voltage) of the traditional structure is shown in the curve. V DS =10V, I DS =1A) is 4.7V, and the threshold voltage of the present invention is 4.2V, a decrease of about 10.64%. Figure 12 This is a comparison curve of the third quadrant IV characteristics of the conventional structure and the present invention. The reverse turn-on voltage of the conventional structure ( V GS =0V, source and drain current ( I SD (1A) is 4.3V, and the threshold voltage of the present invention is 3.1V, a decrease of about 27.91%.

[0036] Example 6 Figure 13 This is a comparison curve of the gate charge characteristics of the conventional structure and the present invention. The gate leakage charge of the conventional structure ( Q GD The temperature of the original sample is 35 nC, while that of the present invention is 26 nC, representing a reduction of approximately 25.71%. Figure 14 The gate-drain capacitor of the present invention is compared with the conventional structure. C GD Characteristic comparison curves, traditional structure C GD 47pF / cm 2 The present invention C GD 15pF / cm 2 In SiC MOSFETs, switching characteristics are primarily dominated by gate-drain capacitance and gate-drain charge, and their charging and discharging processes are the main sources of switching losses and time. To address this, the structural design of this invention achieves higher breakdown voltage while specifically optimizing several key parameters: not only does it obtain lower on-resistance and threshold voltage, but it also significantly reduces... C GD and Q GD This signifies a simultaneous improvement in both the device's static characteristics and dynamic switching performance, ultimately translating into a comprehensive reduction in both static and dynamic power consumption.

[0037] Figure 15 This is a comparison curve of the reverse recovery characteristics of the traditional structure and the present invention. From Figure 15 As can be seen, the reverse recovery charge (Qrr) of the traditional structure is 1227 nC / cm. 2The structure Qrr proposed in this invention has a value of 786 nC / cm. 2 Therefore, the structure proposed in this invention can reduce the reverse conduction voltage and improve the reverse recovery characteristics of the device.

[0038] Figure 16 , 17 Curves 1 and 18 are comparison curves of the short-circuit characteristics of the traditional structure and the present invention at bus voltages of 400V, 600V, and 800V, respectively. Figure 16 The results show the short-circuit withstand time of the traditional structure when the bus voltage is 400V. t SCWT =11μs, the short-circuit withstand time of the present invention t SCWT =19μs, an increase of approximately 72.7%. The peak drain-source current of the conventional structure is 207A, while the peak drain-source current of this invention is 113A, a reduction of approximately 45.41%. From Figure 17 The results show the short-circuit withstand time of the traditional structure when the bus voltage is 600V. t SCWT =6μs, the short-circuit withstand time of this invention t SCWT =10μs, an increase of approximately 66%. The peak drain-source current of the conventional structure is 209A, while the peak drain-source current of this invention is 117A, a reduction of approximately 44.02%. From Figure 18 The results show the short-circuit withstand time of the traditional structure when the bus voltage is 800V. t SCWT =4μs, the short-circuit withstand time of the present invention t SCWT =6μs, an increase of approximately 50%. The peak drain-source current of the conventional structure is 212A, while the peak drain-source current of this invention is 118A, a reduction of approximately 44.34%. Therefore, the structure proposed in this invention achieves an improvement in short-circuit withstand time and a reduction in peak drain-source current across the entire bus voltage range of silicon carbide applications. This invention is a silicon carbide MOSFET with high short-circuit robustness and an integrated channel diode.

[0039] This invention relates to a silicon carbide MOSFET with high short-circuit robustness integrated with a channel diode. By integrating the channel diode, it solves the problems of high reverse turn-on voltage and poor reverse recovery characteristics in traditional structures. The proposed structure has a lower reverse turn-on voltage and better reverse recovery characteristics, thereby reducing the dynamic losses of the device. It also solves the problems of short short-circuit withstand time and high peak short-circuit current in traditional structures. This invention has better short-circuit robustness and a higher static FOM value. V B 2 / R SPThis invention achieves a comprehensive improvement in the static and dynamic characteristics and short-circuit robustness of the device, providing the industry with a high-performance and high-reliability device. Therefore, while reducing the reverse turn-on voltage of SiC MOSFETs, this invention optimizes reverse recovery characteristics and short-circuit reliability, marking a significant technological breakthrough and playing a crucial role in driving the entire silicon carbide power device industry towards higher-end and more reliable application areas.

Claims

1. A silicon carbide MOSFET with integrated channel diode, characterized in that: The structure includes, from bottom to top, a drain metal layer (17), a SiC-N substrate (1), a SiC-N epitaxial region (2), and a SiC-N current spread layer (3). Source trenches SiC-P+ regions (4) are provided on opposite sides of the N-type current spread layer (3), and a source trench is provided above each source trench SiC-P+ region (4). A SiC-P pillar region (5) is provided at the center of the N-type current spread layer (3), and a gate trench is provided above the SiC-P pillar region (5).

2. The integrated trench diode silicon carbide MOSFET of claim 1, wherein: The source trench includes a source trench gate oxide layer (10), and a source trench gate N-type polysilicon (13) is disposed within the source trench gate oxide layer (10).

3. The silicon carbide MOSFET with integrated channel diode according to claim 2, characterized in that: The gate trench includes a U-shaped trench gate oxide layer (11), and a trench gate N-type polysilicon (12) is disposed above the trench gate oxide layer (11).

4. The integrated trench diode silicon carbide MOSFET of claim 3, wherein: SiC-P type base region (6) and SiC-N type base region (7) are sequentially arranged above the SiC-N type current extension layer (3). SiC-P type source region (9) is arranged at the center of SiC-N type base region (7). SiC-N type source regions (8) are arranged on opposite sides of SiC-P type source region (9). Trench gate oxide layer (11) is disposed through the center of SiC-P type source region (9), SiC-N type base region (7) and SiC-P type base region (6).

5. The integrated trench diode silicon carbide MOSFET of claim 4, wherein: A source metal layer (16) is provided above the source trench gate N-type polysilicon (13), the source trench gate oxide layer (10), the SiC N-type source region (8), the source trench P+ region (9), the trench gate oxide layer (11), and the trench gate N-type polysilicon (12).

6. The silicon carbide MOSFET with integrated channel diode according to claim 4, characterized in that: An insulating isolation dielectric layer (15) is provided at the center of the source metal layer (16), and a gate metal layer (14) is wrapped inside the insulating isolation dielectric layer (15).

7. A method for fabricating a silicon carbide MOSFET with integrated channel diode, characterized in that: Specifically, the steps include the following: Step 1: SiC-N type epitaxial region (2) and SiC-N type current spreading layer (3) are sequentially formed on SiC-N substrate (1). Step 2: Two source trench SiC-P+ regions (4) and one SiC-P type pillar region (5) are grown in the SiC-N type current extension layer (3); Step 3: SiC-P type base region (6), SiC-N type base region (7), SiC-P type source region (9) and SiC N type source region (8) are formed on the SiC-N type current extension layer (3). Step 4: Etch source trenches and gate trenches on the SiC-P type base region (6) and the SiC-N type base region (7), respectively.

8. The method for fabricating a silicon carbide MOSFET with an integrated channel diode according to claim 7, characterized in that: A source metal layer (16) is formed above the SiC-P type source region (9) and the SiC N type source region (8), and a drain metal layer (17) is formed at the bottom of the SiC-N substrate (1).

9. The method for fabricating a silicon carbide MOSFET with an integrated channel diode according to claim 7, characterized in that: The source trench includes a source trench gate oxide layer (10), and N-type polysilicon is deposited in the source trench gate oxide layer (10) to generate source trench gate N-type polysilicon (13).

10. The method for fabricating a silicon carbide MOSFET with an integrated channel diode according to claim 7, characterized in that: The gate trench includes a trench gate oxide layer (11), and N-type polysilicon is deposited in the trench gate oxide layer (11) to generate trench gate N-type polysilicon (12).

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