Preparation method of semiconductor device and semiconductor device

Abstract

The invention relates to a preparation method of a semiconductor device and the semiconductor device. The preparation method comprises the steps of providing a semiconductor material layer; forming a first mask layer, wherein the first mask layer forms a first opening exposing the first region of the semiconductor material layer and at least shields the second region of the semiconductor material layer; performing a first ion implantation process on the first region based on the first mask layer to form a first drift region of the first conductive type; forming a second mask layer which forms a second opening exposing the second area and at least shields the first area; performing a second ion implantation process on the second region based on the second mask layer to form a first well region of the first conductive type; the second injection concentration of the second ion injection process is greater than the first injection concentration of the first ion injection process; forming a second drift region of a second conductive type; a first source region and a first drain region are respectively formed in the first well region and the second drift region. Therefore, the influence on the threshold voltage is reduced while the hot carrier effect is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor device and the semiconductor device itself. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) technology is an advanced manufacturing process that integrates bipolar transistors, CMOS (Complementary Metal-Oxide-Semiconductor), and DMOS (Double-Diffused Metal-Oxide-Semiconductor) on a single chip. This process significantly reduces chip area, lowers system power consumption, and improves energy efficiency and reliability, thus finding wide application in power management, automotive electronics, audio amplifiers, and other fields.

[0003] In integrated circuit chip manufacturing, the reliability of semiconductor devices (such as transistors) is one of the key performance indicators that determines whether a chip can function properly. Among these, the HCI (Hot Carrier Injection) effect is one of the core issues restricting device reliability. When a high voltage is applied to the drain terminal of a device, collisional ionization occurs in the channel region, generating hot carriers. The higher the collisional ionization concentration, the more high-energy hot carriers are generated. These high-energy hot carriers penetrate the gate dielectric, exacerbating the HCI effect.

[0004] Currently, the following three methods are commonly used to improve the HCI effect of devices: First, change the device material, for example, use a high-k dielectric material (such as HfO2) as the gate dielectric to achieve higher capacitance density and reduce operating voltage, or use strained silicon technology to stretch or compress the lattice to improve carrier mobility and reduce the need for high electric fields; Second, optimize the device structure, for example, form a gradient doped region at the drain end through LDD (Lightly Doped Drain) to disperse the electric field peak, or use a three-dimensional structure such as Fin FET (Fin Field-Effect Transistor) to strengthen the gate's control over the channel and reduce operating voltage; Third, design system-level protection, for example, design a dynamic voltage frequency adjustment system that reduces voltage in real time according to the load, or integrate an HCI lifetime prediction model through EDA (Electronic Design Automation) tools to optimize wiring during the design phase.

[0005] In addition, a new method for improving the high-conductivity interferometry (HCI) effect in devices has been proposed in recent years. Specifically, a drift region with the same conductivity type as the well region is added to the source end of the device, and doping is superimposed within the drift region to form a well region. Thus, the low-doped drift region and the high-doped well region constitute the source end doped region. The PN junction formed between the source end doped region and the drain end doped region (drain end drift region) exhibits a gradually changing junction, which can effectively reduce the collisional ionization concentration in the channel, thereby improving HCI. However, due to the superposition effect of the doping concentration in the source end drift region, the doping concentration of the source end well region formed by this method is increased, which increases the doping concentration in the channel, thereby increasing the threshold voltage of the device and increasing the turn-on power consumption.

[0006] Therefore, how to improve HCI while reducing its impact on the threshold voltage has become an urgent problem to be solved in this field. Summary of the Invention

[0007] In view of the above, this application provides a method for fabricating a semiconductor device and a semiconductor device to solve at least one problem existing in the background art.

[0008] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising: Provides a semiconductor material layer; A first mask layer is formed on the semiconductor material layer, the first mask layer having a first opening that exposes a first region of the semiconductor material layer, and the first mask layer at least covering a second region of the semiconductor material layer; A first ion implantation process is performed on the first region based on the first mask layer to form a first drift region having a first conductivity type; A second mask layer is formed on the semiconductor material layer, the second mask layer having a second opening that exposes the second region, and the second mask layer at least shielding the first region; A second ion implantation process is performed on the second region based on the second mask layer to form a first well region having a first conductivity type; wherein, the second implantation concentration of the first conductivity type ions in the second ion implantation process is greater than the first implantation concentration of the first conductivity type ions in the first ion implantation process, so that the doping concentration of the first well region is greater than the doping concentration of the first drift region. A second drift region having a second conductivity type is formed within the semiconductor material layer; wherein the first conductivity type and the second conductivity type are different; A first source region and a first drain region are formed in the first well region and the second drift region, respectively; wherein the first drift region and the first well region are used to form a channel between the first source region and the first drain region.

[0009] In conjunction with a first aspect of this application, in an alternative embodiment, the projections of the first opening and the second opening are spaced apart from each other along the thickness direction of the semiconductor material layer.

[0010] In conjunction with the first aspect of this application, in an optional embodiment, the first drift region includes a first region and a first lateral diffusion region located on the periphery of the first region; The first trap region includes a second region and a second lateral diffusion region located on the periphery of the second region; The portion where the first lateral diffusion region overlaps with the second lateral diffusion region constitutes a diffusion overlap region; Wherein, the net doping concentration of the first conductivity type ions in the diffusion overlap region is less than or equal to the net doping concentration of the first conductivity type ions in the second region.

[0011] In conjunction with the first aspect of this application, in an optional embodiment, the line width of the first opening is greater than or equal to the line width of the second opening.

[0012] In conjunction with the first aspect of this application, in an optional embodiment, the ratio of the line width of the first opening to the line width of the second opening is in the range of 1:1 to 2:1.

[0013] In conjunction with the first aspect of this application, in an optional embodiment, the method further includes: A third drift region having a first conductivity type is formed in a third region of the semiconductor material layer; a second drain region is formed within the third drift region; wherein... The first mask layer also has a third opening that exposes the third region, and ions are implanted simultaneously in the first region and the third region during the first ion implantation process.

[0014] Secondly, embodiments of this application provide a semiconductor device, including: Semiconductor material layer; The first drift region and the first well region are located within the semiconductor material layer and both have a first conductivity type. The bottom of the first well region is adjacent only to the undoped region of the semiconductor material layer that forms the first drift region. The doping concentration of the first well region is greater than that of the first drift region. The second drift region is located within the semiconductor material layer and has a second conductivity type different from the first conductivity type; The first source region and the first drain region are located within the first well region and the second drift region, respectively; wherein the first drift region and the first well region are used to form a channel between the first source region and the first drain region.

[0015] In conjunction with a second aspect of this application, in an optional embodiment, the first drift region includes a first region and a first lateral diffusion region located on the periphery of the first region; The first trap region includes a second region and a second lateral diffusion region located on the periphery of the second region; The portion where the first lateral diffusion region overlaps with the second lateral diffusion region constitutes a diffusion overlap region; Wherein, the net doping concentration of the first conductivity type ions in the diffusion overlap region is less than or equal to the net doping concentration of the first conductivity type ions in the second region.

[0016] In conjunction with a second aspect of this application, in an optional embodiment, the width of the first drift region is greater than or equal to the width of the first well region along a direction perpendicular to the thickness of the semiconductor material layer.

[0017] In conjunction with the second aspect of this application, in an optional embodiment, it further includes: a third drift region having a first conductivity type, located within the semiconductor material layer; wherein the third drift region and the first drift region are implanted within the same ion implantation process based on the same mask layer; The second drain region is located within the third drift region.

[0018] The semiconductor device fabrication method and semiconductor device provided in this application embodiment involve ion implantation during fabrication. Ion implantation is performed on a first mask layer exposing a first region and shielding a second region to form a first drift region. Ion implantation is then performed on a second mask layer exposing the second region and shielding the first region to form a first well region. This ensures that the implanted regions of the two ion implantations do not overlap, guaranteeing that the net doping concentration of the first well region will not passively increase due to the superimposed implantation with the first drift region, thereby reducing the threshold voltage and power consumption. Furthermore, the lower doping concentration of the first drift region and the higher doping concentration of the first well region form a doping gradient. The source-end doped region formed by these two regions can form a gradually changing junction with the drain-end doped region (the second drift region), reducing the degree of collisional ionization within the channel and improving the hot carrier effect. Therefore, the impact on the threshold voltage can be reduced while improving the hot carrier effect.

[0019] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0020] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1This is a schematic diagram of the cross-sectional structure of a PLDMOS device in the prior art; Figure 2 A schematic flowchart illustrating the fabrication method of the semiconductor device provided in the embodiments of this application; Figures 3 to 16 A cross-sectional structural diagram of the PLDMOS device provided in the embodiments of this application during the fabrication process; Figure 17 for Figure 10 A partially enlarged schematic diagram of the first drift region in the structure shown; Figure 18 for Figure 13 A partially enlarged schematic diagram of the first drift region and the first well region in the structure shown. Detailed Implementation

[0021] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0022] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0023] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0024] When an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0025] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship of one element or feature shown in the figure to other elements or features. In addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0027] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0028] Figure 1 This is a cross-sectional structural diagram of a PLDMOS device in related technologies. Specifically, the PLDMOS device is a P-type LDMOS device, i.e., a P-type laterally diffused metal-oxide semiconductor device.

[0029] Understandably, in related technologies, to improve the hot carrier effect, a doped region with a doping concentration gradient is formed at the source end. Specifically, a first drift region 410 of the first conductivity type is set between a first well region 420 of the first conductivity type and a second drift region 510 of the second conductivity type, thereby forming a doping concentration gradient between the first well region 420 with a higher doping concentration and the first drift region 410 with a lower doping concentration. In actual fabrication, specifically, while performing first conductivity type ion implantation on the semiconductor material layer 100 to form the drain end drift region of a semiconductor device (e.g., an NDMOS device), the first drift region 410 is formed simultaneously; while performing first conductivity type ion implantation on the semiconductor material layer 100 to form the source end well region of another semiconductor device (e.g., a CMOS device), the first well region 420 is superimposed and formed within the first drift region 410. Compared to the first well region 420 without the addition of the first drift region 410, the net doping concentration of the first conductivity type ions in the first well region 420 formed by the above method is higher.

[0030] Understandably, for ion implantation with the same conductivity type, the net doping concentration can be calculated by summing the concentrations of dopants of different conductivity types during ion implantation; for ion implantation with different conductivity types, the net doping concentration can be calculated by the difference between the concentrations of the first conductivity type dopant and the second conductivity type dopant during ion implantation. The net doping concentration of the first conductivity type ions in the first well region 420 formed by the above method is the superposition of the concentration of the first conductivity type dopant when forming the first drift region 410 and the concentration of the first conductivity type dopant when forming the first well region 420. This increases the doping concentration in the first well region 420, increases the doping concentration in the channel, and correspondingly increases the turn-on power consumption and threshold voltage of the PLDMOS device.

[0031] Furthermore, while forming the first drift region 410 and the first well region 420 of the PLDMOS device on the same mask layer as the doped regions of other semiconductor devices in the same ion implantation process can save steps, it also limits the PLDMOS device. For example, the implantation concentration of the first drift region 410 (corresponding to the drain end drift region of the NDMOS device) must preferentially meet the low on-resistance requirement of the NDMOS device, and its implantation dose is increased accordingly. This directly leads to a synchronous increase in the doping concentration of the first drift region 410, which in turn results in a higher net doping concentration in the subsequently superimposed first well region 420, further increasing the threshold voltage of the PLDMOS and increasing the turn-on power consumption.

[0032] Based on this, embodiments of this application provide a method for fabricating a semiconductor device. Please refer to... Figure 2 The preparation method includes: Step S1: Provide a semiconductor material layer; Step S2: A first mask layer is formed on the semiconductor material layer. The first mask layer has a first opening that exposes a first region of the semiconductor material layer. The first mask layer at least blocks a second region of the semiconductor material layer. Step S3: Perform a first ion implantation process on the first region based on the first mask layer to form a first drift region having a first conductivity type; Step S4: A second mask layer is formed on the semiconductor material layer. The second mask layer has a second opening that exposes the second region. The second mask layer at least blocks the first region. Step S5: Perform a second ion implantation process on the second region based on the second mask layer to form a first well region with a first conductivity type; wherein, the second implantation concentration of the first conductivity type ions in the second ion implantation process is greater than the first implantation concentration of the first conductivity type ions in the first ion implantation process, so that the doping concentration of the first well region is greater than the doping concentration of the first drift region. Step S6: Form a second drift region having a second conductivity type within the semiconductor material layer; wherein the first conductivity type and the second conductivity type are different; Step S7: A first source region and a first drain region are formed in the first well region and the second drift region, respectively; wherein, the first drift region and the first well region are used to form a channel between the first source region and the first drain region.

[0033] During fabrication, a first drift region is formed by doping a first mask layer that exposes the first region and blocks the second region, and a first well region is formed by doping a second mask layer that exposes the second region and blocks the first region. This ensures that the implanted regions of the two ion implantations do not overlap, guaranteeing that the net doping concentration of the first well region will not passively increase due to the superimposed implantation with the first drift region, thereby reducing the threshold voltage and power consumption. Furthermore, the lower doping concentration of the first drift region and the higher doping concentration of the first well region form a doping gradient. The source-end doped region formed by these two regions can form a gradually changing junction with the drain-end doped region (the second drift region), reducing the degree of collisional ionization within the channel and improving the hot carrier effect. Thus, the impact on the threshold voltage can be reduced while improving the hot carrier effect.

[0034] In the embodiments of this application, the source terminal refers to the location of the source region, and the drain terminal refers to the location of the drain region.

[0035] It should be noted that, although Figure 2 The steps are displayed sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Furthermore, Figure 2 At least some of the steps in the process may include multiple steps or multiple stages, which are not necessarily completed at the same time, nor are they necessarily executed sequentially.

[0036] Below, in conjunction with Figures 3 to 16 The schematic diagram of the cross-sectional structure of the PLDMOS device during the fabrication process shown below provides a further detailed explanation of the technical solution of this application.

[0037] It should be noted that the semiconductor device fabrication method provided in this application embodiment can be used for the fabrication of LDMOS devices, especially PLDMOS devices, but this does not mean that it is only applicable to the fabrication of LDMOS devices or PLDMOS devices. Obviously, other semiconductor devices with similar requirements can also be fabricated using the method provided in this application embodiment.

[0038] First, step S1 is performed to provide a semiconductor material layer.

[0039] In this embodiment, the semiconductor material layer can be a semiconductor substrate, or it can include an epitaxial layer grown on the semiconductor substrate. The semiconductor material layer has a second conductivity type. In this embodiment, taking a PLDMOS device as an example, the semiconductor material layer is a P-type semiconductor material layer.

[0040] In some embodiments, the fabrication method may further include forming an isolation ring having a first conductivity type in a semiconductor material layer. Thus, the isolation ring isolates the PLDMOS device from other adjacent devices in the BCD device, effectively blocking leakage current paths, preventing signal crosstalk, and suppressing latch-up effects.

[0041] The steps for forming an isolation ring with a first conductivity type in a semiconductor material layer are described below. Please refer to... Figure 3 A semiconductor substrate 101 having a second conductivity type is provided; a third mask layer 130 is formed on the semiconductor substrate 101; a third ion implantation process is performed on the semiconductor substrate 101 based on the third mask layer 130 to form a buried layer 210 having a first conductivity type; please refer to Figure 4 A first epitaxial layer 102 is epitaxially grown on a semiconductor substrate 101; please refer to... Figure 5 A fourth mask layer 140 is formed on the first epitaxial layer 102; a fourth ion implantation process is performed on the first epitaxial layer 102 based on the fourth mask layer 140 to form a deep well region 220 with a first conductivity type, the bottom of the deep well region 220 being adjacent to the buried layer 210; please refer to Figure 6 A second epitaxial layer 103 is epitaxially grown on the first epitaxial layer 102; please refer to Figure 8 A fifth mask layer 150 is formed on the second epitaxial layer 103; a fifth ion implantation process is performed on the second epitaxial layer 103 based on the fifth mask layer 150 to form a high-voltage drift region 230 with a first conductivity type, the bottom of the high-voltage drift region 230 being adjacent to the side of the deep well region 220 facing away from the buried layer 210; please refer to Figure 13 A second well region 240 with a first conductivity type is formed within the high-voltage drift region 230; please refer to Figure 16 A first heavily doped region 250 with a first conductivity type is formed within the second well region 240. The stacked semiconductor substrate 101, first epitaxial layer 102, and second epitaxial layer 103 constitute the semiconductor material layer 100. Along the thickness direction of the semiconductor material layer 100, the projections of the deep well region 220, high-voltage drift region 230, second well region 240, and first heavily doped region 250 are all annular, and the buried layer 210, deep well region 220, high-voltage drift region 230, second well region 240, and first heavily doped region 250 constitute an isolation ring.

[0042] Understandably, when the first conductivity type is N-type, the second conductivity type is P-type; and when the first conductivity type is P-type, the second conductivity type is N-type. In this embodiment, the first conductivity type is specifically N-type, and the second conductivity type is specifically P-type.

[0043] Specifically, the buried layer 210 is an N-type buried layer 210 (NBL), the deep well region 220 is specifically an N-type deep well region 220 (NDW), the high-voltage drift region 230 is specifically a high-voltage N-type drift region (HNDR), the second well region 240 is specifically an N-type well region (NW), and the first heavily doped region 250 is specifically an N+ region.

[0044] In some embodiments, the material of each mask layer may be photoresist.

[0045] In some embodiments, please refer to Figure 7 After forming the semiconductor material layer 100, the fabrication method may further include forming a shallow trench isolation structure at a first selected location on the semiconductor material layer 100. Therefore, when multiple doped regions with different conductivity types are subsequently formed on the surface of the semiconductor material layer 100, the shallow trench isolation structure can effectively prevent these doped regions from contacting or merging due to lateral diffusion, thereby ensuring the independence of each functional region of the device.

[0046] Please refer to Figure 9 In some embodiments, the fabrication method may further include forming a local oxide isolation structure 320 at a second selected location on the semiconductor material layer 100. Understandably, the second selected location is above a second drift region formed in a subsequent step, serving as a field oxygen structure. Specifically, the local oxide isolation structure 320 is, for example, a local oxide isolation of silicon (LOCOS) structure. In a specific example, the top surface of the local oxide isolation structure 320 protrudes from the surface of the semiconductor material layer 100.

[0047] Next, please refer to Figure 10 and Figure 17 Steps S2 and S3 are executed to form a first mask layer 110 on the semiconductor material layer 100. The first mask layer 110 has a first opening 111 that exposes a first region 411 of the semiconductor material layer 100, and the first mask layer 110 at least blocks a second region 421 of the semiconductor material layer 100. A first ion implantation process is performed on the first region 411 based on the first mask layer 110 to form a first drift region 410 having a first conductivity type. In this embodiment, the first drift region 410 is specifically an N-type drift region (NDR).

[0048] In one example, please refer to Figure 17The first drift region 410 includes a first region 411 and a first lateral diffusion region 412 located on the periphery of the first region 411. The implanted ions not only move longitudinally, forming a first region 411 with a high doping concentration directly below the first opening 111, but also diffuse laterally, forming a first lateral diffusion region 412 with a gradually decreasing doping concentration outwards. This phenomenon results in the actual first drift region 410 always being slightly larger in physical size than the geometry of the first opening 111.

[0049] In some embodiments, the net doping concentration of the first conductivity type ions in the first drift region 410 increases with the depth of the first drift region 410. Therefore, the net doping concentration of the first conductivity type ions at the top of the first drift region 410 is lower, and the top of the first drift region 410 is used to form a channel, which can effectively reduce on-resistance, turn-on power consumption, and threshold voltage; simultaneously, the net doping concentration of the first conductivity type ions at the bottom of the first drift region 410 is higher, which can effectively improve the withstand voltage.

[0050] Next, please refer to Figure 11 First, step S6 is executed to form a second drift region 510 with a second conductivity type within the semiconductor material layer 100; wherein the first conductivity type and the second conductivity type are different. In this embodiment, the second drift region 510 is specifically a P-type drift region (PDR). Specifically, a sixth mask layer 160 is formed on the semiconductor material layer 100; a sixth ion implantation process is performed on the semiconductor material layer 100 based on the sixth mask layer 160 to form the second drift region 510 with the second conductivity type.

[0051] In some embodiments, please refer to Figure 12 The fabrication method may further include: forming a seventh mask layer 170 on the semiconductor material layer 100; and performing a seventh ion implantation process on the semiconductor material layer 100 based on the seventh mask layer 170 to form a third well region 610 having a second conductivity type. In this embodiment, the third well region 610 is specifically a P-type well region (PW).

[0052] Next, please refer to Figure 13 and Figure 18 Steps S4 and S5 are executed to form a second mask layer 120 on the semiconductor material layer 100. The second mask layer 120 has a second opening 121 that exposes the second region 421, and the second mask layer 120 at least blocks the first region 411. A second ion implantation process is performed on the second region 421 based on the second mask layer 120 to form a first well region 420 having a first conductivity type. In this embodiment, the first well region 420 is specifically an N-type well region (NW).

[0053] Understandably, to mitigate the hot carrier effect, a gradually changing junction needs to be formed between the source and drain terminals. In related technologies, the first well region 420 is formed by superimposing implantation on the first drift region 410, and its doping concentration is necessarily greater than that of the first drift region 410, thus forming a doping gradient. In this application, the implantation regions of the first ion implantation process and the second ion implantation process do not overlap. To form a doping gradient, the embodiments of this application set the second implantation concentration of the first conductivity type ions in the second ion implantation process to be greater than the first implantation concentration of the first conductivity type ions in the first ion implantation process, so that the doping concentration of the first well region 420 is greater than that of the first drift region 410. Preferably, the ratio between the second implantation concentration and the first implantation concentration is in the range of 5:3 to 5:1. The range of the second implantation concentration is 4e12cm. -3 up to 1e13cm -3 .

[0054] In some embodiments, along the thickness direction of the semiconductor material layer 100, the projections of the first opening 111 and the second opening 121 are spaced apart from each other. This provides sufficient process margin for alignment between the first opening 111 of the first mask layer 110 and the second opening 121 of the second mask layer 120, reducing the requirements for mask layer overlay accuracy. Furthermore, it provides space for lateral diffusion after ion implantation, allowing controllable lateral diffusion between the first drift region 410 and the first well region 420, preventing the overlap of the highly concentrated first region 411 and the second region 421 to form a doped region with an even higher doping concentration. This would further increase the doping concentration in the channel, increase turn-on power consumption, and affect the gradually decreasing concentration gradient, exacerbating the hot carrier effect.

[0055] Please refer to Figure 18 In some embodiments, the first drift region 410 includes a first region 411 and a first lateral diffusion region 412 located on the periphery of the first region 411; the first well region 420 includes a second region 421 and a second lateral diffusion region 422 located on the periphery of the second region 421; the overlapping portion of the first lateral diffusion region 412 and the second lateral diffusion region 422 constitutes a diffusion overlap region 423; wherein the net doping concentration of the first conductivity type ions in the diffusion overlap region 423 is less than or equal to the net doping concentration of the first conductivity type ions in the second region 421. This ensures that no region with a higher doping concentration than the second region 421 of the first well region 420 is formed within the channel jointly formed by the first well region 420 and the first drift region 410, avoiding a rise in threshold voltage and improving the hot carrier effect.

[0056] In some embodiments, the linewidth of the first opening 111 is greater than or equal to the linewidth of the second opening 121. This makes the first drift region 410, with a lower doping concentration, wider than the first well region 420, with a higher doping concentration. This allows for a wider buffer zone, more effectively suppressing hot carrier generation and improving device reliability.

[0057] In one example, the ratio of the linewidth of the first opening 111 to the linewidth of the second opening 121 ranges from 1:1 to 2:1. Within this range, a balance can be achieved between hot carrier suppression and device size.

[0058] In the example where an isolation ring is formed within the semiconductor material layer 100, the second well region 240 and the first well region 420 are formed based on the same mask layer in the same ion implantation process. Specifically, please refer to... Figure 13 The second mask layer 120 also has an opening that exposes at least a portion of the high-voltage drift region 230; a second ion implantation process is performed on the high-voltage drift region 230 based on the second mask layer 120 to form a second well region 240 having a first conductivity type.

[0059] Please refer to Figure 14 The preparation method further includes: forming a gate structure on the semiconductor material layer 100; wherein, along the thickness direction of the semiconductor material layer 100, the gate structure at least partially overlaps with the first well region 420 and the first drift region 410, and the gate structure covers the region between the first drift region 410 and the second drift region 510.

[0060] Specifically, the gate structure may include a gate dielectric layer 330 and a gate 340 sequentially formed on the semiconductor material layer 100; furthermore, it may include a gate sidewall 350. The gate dielectric layer 330 may be a gate oxide layer, such as a silicon oxide layer. The gate 340 may be a polysilicon gate. The gate sidewall 350 covers the sidewalls of the gate 340; the material of the gate sidewall may be the same as the material of the gate dielectric layer 330.

[0061] Next, please refer to Figure 15 In one example, the fabrication method may further include: forming an eighth mask layer 180 on the semiconductor material layer 100; and performing an eighth ion implantation process on the third well region 610 based on the eighth mask layer 180 to form a body region 620 having a second conductivity type. In this embodiment, the body region 620 is specifically a P-type body region (PB).

[0062] Then, please refer to Figure 16Step S7 is executed, forming a first source region 430 and a first drain region 520 in the first well region 420 and the second drift region 510, respectively; wherein the first drift region 410 and the first well region 420 are used to form a channel between the first source region 430 and the first drain region 520. In this embodiment, the first source region 430 and the first drain region 520 have a second conductivity type and are both heavily doped regions, specifically the first source region 430 is a P+ region and the first drain region 520 is specifically a P+ region. In one example, the first source region 430 and the first drain region 520 are formed based on the same mask layer in the same ion implantation process.

[0063] Understandably, in the example of forming a body region 620 having a second conductivity type, the fabrication method may further include: forming a second heavily doped region 630 having a second conductivity type within the body region 620. The second heavily doped region 630 is formed in the same ion implantation process based on the same mask layer as the first source region 430 and / or the first drain region 520. In one example, the second heavily doped region 630 is isolated from the first heavily doped region 250 by a shallow channel isolation structure 310; and / or, the first heavily doped region 250 is isolated from the first drain region 520 by a shallow channel isolation structure 310.

[0064] The fabrication method may further include forming a body lead-out region 440 having a first conductivity type within the first well region 420. In this embodiment, the body lead-out region 440 is specifically an N-type body lead-out region, specifically an N+ region. The body lead-out region 440 and the first source region 430 are in lateral contact.

[0065] In an example where an isolation ring is formed in the semiconductor material layer 100, the first heavily doped region 250 and the body lead-out region 440 are formed in the same ion implantation process based on the same mask layer.

[0066] Finally, please refer to Figure 16 The fabrication method may further include: forming an interlayer dielectric film (not shown) on the semiconductor material layer 100; forming a contact hole through the interlayer dielectric film, the contact hole exposing a first source region 430, a body lead-out region 440, a first drain region 520, and a gate 340; filling contact plugs within the interlayer dielectric film and forming a metal layer on the upper surface of the interlayer dielectric film; and further forming a source electrode 712, a drain electrode 722, and a gate electrode 732 by photolithography etching; correspondingly, the contact plugs filled within the interlayer dielectric film are a source contact plug 711, a drain contact plug 721, and a gate contact plug 731, respectively. The source electrode 712 contacts the first source region 430 and the body lead-out region 440 through the source contact plug 711, the drain electrode 722 contacts the first drain region 520 through the drain contact plug 721, and the gate electrode 732 contacts the gate 340 through the gate contact plug 731.

[0067] In some examples, the contact hole also exposes a first heavily doped region 250 and a second heavily doped region 630; an isolation ring electrode 742 and a base electrode 752 are also formed on the interlayer dielectric film, and the contact plugs also include corresponding isolation ring contact plugs 741 and base contact plugs 751. The isolation ring electrode 742 contacts the isolation ring through the isolation ring contact plug 741, and the base electrode 752 contacts the semiconductor material layer 100 through the base contact plug 751. In some embodiments, the isolation ring electrode 742 is electrically connected to the source electrode 712.

[0068] Understandably, Figures 3 to 16 The fabrication process of a PLDMOS device is illustrated. In the BCD process, multiple semiconductor devices can be integrated through a semiconductor material layer 100. In related technologies, the first drift region 410 and the first well region 420 of the PLDMOS device are formed simultaneously while forming the doped regions of other semiconductor devices. This makes the doping concentration of the first drift region 410 and the first well region 420 limited by the doped regions of other semiconductor devices. If the implantation concentration of the ion implantation process forming the first drift region 410 and / or the first well region 420 is directly reduced to reduce the net doping concentration of the first well region 420, it will lead to a reduction in the doping concentration of the doped regions of other semiconductor devices, thereby affecting the function of other semiconductor devices. However, the fabrication method provided in this application, through mask layer design, ensures that the implanted regions of the two ion implantation processes do not overlap, and can reduce the net doping concentration of the first well region 420 without adjusting the implantation concentration, providing a basis for the integration process.

[0069] In some embodiments, the fabrication method may further include: forming a third drift region (not shown) having a first conductivity type in a third region of the semiconductor material layer 100; forming a second drain region within the third drift region; wherein the first mask layer 110 further forms a third opening (not shown) exposing the third region, and ions are simultaneously implanted into the first and third regions during the first ion implantation process. Therefore, the fabrication method provided in this application embodiment effectively reduces the doping concentration of the first well region 420 while allowing the first drift region 410 to still be formed simultaneously with the third drift region of another semiconductor device, exhibiting good compatibility with existing integrated circuit processes.

[0070] Correspondingly, embodiments of this application also provide a semiconductor device, please refer to... Figure 16 Semiconductor devices include: Semiconductor material layer 100; The first drift region 410 and the first well region 420 are located within the semiconductor material layer 100 and both have a first conductivity type. The bottom of the first well region 420 is only adjacent to the undoped region of the semiconductor material layer 100 that forms the first drift region 410. The doping concentration of the first well region 420 is greater than that of the first drift region 410. The second drift region 510 is located within the semiconductor material layer 100 and has a second conductivity type different from the first conductivity type; The first source region 430 and the first drain region 520 are located within the first well region 420 and the second drift region 510, respectively; wherein the first drift region 410 and the first well region 420 are used to form a channel between the first source region 430 and the first drain region 520.

[0071] By setting the bottom of the first well region 420 to be adjacent only to the undoped region of the semiconductor material layer 100 forming the first drift region 410, the net doping concentration of the first well region 420 is ensured not to passively increase due to the superimposed injection with the first drift region 410, thereby reducing the threshold voltage and power consumption. Furthermore, the lower doping concentration of the first drift region 410 and the higher doping concentration of the first well region 420 form a doping gradient. The source-end doped region formed by these two regions can form a gradually changing junction with the drain-end doped region (second drift region 510), reducing the degree of collisional ionization within the channel and improving the hot carrier effect. Thus, the impact on the threshold voltage can be reduced while improving the hot carrier effect.

[0072] In some embodiments, please refer to Figure 18 The first drift region 410 includes a first region 411 and a first lateral diffusion region 412 located on the periphery of the first region 411; the first well region 420 includes a second region 421 and a second lateral diffusion region 422 located on the periphery of the second region 421; the overlapping portion of the first lateral diffusion region 412 and the second lateral diffusion region 422 constitutes a diffusion overlap region 423; wherein, the net doping concentration of the first conductivity type ions in the diffusion overlap region 423 is less than or equal to the net doping concentration of the first conductivity type ions in the second region 421. This ensures that no region with a higher doping concentration than the first region 411 of the first well region 420 is formed within the channel jointly formed by the first well region 420 and the first drift region 410, avoiding an increase in threshold voltage and improving the hot carrier effect.

[0073] In some embodiments, the width of the first drift region 410 is greater than or equal to the width of the first well region 420 along a direction perpendicular to the thickness of the semiconductor material layer 100. This allows for a wider buffer zone, more effectively suppressing the generation of hot carriers and improving device reliability.

[0074] In some embodiments, the semiconductor device further includes: a third drift region having a first conductivity type, located within the semiconductor material layer 100; wherein the third drift region and the first drift region 410 are formed by implantation based on the same mask layer in the same ion implantation process; and a second drain region located within the third drift region. This effectively reduces the doping concentration of the first well region 420 while allowing the first drift region 410 to still be formed synchronously with the third drift region of another semiconductor device, resulting in good compatibility with existing integration processes.

[0075] It should be noted that the semiconductor device embodiments and the semiconductor device fabrication method embodiments provided in this application belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict. However, it should be further noted that the combination of technical features of the semiconductor device provided in the embodiments of this application can already solve the technical problem to be solved by this application; therefore, the semiconductor device provided in the embodiments of this application is not limited to the fabrication method of the semiconductor device provided in the embodiments of this application, and any semiconductor device prepared by a fabrication method that can form the semiconductor device structure provided in the embodiments of this application is within the scope of protection of this application.

[0076] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations included in the claims. Various modifications and changes can be made to the above embodiments without departing from the scope of this disclosure. Similarly, the various technical features of the above embodiments can be arbitrarily combined to form other embodiments of this application that may not be explicitly described. Therefore, the above embodiments only illustrate several implementations of this application and do not limit the scope of protection of this patent application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, The method includes: Provides a semiconductor material layer; A first mask layer is formed on the semiconductor material layer, the first mask layer having a first opening that exposes a first region of the semiconductor material layer, and the first mask layer at least covering a second region of the semiconductor material layer; A first ion implantation process is performed on the first region based on the first mask layer to form a first drift region having a first conductivity type; A second mask layer is formed on the semiconductor material layer, the second mask layer having a second opening that exposes the second region, and the second mask layer at least shielding the first region; A second ion implantation process is performed on the second region based on the second mask layer to form a first well region having a first conductivity type; wherein, the second implantation concentration of the first conductivity type ions in the second ion implantation process is greater than the first implantation concentration of the first conductivity type ions in the first ion implantation process, so that the doping concentration of the first well region is greater than the doping concentration of the first drift region. A second drift region having a second conductivity type is formed within the semiconductor material layer; wherein the first conductivity type and the second conductivity type are different; A first source region and a first drain region are formed in the first well region and the second drift region, respectively; wherein the first drift region and the first well region are used to form a channel between the first source region and the first drain region.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, Along the thickness direction of the semiconductor material layer, the projections of the first opening and the second opening are spaced apart from each other.

3. The method for fabricating a semiconductor device according to claim 1 or 2, characterized in that, The first drift region includes a first region and a first lateral diffusion region located on the periphery of the first region; The first trap region includes a second region and a second lateral diffusion region located on the periphery of the second region; The portion where the first lateral diffusion region overlaps with the second lateral diffusion region constitutes a diffusion overlap region; Wherein, the net doping concentration of the first conductivity type ions in the diffusion overlap region is less than or equal to the net doping concentration of the first conductivity type ions in the second region.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The line width of the first opening is greater than or equal to the line width of the second opening.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The ratio of the line width of the first opening to the line width of the second opening is in the range of 1:1 to 2:

1.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method further includes: A third drift region having a first conductivity type is formed in a third region of the semiconductor material layer; a second drain region is formed within the third drift region; wherein... The first mask layer also has a third opening that exposes the third region, and ions are implanted simultaneously in the first region and the third region during the first ion implantation process.

7. A semiconductor device, characterized in that, include: Semiconductor material layer; The first drift region and the first well region are located within the semiconductor material layer and both have a first conductivity type. The bottom of the first well region is adjacent only to the undoped region of the semiconductor material layer that forms the first drift region. The doping concentration of the first well region is greater than that of the first drift region. The second drift region is located within the semiconductor material layer and has a second conductivity type different from the first conductivity type; The first source region and the first drain region are located within the first well region and the second drift region, respectively; wherein the first drift region and the first well region are used to form a channel between the first source region and the first drain region.

8. The semiconductor device according to claim 7, characterized in that, The first drift region includes a first region and a first lateral diffusion region located on the periphery of the first region; The first trap region includes a second region and a second lateral diffusion region located on the periphery of the second region; The portion where the first lateral diffusion region overlaps with the second lateral diffusion region constitutes a diffusion overlap region; Wherein, the net doping concentration of the first conductivity type ions in the diffusion overlap region is less than or equal to the net doping concentration of the first conductivity type ions in the second region.

9. The semiconductor device according to claim 7, characterized in that, Along a direction perpendicular to the thickness of the semiconductor material layer, the width of the first drift region is greater than or equal to the width of the first well region.

10. The semiconductor device according to claim 7, characterized in that, Also includes: A third drift region having a first conductivity type is located within the semiconductor material layer; wherein the third drift region and the first drift region are formed by implantation based on the same mask layer in the same ion implantation process; The second drain region is located within the third drift region.

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