Semiconductor structure, manufacturing method thereof and electronic equipment

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and electronic equipment. The manufacturing method of the semiconductor structure comprises the following steps: manufacturing a plurality of first isolation structures on a substrate; a first signal line located between any two adjacent first isolation structures is manufactured; manufacturing a first insulating layer covering the first isolation structure and the first signal line; manufacturing a plurality of second isolation structures on the first insulating layer; manufacturing a second signal line between any two adjacent second isolation structures; manufacturing a second insulating layer covering the second isolation structure and the second signal line; forming a plurality of through holes penetrating through the second insulating layer, the second signal line and the first insulating layer; the bottom of the through hole exposes the first signal line; and sequentially manufacturing a semiconductor layer, a gate insulating layer and a conductive layer which at least cover and fill the plurality of through holes in a conformal manner to obtain a plurality of transistors. According to the invention, the hole problem is avoided, the channel length difference problem of the transistor is improved, and the stability and reliability of the process can be greatly improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and its manufacturing method, and an electronic device. Background Technology

[0002] With the development and progress of semiconductor technology, semiconductor devices are constantly moving towards miniaturization, high storage density, high integration, and low power consumption. At the same time, they are also facing problems and challenges from processes and other aspects. Summary of the Invention

[0003] This application proposes a semiconductor structure and its manufacturing method, as well as an electronic device, to solve the problems in related technologies where depositing oxides between small-sized metals easily generates voids, and thickness differences easily affect the stability of the channel length.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor structure, comprising: Multiple first isolation structures are fabricated on a substrate; the multiple first isolation structures are distributed along a first direction and each extends along a second direction, the first direction and the second direction intersect and are both parallel to the substrate; Create a first signal line located between any two adjacent first isolation structures; Fabricate a first insulating layer covering the first isolation structure and the first signal line; A plurality of second isolation structures are fabricated on a first insulating layer; the plurality of second isolation structures are distributed along a second direction and each extends along a first direction; Create a second signal line located between any two adjacent second isolation structures; Fabricate a second insulating layer covering the second isolation structure and the second signal line; Multiple through-holes are formed, penetrating the second insulating layer, the second signal line, and the first insulating layer; the bottom of the through-holes exposes the first signal line; Multiple transistors are obtained by sequentially fabricating a semiconductor layer, a gate insulating layer, and a conductive layer that conformally cover and fill multiple vias.

[0005] In some optional embodiments of this application, before fabricating a plurality of first isolation structures on the substrate, the method further includes: An interlayer insulating layer is fabricated on the substrate; In addition, a plurality of first isolation structures are fabricated on the substrate, including: A first insulating layer is fabricated on the interlayer insulation layer; The pattern is formed to create a plurality of first trenches that are spaced apart in a first direction and each extends along a second direction; the plurality of first trenches divide the first isolation layer into a plurality of first isolation structures.

[0006] In some optional embodiments of this application, fabricating a first signal line located between any two adjacent first isolation structures includes: A conductive material is deposited to form a first conductive layer; the first conductive layer fills the first trench and covers the first isolation structure. Planarization is performed until the first isolation structure is exposed, and the first conductive layer located in any of the first trenches forms a first signal line; the first signal line is flush with the surface of the first isolation structure.

[0007] In some optional embodiments of this application, fabricating a first insulating layer covering the first isolation structure and the first signal line includes: The first insulating layer is formed using atomic layer deposition (ALD) technology. In addition, a plurality of second insulating structures are fabricated on the first insulating layer, including: The second isolation layer is formed using atomic layer deposition (ALD) technology. The pattern is formed to create a plurality of second trenches that are spaced apart in a second direction and each extends along a first direction; the plurality of second trenches divide the second isolation layer into a plurality of second isolation structures.

[0008] In some optional embodiments of this application, fabricating a second signal line located between any two adjacent second isolation structures includes: A conductive material is deposited to form a second conductive layer; the second conductive layer fills the second trench and covers the second isolation structure. Planarization is performed until the second isolation structure is exposed, and the second conductive layer located in any of the second trenches forms a second signal line; the surface of the second signal line and the second isolation structure are flush.

[0009] In some optional embodiments of this application, fabricating a second insulating layer covering the second isolation structure and the second signal line includes: The second insulating layer is formed using atomic layer deposition (ALD) technology. In addition, forming a plurality of through-holes penetrating the second insulating layer, the second signal line, and the first insulating layer, including: The second insulating layer, the second signal line, and the first insulating layer are etched to expose the first signal line, forming multiple vias arranged in an array in the first and second directions.

[0010] Secondly, embodiments of this application provide a semiconductor structure, including: Multiple first isolation structures and multiple first signal lines are disposed on a substrate, and are alternately distributed along a first direction and each extends along a second direction; The first insulating layer is disposed on each first isolation structure and each first signal line; Multiple second isolation structures and multiple second signal lines are disposed on the first insulating layer, and are alternately distributed along the second direction and each extends along the first direction; The second insulating layer is disposed on each second isolation structure and each second signal line; A plurality of transistors, each transistor including at least a conductive layer extending in a direction perpendicular to the substrate and a gate insulating layer and a semiconductor layer sequentially disposed around the outer periphery of the conductive layer, the semiconductor layer being electrically connected to a first signal line and a second signal line.

[0011] In some optional embodiments of this application, at least one of the following is included: The semiconductor structure also includes an interlayer insulating layer disposed on the substrate and located on the side of each first isolation structure and each first signal line closer to the substrate; The surfaces of the first signal line and the first isolation structure on the side away from the substrate are flush; The second signal line and the second isolation structure are flush with the surface on the side away from the substrate.

[0012] In some optional embodiments of this application, at least one of the following is included: Multiple transistors are arranged in an array in a first direction and a second direction. Several transistors arranged sequentially along the first direction are electrically connected to a second signal line, and several transistors arranged sequentially along the second direction are electrically connected to a first signal line. The semiconductor layer located between the first signal line and the second signal line serves as the channel region of the transistor, and the conductive layer corresponding to the channel region serves as the gate of the transistor. The first signal line serves as one of the source and drain terminals, and the second signal line serves as the other of the source and drain terminals.

[0013] Thirdly, embodiments of this application provide an electronic device, including: A semiconductor structure manufactured using the semiconductor structure manufacturing method described above; or, The semiconductor structure described above.

[0014] The beneficial technical effects of the technical solutions provided in this application include: The semiconductor structure manufacturing method provided in this application not only allows for the fabrication of isolation structures before signal lines, such as fabricating a first isolation structure before a first signal line or a second isolation structure before a second signal line, but also improves the uniformity and filling effect of the conductive film obtained by backfilling conductive material. Therefore, it is less likely to generate voids when fabricating signal lines between insulating isolation structures, avoiding the problem of voids easily generated when depositing oxides between small-sized metals in related technologies. Furthermore, it can define the channel length through a first insulating layer, and reduce thickness differences by adjusting or selecting the fabrication process of the first insulating layer, thereby improving the problem of transistor channel length differences and greatly enhancing the stability and reliability of the process.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0016] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this application; Figures 2 to 26 This is a schematic diagram of a semiconductor structure manufacturing method provided in this application at different processes.

[0017] Figure label: 100-Semiconductor structure; 10-Substrate; 20-Interlayer insulation layer; 30 - First isolation structure; 31 - First isolation layer; 41-First trench; 42-Second trench; 50 - First signal line; 51 - First conductive layer; 60 - First insulating layer; 70 - Second isolation structure; 71 - Second isolation layer; 80 - Second signal line; 81 - Second conductive layer; 90 - Second insulating layer; 101 - Through hole; 110-transistor; 111 - Semiconductor layer; 112 - Gate insulating layer; 113 - Conductive layer. Detailed Implementation

[0018] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0019] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, and / or components, but does not exclude implementation as other features, information, data, steps, operations, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] In existing ring-channel transistor (RCT) process flows, the deposition of oxide (OXide) using PECVD (Plasma Enhanced Chemical Vapor Deposition) based on TEOS (liquid silicon) between small-sized metal layers can easily lead to voids within the OX. Due to the effects of CVD deposition and the CMP (Chemical Mechanical Polishing) process itself, voids can easily be opened after CMP in both the within-wafer (WIW) and WTW (Wafer to Wafer) layers. In subsequent process steps, conductive material may fill these open voids, potentially causing contact shorts in the transistor. Furthermore, variations in OX thickness can affect the stability of the channel length.

[0022] The semiconductor structure, its manufacturing method, and electronic device provided in this application are intended to solve the aforementioned technical problems in related technologies.

[0023] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0024] This application provides a method for manufacturing a semiconductor structure, and the flowchart of the method is shown below. Figure 1 As shown, schematic diagrams of the semiconductor structure fabrication method at different stages are illustrated below. Figures 2 to 26 As shown, the method for manufacturing this semiconductor structure includes: S101. A plurality of first isolation structures 30 are fabricated on the substrate 10. The plurality of first isolation structures 30 are distributed along a first direction and each extends along a second direction. The first direction and the second direction intersect and are both parallel to the substrate 10. S102. Fabricate a first signal line 50 located between any two adjacent first isolation structures 30; S103. Fabricate a first insulating layer 60 covering the first isolation structure 30 and the first signal line 50; S104. A plurality of second isolation structures 70 are fabricated on the first insulating layer 60; the plurality of second isolation structures 70 are distributed along the second direction and each extends along the first direction; S105. Fabricate a second signal line 80 located between any two adjacent second isolation structures 70; S106. Fabricate a second insulating layer 90 covering the second isolation structure 70 and the second signal line 80; S107, Forming a plurality of through holes 101 penetrating the second insulating layer 90, the second signal line 80 and the first insulating layer 60; The bottom of the through holes 101 exposes the first signal line 50; S108. A semiconductor layer 111, a gate insulating layer 112, and a conductive layer 113 are sequentially fabricated to cover and fill at least a plurality of vias 101, thereby obtaining a plurality of transistors 110.

[0025] In this embodiment, a plurality of first isolation structures 30 are firstly fabricated, and then a first signal line 50 is fabricated between two adjacent first isolation structures 30. The first signal line 50 is fabricated by backfilling conductive material between two first isolation structures 30. The filling uniformity is better, the filling effect is better, and it is less likely to produce voids. This can avoid the problem of voids easily generated when depositing OX between small-sized metals in related technologies.

[0026] Next, a first insulating layer 60 is fabricated, which covers the first isolation structure 30 and the first signal line 50. The first insulating layer 60 can electrically isolate the first signal line 50 from the subsequently fabricated second signal line 80. Furthermore, by adjusting or selecting the fabrication process of the first insulating layer 60, the thickness difference can be reduced, thus improving the transistor channel length difference problem.

[0027] First, multiple second isolation structures 70 are fabricated. Then, a second signal line 80 is fabricated between two adjacent second isolation structures 70. The second signal line 80 is fabricated by backfilling conductive material between two second isolation structures 70. This method has better filling uniformity and filling effect, and is less likely to produce voids. It can avoid the problem of voids that are easily generated when depositing OX between small-sized metals in related technologies.

[0028] Next, a second insulating layer 90 is fabricated, which covers the second isolation structure 70 and the second signal line 80. The second insulating layer 90 can electrically isolate the second signal line 80 from the subsequently fabricated semiconductor layer 111.

[0029] Then, a plurality of through holes 101 are formed through the second insulating layer 90, the second signal line 80 and the first insulating layer 60. The sides of the through holes 101 expose the second insulating layer 90, the second signal line 80 and the first insulating layer 60 respectively, and the bottom exposes the first signal line 50, so as to facilitate the subsequent fabrication of transistors.

[0030] Then, a semiconductor layer 111, a gate insulating layer 112, and a conductive layer 113 are fabricated sequentially. The semiconductor layer 111 conformally covers at least the inner wall of the via 101. The semiconductor layer 111 is electrically connected to the first signal line 50 and the second signal line 80, respectively. The semiconductor layer located between the first signal line 50 and the second signal line 80 serves as the channel region. The first insulating layer 60 defines the length of the channel region. By selecting an appropriate fabrication process to fabricate the first insulating layer 60, thickness differences are reduced, improving the transistor channel length difference problem, thereby greatly improving the stability and reliability of the process. The gate insulating layer 112 covers the semiconductor layer 111, and the conductive layer 113 covers the gate insulating layer 112 and fills the via 101. The conductive layer 113 is electrically isolated from the semiconductor layer 111 through the gate insulating layer 112. The conductive layer 113 includes a gate corresponding to the channel region. A corresponding channel region and a gate form a transistor 110.

[0031] The semiconductor structure manufacturing method provided in this application not only allows for the fabrication of isolation structures before signal lines, such as fabricating the first isolation structure 30 before the first signal line 50, or the second isolation structure 70 before the second signal line 80, but also improves the uniformity and filling effect of the conductive film obtained by backfilling conductive material. Therefore, it is less likely to generate voids when fabricating signal lines between insulating isolation structures, avoiding the problem of voids easily generated when depositing OX between small-sized metals in related technologies. Furthermore, the first insulating layer 60 defines the channel length, and by adjusting or selecting the fabrication process of the first insulating layer 60, the thickness difference can be reduced, improving the transistor channel length difference problem, thereby greatly improving the stability and reliability of the process.

[0032] It should be noted that, in the embodiments of this application, the first direction is... Figure 3 , Figure 4 , Figure 6 , Figure 8 , Figure 9 , Figure 11 , Figure 13 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 23 and Figure 25 The middle a-a' direction is parallel, and the second direction is parallel to... Figure 3 , Figure 5 , Figure 7 , Figure 8 , Figure 10 , Figure 12 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21 , Figure 22 , Figure 24 and Figure 26 The middle b-b' direction is parallel.

[0033] Optionally, in this embodiment, the substrate 10 may be made of a semiconductor material. Optionally, the semiconductor material may include, but is not limited to, silicon.

[0034] In some optional embodiments of this application, such as Figure 2 As shown, before fabricating a plurality of first isolation structures 30 on substrate 10, the method for manufacturing the semiconductor structure further includes: An interlayer insulating layer 20 is fabricated on the substrate 10. The interlayer insulating layer 20 is located between the substrate 10 and the subsequently fabricated first isolation structure 30 and first signal line 50, and electrical isolation between the substrate 10 and the subsequently fabricated first signal line 50 can be achieved through the interlayer insulating layer 20.

[0035] Optionally, in the embodiments of this application, the material of the interlayer insulating layer 20 includes, but is not limited to, oxides, such as SiO or SiO2.

[0036] In some optional embodiments of this application, such as Figures 2 to 5 As shown, a plurality of first isolation structures 30 are fabricated on the substrate 10, including: like Figure 2 As shown, a first insulating layer 31 is formed on the interlayer insulating layer 20. The first insulating layer 31 covers the interlayer insulating layer 20.

[0037] Optionally, in this embodiment, the material of the first isolation layer 31 includes, but is not limited to, SiN. SiN can be deposited on the interlayer insulating layer 20 using thin-film deposition technology to form the first isolation layer 31.

[0038] Next, as Figures 3 to 5 As shown, the pattern is formed to create a plurality of first grooves 41 that are spaced apart in a first direction and each extends along a second direction; the plurality of first grooves 41 divide the first isolation layer 31 into a plurality of first isolation structures 30.

[0039] In this embodiment of the application, there is a first isolation structure 30 between any two adjacent first trenches 41, and there is a first trench 41 between any two adjacent first isolation structures 30. The first trenches 41 and the first isolation structures 30 are alternately distributed in the first direction and each extends along the second direction.

[0040] Optionally, in this embodiment, the first isolation layer 31 is etched using a photolithography process to form a plurality of first trenches 41. Optionally, a positive resist negative development technique is used for photolithography to etch a plurality of first trenches 41 on the first isolation layer 31 to obtain a plurality of first isolation structures 30.

[0041] In some optional embodiments of this application, such as Figures 6 to 10 As shown, fabricating a first signal line 50 located between any two adjacent first isolation structures 30 includes: like Figure 6 and Figure 7 As shown, a conductive material is deposited to form a first conductive layer 51; the first conductive layer 51 fills the first trench 41 and covers the first isolation structure 30.

[0042] Optionally, in this embodiment, the material of the first conductive layer 51 includes, but is not limited to, W, TiN, etc. Optionally, the material of the first conductive layer 51 is W, and a process of backfilling metal W between the first isolation structure 30 is adopted, resulting in a thin film with better uniformity of filling, better filling effect, and less likelihood of forming voids.

[0043] Next, as Figures 8 to 10 As shown, planarization is performed until the first isolation structure 30 is exposed, and the first conductive layer located in any of the first trenches 41 forms a first signal line 50; the surface of the first signal line 50 is flush with the surface of the first isolation structure 30.

[0044] In this embodiment, the first conductive layer located on the side of the first isolation structure 30 away from the substrate 10 is removed by planarization, while the first conductive layer located in the first trench 41 is retained. The first conductive layer that is not removed in each first trench 41 forms a first signal line 50. Multiple first signal lines 50 and multiple first isolation structures 30 are sequentially and alternately distributed in a first direction, and each extends along a second direction. A first isolation structure 30 is located between any two adjacent first signal lines 50, and electrical isolation is achieved through this first isolation structure 30.

[0045] Optionally, in this embodiment of the application, the first conductive layer 51 is polished by CMP process, with the first isolation structure 30 as the polishing barrier layer, and polishing is stopped when the first isolation structure 30 is exposed, so that the obtained first signal line 50 and the surface of the first isolation structure 30 away from the substrate 10 are flush, thus achieving better planarization.

[0046] In this embodiment, the surfaces of the first signal line 50 and the first isolation structure 30 away from the substrate 10 are flush, so that the bottom surface of the subsequently fabricated first insulating layer 60 (i.e. the surface near the first signal line 50 and the first isolation structure 30) is on the same horizontal plane, which facilitates the control of the thickness of the first insulating layer 60, reduces thickness differences, and improves the problem of transistor channel length differences.

[0047] It should be noted that in this embodiment, the horizontal plane is parallel to the substrate 10, that is, parallel to the first direction and the second direction. The bottom surface of the first insulating layer 60 is located on the same horizontal plane, that is, the distances from each point on the bottom surface of the first insulating layer 60 relative to a point on the substrate 10 (or a line or surface parallel to the first direction and the second direction) in the direction perpendicular to the substrate 10 are equal.

[0048] In some optional embodiments of this application, such as Figure 11 and Figure 12 As shown, fabricating a first insulating layer 60 covering the first isolation structure 30 and the first signal line 50 includes: A first insulating layer 60 is formed using atomic layer deposition (ALD). The first insulating layer 60 covers the first signal line 50 and is located below the subsequently fabricated second signal line 80. The first insulating layer 60 enables electrical isolation between the first signal line 50 and the subsequently fabricated second signal line 80.

[0049] Optionally, in the embodiments of this application, the material of the first insulating layer 60 includes, but is not limited to, Oxide, such as SiO or SiO2.

[0050] In some optional embodiments of this application, such as Figures 11 to 15As shown, a plurality of second insulating structures 70 are fabricated on the first insulating layer 60, including: like Figure 11 and Figure 12 As shown, a second insulating layer 71 is formed using atomic layer deposition (ALD) technology. The second insulating layer 71 covers the first insulating layer 60.

[0051] Optionally, in this embodiment, the material of the second isolation layer 71 includes, but is not limited to, SiN.

[0052] Next, as Figures 13 to 15 As shown, the pattern is formed to create a plurality of second trenches 42 that are spaced apart in a second direction and each extends along a first direction; the plurality of second trenches 42 divide the second isolation layer 71 into a plurality of second isolation structures 70.

[0053] In this embodiment of the application, there is a second isolation structure 70 between any two adjacent second trenches 42, and there is a second trench 42 between any two adjacent second isolation structures 70. The multiple second trenches 42 and the multiple second isolation structures 70 are alternately distributed in the second direction and each extends along the first direction.

[0054] Optionally, in this embodiment, the second isolation layer 71 is etched using a photolithography process to form a plurality of second trenches 42. Optionally, a positive resist negative development technique is used for photolithography to etch a plurality of second trenches 42 on the second isolation layer 71, thereby obtaining a plurality of second isolation structures 70.

[0055] In some optional embodiments of this application, such as Figures 16 to 19 As shown, fabricating a second signal line 80 located between any two adjacent second isolation structures 70 includes: like Figure 16 and Figure 17 As shown, a conductive material is deposited to form a second conductive layer 81; the second conductive layer 81 fills the second trench 42 and covers the second isolation structure 70.

[0056] Optionally, in this embodiment, the material of the second conductive layer 81 includes, but is not limited to, W, TiN, etc. The conductive material can be deposited using thin-film deposition technology to form the second conductive layer 81.

[0057] Optionally, the material of the second conductive layer 81 is W, and a process of backfilling metal W between the second isolation structure 70 is adopted, resulting in a thin film with better uniformity of filling, better filling effect, and less likelihood of generating voids.

[0058] Next, as Figure 18 and Figure 19As shown, planarization is performed until the second isolation structure 70 is exposed, and the second conductive layer located in any of the second trenches 42 forms a second signal line 80; the surfaces of the second signal line 80 and the second isolation structure 70 are flush.

[0059] In this embodiment, the second conductive layer located on the side of the second isolation structure 70 away from the substrate 10 is removed by planarization, while the second conductive layer located in the second trench 42 is retained. The second conductive layer that is not removed in each second trench 42 forms a second signal line 80. The plurality of second signal lines 80 and the plurality of second isolation structures 70 are sequentially and alternately distributed in the second direction, and each extends along the first direction.

[0060] In this embodiment, a second isolation structure 70 is provided between any two adjacent second signal lines 80, and electrical isolation is achieved through the second isolation structure 70. The first isolation structure 30 and the first signal line 50 are located on the side of the first insulating layer 60 closer to the substrate 10, and the second signal line 80 and the second isolation structure 70 are located on the side of the first insulating layer 60 away from the substrate 10. Electrical isolation between the first signal line 50 and the second signal line 80 can be achieved through the first insulating layer 60.

[0061] Optionally, in this embodiment, the second conductive layer 81 is polished by CMP process, with the second isolation structure 70 as the polishing barrier layer, and polishing is stopped when the second isolation structure 70 is exposed, so that the surface of the obtained second signal line 80 and the side of the second isolation structure 70 away from the substrate 10 is flush, thus achieving better planarization.

[0062] In this embodiment, the surfaces of the second signal line 80 and the second isolation structure 70 away from the substrate 10 are flush, so that the bottom surface of the subsequently fabricated second insulating layer 90 (i.e. the surface near the second signal line 80 and the second isolation structure 70) is on the same horizontal plane, which facilitates the control of the thickness of the second insulating layer 90, reduces thickness differences, and improves the problem of transistor channel length differences.

[0063] In some optional embodiments of this application, such as Figure 20 and Figure 21 As shown, fabricating a second insulating layer 90 covering the second isolation structure 70 and the second signal line 80 includes: A second insulating layer 90 is formed using atomic layer deposition (ALD) technology. The second insulating layer 90 covers the second signal line 80, and electrical isolation between the second signal line 80 and the subsequently fabricated semiconductor layer 111 is achieved through the second insulating layer 90.

[0064] Optionally, in the embodiments of this application, the material of the second insulating layer 90 includes, but is not limited to, Oxide, such as SiO or SiO2.

[0065] In some optional embodiments of this application, such as Figures 22 to 24 As shown, a plurality of through holes 101 are formed penetrating the second insulating layer 90, the second signal line 80, and the first insulating layer 60, including: The second insulating layer 90, the second signal line 80 and the first insulating layer 60 are etched until the first signal line 50 is exposed, forming a plurality of through holes 101 arranged in an array in the first direction and the second direction.

[0066] In this embodiment, the side portion of each through hole 101 exposes the first insulating layer 60, the second signal line 80, and the second insulating layer 90, respectively, and the bottom portion exposes the first signal line 50, so that the semiconductor layer 111 subsequently fabricated can be electrically connected to the first signal line 50 and the second signal line 80 exposed in the through hole 101.

[0067] Optionally, in this embodiment, the second insulating layer 90, the second signal line 80, and the first insulating layer 60 are etched using a photolithography process until the first signal line 50 is exposed or a portion of the first signal line 50 is removed, forming a plurality of vias 101. Optionally, a positive resist and negative development technique is used for photolithography to obtain the plurality of vias 101.

[0068] In some optional embodiments of this application, such as Figure 25 and Figure 26 As shown, a semiconductor layer 111, a gate insulating layer 112, and a conductive layer 113 are sequentially fabricated to conformally cover and fill at least a plurality of vias 101, including: A channel material, an insulating material, and a conductive material are deposited sequentially to form a semiconductor layer 111, a gate insulating layer 112, and a conductive layer 113. The semiconductor layer 111 conformally covers the via 101 and the second insulating layer 90. The gate insulating layer 112 covers the semiconductor layer 111, and the conductive layer 113 covers the gate insulating layer 112 and fills the via 101.

[0069] In this embodiment, the semiconductor layer 111 is electrically connected to the first signal line 50 and the second signal line 80 exposed in each via 101. The first signal line 50 and the second signal line 80 serve as the source and drain of the transistor 110, respectively, and the semiconductor layer located between the first signal line 50 and the second signal line 80 serves as the channel region of the transistor 110.

[0070] The first insulating layer 60 is located between the first signal line 50 and the second signal line 80. The thickness of the first insulating layer 60 defines the channel length. The small difference in the thickness of the first insulating layer 60 results in high uniformity and stability of the channel length, which helps to improve the performance of the semiconductor structure and alleviate the problem of transistor channel length differences.

[0071] Semiconductor layer 111 is electrically isolated from conductive layer 113 via gate insulating layer 112. Conductive layer 113 includes a gate corresponding to the channel region, a first signal line 50, a channel region, a second signal line 80, gate insulating layer 112, and gate forming transistor 110. Gate insulating layer 112 and channel region are sequentially arranged around the outer periphery of the gate in a direction away from the gate, and transistor 110 is a ring-channel transistor. Vias 101 are arrayed in a first direction and a second direction, such that the fabricated transistors 110 are arrayed in the first direction and a second direction.

[0072] Optionally, in this embodiment, the first signal line 50 serves as one of the drain and source of the transistor 110, and the second signal line 80 serves as the other of the drain and source of the transistor 110. Optionally, the first signal line 50 serves as the drain, and the second signal line 80 serves as the source.

[0073] Optionally, such as Figure 26 As shown in the embodiment of this application, the first signal line 50 extends along a second direction, and a plurality of transistors 110 sequentially distributed in the second direction are electrically connected to the same first signal line 50, that is, they share a single first signal line 50. Figure 25 As shown in the embodiment of this application, the second signal line 80 extends along the first direction, and a plurality of transistors 110 distributed sequentially along the first direction are electrically connected to the same second signal line 80, that is, they share a single second signal line 80. This reduces the number of traces, which is beneficial for layout design, improving structural density and practicality.

[0074] Optionally, in this embodiment, the channel material includes, but is not limited to, IGZO. The material of the gate insulating layer 112 includes, but is not limited to, HK (High-K, i.e., high dielectric constant material, high dielectric constant material includes dielectrics with a dielectric constant K greater than or equal to 3.9) materials, such as Al2O3. The material of the conductive layer 113 includes, but is not limited to, ITO.

[0075] The semiconductor structure manufacturing method provided in this application can be applied to the field of semiconductor device fabrication.

[0076] Optionally, the semiconductor structure manufacturing method provided in this application embodiment can be used as a process method to improve the void of IGZO ring channel transistors and enhance the stability of channel length.

[0077] First, a first isolation layer 31 is formed by SiN deposition. Then, multiple first trenches 41 are etched on the first isolation layer 31 by photolithography (such as positive resist negative development technology). Next, W is deposited to form a first conductive layer 51. Then, W is polished by CMP, with SIN as a stop layer, to obtain the first signal line 50. Then, OX is deposited by ALD to form a first insulating layer 60. The OX thin film (i.e. the first insulating layer 60) is only affected by ALD deposition in WIW and WTW, and the thickness difference is small.

[0078] Therefore, by fabricating the isolation structure first and then the signal line (e.g., fabricating the first isolation structure 30 first and then the first signal line 50, or fabricating the second isolation structure 70 first and then the second signal line 80), the backfill metal W process can be used to obtain a thin film with better uniformity and filling effect, thus improving the void problem. Furthermore, by depositing OX through ALD, the thickness difference of the OX thin film can be reduced, and the channel length can be defined by the thickness of the OX thin film, which can improve the transistor channel length difference problem and greatly improve the stability and reliability of the process.

[0079] Based on the same inventive concept, this application provides a semiconductor structure 100, the schematic diagram of which is shown below. Figure 25 and Figure 26 As shown, the semiconductor structure 100 includes: a plurality of first isolation structures 30, a plurality of first signal lines 50, a first insulating layer 60, a plurality of second isolation structures 70, a plurality of second signal lines 80, a second insulating layer 90, and a plurality of transistors 110.

[0080] Multiple first isolation structures 30 and multiple first signal lines 50 are disposed on the substrate 10, alternately distributed along a first direction and each extending along a second direction; a first insulating layer 60 is disposed on each of the first isolation structures 30 and each of the first signal lines 50; multiple second isolation structures 70 and multiple second signal lines 80 are disposed on the first insulating layer 60, alternately distributed along a second direction and each extending along a first direction; a second insulating layer 90 is disposed on each of the second isolation structures 70 and each of the second signal lines 80; the transistor 110 includes at least a conductive layer 113 extending along a direction perpendicular to the substrate 10, and a gate insulating layer 112 and a semiconductor layer 111 sequentially wound around the outer periphery of the conductive layer 113, the semiconductor layer 111 being electrically connected to the first signal line 50 and the second signal line 80 respectively.

[0081] In this embodiment, the substrate 10 is used to carry the first isolation structure 30, the first signal line 50, the first insulating layer 60, the second isolation structure 70, the second signal line 80, the second insulating layer 90, and the transistor 110.

[0082] There is a first isolation structure 30 between any two adjacent first signal lines 50, and the two lines are electrically isolated through the first isolation structure 30.

[0083] The first insulating layer 60 is located between the first signal line 50 and the second signal line 80, and electrical isolation between the first signal line 50 and the second signal line 80 can be achieved through the first insulating layer 60.

[0084] There is a second isolation structure 70 between any two adjacent second signal lines 80, and the two lines are electrically isolated through the second isolation structure 70.

[0085] Semiconductor layer 111 is electrically connected to first signal line 50 and second signal line 80, respectively. First signal line 50 and second signal line 80 serve as the source and drain of transistor 110. Semiconductor layer located between first signal line 50 and second signal line 80 serves as the channel region of transistor 110. The thickness of first insulating layer 60 defines the channel region length. The smaller the thickness difference of first insulating layer 60, the higher the stability of channel region length. By reducing the thickness difference, the stability of channel region length can be improved, the problem of transistor channel length difference can be resolved, and thus the stability and reliability of the device can be greatly improved.

[0086] In some optional embodiments of this application, such as Figure 25 and Figure 26 As shown, the semiconductor structure 100 further includes an interlayer insulating layer 20, which is disposed on the substrate 10 and located on the side of each first isolation structure 30 and each first signal line 50 close to the substrate 10. Electrical isolation between the substrate 10 and the first signal line 50 can be achieved through the interlayer insulating layer 20.

[0087] In some optional embodiments of this application, the surfaces of the first signal line 50 and the first isolation structure 30 on the side away from the substrate 10 are flush. This ensures that the surface of the first insulating layer 60 on the side close to the first isolation structure 30 and the first signal line 50 is on the same horizontal plane, which helps to improve the thickness uniformity of the first insulating layer 60 and reduce thickness differences. The thickness of the first insulating layer 60 defines the channel region length. Small thickness differences can improve the transistor channel length difference problem and improve device stability and reliability.

[0088] In some optional embodiments of this application, the surfaces of the second signal line 80 and the second isolation structure 70 on the side away from the substrate 10 are flush. This ensures that the surfaces of the second insulating layer 90 on the side close to the second isolation structure 70 and the second signal line 80 are on the same horizontal plane, which helps to improve the thickness uniformity of the second insulating layer 90, reduce thickness differences, and improve the problem of transistor channel length differences.

[0089] In some optional embodiments of this application, such as Figure 25 and Figure 26 As shown, multiple transistors 110 are arranged in an array along a first direction and a second direction. A number of transistors 110 arranged sequentially along the first direction are electrically connected to a second signal line 80, and a number of transistors 110 arranged sequentially along the second direction are electrically connected to a first signal line 50. This arrangement reduces the number of traces, which is beneficial for layout design, increases structural density, and improves practicality.

[0090] In some optional embodiments of this application, the first signal line 50 serves as the drain and the second signal line 80 serves as the source.

[0091] Of course, in some alternative embodiments of this application, the first signal line 50 can be used as the source and the second signal line 80 can be used as the drain, depending on actual needs.

[0092] In some optional embodiments of this application, the semiconductor layer located between the first signal line 50 and the second signal line 80 serves as the channel region of the transistor 110, and the conductive layer corresponding to the channel region serves as the gate of the transistor 110. Current can flow through the first signal line 50, the channel region, and the second signal line 80. The gate of the transistor 110 corresponds to the channel region, and the gate is used to control the transistor 110 to be turned on or off.

[0093] It should be noted that the semiconductor structure of the present application embodiment can be manufactured using the semiconductor structure manufacturing method provided in the present application embodiment. Therefore, the semiconductor structure of the present application embodiment also has the above-mentioned beneficial effects of the semiconductor structure manufacturing method provided in the present application embodiment, which will not be repeated here.

[0094] In some optional embodiments of this application, the semiconductor structure can be a semiconductor device, which includes, but is not limited to, random access memory, specifically static random access memory or dynamic random access memory, and of course, flash memory, etc.

[0095] Based on the same inventive concept, embodiments of this application provide an electronic device, which includes: a semiconductor structure manufactured using the semiconductor structure manufacturing method described above; or, a semiconductor structure as described above.

[0096] It should be noted that since the electronic devices in the embodiments of this application include semiconductor structures manufactured using the semiconductor structure manufacturing method provided in the embodiments of this application or semiconductor structures as described in the embodiments of this application, the electronic devices in the embodiments of this application also have the above-mentioned beneficial effects of the semiconductor structure manufacturing method provided in the embodiments of this application or semiconductor structures as described in the embodiments of this application, which will not be repeated here.

[0097] In some optional embodiments of this application, the electronic device includes, but is not limited to, a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank. The storage device may include, for example, memory in a computer, and is not limited thereto.

[0098] By applying the embodiments of this application, at least the following beneficial effects can be achieved: The semiconductor structure manufacturing method provided in this application not only allows for the fabrication of isolation structures before signal lines, such as fabricating a first isolation structure before a first signal line or a second isolation structure before a second signal line, but also improves the uniformity and filling effect of the conductive film obtained by backfilling conductive material. Therefore, it is less likely to generate voids when fabricating signal lines between insulating isolation structures, avoiding the problem of voids easily generated when depositing OX between small-sized metals in related technologies. Furthermore, the method can define the channel length through a first insulating layer, and reduce thickness differences by adjusting or selecting the fabrication process of the first insulating layer, thereby improving the transistor channel length difference problem and greatly enhancing the stability and reliability of the process.

[0099] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0100] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0101] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0102] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0103] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Multiple first isolation structures are fabricated on the substrate; A plurality of the first isolation structures are distributed along a first direction and each extends along a second direction, wherein the first direction and the second direction intersect and are both parallel to the substrate; Create a first signal line located between any two adjacent first isolation structures; Fabricate a first insulating layer covering the first isolation structure and the first signal line; Multiple second isolation structures are fabricated on the first insulating layer; Multiple second isolation structures are distributed along the second direction, and each extends along the first direction; Create a second signal line located between any two adjacent second isolation structures; Fabricate a second insulating layer covering the second isolation structure and the second signal line; Multiple through-holes are formed, penetrating the second insulating layer, the second signal line, and the first insulating layer; the bottom of each through-hole exposes the first signal line. A semiconductor layer, a gate insulating layer, and a conductive layer are sequentially fabricated to cover and fill at least a plurality of the vias to obtain a plurality of transistors.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before fabricating multiple first isolation structures on the substrate, the process also includes: An interlayer insulating layer is fabricated on the substrate; And, a plurality of first isolation structures are fabricated on the substrate, including: A first insulating layer is formed on the interlayer insulating layer; The pattern is formed to create a plurality of first trenches that are spaced apart sequentially in the first direction and each extends along the second direction; the plurality of first trenches divide the first isolation layer into a plurality of first isolation structures.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Fabricating a first signal line located between any two adjacent first isolation structures includes: A conductive material is deposited to form a first conductive layer; the first conductive layer fills the first trench and covers the first isolation structure. Planarization is performed until the first isolation structure is exposed, and a first conductive layer located in any of the first trenches forms a first signal line; the first signal line is flush with the surface of the first isolation structure.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Fabricating a first insulating layer covering the first isolation structure and the first signal line includes: The first insulating layer is formed using atomic layer deposition (ALD) technology. Furthermore, a plurality of second isolation structures are fabricated on the first insulating layer, including: The second isolation layer is formed using atomic layer deposition (ALD) technology. The pattern is formed to create a plurality of second trenches that are spaced apart sequentially in the second direction and each extends along the first direction; the plurality of second trenches divide the second isolation layer into a plurality of second isolation structures.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, Fabricating a second signal line located between any two adjacent second isolation structures includes: A conductive material is deposited to form a second conductive layer; the second conductive layer fills the second trench and covers the second isolation structure. Planarization is performed until the second isolation structure is exposed, and a second conductive layer located in any of the second trenches forms a second signal line; the second signal line is flush with the surface of the second isolation structure.

6. The method for manufacturing a semiconductor structure according to any one of claims 1 to 5, characterized in that, Fabricating a second insulating layer covering the second isolation structure and the second signal line includes: The second insulating layer is formed using atomic layer deposition (ALD) technology. In addition, forming a plurality of through holes penetrating the second insulating layer, the second signal line, and the first insulating layer, including: The second insulating layer, the second signal line, and the first insulating layer are etched to expose the first signal line, forming a plurality of vias arranged in an array in the first and second directions.

7. A semiconductor structure, characterized in that, include: Multiple first isolation structures and multiple first signal lines are disposed on a substrate, and are alternately distributed along a first direction and each extends along a second direction; A first insulating layer is disposed on each of the first isolation structures and each of the first signal lines; Multiple second isolation structures and multiple second signal lines are disposed on the first insulating layer, and are alternately distributed along the second direction and each extends along the first direction; A second insulating layer is disposed on each of the second isolation structures and each of the second signal lines; A plurality of transistors, each transistor comprising at least a conductive layer extending in a direction perpendicular to the substrate, and a gate insulating layer and a semiconductor layer sequentially wound around the outer periphery of the conductive layer, the semiconductor layer being electrically connected to the first signal line and the second signal line.

8. The semiconductor structure according to claim 7, characterized in that, Includes at least one of the following: The semiconductor structure further includes an interlayer insulating layer disposed on the substrate and located on the side of each of the first isolation structures and each of the first signal lines close to the substrate; The surfaces of the first signal line and the first isolation structure on the side away from the substrate are flush. The surfaces of the second signal line and the second isolation structure on the side away from the substrate are flush.

9. The semiconductor structure according to claim 7, characterized in that, Includes at least one of the following: The plurality of transistors are arranged in an array in the first direction and the second direction, and a plurality of transistors arranged sequentially along the first direction are electrically connected to a second signal line, and a plurality of transistors arranged sequentially along the second direction are electrically connected to a first signal line. The semiconductor layer located between the first signal line and the second signal line serves as the channel region of the transistor, and the conductive layer corresponding to the channel region serves as the gate of the transistor. The first signal line serves as one of the source and drain, and the second signal line serves as the other of the source and drain.

10. An electronic device, characterized in that, include: A semiconductor structure manufactured using the semiconductor structure manufacturing method as described in any one of claims 1 to 6; or, The semiconductor structure as described in any one of claims 7 to 9.

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