Conductive via structure for improving far-end crosstalk

Abstract

A semiconductor structure includes: a substrate having a plurality of conductive layers and a plurality of insulating layers stacked alternately along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the plurality of conductive layers to a bottom conductive layer of the plurality of conductive layers, and including a first capacitive structure extending in the first conductive layer of the plurality of conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer, and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in either the first or second conductive layer of the plurality of conductive layers, the third capacitive structure forming a first mutual capacitance with the first capacitive structure and forming a second mutual capacitance with the second capacitive structure.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more specifically to a conductive via structure in a semiconductor structure for improving crosstalk. Background Technology

[0002] Advanced signaling systems require transmission performance that includes faster transmission speeds and smaller chip sizes to achieve a better user experience. However, in high-speed signal transmission systems, the increased wiring density and signal transmission frequency make crosstalk between adjacent signal transmission paths increasingly significant. Far-end crosstalk (FEXT) between transmission paths is a major problem that must be addressed when mitigating crosstalk. Therefore, continuous efforts are being made in the field to develop transmission architectures and methods to reduce or eliminate far-end crosstalk. Summary of the Invention

[0003] This invention relates to a semiconductor structure comprising: a substrate having a plurality of conductive layers and a plurality of insulating layers stacked alternately along a vertical direction of the substrate; a first conductive via structure extending from a top conductive layer of the plurality of conductive layers to a bottom conductive layer of the plurality of conductive layers, and including a first capacitive structure extending in the first conductive layer of the plurality of conductive layers; a second conductive via structure extending from the top conductive layer to the bottom conductive layer, and including a second capacitive structure extending in the first conductive layer; and a third capacitive structure extending in either the first or second conductive layer of the plurality of conductive layers, wherein the third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure.

[0004] In some embodiments, the first capacitive structure and the second capacitive structure do not project and overlap in the vertical direction.

[0005] In some embodiments, the third capacitive structure overlaps with the projection of the first capacitive structure and the second capacitive structure in the vertical direction.

[0006] In some embodiments, the first conductive layer is located on the top conductive layer.

[0007] In some embodiments, the first conductive layer is located in the top conductive layer or a conductive layer between the top conductive layer and the bottom conductive layer.

[0008] In some embodiments, the third capacitive structure includes a first conductive pad, which is located in the same conductive layer as the first capacitive structure and the second capacitive structure.

[0009] In some embodiments, the first capacitive structure includes a second conductive pad, and the first conductive via structure further includes a third conductive pad located in the third conductive layer of the plurality of conductive layers, wherein the area of ​​the second conductive pad is larger than the area of ​​the third conductive pad.

[0010] In some embodiments, the first conductive via structure further includes a fourth conductive pad located in the third conductive layer, the third conductive pad and the fourth conductive pad being connected by a connecting portion, wherein the third capacitive structure and the fourth conductive pad form a third mutual capacitance.

[0011] In some embodiments, the second conductive via structure further includes a fifth conductive pad located in the third conductive layer, wherein the third capacitive structure and the fifth conductive pad form a fourth mutual capacitance.

[0012] In some embodiments, the fourth conductive pad and the fifth conductive pad do not overlap in the vertical direction.

[0013] In some embodiments, the third capacitive structure does not project and overlap with the first capacitive structure or the second capacitive structure in the vertical direction.

[0014] In some embodiments, the semiconductor structure further includes a third conductive via structure, separate from the first conductive via structure and the second conductive via structure, and extending from the second conductive layer to a fourth conductive layer among the plurality of conductive layers, wherein the third capacitive structure is included in the third conductive via structure.

[0015] In some embodiments, the semiconductor structure further includes a fourth capacitive structure, wherein the third capacitive structure and the fourth capacitive structure are located on different layers of the plurality of conductive layers and are electrically connected to each other, the fourth capacitive structure and the first capacitive structure form a fifth mutual capacitance, and the fourth capacitive structure and the second capacitive structure form a sixth mutual capacitance.

[0016] In some embodiments, the third capacitive structure is electrically insulated from the fourth capacitive structure.

[0017] In some embodiments, the third capacitive structure and the fourth capacitive structure may project and overlap, partially overlap, or not overlap in the vertical direction.

[0018] In some embodiments, the first via structure includes a sixth conductive pad, and the fourth capacitive structure and the sixth conductive pad are located in the same layer of the plurality of conductive layers, wherein the fourth capacitive structure and the sixth conductive pad form a seventh mutual capacitance.

[0019] This invention relates to an electronic device comprising: a semiconductor structure as described herein; a printed circuit board located on a first side of the semiconductor structure and close to the bottom conductive layer of the semiconductor structure; a connector located between the printed circuit board and the semiconductor structure; and a chip located on a second side of the semiconductor structure opposite to the first side and close to the top conductive layer of the semiconductor structure, wherein the printed circuit board is electrically connected to the chip via the connector and a first conductive via structure and a second conductive via structure of the semiconductor structure.

[0020] This invention relates to a method for eliminating crosstalk, comprising: transmitting an electrical signal in a first conductive via structure and a second conductive via structure of a semiconductor structure, wherein the first conductive via structure includes a first capacitive structure, the second conductive via structure includes a second capacitive structure, and the semiconductor structure further includes a third capacitive structure separate from the first conductive via structure and the second conductive via structure; and storing energy in an electric field during the transmission of the electrical signal in the first conductive via structure and the second conductive via structure through a first mutual capacitance between the first capacitive structure and the third capacitive structure and a second mutual capacitance between the second capacitive structure and the third capacitive structure.

[0021] In some embodiments, the first capacitive structure and the second capacitive structure extend in a vertical direction, and the first capacitive structure and the second capacitive structure do not project and overlap in the vertical direction. The third capacitive structure has a first portion that projects and overlaps with the first capacitive structure in the vertical direction, and the third capacitive structure also has a second portion that projects and overlaps with the second capacitive structure in the vertical direction.

[0022] In some embodiments, the first capacitive structure of the first conductive via structure or the second capacitive structure of the second conductive via structure includes a conductive pad located in the top conductive layer or bottom conductive layer of a plurality of conductive layers of the semiconductor structure.

[0023] By using the capacitive structure configuration and crosstalk elimination method of the present invention, mutual capacitance between adjacent paths of the semiconductor structure can be generated without causing excessive insertion loss, thereby effectively improving the performance of the transmission path and achieving high-density and high-speed signaling transmission performance. Attached Figure Description

[0024] The aspects of this disclosure will be better understood from the following embodiments when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various structures are not drawn to scale. In fact, the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0025] Figures 1A and 1B are perspective and cross-sectional views of wiring paths of an example semiconductor structure according to one embodiment.

[0026] Figures 2A-2E This is a perspective view of the wiring path of an example semiconductor structure according to different embodiments.

[0027] Figure 3A and 3B These are different cross-sectional views of an example electronic device according to one embodiment.

[0028] Figure 4 This is a flowchart of an example crosstalk cancellation method according to one embodiment. Detailed Implementation

[0029] The following disclosure provides numerous different embodiments or examples of various components for implementing the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, such examples are merely illustrative and are not intended to be limiting. For example, in the following description, embodiments in which a first component is formed above or on a second component may include instances in which the first and second components are in direct contact, and embodiments in which additional components may be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0030] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” “above,” and similar terms may be used herein to describe the relationship of one component or member to another component or member illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and therefore the spatial relative descriptors used herein may be interpreted in the same way.

[0031] As used herein, terms such as “first,” “second,” and “third” describe various components, parts, areas, layers, and / or sections, but such components, parts, areas, layers, and / or sections should not be limited by such terms. These terms are used only to distinguish one component, part, area, layer, or section from another. For example, the use of terms such as “first,” “second,” and “third” herein does not imply sequence or order unless explicitly indicated by the context.

[0032] The singular forms "a," "an," and "the" may also include plural forms unless the context explicitly indicates otherwise. The term "connection," along with its derivatives, may be used herein to describe structural relationships between components. "Connection" may be used to describe two or more elements in direct physical or electrical contact with each other. "Connection" may also be used to indicate two or more elements in direct or indirect physical or electrical contact with each other (with intervening elements between them), and / or two or more elements cooperating or interacting with each other.

[0033] This invention relates to a conductive via structure for electronic devices or packaging structures. The conductive via structure can be used between different types of devices, such as substrates, chips, system-on-a-chip (SoC), connectors, or circuit boards, and connects the input / output (I / O) channels of the chip, substrate, connector, or circuit board to transmit information and / or clock signals, thereby forming a high-speed signaling system. In some embodiments, the conductive via structure may also serve as a signaling channel within the various devices mentioned above, such as chips, substrates, SoCs, connectors, or circuit boards. By using the capacitive structure of this invention as a crosstalk canceller, the effects of far-end crosstalk (FEXT) can be effectively reduced or eliminated, thereby achieving a high-speed signaling system with low noise interference.

[0034] In an exemplary embodiment, a pair of adjacent single-ended conductive via structures can be used to describe the effect of far-end crosstalk. The function of far-end crosstalk for any single-ended conductive via structure can be expressed as follows:

[0035] (1)

[0036] In equation 1, V FEXT V represents the magnitude of the far-end crosstalk, Cm is the mutual capacitance between the two conductive via structures, Lm is the mutual inductance between the two conductive via structures, and Cs and Ls are the self-capacitance and self-inductance, respectively. agg It is the voltage of the interference source signal, and time t. pd It is the signal propagation delay.

[0037] In crosstalk in vertical conductive via structures on substrates (such as package substrates, slots, or printed circuit boards), inductance typically dominates, causing V FEXT The value is less than zero. Therefore, in the time domain, far-end crosstalk in vertically conductive via structures often has a negative polarity (i.e., the excitation source relative to the rising edge is negative). Furthermore, in most cases, the mutual inductance Lm, self-capacitance Cs, and self-inductance Ls are difficult to control in closely packed vertically conductive via structures. Therefore, to reduce or eliminate negative far-end crosstalk, the influence of inductance on far-end crosstalk can be reduced by increasing the mutual capacitance Cm.

[0038] Figure 1A and1B These are perspective and cross-sectional views of the wiring path of an example semiconductor structure 100 according to one embodiment. In one embodiment, the semiconductor structure 100 may be a substrate, semiconductor package, circuit board (e.g., printed circuit board PCB), chip, die, slot, interposer, and other similar semiconductor structures. Figure 1A and 1B As shown, the semiconductor structure 100 includes two example conductive via structures 110 and 120, which extend adjacent to each other in a vertical (Z) direction. The vertical direction can be defined as the direction perpendicular to the working surface of each constituent layer or structure (e.g., circuit board, chip, die, interposer) in the substrate, or the Z-direction of the coordinate axis. The conductive via structures 110 and 120 extend through all or a portion of the thickness of the semiconductor structure 100 in the vertical direction, representing at least a portion of the wiring of two transmission paths in the semiconductor structure 100. Figure 1A and 1B Two conductive via structures 110 and 120 are illustrated, but in other embodiments, the semiconductor structure 100 may include other numbers of conductive via structures to enable wiring for other transmission paths of the semiconductor structure 100.

[0039] like Figure 1A and 1B As shown, the conductive via structure 110 has a substrate in which a plurality of vertical segments are disposed, and conductive pads are disposed between each vertical segment to connect each vertical segment in the vertical direction. The conductive pads may be via pads. The conductive via structure 110 includes conductive pads 112, 114, 115, 116, and 118. In one embodiment, conductive pad 112 has a surface extending along a horizontal (XY) direction. The surface of conductive pad 112 is substantially perpendicular to the direction of extension of the conductive via structure 110. Similarly, conductive pads 114, 115, 116, and 118 each have a surface extending along the XY plane. The surfaces of conductive pads 114, 115, 116, and 118 are substantially perpendicular to the direction of extension of the conductive via structure 110. Viewed from top, conductive pads 112, 114, 115, 116, and 118 extend outward from the vertical segments of the conductive via structure 110.

[0040] Similarly, the conductive via structure 120 includes conductive pads 122, 124, 125, 126, and 128. In one embodiment, conductive pad 122 has a surface extending in a horizontal direction. The surface of conductive pad 122 is substantially perpendicular to the direction of extension of the conductive via structure 120. Conductive pads 124, 125, 126, and 128 each have a surface extending in a horizontal direction. The surfaces of conductive pads 124, 125, 126, and 128 are substantially perpendicular to the direction of extension of the conductive via structure 120. Viewed from top, conductive pads 122, 124, 125, 126, and 128 extend outward from the vertical segment of the conductive via structure 120.

[0041] In one embodiment, the substrate of the semiconductor structure 100 has a plurality of insulating layers D1-D4 extending horizontally and stacked vertically. The insulating layers D1-D4 can be made of insulating materials, such as polypropylene (PP), silicon oxide (SiO2), nitric oxide (SiN), or other insulating or dielectric materials, and are therefore also referred to as dielectric layers. The insulating material in the insulating layers D1-D4 insulates the conductive via structure 110 from the conductive via structure 120 or other conductive materials to prevent short circuits or leakage. In one embodiment, the insulating layers D1-D4 of the semiconductor structure 100 are stacked on top of each other; while in other embodiments, the semiconductor structure 100 further includes a plurality of conductive layers M1-M5 extending horizontally and stacked vertically. The conductive layers M1-M5 can be made of conductive materials, such as conductive metals like copper, aluminum, gold, silver, tungsten, and titanium, or alloys of the above materials. The conductive layers M1-M5 and the aforementioned insulating layers D1-D4 can be staggered, so that the conductive via structures 110 and 120 are disposed therein.

[0042] In one embodiment, the conductive pads 112, 114, 115, 116, and 118 of the conductive via structure 110 and the conductive pads 122, 124, 125, 126, and 128 of the conductive via structure 120 are disposed in the corresponding insulating layer of the semiconductor structure 100. In another embodiment, the conductive pads 112, 114, 115, 116, and 118 and the conductive pads 122, 124, 125, 126, and 128 are disposed in the corresponding conductive layer of the semiconductor structure 100. In one embodiment, conductive pads 112 and 122 are located in the same insulating or conductive layer of semiconductor structure 100; conductive pads 114 and 124 are located in the same insulating or conductive layer of semiconductor structure 100; conductive pads 115 and 125 are located in the same insulating or conductive layer of semiconductor structure 100; conductive pads 116 and 126 are located in the same insulating or conductive layer of semiconductor structure 100; and conductive pads 118 and 128 are located in the same insulating or conductive layer of semiconductor structure 100. In one embodiment, the vertical segment of conductive via structure 110 or 120 is disposed in insulating layers D1-D4. In one embodiment, conductive pads 112, 114, 115, 116 and 118 of conductive via structure 110 and conductive pads 122, 124, 125, 126 and 128 of via structure 120 are disposed in conductive layers M1-M5.

[0043] In one embodiment, conductive pads 112 and 122 are located in the bottom conductive layer M1 or the top conductive layer M5 of the substrate of the semiconductor structure 100. In one embodiment, conductive pads 118 and 128 are located in the top conductive layer M5 or the bottom conductive layer M1 of the substrate of the semiconductor structure 100. In one embodiment, conductive pads 112 and 122 or 118 and 128 are located in a conductive layer between the bottom conductive layer M1 and the top conductive layer M5 of the substrate of the semiconductor structure 100. In one embodiment, the area of ​​conductive pad 112 is the largest among all conductive pads of the conductive via structure 110, or larger than the areas of the other conductive pads of the conductive via structure 110, and the area of ​​conductive pad 122 is the largest among all conductive pads of the conductive via structure 120, or larger than the areas of the other conductive pads of the conductive via structure 120. In one embodiment, the conductive pads 114, 115, 116, and 118 of the conductive via structure 110 have substantially the same area, while the conductive pads 124, 125, 126, and 128 of the conductive via structure 120 have substantially the same area. Although the illustrated conductive via structures 110 or 120 show five conductive pads, the number of conductive pads can be varied according to design requirements.

[0044] The conductive via structure 110 or 120 may be made of a conductive material, such as a metal. For example, the conductive via structure 110 or 120 may be made of conductive metals such as copper, aluminum, gold, silver, tungsten, titanium, or alloys of the above materials.

[0045] The semiconductor structure 100 further includes a conductive pad 130 between conductive via structures 110 and 120, located in one of the insulating layers D1-D4 or conductive layers M1-M5. Figure 1A and 1B In the example, conductive pad 130 is located in the underlying conductive layer M1 where conductive pads 114 or 124 are located. Conductive pad 130 is separated from and insulated from conductive via structures 110 or 120 through the insulating material of semiconductor structure 100. Conductive pad 130 may extend horizontally, perpendicular to the direction of extension of conductive via structures 110 or 120. Conductive pad 130 is separate from and not electrically connected to vias 110 and 120, and therefore is not part of the transmission path and does not have the function of transmitting power or information.

[0046] In this document, the term "conductive via structure" refers to at least a vertical conductive via structure composed of conductive vias, such as... Figure 1A The conductive via structures 110 or 120 shown have both ends exposed from the substrate of the semiconductor structure 100 through the conductive pads 112 and 122 of the bottom conductive layer M1 and the conductive pads 118 and 128 of the top conductive pad M5. This structure can also be referred to as a conductive via structure. The conductive via structure referred to herein is applicable to all general vertical via structures and is therefore not limited to conductive via structures. It can also be used for vertical conductive structures composed of blind vias or buried vias. In one embodiment, one end of the conductive blind via structure can be exposed through the conductive pads 112 and 122 of the bottom conductive layer M1 or the conductive pads 118 and 128 of the top conductive pad M5, with one end exposed from the substrate of the semiconductor structure 100 and the other end not exposed. In one embodiment, neither end of the conductive buried via structure is exposed from the substrate of the semiconductor structure 100.

[0047] In one embodiment, conductive pads 112, 122, and 130 can serve as crosstalk cancellers for the semiconductor structure 100. The surface of conductive pad 130 has a first portion that projects onto or overlaps with conductive pad 112 in the vertical direction, and a second portion that projects onto or overlaps with conductive pad 122 in the vertical direction. In this case, conductive pad 112 serves as a first capacitive structure of the semiconductor structure 100 located on the conductive via structure 110, conductive pad 122 serves as a second capacitive structure of the semiconductor structure 100 located on the conductive via structure 120, and conductive pad 130 serves as a third capacitive structure of the semiconductor structure 100, such that the projected overlapping or overlapping regions of conductive pads 112 and 130 form a capacitor with a first mutual capacitance C1 when transmitting electrical signals, and the projected overlapping or overlapping regions of conductive pads 122 and 130 form a capacitor with a second mutual capacitance C2 when transmitting electrical signals. The capacitor that generates the first mutual capacitance C1 or the second mutual capacitance C2 is formed by conductive pads 112 or 122 as the first conductive plate and conductive pad 130 as the second conductive plate. The insulating material between conductive pads 112, 122 and conductive pad 130 serves as the dielectric layer of the capacitor, allowing the capacitor to store energy in the electric field formed between the first and second conductive plates. Thus, the conductive via structures 110 and 120 have an equivalent mutual capacitance Ce composed of the first mutual capacitance C1 and the second mutual capacitance C2, which is formed by the parallel connection of the first mutual capacitance C1 and the second mutual capacitance C2. Referring to equation (1), the conductive pad 130 creates a capacitor with mutual capacitance Ce between the conductive via structures 110 and 120, thereby increasing the mutual capacitance Cm in equation (1) and reducing the magnitude of far-end crosstalk.

[0048] As shown in the capacitor formula, the capacitance is directly proportional to the area of ​​the conductive plates. Therefore, the larger the overlapping area of ​​the projected areas of conductive pads 130 and 112 or 122, the larger the resulting first or second mutual capacitance, and the better the elimination effect on far-end crosstalk between conductive via structures 110 and 120. Figure 1A and 1BAs shown, the conductive pad 130 does not extend from the conductive via structures 110 or 120. In other words, the area of ​​the conductive via structures 110 or 120 extending in the horizontal direction is not increased due to the absence of a crosstalk canceller. In particular, the areas of the conductive pads 114, 115, 116, 118, 124, 125, 126, and 118 are not increased by the presence of a crosstalk canceller. In one embodiment, the conductive pads 112, 114, 115, 116, and 118 do not overlap with their corresponding conductive pads 122, 124, 125, 126, and 118 in the vertical direction. In other words, the mutual capacitance between the conductive via structures 110 or 120 can only be generated through the conductive pad 130, which serves as a third mutual capacitance structure. In this way, the conductive via structures 110 or 120 can increase the mutual capacitance and effectively reduce or prevent the increase of insertion loss when transmitting power or signals, thereby reducing the overall interference and loss effect of the conductive via structures 110 and 120 and improving the transmission performance of the semiconductor structure 100.

[0049] In one embodiment, the conductive pad 130, viewed from above, has a circular, elliptical, approximately circular, elongated, polygonal, or other arbitrary shape. In one embodiment, the conductive pad 130 has a third portion in the middle region that does not overlap or intersect with the vertical projection of the conductive pads 112 or 122, and the width of the third portion is equal to or smaller than the width of the first or second portion of the conductive pad 130 that overlaps or intersects with the vertical projection of the conductive pads 112 or 122 on both sides. Therefore, viewed from above, the two end portions of the conductive pad 130 are wider than the middle portion.

[0050] Figure 2A This is a perspective view of the wiring path of an example semiconductor structure 200 according to different embodiments. Semiconductor structure 200 is similar to semiconductor structure 100 in many respects, therefore these similarities will not be described again. The main difference between semiconductor structure 200 and semiconductor structure 100 is that semiconductor structure 200 includes a conductive via structure 131. Conductive via structure 131 is disposed between conductive via structures 110 and 120, extending vertically through all or part of the thickness of semiconductor structure 100. Unlike conductive via structures 110 or 120, conductive via structure 131 does not form a wiring path in semiconductor structure 100, but rather serves as a capacitive structure for crosstalk cancellation. In one embodiment, the length of conductive via structure 131 is less than the length of conductive via structures 110 or 120. In one embodiment, the conductive via structure 131 is a via structure that includes blind vias or buried vias, at least one end of which is covered within the semiconductor structure 200 and is not exposed from the semiconductor structure 200. Therefore, the conductive via structure 131 can also be called a conductive blind via structure or a conductive buried via structure.

[0051] like Figure 2A As shown, the conductive via structure 131 is similar to conductive via structures 110 and 120. For example, conductive via structure 131 includes multiple vertical segments, with conductive pads disposed between each vertical segment to connect each vertical segment in the vertical direction. The conductive pads of conductive via structure 131 can be via pads. For example, conductive via structure 131 includes conductive pads 130, 135, 136, and 138. The conductive pad 130 of conductive via structure 131 may have the same material, shape, position, and arrangement as the conductive pad 130 of semiconductor structure 100. Similarly, conductive pads 135, 136, and 138 each have a surface extending in the horizontal direction. The respective surfaces of conductive pads 130, 135, 136, and 138 are substantially perpendicular to the direction of extension of conductive via structure 131. Viewed from top, conductive pads 130, 135, 136, and 138 extend outward from the vertical segments of conductive via structure 131. The materials and shapes of conductive pads 135, 136 and 138 are similar to those of conductive pad 130.

[0052] In one embodiment, the conductive pads 130, 135, 136, and 138 of the conductive via structure 131 are disposed in the corresponding insulating layers D1-D4 or the corresponding conductive layers M1-M5 of the semiconductor structure 200. In one embodiment, the conductive pads 130, 135, 136, and 138 are located in the same layer as the corresponding conductive pads 114, 115, 116, and 118 of the conductive via structure 110 or the corresponding conductive pads 124, 125, 126, and 128 of the conductive via structure 120 in the semiconductor structure 200. In one embodiment, the conductive pad 130 is located above the bottom conductive layer M1 or below the top conductive layer M5 of the semiconductor structure 200. In one embodiment, the conductive pad 138 is located above the bottom conductive layer M1 or below the top conductive layer M5 of the semiconductor structure 200. In one embodiment, the surface areas of the conductive pads 130, 135, 136, and 138 are substantially the same.

[0053] In one embodiment, the conductive pads 130, 135, 136, and 138 in the conductive via structure 131 can serve as crosstalk cancellers for the semiconductor structure 200, along with the conductive pads 114, 115, 116, and 118 of the conductive via structure 110 and the conductive pads 124, 125, 126, and 128 of the conductive via structure 120. The conductive via structure 131 is separate from and electrically insulated from the conductive via structure 110 or the conductive via structure 120. Each sidewall of the conductive pads 130, 135, 136, and 138 has a first portion opposite to the sidewall of the corresponding conductive pad 114, 115, 116, and 118, and a second portion opposite to the sidewall of the corresponding conductive pad 124, 125, 126, and 128. In other words, the first portion of the sidewall of each of the conductive pads 130, 135, 136 and 138 is vertically aligned with the sidewall of the corresponding conductive pads 114, 115, 116 and 118, and the second portion of the sidewall of each of the conductive pads 130, 135, 136 and 138 is vertically aligned with the sidewall of the corresponding conductive pads 124, 125, 126 and 128. In this configuration, any one of conductive pads 114, 115, 116, and 118 serves as the first capacitive structure of the semiconductor structure 100 located on the conductive via structure 110; any one of conductive pads 124, 125, 126, and 128 serves as the second capacitive structure of the semiconductor structure 100 located on the conductive via structure 120; and conductive pads 130, 135, 136, and 138 serve as the third capacitive structure of the semiconductor structure 100 located on the conductive via structure 131. This results in the formation of a capacitor with a third mutual capacitance C3 between the opposing sidewalls of the conductive via structures 110 and 131, and a capacitor with a fourth mutual capacitance C4 between the opposing sidewalls of the conductive via structures 120 and 131. Consequently, the conductive via structures 110 and 120 have an equivalent mutual capacitance Cf composed of the third mutual capacitance C3 and the fourth mutual capacitance C4, which is formed by the parallel connection of the third mutual capacitance C3 and the fourth mutual capacitance C4. Referring to equation (1), through the provision of conductive via structure 131, a capacitor with mutual capacitance Cf is generated between conductive via structures 110 and 120, and according to the above... Figure 1A and 1B As described above, a capacitor with mutual capacitance Ce is generated between conductive via structures 110 and 120 via the conductive pad 130. Therefore, conductive via structure 131 provides a higher mutual capacitance Cm than the conductive pad 130 alone, thus reducing far-end crosstalk.

[0054] Figure 2BThis is a perspective view of the wiring path of an example semiconductor structure 201 according to different embodiments. Semiconductor structure 201 is similar to semiconductor structures 100 and 200 in many respects, therefore these similarities will not be described again. The main difference between semiconductor structure 201 and semiconductor structure 100 is that semiconductor structure 201 includes a conductive pad 230. The conductive pad 230 is disposed between conductive via structures 110 and 120 and extends in the horizontal direction. The conductive pad 230 is located in the conductive layer M1 where conductive pads 112 or 122 are located. The conductive pad 230 is separated from and insulated from the conductive via structures 110 or 120 through the insulating material of semiconductor structure 201. Similar to conductive pad 130 or conductive via structure 131, conductive pad 230, as a capacitive structure for crosstalk cancellation of semiconductor structure 201, is not electrically connected to vias 110 and 120, and therefore is not part of the transmission path and does not have the function of transmitting power or information.

[0055] In one embodiment, the conductive pad 230, the conductive pad 112 of the conductive via structure 110, and the conductive pad 122 of the conductive via structure 120 serve as crosstalk cancellers for the semiconductor structure 201. In one embodiment, the conductive pad 230 does not project and overlap with the conductive pads 112 of the conductive via structure 110 and 122 of the conductive via structure 120 in the vertical direction. The sidewall of the conductive pad 230 has a first portion opposite to the sidewall of the corresponding conductive pad 112 and a second portion opposite to the sidewall of the corresponding conductive pad 122. In other words, the first portion of the sidewall of the conductive pad 230 is horizontally aligned with the sidewall of the corresponding conductive pad 112, and the second portion of the sidewall of the conductive pad 230 is horizontally aligned with the sidewall of the corresponding conductive pad 122. In this configuration, conductive pad 112 serves as the first capacitive structure of semiconductor structure 201 located on conductive via structure 110, conductive pad 122 serves as the second capacitive structure of semiconductor structure 201 located on conductive via structure 120, and conductive pad 230 serves as the third capacitive structure of semiconductor structure 201. This results in the opposite sidewall portions of conductive via structure 110 and conductive pad 230 forming a capacitor with a fifth mutual capacitance C5, and the opposite sidewall portions of conductive via structure 120 and conductive pad 230 forming a capacitor with a sixth mutual capacitance C6. Consequently, conductive via structures 110 and 120 have an equivalent mutual capacitance Cg composed of the fifth mutual capacitance C5 and the sixth mutual capacitance C6, which is formed by the fifth mutual capacitance C5 and the sixth mutual capacitance C6 connected in parallel. Referring to equation (1), by setting the conductive pad 230, a capacitor with mutual capacitance Cg is generated between the conductive via structures 110 and 120. According to the description of equation (1) above, a capacitor with mutual capacitance Cg is generated between the conductive via structures 110 and 120, which increases the mutual capacitance Cm and thus reduces far-end crosstalk.

[0056] Figure 2C This is a perspective view of the wiring path of an example semiconductor structure 202 according to different embodiments. Semiconductor structure 202 is similar to semiconductor structures 100, 200, and 201 in many respects, therefore these similarities will not be described again. Semiconductor structure 202 can be considered as a combination of semiconductor structures 200 and 201, wherein semiconductor structure 202 includes a conductive via structure 132 located between conductive via structures 110 and 120 and extending in the vertical direction. Conductive via structure 132 is similar to conductive via structure 131, serving as a capacitive structure for crosstalk cancellation in semiconductor structure 202, and is not electrically connected to vias 110 and 120, therefore it does not have the function of transmitting power or information. Conductive via structure 132 includes multiple vertical segments, with conductive pads disposed between each vertical segment to connect each vertical segment in the vertical direction, and these conductive pads of conductive via structure 132 can be via pads. For example, conductive via structure 131 includes conductive pads 230, 130, 135, 136, and 138.

[0057] Based on the above description of conductive pads 230 and conductive via structure 131, it can be understood that conductive pads 230, 130, 135, 136, and 138 in conductive via structure 131, together with conductive pads 112, 114, 115, 116, and 118 in conductive via structure 110 and conductive pads 122, 124, 125, 126, and 128 in conductive via structure 120, can serve as crosstalk cancellers for semiconductor structure 200. Referring to equation (1), through the arrangement of conductive via structure 132, at least two capacitors with mutual capacitances Cf and Cg are generated between conductive via structures 110 and 120. Therefore, conductive via structure 132 provides a higher mutual capacitance Cm than conductive pads 130 and 230 alone or conductive via structure 131 alone, thus reducing far-end crosstalk more effectively.

[0058] Figure 2DThis is a perspective view of the wiring path of an example semiconductor structure 203 according to different embodiments. Semiconductor structure 203 is similar to semiconductor structures 100, 200, 201, and 202 in many respects, therefore these similarities will not be described again. Semiconductor structure 203 includes a conductive pad 133 between conductive via structures 110 and 120, extending in the horizontal direction. The conductive pad 133, similar to conductive pad 130, is a capacitive structure serving as a crosstalk canceller for semiconductor structure 203 and is not electrically connected to vias 110 and 120, therefore it does not have the function of transmitting power or information. In one embodiment, conductive pad 133 and conductive pad 130 are separate from each other, located on different layers, and projected to overlap or overlap in the vertical direction. In other embodiments, conductive pad 133 and conductive pad 130 may project to overlap completely, partially, or not at all in the vertical direction. Conductive pad 133 may be located on the same layer as conductive pad 116 of conductive via structure 110 or conductive pad 126 of conductive via structure 120.

[0059] Reference Figure 2D The conductive via structure 110 includes an extension 210 extending horizontally outward from one or more conductive pads. In one embodiment, the extension 210 extends horizontally toward the conductive via structure 120. The extension 210 may include a connector and a conductive pad. For example, the extension 210 provides a connector 215 and a conductive pad 225 on the layer containing the conductive pad 115, and a connector 218 and a conductive pad 228 on the layer containing the conductive pad 118. The connectors 215, 218 and the conductive pads 225, 228 may be made of conductive materials, such as conductive metals like copper, aluminum, gold, silver, tungsten, and titanium, or alloys of the above materials. The connectors 215 or 218 may be sheet-like, rod-like, or strip-like, extending from one side of the conductive pads 115 or 118 to connect the conductive pads 225 or 228. The conductive pads 225 or 228, viewed from top view, may be circular, elliptical, approximately circular, polygonal, or other arbitrary shapes.

[0060] The conductive via structure 110, through the extension 210, can increase the exposed area in the vertical direction, excluding the conductive pad 112. For example, conductive pads 225 or 228 can be considered as conductive pads extending outward from conductive pads 115 or 118. In one embodiment, the area of ​​conductive pads 225 or 228 is substantially the same as that of conductive pads 114, 115, 116, or 118. Conductive pads 130 or 133 each have a first portion that overlaps or overlaps with the vertical projection of conductive pads 225 or 228.

[0061] Similarly, the conductive via structure 120 includes an extension 220 extending horizontally outward from one or more conductive pads. In one embodiment, the extension 220 extends horizontally toward the conductive via structure 110. The extension 220 may include a connector and a conductive pad. For example, the extension 220 has a connector 235 and a conductive pad 245 on the layer containing the conductive pad 125, and a connector 238 and a conductive pad 248 on the layer containing the conductive pad 128. The connector 235 or 238 and the conductive pad 245 or 248 may be made of conductive materials, such as conductive metals like copper, aluminum, gold, silver, tungsten, and titanium, or alloys of these materials. The connector 235 or 238 may be sheet-like, rod-like, or strip-like, extending from one side of the conductive pad 125 or 128 to connect the conductive pad 245 or 248. The conductive pad 245 or 248, viewed from top view, may be circular, elliptical, approximately circular, polygonal, or any other arbitrary shape.

[0062] The conductive via structure 120, through the extension 220, can increase the exposed area in the vertical direction besides the conductive pad 122. For example, conductive pads 245 or 248 can be considered as conductive pads extending outward from conductive pads 125 or 128 by the conductive via structure 120. In one embodiment, the area of ​​conductive pads 245 or 248 is substantially the same as that of conductive pads 124, 125, 126, or 128. Conductive pads 130 or 133 each have a second portion that overlaps or overlaps with the vertical projection of conductive pads 245 or 248.

[0063] Conductive pads 130 and 133, conductive pads 225 and 228 of conductive via structure 110, and conductive pads 245 and 248 of conductive via structure 120 can serve as crosstalk cancellers for semiconductor structure 203. Each surface of conductive pads 130 and 133 has a first portion that projects an overlapping region with conductive pads 225 and 228 in the vertical direction, and a second portion that projects an overlapping region with conductive pads 245 and 248 in the vertical direction. In this configuration, at least one of the conductive pads 225 and 228 serves as the first capacitive structure of the semiconductor structure 203 located on the conductive via structure 110, while at least one of the conductive pads 245 and 248 serves as the second capacitive structure of the semiconductor structure 203 located on the conductive via structure 120, and at least one of the conductive pads 130 and 133 serves as the third capacitive structure of the semiconductor structure 203. This results in the overlapping or intersecting regions of the projected projections of at least one of the conductive pads 225 and 228 and at least one of the conductive pads 130 and 133 forming a capacitor with a seventh mutual capacitance C7, and the overlapping or intersecting regions of the projected projections of at least one of the conductive pads 245 and 248 and at least one of the conductive pads 130 and 133 forming a capacitor with an eighth mutual capacitance C8. Consequently, the conductive via structures 110 and 120 have an equivalent mutual capacitance Ch composed of the seventh mutual capacitance C7 and the eighth mutual capacitance C8, which is formed by the parallel connection of the seventh mutual capacitance C7 and the eighth mutual capacitance C8. Referring to equation (1), by setting conductive pads 130, 133 and conductive pads 225, 228, 245, 248, a capacitor with mutual capacitance Ch is generated between conductive via structures 110 and 120, thus increasing the mutual capacitance Cm in equation (1) and thus reducing the magnitude of far-end crosstalk.

[0064] Since the capacitance generated by a capacitor is directly proportional to the area of ​​its conductive plates, the larger the overlapping area of ​​the projections of conductive pads 130 or 133 with conductive pads 225, 228, 245, and 248, the larger the resulting seventh mutual capacitance C7 or eighth mutual capacitance C8 will be. This also leads to better elimination of far-end crosstalk between conductive via structures 110 and 120. By appropriately increasing the vertical area of ​​conductive via structures 110 or 120 in the horizontal direction through the extensions 210 and 220, and forming a capacitive structure with the separately formed conductive pads 130 and 133, the capacitor area of ​​the seventh mutual capacitance C7 or eighth mutual capacitance C8 can be significantly increased. In this way, the conductive via structures 110 or 120 can increase the mutual capacitance and control the insertion loss during power or signal transmission within a reasonable range, thereby reducing the overall interference and loss effect between the conductive via structures 110 and 120 and improving the transmission performance of the semiconductor structure 203.

[0065] Figure 2E This is a perspective view of the wiring path of an example semiconductor structure 204 according to different embodiments. Semiconductor structure 204 is similar to semiconductor structures 100 and 200 in many respects, therefore these similarities will not be described again. The main difference between semiconductor structure 204 and semiconductor structure 100 is that in semiconductor structure 203, conductive pad 114 serves as a first capacitive structure located between conductive pads 112 and 116, and conductive pad 124 serves as a second capacitive structure located between conductive pads 122 and 126. In one embodiment, conductive pads 114 and 124 are located in any conductive layer between the top conductive layer M5, the bottom conductive layer M1, and the top conductive layer M5 of the substrate of semiconductor structure 203. In one embodiment, the area of ​​conductive pad 114 is the largest among all conductive pads of conductive via structure 110, or larger than the areas of other conductive pads of conductive via structure 110, and the area of ​​conductive pad 124 is the largest among all conductive pads of conductive via structure 120, or larger than the areas of other conductive pads of conductive via structure 120.

[0066] Conductive pad 134 is disposed between conductive via structures 110 and 120 and extends horizontally. Conductive pad 134 is located in the conductive layer M1 where conductive pad 112 or 122 is located. Conductive pad 134 is separated from and insulated from conductive via structures 110 or 120 through the insulating material of semiconductor structure 203. Similar to conductive pad 130, conductive pad 134 serves as a capacitive structure for crosstalk cancellation in semiconductor structure 203 and is not electrically connected to vias 110 and 120. Therefore, it is not part of the transmission path and does not have the function of transmitting power or information.

[0067] In one embodiment, conductive pads 114, 124, and 134 can serve as crosstalk cancellers for semiconductor structure 203. The surface of conductive pad 134 has a first portion overlapping with a projected region of conductive pad 114 in the vertical direction, and a second portion overlapping with a projected region of conductive pad 124 in the vertical direction. In this case, conductive pad 114 serves as a first capacitive structure of semiconductor structure 203 on conductive via structure 110, conductive pad 124 serves as a second capacitive structure of semiconductor structure 203 on conductive via structure 120, and conductive pad 134 serves as a third capacitive structure of semiconductor structure 203, such that the overlapping regions of the projected regions of conductive pads 114 and 134 form a capacitor with a ninth mutual capacitance C9 when transmitting electrical signals, and the overlapping regions of the projected regions of conductive pads 124 and 134 form a capacitor with a tenth mutual capacitance C when transmitting electrical signals. The capacitor that generates the ninth mutual capacitance C9 or the tenth mutual capacitance C10 is constructed with conductive pad 114 or 124 as the first conductive plate and conductive pad 134 as the second conductive plate. The insulating material between conductive pads 114, 124 and 134 serves as the dielectric layer, allowing the capacitor to store energy in the electric field formed between the first and second conductive plates. Thus, the conductive via structures 110 and 120 have an equivalent mutual capacitance Ci composed of the ninth mutual capacitance C9 and the tenth mutual capacitance C10, which are connected in parallel. Referring to equation (1), the conductive pad 134 creates a capacitor with mutual capacitance Ci between the conductive via structures 110 and 120, thereby increasing the mutual capacitance Cm in equation (1) and reducing the magnitude of far-end crosstalk.

[0068] In one embodiment, conductive pad 134, conductive pad 112 of conductive via structure 110, and conductive pad 122 of conductive via structure 120 serve as crosstalk cancellers for semiconductor structure 203. In one embodiment, conductive pad 134 does not project and overlap with conductive pad 112 of conductive via structure 110 and conductive pad 122 of conductive via structure 120 in the vertical direction. The sidewall of conductive pad 134 has a first portion opposite to the sidewall of the corresponding conductive pad 112 and a second portion opposite to the sidewall of the corresponding conductive pad 122. In other words, the first portion of the sidewall of conductive pad 134 is horizontally aligned with the sidewall of the corresponding conductive pad 112, and the second portion of the sidewall of conductive pad 134 is horizontally aligned with the sidewall of the corresponding conductive pad 122. In this configuration, conductive pad 112 serves as the first capacitive structure of semiconductor structure 203 located on conductive via structure 110, while conductive pad 122 serves as the second capacitive structure of semiconductor structure 201 located on conductive via structure 120. The conductive pad also serves as the third capacitive structure of semiconductor structure 203. This results in the portions of the opposite sidewalls of conductive via structure 110 and conductive pad 34 forming a capacitor with an eleventh mutual capacitance C11, and the portions of the opposite sidewalls of conductive via structure 120 and conductive pad 134 forming a capacitor with a twelfth mutual capacitance C12. Consequently, there is an equivalent mutual capacitance Cj between conductive via structures 110 and 120, consisting of the eleventh mutual capacitance C11 and the twelfth mutual capacitance C11, which is formed by the parallel connection of the eleventh mutual capacitance C11 and the twelfth mutual capacitance Ce. Referring to equation (1), through the setting of conductive pad 134, a capacitor with mutual capacitance Cj is generated between conductive via structures 110 and 120. According to the description of equation (1) above, a capacitor with mutual capacitance Cj is generated between conductive via structures 110 and 120, which increases the mutual capacitance Cm and thus reduces far-end crosstalk.

[0069] Figure 3A This is a cross-sectional view of an example electronic device 300 according to one embodiment. The electronic device 300 is an integrated system for displaying the above text. Figure 1A and 1B The conductive via structures described in 2A-2D are implemented in different locations of a device, system, or package, such as in the wiring of signal or power transmission paths of a substrate, slot, printed circuit board, die, or chip.

[0070] Electronic device 300 includes a printed circuit board 310 and a package structure 320. The printed circuit board 310 and the package structure 320 are electrically connected via a connector 302, wherein the connector 302 may be a conductive bump, conductive pad, interconnect structure, or pin socket, such as a ball grid array (BGA), pin grid array (PGA), or block grid array (LGA). The package structure 320 includes a substrate 330 and a chip 340, and the chip 340 is electrically connected to the printed circuit board 310 via a connector 304 and a signal transmission path or power transmission path of the substrate 330. The chip 340 may be a bare die or another package. In one embodiment, the connector 304 may be a conductive bump, conductive pad, or interconnect structure, or a pin socket, such as a ball grid array, pin grid array, or block grid array. In one embodiment, electronic device 300 further includes a molding compound 350 for molding the chip 340 and the connector 304.

[0071] In one embodiment, the substrate 330 has a multilayer structure, such as including a first stacked layer 332, a core layer 334, and a second stacked layer 336 to form a multilayer transmission structure. In one embodiment, the first stacked layer 332 or the second stacked layer 336 is formed by stacking multiple insulating or conductive layers alternately. In one embodiment, the core layer 334 has one or more through-holes 352 and 354 electrically connecting the first stacked layer 332 and the second stacked layer 336. The substrate 330 is used to form a signal or power transmission path between the connectors 302 and 304, and can be implemented by one or more conductive via structures extending in a vertical direction. For example, the first stacked layer 332 includes conductive via structures 342 and 344, and the second stacked layer 336 includes conductive via structures 362 and 364. Conductive via structure 342 and conductive via structure 362 are electrically connected through through via 352 in core layer 334, while conductive via structure 344 and conductive via structure 364 are electrically connected through through via 354 in core layer 334.

[0072] In one embodiment, the first stacked layer 332 is further provided with a capacitive structure 346 to generate mutual capacitance with the conductive via structures 342 and 344, thereby reducing or eliminating far-end crosstalk between the conductive via structures 342 and 344. The capacitive structure 346 may be composed of... Figure 1A-1B Conductive pad 130 or Figure 2A-2D The conductive pads 230 and 133, and conductive via structures 131 and 132 are used to achieve this. The first stacked layer 332 can be achieved through... Figure 1A-1B or Figure 2A-2DThe crosstalk canceller design causes mutual capacitance between the capacitive structure 346 and the conductive via structures 342 and 344, thereby reducing or eliminating far-end crosstalk between the conductive via structures 342 and 344. Furthermore, although Figure 3A The conductive via structures 342 and 344 of the first stacked layer 332 are not shown, but can still be referred to. Figure 2D The conductive via structures 110 and 120 are used to realize the extensions 210 and 220 to generate mutual capacitance with the capacitive structure 346, thereby reducing or eliminating far-end crosstalk between the conductive via structures 342 and 344.

[0073] In one embodiment, the second stacked layer 336 is further provided with a capacitive structure 366 to generate mutual capacitance with the conductive via structures 362 and 364, thereby reducing or eliminating far-end crosstalk between the conductive via structures 362 and 364. The capacitive structure 366 may be composed of... Figure 1A-1B Conductive pad 130 or Figure 2A-2D The conductive pads 230 and 133, and conductive via structures 131 and 132 are used to achieve this. The second stacked layer 336 can be achieved through... Figure 1A-1B or Figure 2A-2D The crosstalk canceller design causes mutual capacitance between the capacitive structure 366 and the conductive via structures 362 and 364, thereby reducing or eliminating far-end crosstalk between the conductive via structures 362 and 364. Furthermore, although Figure 3A The conductive via structures 362 and 364 of the second stacked layer 336 are not shown, but can still be referred to. Figure 2D The conductive via structures 110 and 120 are used to realize extensions 210 and 220 to generate mutual capacitance with the capacitive structure 366, thereby reducing or eliminating far-end crosstalk between the conductive via structures 362 and 364.

[0074] Figure 3A The capacitive structures 346 and 366 of the illustrated electronic device 300 are merely illustrative crosstalk cancellers. The electronic device 300 may, as needed, provide one or more conductive pads or conductive via structures as crosstalk cancellers between multiple conductive via structures that may generate far-end crosstalk. These pads or via structures are separated from and insulated from the original conductive via structures, and generate mutual capacitance with the original conductive via structures, thereby eliminating or reducing far-end crosstalk between adjacent or nearby conductive via structures.

[0075] Figure 3BThis is an enlarged cross-sectional view of the printed circuit board 310 of the electronic device 300. Conductive via structures 402 and 404 are provided near the surface of the printed circuit board 310 facing the substrate 320, electrically connecting to corresponding connectors 302. The conductive via structures 402 and 404 are components used to electrically connect the chip 340 to the printed circuit board 310 through the substrate 320 and the connectors 302. The conductive via structures 402 and 404 can be signal transmission paths or power transmission paths. A capacitive structure 406 is also provided in the printed circuit board 310, insulated from the conductive via structures 402 and 404, and forming mutual capacitance with them. The capacitive structure 406 can be composed of… Figure 1A-1B Conductive pad 130, Figure 2A-2D Conductive pads 230 and 133, or conductive via structures 131 and 132, can be used to achieve this. Conductive via structure 402 can be achieved through... Figure 1A-1B or Figure 2A-2D The crosstalk canceller design causes mutual capacitance between the capacitive structure 406 and the conductive via structures 402 and 404, thereby reducing or eliminating far-end crosstalk between the conductive via structures 402 and 404. Furthermore, although Figure 3A Not shown, but conductive via structures 402 and 404 can still be referenced. Figure 2D The conductive via structures 110 and 120 are used to realize the extensions 210 and 220 to generate mutual capacitance with the capacitive structure 406, thereby reducing or eliminating far-end crosstalk between the conductive via structures 402 and 404.

[0076] Figure 4 This is a flowchart of an example crosstalk cancellation method 400 according to one embodiment. In one embodiment, method 400 is performed using, for example, the electronic device or semiconductor structure shown in the foregoing figures. The embodiments of this application are not limited to... Figure 4 The specific method shown may be modified by adding, omitting, rearranging or modifying one or more steps in other embodiments.

[0077] In step 410, the electronic device or semiconductor structure transmits electrical signals in at least two or more conductive via structures, for example, transmitting electrical signals in a first conductive via structure and a second conductive via structure. The electrical signals may include information signals or clock signals. The electrical signals may be digital signals or analog signals.

[0078] In one embodiment, step 410 is performed by... Figure 1A-1B , Figure 2A-2D or Figures 3A-3B The conductive via structures transmit electrical signals. Since the multiple conductive via structures are adjacent to each other, crosstalk may occur between adjacent conductive via structures, such as far-end crosstalk.

[0079] In step 420, during the transmission of the electrical signal, the first capacitive structure of the first conductive via structure, which acts as a crosstalk canceller, and the third capacitive structure of the semiconductor structure store energy in the electric field by generating a first mutual capacitance. Similarly, the second capacitive structure of the second conductive via structure, which acts as a crosstalk canceller, and the third capacitive structure of the semiconductor structure also store energy in the electric field by generating a second mutual capacitance. For example, in... Figure 1A-1B In the semiconductor structure 100, a first capacitive structure 112 serving as a crosstalk canceller, a second capacitive structure 122 serving as a crosstalk canceller, and a third capacitive structure 130 serving as a crosstalk canceller, are included. A first mutual capacitance is generated between the first capacitive structure 112 and the third capacitive structure 130, and a second mutual capacitance is generated between the second capacitive structure 122 and the third capacitive structure 130. As a result, the conductive via structures 110 and 120 reduce or eliminate far-end crosstalk through the mutual capacitance formed by the first and second mutual capacitances.

[0080] In the above embodiments, steps 410 and 420 of method 400 are described sequentially; however, it should be understood that in one embodiment, steps 410 and 420 occur substantially simultaneously in the semiconductor structure.

[0081] The foregoing outlines the structures of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other manufacturing processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that... include: A substrate having multiple conductive layers and multiple insulating layers stacked alternately along the vertical direction of the substrate; A first conductive via structure extends from the top conductive layer of the plurality of conductive layers to the bottom conductive layer of the plurality of conductive layers, and includes a first capacitive structure extending in the first conductive layer of the plurality of conductive layers. The second conductive via structure extends from the top conductive layer to the bottom conductive layer and includes a second capacitive structure that extends in the first conductive layer. as well as A third capacitive structure extends within the first or second conductive layer of the plurality of conductive layers. The third capacitive structure forms a first mutual capacitance with the first capacitive structure and a second mutual capacitance with the second capacitive structure. The plurality of insulating layers include a top insulating layer and a bottom insulating layer, wherein the first conductive via structure and the second conductive via structure both penetrate the top insulating layer and the bottom insulating layer, and wherein the third capacitive structure is completely covered by the plurality of insulating layers and is not electrically connected to any conductive element that penetrates the top insulating layer or the bottom insulating layer.

2. The semiconductor structure according to claim 1, characterized in that, The first capacitive structure and the second capacitive structure do not overlap in the vertical direction.

3. The semiconductor structure according to claim 1, characterized in that, The third capacitive structure overlaps with the projections of the first capacitive structure and the second capacitive structure in the vertical direction.

4. The semiconductor structure according to claim 1, characterized in that, The first conductive layer is located on the bottom conductive layer.

5. The semiconductor structure according to claim 1, characterized in that, The first conductive layer is located in the top conductive layer or a conductive layer between the top conductive layer and the bottom conductive layer.

6. The semiconductor structure according to claim 1, characterized in that, The third capacitive structure includes a first conductive pad, which is located in the same conductive layer as the first capacitive structure and the second capacitive structure.

7. The semiconductor structure according to claim 6, characterized in that, The first capacitive structure includes a second conductive pad, and the first conductive via structure further includes a third conductive pad located in the third conductive layer of the plurality of conductive layers, wherein the area of ​​the second conductive pad is larger than the area of ​​the third conductive pad.

8. The semiconductor structure according to claim 7, characterized in that, The first conductive via structure further includes a fourth conductive pad located in the third conductive layer. The third conductive pad and the fourth conductive pad are connected by a connecting portion, wherein the third capacitive structure and the fourth conductive pad form a third mutual capacitance.

9. The semiconductor structure according to claim 8, characterized in that, The second conductive via structure further includes a fifth conductive pad located in the third conductive layer, wherein the third capacitive structure and the fifth conductive pad form a fourth mutual capacitance.

10. The semiconductor structure according to claim 9, characterized in that, The fourth conductive pad and the fifth conductive pad do not overlap in projection in the vertical direction.

11. The semiconductor structure according to claim 1, characterized in that, The third capacitive structure does not project and overlap with the first capacitive structure or the second capacitive structure in the vertical direction.

12. The semiconductor structure according to claim 1, characterized in that, It further includes a third conductive via structure, separate from the first conductive via structure and the second conductive via structure, and extending from the second conductive layer to a fourth conductive layer among the plurality of conductive layers, wherein the third capacitive structure is included in the third conductive via structure.

13. The semiconductor structure according to claim 1, characterized in that, It further includes a fourth capacitive structure, wherein the third capacitive structure and the fourth capacitive structure are located on different layers of the plurality of conductive layers, the fourth capacitive structure forms a fifth mutual capacitance with the first conductive via structure, and forms a sixth mutual capacitance with the second conductive via structure.

14. The semiconductor structure according to claim 13, characterized in that, The third capacitive structure is electrically insulated from the fourth capacitive structure.

15. The semiconductor structure according to claim 13, characterized in that, The third capacitive structure and the fourth capacitive structure may have overlapping, partially overlapping, or not overlapping projections in the vertical direction.

16. The semiconductor structure according to claim 13, characterized in that, The first conductive via structure includes a sixth conductive pad, and the fourth capacitive structure and the sixth conductive pad are located in the same conductive layer among the plurality of conductive layers, wherein the fourth capacitive structure and the sixth conductive pad form a seventh mutual capacitance.

17. An electronic device, characterized in that... include: The semiconductor structure according to any one of claims 1-16; A printed circuit board is located on the first side of the semiconductor structure and close to the bottom conductive layer of the semiconductor structure; A connector is located between the printed circuit board and the semiconductor structure; as well as A chip is located on a second side of the semiconductor structure opposite to the first side and close to the top conductive layer of the semiconductor structure, wherein the printed circuit board is electrically connected to the chip through the connector and the first conductive via structure and the second conductive via structure of the semiconductor structure.

18. A method for eliminating crosstalk, characterized in that... include: Electrical signals are transmitted in a first conductive via structure and a second conductive via structure of a semiconductor structure. The first conductive via structure includes a first capacitive structure, the second conductive via structure includes a second capacitive structure, and the semiconductor structure further includes a third capacitive structure, which is separate from the first conductive via structure and the second conductive via structure. as well as During the transmission of the electrical signal in the first and second conductive via structures, energy is stored in the electric field through the first mutual capacitance between the first and third capacitive structures and the second mutual capacitance between the second and third capacitive structures. The semiconductor structure includes multiple insulating layers stacked vertically, the multiple insulating layers including a top insulating layer and a bottom insulating layer, wherein the first conductive via structure and the second conductive via structure both penetrate the top insulating layer and the bottom insulating layer, and wherein the third capacitive structure is completely covered by the multiple insulating layers and is not electrically connected to any conductive element penetrating the top insulating layer or the bottom insulating layer.

19. The method according to claim 18, characterized in that, The first capacitive structure and the second capacitive structure extend in a vertical direction, and the first capacitive structure and the second capacitive structure do not overlap in projection in the vertical direction. The third capacitive structure has a first portion that overlaps in projection with the first capacitive structure in the vertical direction, and the third capacitive structure also has a second portion that overlaps in projection with the second capacitive structure in the vertical direction.

20. The method according to claim 18, characterized in that, The first capacitive structure of the first conductive via structure or the second capacitive structure of the second conductive via structure includes a conductive pad located in the top conductive layer or bottom conductive layer of the plurality of conductive layers of the semiconductor structure.

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