Display device and manufacturing method thereof

Abstract

Disclosed are a display device and a method of manufacturing the same, which can prevent or reduce the occurrence of a cathode uplift phenomenon when removing a temporary protective film. The display device includes: a substrate including a display area and a non-display area; a thin film transistor disposed on the substrate in the display area; a planarization layer disposed in the display area and in the non-display area on the thin film transistor, and having a first contact hole on the thin film transistor; a bank layer disposed in the display area and the non-display area on the planarization layer, and having an opening area in the light emitting area; a light emitting element disposed on the planarization layer to be connected to the thin film transistor through the first contact hole; and an organic insulating layer pattern disposed on the bank layer in the non-display area to cover an end portion of the cathode of the light emitting element.

Description

Technical Field

[0001] This disclosure relates to a display device, and more specifically, to a display device and a method thereof capable of preventing or reducing cathode lift-up when a temporary protective film is removed. Background Technology

[0002] Image display devices that present various information on a screen are a core technology of the information and communication era, and are developing towards thinner, lighter, larger portability and higher performance. Therefore, there is an emphasis on manufacturing display devices with a thin and light structure.

[0003] Specific examples of such display devices include liquid crystal display (LCD) devices, quantum dot (QD) display devices, field emission display (FED) devices, organic light-emitting diode (OLED) display devices, etc.

[0004] An OLED display device includes a light-emitting diode comprising a cathode and an anode facing each other between organic light-emitting layers. Light is emitted and an image is displayed when holes and electrons injected into the organic light-emitting layers from the cathode and anode, respectively, recombine with each other within the organic light-emitting layers.

[0005] Therefore, OLED displays are self-emissive display devices, which not only have advantages in terms of power consumption due to low voltage driving, but also offer excellent color rendering, fast response time, wide viewing angle, and high contrast ratio (CR). In this regard, OLED displays are emphasized as the next generation of display devices, and research on them is ongoing.

[0006] Meanwhile, in recent years, there has been an increasing demand for flexible display devices using flexible substrates such as plastic substrates. These flexible display devices offer advantages such as large-screen display and portability, as they can be carried in a folded state and display images when unfolded.

[0007] Because of the flexible nature of this type of plastic substrate, it is difficult to use the plastic substrate itself in the manufacturing process of display devices. Therefore, the process is carried out by attaching the plastic substrate to one surface of a carrier substrate, such as a glass substrate.

[0008] Specifically, a plastic substrate is formed on a carrier substrate, and then a thin-film transistor array layer, a light-emitting element array layer, and an encapsulation layer are sequentially formed on the plastic substrate. A temporary protective film is then attached to the encapsulation layer. Afterward, the carrier substrate is removed from the plastic substrate, and the temporary protective film is removed from the encapsulation layer. Finally, a polarizer and a cover glass are bonded to the encapsulation layer.

[0009] The descriptions provided in the background section should not be construed as prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0010] The inventors of this disclosure have realized that in the manufacturing process described above, the end of the cathode may be lifted due to the force applied when removing the temporary protective film, which may cause a malfunction.

[0011] Therefore, this disclosure relates to a display device and a method of manufacturing the same, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art.

[0012] The purpose of this disclosure is to provide a display device and a method for manufacturing the same, which can prevent or reduce cathode lift-up when removing a temporary protective film, thereby preventing or reducing malfunctions and improving yield.

[0013] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not described herein will become clearer to those skilled in the art from the following detailed description.

[0014] According to one aspect of this disclosure, a display device may include: a substrate including a display area configured to display an image and a non-display area disposed around the display area; a thin-film transistor disposed on the substrate in the display area; a planarization layer disposed on the thin-film transistor in both the display area and the non-display area, and the planarization layer having a first contact hole in the thin-film transistor; a dam layer disposed on the planarization layer in both the display area and the non-display area, and the dam layer having an opening area in the light-emitting area; a light-emitting element disposed on the planarization layer for connection to the thin-film transistor through the first contact hole; and an organic insulating layer pattern disposed on the dam layer in the non-display area to cover the cathode end of the light-emitting element.

[0015] According to another aspect of this disclosure, a method of manufacturing a display device may include the following steps: preparing a substrate, the substrate including a display area configured to display an image and a non-display area disposed around the display area; forming a thin-film transistor on the substrate in the display area; forming a voltage supply line on the substrate in the non-display area; forming a planarization layer on the thin-film transistor and the voltage supply line, such that the planarization layer has a first contact hole on the thin-film transistor and a second contact hole on the voltage supply line, respectively; forming an anode of a light-emitting element on the planarization layer, such that the anode is connected to the thin-film transistor through the first contact hole; forming a connection electrode on the planarization layer, such that the connection electrode is connected to the voltage supply line through the second contact hole; forming a dam layer on the planarization layer having the anode and the connection electrode, such that the dam layer has an opening region on the anode and a third contact hole on the connection electrode; forming a light-emitting layer on the anode in the opening region; forming a cathode on the light-emitting layer and the dam layer, such that the cathode is electrically connected to the connection electrode through the third contact hole; and forming an organic insulating layer pattern on the dam layer in the non-display area, such that the organic insulating layer covers the end of the cathode, the third contact hole, and the end of the dam layer.

[0016] Details of other embodiments are included in the following detailed description and accompanying drawings.

[0017] According to this disclosure, a metal pattern is formed in the area overlapping the end of the cathode of the light-emitting element on the embankment layer in the non-display area, and then the end of the cathode overlapping the metal pattern is removed by laser irradiation. Therefore, it is possible to prevent or reduce the phenomenon that the underlying layer is lifted due to the removal force applied to it when the temporary protective film is removed in order to perform subsequent processes.

[0018] According to this disclosure, an organic insulating layer pattern is formed on the dam layer to cover the metal pattern, the end of the cathode, and the end of the dam layer. Therefore, it is possible to prevent or reduce the occurrence of the cathode being lifted due to the removal force applied to it when the temporary protective film is removed for subsequent processes. Furthermore, it is possible to reduce the occurrence of display device malfunctions.

[0019] Furthermore, the organic insulating layer pattern can act as a barrier to prevent the flow of the organic encapsulation layer during the formation of the encapsulation layer. Therefore, it is not necessary to form a separate barrier, which simplifies the process and allows for a reduction in the cell bezel. This reduction in the cell bezel enables the achievement of narrow bezels.

[0020] Because the number of display device failures is reduced, product costs can be lowered. Furthermore, environmental / social / governance (ESG) goals that reduce product costs can be achieved.

[0021] The effects of the embodiments according to this disclosure are not limited to those described above, and this disclosure may include a variety of effects.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0023] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate (multiple) embodiments of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0024] Figure 1 This is a schematic cross-sectional view of a flexible display device according to an embodiment of the present disclosure;

[0025] Figure 2 This is a circuit diagram of the sub-pixels included in a display device according to an embodiment of the present disclosure;

[0026] Figure 3 This is a view showing a cross-section of a pixel disposed in the display area of ​​a display panel according to an embodiment of the present disclosure;

[0027] Figure 4 This is a cross-sectional view showing the non-display area of ​​a light-emitting display panel according to an embodiment of the present disclosure;

[0028] Figures 5A to 5E This is a view showing a cross-section of a display panel formed in a process according to an embodiment of the present disclosure in the display area;

[0029] Figures 6A to 6E This is a view showing a cross-section of a display panel formed in a non-display area according to an embodiment of the present disclosure; and

[0030] Figure 7 This is a plan view of the display panel in the border area according to an embodiment of the present disclosure. Detailed Implementation

[0031] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the present disclosure, the same reference numerals denote the same constituent elements.

[0032] In the following description of this disclosure, detailed descriptions of known techniques or configurations incorporated herein will be omitted where such descriptions may obscure the subject matter. Furthermore, the terms used below in connection with the constituent elements have been chosen for ease of preparation of this disclosure and may differ in practice from the names of the corresponding elements.

[0033] The shapes, dimensions, scales, angles, quantities, etc., shown in the accompanying drawings for the purpose of illustrating embodiments of this disclosure are for illustrative purposes only and are not limited to the contents shown in the drawings. Where possible, the same reference numerals will be used throughout the drawings to refer to the same or similar parts.

[0034] In the following description, detailed descriptions of known techniques related to this disclosure may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0035] When terms such as “comprising,” “having,” and “including” are used throughout the specification, additional components may be present unless “only” is used. Unless otherwise specified, components described in the singular include components described in the plural.

[0036] It should be understood that the components included in the embodiments of this disclosure include tolerance ranges, although they are not described in further detail.

[0037] In describing various embodiments of this disclosure, when using terms for positional relationships such as “above,” “over,” “below,” and “beside,” at least one intermediate element may exist between two elements unless “exactly” or “directly” is used.

[0038] When describing various embodiments of this disclosure, when describing time relationships, for example when using terms such as "after," "following," "next," and "before" to describe the time relationships of events, there may be cases where events are not consecutive, unless "immediately" or "directly" is used.

[0039] Furthermore, while various constituent elements may be described using terms including ordinal numbers such as first or second, the constituent elements are not limited to these terms, and these terms are used only for the purpose of distinguishing one constituent element from another. Therefore, unless otherwise specified, within the scope of this disclosure, a first component may refer to a second component.

[0040] The corresponding features of various embodiments according to this disclosure may be combined or integrated in part or in whole, and may be variably related or operated in terms of technology, and the embodiments may be implemented independently or in combination.

[0041] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope.

[0042] Any implementation described as an "example" in this document is not necessarily to be construed as preferred or superior to other implementations.

[0043] Furthermore, when a component or layer is “connected,” “linked,” or “attached” to another component or layer, unless otherwise stated, the component or layer may not only be directly connected or attached to the other component or layer, but also indirectly connected or adhered to it, wherein one or more intermediate components or layers are “set” or “intercalated” between the components or layers. This should be understood to mean that components may be arranged to be in direct contact with each other, or may be arranged to be in direct contact with each other.

[0044] The terms “first element,” “second element,” and / or “third element” should be understood as one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. For example, A, B, and / or C can refer to only A; only B; only C; any or some combinations of A, B, and C; or all of A, B, and C.

[0045] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element, the first element, the second element, or the third element.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments pertain. It should also be understood that terms, such as those defined in common dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense unless expressly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the functions described herein that would be understood by one of ordinary skill in the art.

[0047] In the following description, a display device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0048] Figure 1 This is a schematic cross-sectional view of a flexible display device according to an embodiment of the present disclosure. Figure 2 This is a circuit diagram of the sub-pixels included in a display device according to an embodiment of the present disclosure.

[0049] like Figure 1As shown, the display device according to the embodiments of the present disclosure may include a display panel 100, a back plate 200 disposed below the display panel 100, and a cover window 300 disposed above the display panel 100.

[0050] The cover window 300 can be made of impact-resistant and light-transmitting reinforced glass or plastic film to protect the display panel 100 from external impacts, moisture, heat, etc. When the cover window 300 is made of plastic film, the plastic film may include, but is not limited to, polyimide (PI) film, polyethylene terephthalate (PET) film, polypropylene glycol (PPG) film, polycarbonate (PC) film, etc.

[0051] When the cover window 300 is made of tempered glass, it may break due to external force or stress. In this case, to prevent or reduce the scattering of fragments from the cover window 300, a shatterproof film can be installed on the upper surface of the cover window 300. The shatterproof film may include, for example, a base film containing polyethylene terephthalate (PET) and colorless polyimide (CPI), or a laminate of polyethylene terephthalate (PET) and colorless polyimide (CPI). A hard coating, an anti-reflective layer, an anti-fingerprint layer, etc., may be coated on the upper surface of the base film.

[0052] The display panel 100 may include a display area and a non-display area. The display area has multiple pixels for displaying images, and the non-display area is arranged around the display area to surround it.

[0053] The display panel 100 may be a flexible display panel including a plurality of sub-pixels formed on a flexible substrate. The display panel 100 may be an organic light-emitting diode panel.

[0054] When the display panel 100 is an organic light-emitting diode (OLED) panel, each sub-pixel includes a light-emitting element and a pixel circuit configured to control the driving of the light-emitting element. In this case, the light-emitting element may consist of an anode, a cathode, and a light-emitting layer between the anode and the cathode.

[0055] like Figure 2 As shown, each sub-pixel may include a switching transistor ST, a driving transistor DT, a compensation circuit CC, a light-emitting element OLED, and a storage capacitor Cst.

[0056] The light-emitting element OLED can be operated to emit light according to the driving current generated by the driving transistor DT.

[0057] The switching transistor ST can perform a switching operation, causing the data signal provided via the data line, corresponding to the scan signal provided via the gating line, to be stored as a data voltage in the storage capacitor Cst. The storage capacitor Cst can maintain the data voltage for one frame.

[0058] The driving transistor DT can be operated such that a constant driving current can flow between the high-level driving voltage supply line EVDD and the low-level driving voltage supply line EVSS, corresponding to the data voltage stored in the storage capacitor Cst.

[0059] The compensation circuit CC is a circuit configured to compensate for the threshold voltage, etc., of the driving transistor DT. The compensation circuit CC may include one or more thin-film transistors and one or more capacitors. The compensation circuit CC can have various configurations depending on its compensation method.

[0060] For example, although Figure 2 The sub-pixel shown is configured with a 2T (transistor) 1C (capacitor) structure including a switching transistor ST, a driving transistor DT, a storage capacitor Cst, and a light-emitting element OLED. However, when a compensation circuit CC is added, the sub-pixel can be configured with various structures such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, and 8T1C.

[0061] Each subpixel can be divided into red, green, and blue pixels for color rendering. Subpixels can also include white pixels.

[0062] The backsheet 200 may be made of a polymer film. The polymer film that can be used for the backsheet 200 may be made of polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC) or polyethylene naphthalate (PEN), but is not limited to these.

[0063] Figure 3 This is a cross-sectional view showing a pixel disposed in the display area of ​​a display panel according to an embodiment of the present disclosure.

[0064] The light-emitting element OLED, the transistors TFT1 and TFT2 configured to drive the light-emitting element OLED, the capacitor CST, and the encapsulation layer 120 can be disposed on the substrate 111 of the display area.

[0065] Transistors TFT1 and TFT2 may include silicon thin-film transistors containing polycrystalline semiconductor materials and oxide thin-film transistors containing oxide semiconductor materials. In this case, the thin-film transistor containing polycrystalline semiconductor materials is sometimes referred to as "polycrystalline thin-film transistor TFT1," and the thin-film transistor containing oxide semiconductor materials is referred to as "oxide thin-film transistor TFT2." For example, polycrystalline thin-film transistor TFT1 may be a transistor connected to a light-emitting element OLED, and oxide thin-film transistor TFT2 may be a transistor connected to a capacitor CST.

[0066] Conversely, a thin-film transistor containing polycrystalline semiconductor material can be called a "polycrystalline thin-film transistor TFT2", and a thin-film transistor containing oxide semiconductor material can be called an "oxide thin-film transistor TFT1". For example, polycrystalline thin-film transistor TFT2 can be a transistor connected to a capacitor CST, and oxide thin-film transistor TFT1 can be a transistor connected to a light-emitting element OLED.

[0067] In the following description, a thin-film transistor containing polycrystalline semiconductor material is sometimes referred to as "polycrystalline thin-film transistor TFT1", and a thin-film transistor containing oxide semiconductor material is referred to as "oxide thin-film transistor TFT2".

[0068] The substrate 111 can be a flexible substrate. When the substrate 111 is a flexible substrate, the substrate 111 can be implemented as a multilayer structure having alternating layers of organic and inorganic layers. For example, the substrate 111 can be configured to have an alternating structure of an organic layer made of, for example, polyimide and an inorganic layer made of, for example, silicon oxide (SiO2).

[0069] A lower buffer layer 112a may be formed on the substrate 111. The lower buffer layer 112a may be configured to prevent moisture or the like from being introduced from the outside. The lower buffer layer 112a may be composed of silicon oxide (SiO2) layers or the like stacked to form a multilayer structure. An auxiliary buffer layer 112b may be further disposed on the lower buffer layer 112a to protect the device from moisture.

[0070] A polycrystalline thin-film transistor (TFT) 1 can be formed on a substrate 111. The TFT 1 can use a polycrystalline semiconductor as its active layer. The TFT 1 may include a first active layer ACT1, a first gate GE1, a first source SD1, and a first drain SD2. The first active layer ACT1 includes a channel through which electrons or holes move. A first gate insulating layer 113 may be disposed between the first gate GE1 and the first active layer ACT1. The first gate insulating layer 113 may be made of materials such as silicon oxide (SiO2) or silicon nitride (SiN). x It is composed of inorganic layers such as layers, and has a single-layer structure or a multi-layer structure.

[0071] The first active layer ACT1 may include a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the other side of the first channel region. In this case, the first channel region is disposed between the first source region and the first drain region. The first source region and the first drain region are processed into conductive regions by doping an intrinsic polycrystalline semiconductor material with group V or group III impurity ions such as phosphorus (P) or boron (B) ions at a predetermined concentration. In the first channel region, the polycrystalline semiconductor material remains in its intrinsic state; therefore, the first channel region can provide pathways for electron and hole movement.

[0072] According to an embodiment, the polycrystalline thin-film transistor TFT1 can be implemented with a top-gate structure, wherein a first gate GE1 is disposed above a first active layer ACT1. Therefore, the same material as the first gate GE1 can be used to form the first electrode CST1 included in the capacitor CST and the light-shielding layer LS included in the oxide thin-film transistor TFT2. In this case, the first gate GE1, the first electrode CST1, and the light-shielding layer LS can be formed by a single mask process, and thus the number of mask processes can be reduced.

[0073] The first gate GE1 can be made of a metallic material. For example, the first gate GE1 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0074] The first interlayer insulating layer 114 can be disposed on the first gate GE1. The first interlayer insulating layer 114 can be made of silicon oxide (SiO2) or silicon nitride (SiN). x This can be achieved through methods such as )

[0075] The display panel 100 may further include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117, which are sequentially disposed above the first interlayer insulating layer 114.

[0076] The first source SD1 and the first drain SD2 of the polycrystalline thin-film transistor TFT1 can be formed on the second interlayer insulating layer 117. The first source SD1 and the first drain SD2 of the polycrystalline thin-film transistor TFT1 can be connected to the first source region and the first drain region of the first active layer ACT1, respectively, through contact holes extending through the first gate insulating layer 113, the first interlayer insulating layer 114, the upper buffer layer 115, the second gate insulating layer 116, and the second interlayer insulating layer 117.

[0077] The upper buffer layer 115 can separate the second active layer ACT2 of the oxide thin film transistor TFT2, which is implemented using an oxide semiconductor material, from the first active layer ACT1, which is implemented using a polycrystalline semiconductor material, and can provide a substrate for forming the second active layer ACT2.

[0078] The oxide thin-film transistor TFT2 can be formed on the upper buffer layer 115. The oxide thin-film transistor TFT2 may include a second active layer ACT2 implemented using an oxide semiconductor material, a second gate GE2 disposed on the second gate insulating layer 116, and a second source SD3 and a second drain SD4 disposed on the second interlayer insulating layer 117.

[0079] The second active layer ACT2 can be implemented using an oxide semiconductor material and may include a second channel region configured to be intrinsic and undoped, and a second source region and a second drain region processed to be conductive by doping.

[0080] The oxide thin-film transistor TFT2 may further include a light-shielding layer LS disposed below the upper buffer layer 115 and overlapping with the second active layer ACT2. The light-shielding layer LS blocks light incident from the substrate 111 side, thereby ensuring the reliability of the oxide thin-film transistor TFT2. The light-shielding layer LS may be made of the same material as the first gate GE1 and may be formed on the upper surface of the first gate insulating layer 113. The light-shielding layer LS may be electrically connected to the second gate GE2, thereby forming a dual-gate configuration.

[0081] The second source electrode SD3 and the second drain electrode SD4 can be formed on the second interlayer insulating layer 117 simultaneously with the first source electrode SD1 and the first drain electrode SD2 using the same material. Therefore, the number of mask processes can be reduced.

[0082] The second gate insulating layer 116 may cover the second active layer ACT2 of the oxide thin-film transistor TFT2. The second gate insulating layer 116 can be implemented using an inorganic layer because it is formed on the second active layer ACT2 implemented using an oxide semiconductor material. For example, the second gate insulating layer 116 may be made of silicon oxide (SiO2), silicon nitride (SiNx), etc.

[0083] The second gate GE2 can be made of a metallic material. For example, the second gate GE2 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0084] Simultaneously, the first electrode CST1 can be disposed on the first gate insulating layer 113, and the second electrode CST2 can be disposed on the first interlayer insulating layer 114, such that the second electrode CST2 overlaps with the first electrode CST1, thereby realizing the capacitor CST. The first electrode CST1 can be formed using the same material as the light-shielding layer LS and the first gate GE1.

[0085] For example, the second electrode CST2 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0086] A capacitor CST can be used to store the data voltage applied to it via the data line DL for a predetermined period. The capacitor CST may include two electrodes facing each other and a dielectric disposed between the two electrodes. A first interlayer insulating layer 114 may be disposed between the first electrode CST1 and the second electrode CST2.

[0087] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the second source SD3 or the second drain SD4 of the oxide thin-film transistor TFT2. Of course, the connection relationship of the capacitor CST can vary depending on the sub-pixel driving circuit and is not limited to the connection relationship described above.

[0088] The first planarization layer 118 and the second planarization layer 119 can be sequentially disposed on the polycrystalline thin-film transistor TFT1, the oxide thin-film transistor TFT2, and the capacitor CST for surface planarization. Each of the first planarization layer 118 and the second planarization layer 119 can be an organic layer made of polyimide or acrylic resin. The light-emitting element OLED can be formed on the second planarization layer 119.

[0089] An OLED (Optical Display Cell) may include an anode (ANO), a cathode (CAT), and an emitting layer (EL) disposed between the ANO and the CAT. When the sub-pixel driving circuit is implemented using a low-level driving voltage commonly connected to the cathode (CAT), the ANO is configured as a separate electrode for each sub-pixel. Conversely, when the sub-pixel driving circuit is implemented using a high-level driving voltage, the cathode (CAT) can be configured as a separate electrode for each sub-pixel.

[0090] The light-emitting element OLED can be electrically connected to the driving element via an intermediate electrode CNE disposed on the first planarization layer 118. For example, the anode ANO of the light-emitting element OLED and the first source SD1 of the polycrystalline thin-film transistor TFT1 can be interconnected via the intermediate electrode CNE.

[0091] The anode ANO can be connected to the intermediate electrode CNE, which is exposed through a contact hole extending through the second planarization layer 119. The intermediate electrode CNE can be connected to the first source SD1, which is exposed through a contact hole extending through the first planarization layer 118.

[0092] The intermediate electrode CNE serves as the dielectric for interconnecting the first source electrode SD1 and the anode ANO. The intermediate electrode CNE can be made of conductive materials such as copper (Cu), silver (Ag), molybdenum (Mo), or titanium (Ti).

[0093] The second planarization layer 119 and the intermediate electrode CNE can be omitted. When the second planarization layer 119 and the intermediate electrode CNE are omitted, the anode ANO can be directly electrically connected to the exposed first source SD1 through a contact hole extending through the first planarization layer 118.

[0094] The anode ANO can be formed as a multilayer structure having a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer can be made of a material with a relatively large work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive layer can be formed as a single-layer or multilayer structure having aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode ANO can be formed as a structure having a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer stacked sequentially, or a structure having a transparent conductive layer and an opaque conductive layer stacked sequentially.

[0095] The dam layer (BNK) can be a subpixel-defining layer configured to expose the anode (ANO) of each subpixel. The dam layer (BNK) can be formed of an opaque material (e.g., black) to prevent or reduce light interference between adjacent subpixels. In this case, the dam layer (BNK) can comprise a light-shielding material composed of at least one of colored pigments, organic black pigments, or carbon black pigments.

[0096] The luminescent layer (EL) can be formed by sequentially or in reverse stacking a hole-correlated layer comprising a hole injection layer (HIL) and a hole transport layer (HTL), an organic luminescent layer comprising an luminescent layer (EM), and an electron-correlated layer comprising an electron transport layer (ETL) and an electron injection layer (EIL). Although in Figure 3 Only the hole transport layer (HTL), the light-emitting layer (EM), and the electron transport layer (ETL) are shown in the diagram, but this disclosure is not limited thereto.

[0097] With the light-emitting layer EL sandwiched between the cathode CAT and the anode ANO, the cathode CAT is formed on the upper and side surfaces of the light-emitting layer EL to face the anode ANO. The cathode CAT can be formed as an integrated structure covering the entire display area. When the cathode CAT is applied to a top-emitting organic light-emitting display device, the cathode CAT can be composed of a transparent conductive layer made of, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0098] Additionally, an encapsulation layer 120 for suppressing moisture penetration can be further disposed on the cathode CAT. The encapsulation layer 120 can prevent or reduce the penetration of ambient moisture or oxygen into the light-emitting layer EL, which is susceptible to ambient moisture or oxygen. For this function, the encapsulation layer 120 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer, but is not limited thereto. The encapsulation layer 120 may include a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123 stacked sequentially.

[0099] The first encapsulation layer 121 and the third encapsulation layer 123 can be made of an inorganic insulating material that can be deposited at low temperatures, such as silicon nitride (SiN). x ), silicon dioxide (SiO) x The first encapsulation layer 121 and the third encapsulation layer 123 are deposited in a low-temperature atmosphere, thus preventing or reducing damage to the light-emitting layer EL, which is susceptible to high-temperature atmospheres, during the deposition process of the first encapsulation layer 121 and the third encapsulation layer 123.

[0100] The second encapsulation layer 122 can perform a buffering function to reduce stress between adjacent layers due to bending of the display device, and can flatten the steps between adjacent layers. The second encapsulation layer 122 can be made of a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene or silicon carbide (SiOC) or a photosensitive organic insulating material such as photoreactive acrylic, but is not limited thereto.

[0101] A temporary protective film 151 may be applied to the encapsulation layer 120 for use in subsequent processes. The temporary protective film 151 may also be removed (peeled off) before performing subsequent processes.

[0102] Figure 4 This is a cross-sectional view showing the non-display area of ​​a light-emitting display panel according to an embodiment of the present disclosure.

[0103] Figure 4 The layers shown and their construction and reference Figure 3 The same as those described, therefore, with Figure 3 The same reference numerals in the figures are specified, and their specific details are omitted.

[0104] The lower buffer layer 112a and the auxiliary buffer layer 112b can be disposed on the substrate 111 in the non-display area to prevent moisture and other substances from being introduced from the outside.

[0105] In addition, the first gate insulating layer 113, the first interlayer insulating layer 114, the upper buffer layer 115, the second gate insulating layer 116, and the second interlayer insulating layer 117 are disposed on the substrate 111 in the non-display area.

[0106] A low-level drive voltage supply line EVSS configured to supply a low-level drive voltage can be disposed on the second interlayer insulation layer 117.

[0107] The first planarization layer 118 and the second planarization layer 119 can be sequentially disposed on the low-level drive voltage supply line EVSS for surface planarization. (See reference...) Figure 3 The second planarization layer 119 can be omitted. The first planarization layer 118 and the second planarization layer 119 on the low-level drive voltage supply line EVSS can be selectively removed to expose the low-level drive voltage supply line EVSS, and thus the first contact hole C1 can be formed.

[0108] The connecting electrode 127 can be disposed on the second planarization layer 119. The connecting electrode 127 can be used with a reference... Figure 3 The anode of the described OLED is formed of the same material. The connecting electrode 127 can be electrically connected to the low-level drive voltage supply line EVSS through the first contact hole C1.

[0109] A dam layer (BNK) can be disposed on the connecting electrode 127. The dam layer (BNK) has a second contact hole (C2) exposing the connecting electrode 127. The hole transport layer (HTL) and electron transport layer (ETL), which are part of the light-emitting layer (EL), can extend to be disposed on the dam layer (BNK) in the non-display area.

[0110] The cathode CAT of the OLED light-emitting element can extend to be disposed on the embankment layer BNK in the non-display area. The cathode CAT can be electrically connected to the connecting electrode 127 through the second contact hole C2.

[0111] Metal pattern 130 can be formed on the embankment layer BNK at the end of the cathode CAT in the non-display area.

[0112] To cover the metal pattern 130, the end of the cathode CAT, the second contact hole C2, and the end of the embankment layer BNK, an organic insulating layer pattern 131 may be formed on the embankment layer BNK. The organic insulating layer pattern 131 may include a high-viscosity material. For example, the organic insulating layer pattern 131 may be formed from a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon carbide (SiOC), or a photosensitive organic insulating material such as photoreactive acrylic acid.

[0113] An encapsulation layer 120 configured to inhibit moisture penetration can be disposed on the cathode CAT and organic insulating layer pattern 131. The encapsulation layer 120 may include a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123 stacked sequentially.

[0114] The first encapsulation layer 121 can extend from the display area to the non-display area, such that the first encapsulation layer 121 is disposed in both the display area and the non-display area. The first encapsulation layer 121 can extend to the border area via the organic insulating layer pattern 131.

[0115] The second encapsulation layer 122 can extend from the display area to the non-display area, such that the second encapsulation layer 122 is disposed on the first encapsulation layer 121. The second encapsulation layer 122 can extend into the interior of the organic insulating layer pattern 131.

[0116] The third encapsulation layer 123 can extend from the display area to the non-display area, such that the third encapsulation layer 123 is disposed on the second encapsulation layer 122 and the first encapsulation layer 121. The third encapsulation layer 123 can extend to the border area via the organic insulating layer pattern 131.

[0117] A temporary protective film 151 may be disposed on the encapsulation layer 120 to extend over the display area and non-display area for subsequent processing. The temporary protective film 151 may also be removed (peeled off) before performing subsequent processing.

[0118] Hereinafter, a method for manufacturing a display device according to embodiments of the present disclosure will be described.

[0119] Figures 5A to 5E This is a view showing a cross-section of a display panel formed in a display area according to an embodiment of the present disclosure. Figures 6A to 6E This is a view showing a cross-section of a display panel formed in a non-display area according to an embodiment of the present disclosure.

[0120] like Figure 5A and Figure 6AAs shown, substrate 111 is fabricated. Substrate 111 can be a flexible substrate. When substrate 111 is a flexible substrate, substrate 111 can be implemented as a multilayer structure in which organic layers and inorganic layers are alternately stacked. For example, substrate 111 can be configured to have a structure in which organic layers, such as polyimide, and inorganic layers, such as silicon oxide (SiO2), are alternately stacked.

[0121] Because of the flexible nature of this type of plastic substrate, it is difficult to use the plastic substrate itself in the manufacturing process of display devices. Therefore, the process is carried out by attaching the plastic substrate to one surface of a carrier substrate such as a glass substrate.

[0122] Specifically, a plastic substrate is formed on a carrier substrate, and then a thin-film transistor array layer, a light-emitting element array layer, and an encapsulation layer (described later) are sequentially formed on the plastic substrate. A temporary protective film is then attached to the encapsulation layer. Afterward, the carrier substrate is removed from the plastic substrate, and the temporary protective film is removed from the encapsulation layer. Finally, the polarizer and cover glass are bonded to the encapsulation layer. Figure 5A and Figure 6A The image shows a state where the carrier substrate is omitted.

[0123] The lower buffer layer 112a and the auxiliary buffer layer 112b can be sequentially formed on the substrate 111 in both the display area and the non-display area. The lower buffer layer 112a can be configured to prevent moisture or the like from being introduced from the outside. The lower buffer layer 112a can be composed of silicon oxide (SiO2) layers or the like stacked to form a multilayer structure. At least one of the lower buffer layer 112a or the auxiliary buffer layer 112b may be omitted.

[0124] A first thin-film transistor (TFT1), a capacitor CST, and a second thin-film transistor (TFT2) can be formed on a substrate 111 in the display area. The first thin-film transistor (TFT1) can use a polycrystalline semiconductor as its active layer. The first thin-film transistor (TFT1), as a polycrystalline thin-film transistor, may include a first active layer ACT1, a first gate GE1, a first source SD1, and a first drain SD2. The first active layer ACT1 includes a channel through which electrons or holes move. A first gate insulating layer 113 can be disposed between the first gate GE1 and the first active layer ACT1. The first gate insulating layer 113 may be made of materials such as silicon oxide (SiO2) or silicon nitride (SiN). x It is composed of inorganic layers such as layers, and has a single-layer structure or a multi-layer structure.

[0125] The first active layer ACT1 may include a first channel region, a first source region disposed on one side of the first channel region, and a first drain region disposed on the other side of the first channel region. The first channel region is disposed between the first source region and the first drain region. The first source region and the first drain region are processed into conductive regions by doping an intrinsic polycrystalline semiconductor material with group V or group III impurity ions such as phosphorus (P) or boron (B) at a predetermined concentration. In the first channel region, the polycrystalline semiconductor material remains in its intrinsic state; therefore, the first channel region can provide pathways for electron and hole movement.

[0126] According to an embodiment, the first thin-film transistor TFT1 can be implemented with a top-gate structure, wherein the first gate GE1 is disposed above the first active layer ACT1. Therefore, the same material as the first gate GE1 can be used to form the first electrode CST1 included in the capacitor CST and the light-shielding layer LS included in the second thin-film transistor TFT2, which is an oxide thin-film transistor. In this case, the first gate GE1, the first electrode CST1, and the light-shielding layer LS can be formed by a single mask process, and thus the number of mask processes can be reduced.

[0127] The first gate GE1 can be made of a metallic material. For example, the first gate GE1 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0128] The first interlayer insulating layer 114 can be disposed on the first gate GE1. The first interlayer insulating layer 114 can be made of silicon oxide (SiO2) or silicon nitride (SiN). x This can be achieved through methods such as )

[0129] The substrate 111 may also include an upper buffer layer 115, a second gate insulating layer 116, and a second interlayer insulating layer 117 sequentially disposed above the first interlayer insulating layer 114.

[0130] The first source SD1 and the first drain SD2 of the first thin-film transistor TFT1 can be formed on the second interlayer insulating layer 117. The first source SD1 and the first drain SD2 of the first thin-film transistor TFT1 can be connected to the first source region and the first drain region of the first active layer ACT1 respectively through contact holes extending through the first gate insulating layer 113, the first interlayer insulating layer 114, the upper buffer layer 115, the second gate insulating layer 116, and the second interlayer insulating layer 117.

[0131] The upper buffer layer 115 can separate the second active layer ACT2 of the second thin film transistor TFT2, which is implemented using an oxide semiconductor material, from the first active layer ACT1, which is implemented using a polycrystalline semiconductor material, and can provide a substrate for forming the second active layer ACT2.

[0132] The second thin-film transistor TFT2 can be formed on the upper buffer layer 115. The second thin-film transistor TFT2 may include a second active layer ACT2 implemented using an oxide semiconductor material, a second gate GE2 disposed on the second gate insulating layer 116, and a second source SD3 and a second drain SD4 disposed on the second interlayer insulating layer 117.

[0133] The second active layer ACT2 can be implemented using an oxide semiconductor material and may include a second channel region configured to be intrinsic and undoped, and a second source region and a second drain region processed to be conductive by doping.

[0134] The second thin-film transistor TFT2 may further include a light-shielding layer LS disposed below the upper buffer layer 115 and overlapping with the second active layer ACT2. The light-shielding layer LS blocks light incident from the substrate 111 side, thereby ensuring the reliability of the second thin-film transistor TFT2. The light-shielding layer LS may be made of the same material as the first gate GE1 and may be formed on the upper surface of the first gate insulating layer 113. The light-shielding layer LS may be electrically connected to the second gate GE2, thereby forming a dual-gate configuration.

[0135] The second source electrode SD3 and the second drain electrode SD4 can be formed on the second interlayer insulating layer 117 simultaneously with the first source electrode SD1 and the first drain electrode SD2 using the same material. Therefore, the number of mask processes can be reduced.

[0136] Using the same material as the first source SD1, first drain SD2, second source SD3 and second drain SD4, a low-level drive voltage supply line EVSS is formed on the second interlayer insulating layer 117 in the non-display area.

[0137] The second gate insulating layer 116 can cover the second active layer ACT2 of the second thin-film transistor TFT2. The second gate insulating layer 116 can be implemented using an inorganic layer because it is formed on the second active layer ACT2 implemented using an oxide semiconductor material. For example, the second gate insulating layer 116 can be made of silicon oxide (SiO2) or silicon nitride (SiN). x Made from (etc.)

[0138] The second gate GE2 can be made of a metallic material. For example, the second gate GE2 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys, but is not limited thereto.

[0139] Simultaneously, the first electrode CST1 can be disposed on the first gate insulating layer 113, and the second electrode CST2 can be disposed on the first interlayer insulating layer 114, such that the second electrode CST2 overlaps with the first electrode CST1, thereby realizing the capacitor CST. The first electrode CST1 can be formed using the same material as the light-shielding layer LS and the first gate GE1.

[0140] For example, the second electrode CST2 can be a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or their alloys.

[0141] A capacitor CST can be used to store the data voltage applied to it via a data line DL for a predetermined period of time. The capacitor CST may include two electrodes facing each other and a dielectric material disposed between the two electrodes. A first interlayer insulating layer 114 may be disposed between the first electrode CST1 and the second electrode CST2.

[0142] The first electrode CST1 or the second electrode CST2 of the capacitor CST can be electrically connected to the second source SD3 or the second drain SD4 of the second thin-film transistor TFT2. Of course, the connection relationship of the capacitor CST can vary according to the sub-pixel driving circuit and is not limited to the connection relationship described above.

[0143] The first gate insulating layer 113, the first interlayer insulating layer 114, the upper buffer layer 115, the second gate insulating layer 116, and the second interlayer insulating layer 117 can be formed as a non-display area extending onto the substrate 111, such as... Figure 6A As shown.

[0144] like Figure 5B and Figure 6B As shown, a first planarization layer 118 can be formed on the first thin-film transistor TFT1, the second thin-film transistor TFT2, and the capacitor CST for surface planarization. The first planarization layer 118 is then selectively removed to expose the first source electrode SD1, thereby forming a contact hole.

[0145] A conductive material such as copper (Cu), silver (Ag), or titanium (Ti) is deposited on the first planarization layer 118, and then the conductive material is selectively removed, such that an intermediate electrode CNE is formed on the first planarization layer 118 in the display area to be electrically connected to the first source electrode SD1 through a contact hole.

[0146] A second planarization layer 119 is formed on a first planarization layer 118, which includes the intermediate electrode CNE. A first contact hole C1 is formed through the first planarization layer 118 and the second planarization layer 119 to expose the intermediate electrode CNE and the low-level drive voltage supply line EVSS.

[0147] The first planarization layer 118 and the second planarization layer 119 can be organic layers made of polyimide or acrylic resin.

[0148] An anode (ANO) is formed on the second planarization layer 119 in the display area, such that the anode (ANO) is electrically connected to the intermediate electrode (CNE) through the first contact hole (C1). Simultaneously, a connection electrode (127) is formed on the second planarization layer 119 in the non-display area, such that the connection electrode (127) is electrically connected to the low-level drive voltage supply line (EVSS) through the first contact hole (C1).

[0149] The anode (ANO) and connecting electrode 127 can be formed as a multilayer structure having a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer can be made of a material with a relatively large work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive layer can be formed as a single-layer or multilayer structure having aluminum (Al), silver (Ag), copper (Cu), lead (Pb), molybdenum (Mo), titanium (Ti), or alloys thereof. For example, the anode (ANO) can be formed as a structure having a transparent conductive layer, an opaque conductive layer, and a transparent conductive layer stacked sequentially, or a structure having a transparent conductive layer and an opaque conductive layer stacked sequentially.

[0150] The second planarization layer 119 and the intermediate electrode CNE can be omitted. When the second planarization layer 119 and the intermediate electrode CNE are omitted, the anode ANO that will be formed subsequently can be directly electrically connected to the first source SD1 exposed through a contact hole extending through the first planarization layer 118.

[0151] like Figure 5C and Figure 6C As shown, a dam layer BNK is formed on a second planarization layer 119 including the anode ANO and the connecting electrode 127. Subsequently, the dam layer BNK is selectively removed to form an opening region on the anode ANO and a second contact hole C2 at the connecting electrode 127.

[0152] The dam layer (BNK) can be a subpixel-defining layer configured to expose the anode (ANO) of each subpixel. The dam layer (BNK) can be formed of an opaque material (e.g., black) to prevent light interference between adjacent subpixels. In this case, the dam layer (BNK) can comprise a light-shielding material composed of at least one of colored pigments, organic black pigments, or carbon black pigments.

[0153] Subsequently, as Figure 6C As shown, a metal pattern 130 can be formed on the embankment layer BNK in the non-display area. The metal pattern 130 can be formed at a location overlapping with the end of the cathode CAT that will be subsequently formed.

[0154] like Figure 5D and Figure 6D As shown, a light-emitting layer EL is formed on the anode ANO. The light-emitting layer EL can be formed by sequentially or in reverse stacking a hole-correlated layer comprising a hole injection layer HIL and a hole transport layer HTL, an organic light-emitting layer comprising a light-emitting layer EM, and an electron-correlated layer comprising an electron transport layer ETL and an electron injection layer EIL. Although in Figure 5D Only the hole transport layer (HTL), the light-emitting layer (EM), and the electron transport layer (ETL) are shown in the diagram, but this disclosure is not limited thereto.

[0155] The hole transport layer (HTL) and electron transport layer (ETL), which are part of the light-emitting layer (EL), can be extended to be set on the embankment layer (BNK) in the non-display area.

[0156] The cathode CAT is formed on the light-emitting layer EL and the embankment layer BNK. The cathode CAT can be formed on the upper and side surfaces of the light-emitting layer EL to face the anode ANO. The cathode CAT can be formed as an integrated structure covering the entire display area. The cathode CAT can be electrically connected to the connecting electrode 127 through the second contact hole C2 of the embankment layer BNK. When the cathode CAT is applied to a top-emitting type organic light-emitting display device, the cathode CAT can be composed of a transparent conductive layer made of, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0157] In the non-display area, the end of the cathode CAT may overlap with the metal pattern 130.

[0158] At the same time, such as Figure 6E As shown, in the non-display area, the end of the cathode CAT overlapping with the metal pattern 130 is removed by laser irradiation.

[0159] To cover the metal pattern 130, the end of the cathode CAT, the second contact hole C2, and the end of the embankment layer BNK, an organic insulating layer pattern 131 is formed on the embankment layer BNK. The organic insulating layer pattern 131 may include a high-viscosity material. For example, the organic insulating layer pattern 131 may be formed from a non-photosensitive organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon carbide (SiOC), or a photosensitive organic insulating material such as photoreactive acrylic acid.

[0160] An encapsulation layer 120 for inhibiting moisture penetration is formed on the cathode CAT and organic insulating layer pattern 131. The encapsulation layer 120 may include a first encapsulation layer 121, a second encapsulation layer 122, and a third encapsulation layer 123 stacked sequentially.

[0161] The first encapsulation layer 121 can extend from the display area to the non-display area, such that the first encapsulation layer 121 is disposed in both the display area and the non-display area. The first encapsulation layer 121 can extend to the border area via the organic insulating layer pattern 131.

[0162] The second encapsulation layer 122 can extend from the display area to the non-display area, such that the second encapsulation layer 122 is disposed on the first encapsulation layer 121. The second encapsulation layer 122 can extend into the interior of the organic insulating layer pattern 131.

[0163] The third encapsulation layer 123 can extend from the display area to the non-display area, such that the third encapsulation layer 123 is disposed on the second encapsulation layer 122 and the first encapsulation layer 121. The third encapsulation layer 123 can extend to the border area via the organic insulating layer pattern 131.

[0164] A temporary protective film 151 may be disposed on the encapsulation layer 120 to extend over the display area and non-display area for subsequent processing. The temporary protective film 151 may also be removed (peeled off) before performing subsequent processing.

[0165] Additionally, as described above, the carrier substrate is removed from the substrate 111, and the temporary protective film 151 is removed (peeled off) before performing subsequent processes. Then, the polarizer (not shown), touch sensor, cover glass, etc., are sequentially bonded.

[0166] Figure 7 This is a plan view of the display panel in the border area according to an embodiment of the present disclosure.

[0167] like Figure 7 As shown, in the display panel according to the embodiments of the present disclosure, the ends of the third encapsulation layer 123, the first encapsulation layer 121, the second encapsulation layer 122, the cathode CAT, and the light-emitting layer EM can be arranged sequentially from the outermost to the innermost direction with reference to the cutting lines in the frame area.

[0168] In addition, the organic insulating layer pattern 131 can be disposed between the end of the first encapsulation layer 121 and the end of the light-emitting layer EM, and the metal pattern 130 can be disposed on the portion of the embankment layer BNK adjacent to the end of the cathode CAT.

[0169] As described above, since the end of the cathode CAT overlapping with the metal pattern 130 is removed by laser irradiation, and the organic insulating layer pattern 131 is formed on the embankment layer BNK to cover the metal pattern 130, the end of the cathode CAT, the second contact hole C2, and the end of the embankment layer BNK, the phenomenon of the lower layer being lifted due to the removal force applied thereto when the temporary protective film 151 is removed to perform subsequent processes can be prevented or reduced. In particular, since the lifting of the cathode CAT is prevented or reduced, the occurrence of display device malfunctions can be reduced.

[0170] Furthermore, the organic insulating layer pattern 131 can serve as a barrier to block the flow of the second encapsulation layer 122 during the formation of the encapsulation layer 120. Therefore, it is not necessary to form a separate barrier, thus simplifying the process and reducing the panel bezel. With the reduction in panel bezel size, a narrow bezel can be achieved.

[0171] Because the number of display device failures is reduced, product costs can be lowered. Furthermore, environmental / social / governance (ESG) goals that reduce product costs can be achieved.

[0172] The display device and its manufacturing method according to various embodiments of the present disclosure can be explained as follows.

[0173] According to an embodiment of the present disclosure, the display device may include: a substrate including a display area configured to display an image and a non-display area disposed around the display area; a thin-film transistor disposed on the substrate in the display area; a planarization layer disposed on the thin-film transistor in both the display area and the non-display area, and having a first contact hole in the thin-film transistor; a dam layer disposed on the planarization layer in both the display area and the non-display area, and having an opening in the light-emitting area; a light-emitting element disposed on the planarization layer for connection to the thin-film transistor through the first contact hole; and an organic insulating layer pattern disposed on the dam layer in the non-display area to cover the cathode end of the light-emitting element.

[0174] According to embodiments of this disclosure, the display device may further include a metal pattern disposed on the embankment layer in a non-display area.

[0175] According to embodiments of this disclosure, a metal pattern can be disposed at the end of the cathode.

[0176] According to embodiments of this disclosure, the display device may further include a voltage supply line disposed below the planarization layer in a non-display area to provide voltage, and a connection electrode disposed on the planarization layer in the non-display area. The connection electrode may be electrically connected to the voltage supply line through a second contact hole formed in the planarization layer.

[0177] According to an embodiment of this disclosure, the cathode of the light-emitting element can be connected to the connecting electrode through a third contact hole formed in the embankment layer in the non-display area.

[0178] According to embodiments of this disclosure, the organic insulating layer pattern can cover the end of the cathode, the third contact hole, and the end of the dam layer.

[0179] According to embodiments of this disclosure, the display device may further include an encapsulation layer disposed on a cathode and an organic insulating layer pattern.

[0180] According to embodiments of the present disclosure, the encapsulation layer may include: a first inorganic encapsulation layer extending from a display area to a non-display area, such that the first inorganic encapsulation layer is disposed in both the display area and the non-display area, the first inorganic encapsulation layer extending to a border area via an organic insulating layer pattern; an organic encapsulation layer disposed on the first inorganic encapsulation layer, the organic encapsulation layer extending from the display area to the interior of the organic insulating layer pattern; and a second inorganic encapsulation layer disposed on the organic encapsulation layer, the second inorganic encapsulation layer extending from the display area through the organic insulating layer pattern to the border area.

[0181] According to embodiments of this disclosure, the organic insulating layer pattern may include a high-viscosity material.

[0182] According to embodiments of this disclosure, the organic insulating layer pattern may include non-photosensitive organic insulating materials, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or carbon dioxide silicon dioxide, or photosensitive organic insulating materials, such as photoreactive acrylic acid.

[0183] A method for manufacturing a display device according to embodiments of the present disclosure may include the following steps: preparing a substrate including a display area configured to display an image and a non-display area disposed around the display area; forming a thin-film transistor on the substrate in the display area and forming a voltage supply line on the substrate in the non-display area; forming a planarization layer on the thin-film transistor and the voltage supply line, such that the planarization layer has a first contact hole and a second contact hole on the thin-film transistor and the voltage supply line, respectively; forming an anode of a light-emitting element on the planarization layer, such that the anode is connected to the thin-film transistor through the first contact hole; forming a connection electrode on the planarization layer, such that the connection electrode is connected to the voltage supply line through the second contact hole; forming a dam layer on the planarization layer having the anode and the connection electrode, such that the dam layer has an opening region on the anode and a third contact hole on the connection electrode; forming a light-emitting layer on the anode in the opening region; forming a cathode on the light-emitting layer and the dam layer, such that the cathode is electrically connected to the connection electrode through the third contact hole; and forming an organic insulating layer pattern on the dam layer in the non-display area, such that the organic insulating layer covers the end of the cathode, the third contact hole, and the end of the dam layer.

[0184] According to embodiments of the present disclosure, the method may further include the following steps: forming a metal pattern between the embankment layer and the cathode in a non-display area, such that the metal pattern overlaps with the end of the cathode.

[0185] According to embodiments of this disclosure, the end of the cathode overlapping with the metal pattern can be removed by laser irradiation.

[0186] According to embodiments of this disclosure, the method may further include the step of forming an encapsulation layer on a cathode and an organic insulating layer pattern.

[0187] According to embodiments of this disclosure, the encapsulation layer may include: a first inorganic encapsulation layer extending from a display area to a non-display area, such that the first inorganic encapsulation layer is disposed in the display area and the non-display area, the first inorganic encapsulation layer extending to a border area through an organic insulating layer pattern; an organic encapsulation layer disposed on the first inorganic encapsulation layer, the organic encapsulation layer extending from the display area into the interior of the organic insulating layer pattern; and a second inorganic encapsulation layer disposed on the organic encapsulation layer, the second inorganic encapsulation layer extending from the display area through the organic insulating layer pattern to the border area.

[0188] According to embodiments of this disclosure, the method may further include the step of bonding a temporary protective film to an encapsulation layer.

[0189] According to embodiments of this disclosure, the method may further include the following steps: attaching a polarizer, a touch sensor, and a cover glass sequentially after removing the temporary protective film.

[0190] The present disclosure described above is not limited to the embodiments and drawings described herein. Therefore, those skilled in the art will understand that various substitutions, changes, and modifications can be made without departing from the scope of this disclosure.

[0191] Cross-references to related applications

[0192] This application claims the benefit of Korean Patent Application No. 10-2024-0154452, filed on November 4, 2024, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display device, comprising: A substrate, the substrate including a display area configured to display an image and a non-display area disposed around the display area; Thin-film transistors, wherein the thin-film transistors are disposed on the substrate in the display area; A planarization layer is disposed in the non-display area and on the thin-film transistor in the display area, the planarization layer having a first contact hole on the thin-film transistor; A dike layer, wherein the dike layer is disposed on the planarization layer in the display area and the non-display area, the dike layer having an opening area; A light-emitting element disposed on the planarization layer to be connected to the thin-film transistor through the first contact hole; as well as An organic insulating layer pattern is disposed on the embankment layer in the non-display area to cover the end of the cathode of the light-emitting element.

2. The display device according to claim 1, further comprising: A metallic pattern is disposed on the embankment layer in the non-display area.

3. The display device according to claim 2, wherein, The metal pattern is disposed at the end of the cathode.

4. The display device according to claim 1, further comprising: A voltage supply line is disposed in the non-display area below the planarization layer to supply voltage; as well as A connecting electrode is disposed on the planarization layer in the non-display area. The connecting electrode is electrically connected to the voltage supply line through a second contact hole formed in the planarization layer.

5. The display device according to claim 4, wherein, The cathode of the light-emitting element is connected to the connecting electrode through a third contact hole formed in the embankment layer in the non-display area.

6. The display device according to claim 5, wherein, The organic insulating layer pattern covers the end of the cathode, the third contact hole, and the end of the embankment layer.

7. The display device according to claim 1, further comprising: An encapsulation layer is disposed on the pattern of the cathode and the organic insulating layer.

8. The display device according to claim 7, wherein, The encapsulation layer includes: A first inorganic encapsulation layer extends from the display area to the non-display area, such that the first inorganic encapsulation layer is disposed in both the display area and the non-display area, and the first inorganic encapsulation layer extends to the border area via the organic insulating layer pattern. An organic encapsulation layer, disposed on the first inorganic encapsulation layer, extending from the display area to the organic insulating layer pattern; and A second inorganic encapsulation layer is disposed on the organic encapsulation layer, and the second inorganic encapsulation layer extends from the display area to the border area via the organic insulating layer pattern.

9. The display device according to claim 1, wherein, The organic insulating layer pattern includes a high-viscosity material.

10. The display device according to claim 9, wherein, The organic insulating layer pattern includes non-photosensitive organic insulating materials or photosensitive organic insulating materials.

11. The display device according to claim 10, wherein, The non-photosensitive organic insulating material is acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon carbide.

12. The display device according to claim 10, wherein, The photosensitive organic insulating material is photoreactive acrylic acid.

13. A method for manufacturing a display device, the method comprising the following steps: A substrate is prepared, the substrate including a display area configured to display an image and a non-display area disposed around the display area; Thin-film transistors are formed on the substrate in the display area; A voltage supply line is formed on the substrate in the non-display area; A planarization layer is formed on the thin-film transistor and the voltage supply line, such that the planarization layer has a first contact hole on the thin-film transistor and a second contact hole on the voltage supply line, respectively; An anode of a light-emitting element is formed on the planarization layer such that the anode is connected to the thin-film transistor through the first contact hole; A connection electrode is formed on the planarization layer such that the connection electrode is connected to the voltage supply line through the second contact hole; A dam layer is formed on the planarization layer having the anode and the connecting electrode, such that the dam layer has an opening region on the anode and a third contact hole on the connecting electrode; A light-emitting layer is formed on the anode in the opening region; A cathode is formed on the light-emitting layer and the embankment layer, such that the cathode is electrically connected to the connecting electrode through the third contact hole; as well as An organic insulating layer pattern is formed on the embankment layer in the non-display area such that the organic insulating layer covers the end of the cathode, the third contact hole, and the end of the embankment layer.

14. The method of claim 13, further comprising the step of: A metal pattern is formed in the non-display area between the embankment layer and the cathode, such that the metal pattern overlaps with the end of the cathode.

15. The method according to claim 14, wherein, The end of the cathode that overlaps with the metal pattern is removed by laser irradiation.

16. The method of claim 13, further comprising the step of: An encapsulation layer is formed on the cathode and the organic insulating layer pattern.

17. The method according to claim 16, wherein, The encapsulation layer includes: A first inorganic encapsulation layer extends from the display area to the non-display area, such that the first inorganic encapsulation layer is disposed in both the display area and the non-display area, and the first inorganic encapsulation layer extends to the border area via the organic insulating layer pattern. An organic encapsulation layer, disposed on the first inorganic encapsulation layer, extending from the display area to the organic insulating layer pattern; and A second inorganic encapsulation layer is disposed on the organic encapsulation layer, and the second inorganic encapsulation layer extends from the display area to the border area via the organic insulating layer pattern.

18. The method of claim 16, further comprising the step of: A temporary protective film is bonded to the encapsulation layer.

19. The method of claim 18, further comprising the step of: After removing the temporary protective film, the polarizer, touch sensor, and cover glass are attached in sequence.

20. The method according to claim 13, wherein, The organic insulating layer pattern includes non-photosensitive organic insulating materials or photosensitive organic insulating materials.

21. The method according to claim 20, wherein, The non-photosensitive organic insulating material is acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, polyethylene, or silicon carbide.

22. The method according to claim 20, wherein, The photosensitive organic insulating material is photoreactive acrylic acid.

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