Display device and electronic device including the same

Abstract

The present application relates to a display device and an electronic device including the same, the display device including: a substrate in which a display area including a first area and a second area and a non-display area surrounding one side of the display area are defined; a sub-pixel in the display area; dummy pixels in the non-display area; and a repair line provided to the display area and the non-display area. The repair lines include a first repair line and a second repair line arranged between the first pixel row and the second pixel row in the first region. The dummy pixels include a first dummy pixel and a second dummy pixel arranged in each of the first pixel row and the second pixel row. Each of the first dummy pixel and the second dummy pixel includes a dummy pixel circuit and a first capacitor. The first capacitor of each of the first dummy pixel and the second dummy pixel is between the dummy pixel circuit of the first dummy pixel and the dummy pixel circuit of the second dummy pixel.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0157063, filed on November 7, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of this disclosure relate to a display device, a method for repairing the display device, and an electronic device including the display device. Background Technology

[0004] With the recent increase in interest in information display, research and development of display devices are underway. Summary of the Invention

[0005] This disclosure provides a display device, a method for repairing the same, and an electronic device including the display device, which can improve reliability by preventing pixel dark spot failures.

[0006] Embodiments of this disclosure include a display device comprising: a substrate defining a display area including a first region and a second region, and a non-display area surrounding one side of the display area; sub-pixels disposed in the display area; dummy pixels disposed in the non-display area; and repair lines provided together to the display area and the non-display area, and extending in a first direction. The repair lines include: a first repair line and a second repair line disposed in the first region between a first pixel row and a second pixel row of the substrate. The dummy pixels include a first dummy pixel and a second dummy pixel respectively disposed corresponding to the first pixel row and the second pixel row. Each of the first dummy pixels and the second dummy pixel includes a dummy pixel circuit and a first capacitor electrically connected to the dummy pixel circuit. The first capacitor of each of the first dummy pixels and the second dummy pixel is disposed between the dummy pixel circuit of the first dummy pixel and the dummy pixel circuit of the second dummy pixel.

[0007] In this implementation, the first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel can be configured as a single entity. The first dummy pixel and the second dummy pixel can share the first capacitor.

[0008] In the implementation, the first repair line and the second repair line may extend in a first direction, may be spaced apart from each other in a second direction that intersects the first direction, and may be electrically insulated from each other.

[0009] In an embodiment, the display device may further include: a first bridging pattern extending in a second direction and electrically connected to the first repair line; and a second bridging pattern extending in a second direction and electrically connected to the second repair line.

[0010] In an implementation, a subpixel may include: a transistor disposed on a substrate; a light-emitting element electrically connected to the transistor and emitting light; and a contact electrode electrically connected to the light-emitting element and the transistor.

[0011] In one embodiment, the contact electrode may be arranged on the semiconductor pattern of the transistor, and the insulating layer is inserted between the contact electrode and the semiconductor pattern of the transistor, and can be electrically connected to the semiconductor pattern of the transistor through a first contact hole passing through the insulating layer.

[0012] In an implementation, in a plan view, based on the first contact hole, a first bridging pattern may be disposed on one side of the first contact hole, and a second bridging pattern may be disposed on the opposite side of the first contact hole.

[0013] In an implementation, in a plan view, based on the first contact hole, the first bridging pattern and the second bridging pattern can be disposed on one side of the first contact hole.

[0014] In one embodiment, the contact electrode may overlap with the first bridging pattern and the second bridging pattern. The contact electrode, the first bridging pattern, and the second bridging pattern may be electrically insulated from each other.

[0015] In one implementation, the first dummy pixel may be electrically connected to one of the first repair line and the second repair line, and the second dummy pixel may be electrically connected to the remaining (other) repair line of the first repair line and the second repair line.

[0016] In an implementation, a subpixel may include a pixel circuit. The pixel circuits of two subpixels facing each other in a second direction in a first region, with a first repair line and a second repair line interposed between them, may be mirror-symmetrical with respect to each other.

[0017] In one embodiment, a sub-pixel may include a transistor disposed on a substrate, a light-emitting element electrically connected to the transistor and emitting light, and a contact electrode electrically connecting the light-emitting element and the transistor. The display device also includes a bridging pattern disposed between sub-pixels disposed in a first pixel row and sub-pixels disposed in a second pixel row, and the bridging pattern is connected to corresponding repair lines in the first and second repair lines. The contact electrode of the sub-pixel disposed in the first pixel row overlaps with one end of the bridging pattern, and the contact electrode of the sub-pixel disposed in the second pixel row overlaps with the other end of the bridging pattern opposite to one end of the bridging pattern.

[0018] In an implementation, in each of the first pixel row and the second pixel row, the sub-pixel may include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in a first direction. A bridging pattern disposed between the first sub-pixel arranged in the first pixel row and the first sub-pixel arranged in the second pixel row can be connected to a first repair line. A bridging pattern disposed between the second sub-pixel arranged in the first pixel row and the second sub-pixel arranged in the second pixel row can be connected to a second repair line. A bridging pattern disposed between the third sub-pixel arranged in the first pixel row and the third sub-pixel arranged in the second pixel row can be connected to the first repair line.

[0019] In this implementation, the non-display area may include a first non-display area immediately adjacent to the first region and a second non-display area immediately adjacent to the second region. The first and second repair lines may be arranged within the first non-display area between the first and second dummy pixels arranged in the first pixel row and between the first and second dummy pixels arranged in the second pixel row.

[0020] Embodiments of this disclosure include a display device comprising: a substrate defining a display area and a non-display area surrounding one side of the display area; a subpixel disposed in the display area and including a transistor, a light-emitting element electrically connected to the transistor, and a contact electrode electrically connecting the light-emitting element and the transistor; a first repair line and a second repair line extending in a first direction and disposed between a first pixel row and a second pixel row of the substrate; a first dummy pixel and a second dummy pixel disposed in the non-display area and respectively disposed in the first pixel row and the second pixel row; and a first bridging pattern and a second bridging pattern disposed between the first repair line and the second repair line and extending in a second direction intersecting the first direction. The first bridging pattern is connected to the first repair line, and the second bridging pattern is connected to the second repair line. The contact electrode is disposed on a semiconductor pattern of the transistor, and an insulating layer is interposed between the contact electrode and the semiconductor pattern of the transistor, and the contact electrode is electrically connected to the semiconductor pattern through a first contact hole passing through the insulating layer. Based on the first contact hole, the first bridging pattern is disposed on one side of the first contact hole, and the second bridging pattern is disposed on the opposite side of the first contact hole.

[0021] In one embodiment, the contact electrode may overlap with the first bridging pattern and the second bridging pattern. The contact electrode, the first bridging pattern, and the second bridging pattern may be electrically insulated from each other.

[0022] In one implementation, each of the first dummy pixel and the second dummy pixel may include a dummy pixel circuit containing a first capacitor. The dummy pixel circuits of the first dummy pixel and the second dummy pixel may share the first capacitor.

[0023] In one implementation, the first dummy pixel may be electrically connected to one of the first repair line and the second repair line, and the second dummy pixel may be electrically connected to the remaining (other) repair line of the first repair line and the second repair line.

[0024] Embodiments of this disclosure include a method for repairing a display device, the display device comprising: a substrate defining a display area and a non-display area surrounding one side of the display area; sub-pixels disposed in the display area and including transistors, light-emitting elements electrically connected to the transistors, and contact electrodes electrically connecting the light-emitting elements and the transistors; a first repair line and a second repair line disposed between a first pixel row and a second pixel row on the substrate and spaced apart from each other; a first bridging pattern disposed between the first pixel row and the second pixel row and connected to the first repair line; a second bridging pattern disposed between the first pixel row and the second pixel row and connected to the second repair line; a first dummy pixel disposed in the non-display area corresponding to each of the first pixel row and the second pixel row and connected to one of the first repair line and the second repair line; and a second dummy pixel connected to the first repair line and the second repair line. The remaining (other) repair line in the image, the repair method includes: separating a first bad pixel circuit arranged in a first pixel column of a first pixel row from a first light-emitting element corresponding to the first bad pixel circuit; electrically connecting a contact electrode electrically connected to the anode electrode of the first light-emitting element to one of a first bridging pattern and a second bridging pattern to electrically connect the anode electrode of the first light-emitting element to a dummy pixel circuit of one of a first dummy pixel and a second dummy pixel; separating a second defective pixel circuit arranged in a third pixel column of the first pixel row from a second light-emitting element corresponding to the second defective pixel circuit; and electrically connecting a contact electrode electrically connected to the anode electrode of the second light-emitting element to a remaining (other) bridging pattern in the first bridging pattern and the second bridging pattern to electrically connect the anode electrode of the second light-emitting element to a remaining (other) dummy pixel circuit in the first dummy pixel and the second dummy pixel.

[0025] In one embodiment, the contact electrode of each of the first and second light-emitting elements can be arranged on the semiconductor pattern of the transistor, and an insulating layer is inserted between the contact electrode and the semiconductor pattern of the transistor, and can be electrically connected to the semiconductor pattern through a first contact hole passing through the insulating layer. Based on the first contact hole, a first bridging pattern can be disposed on one side of the first contact hole, and a second bridging pattern can be disposed on the opposite side of the first contact hole.

[0026] Embodiments of this disclosure include an electronic device comprising: a processor for providing input image data to a display device; and a display device for displaying an image based on the input image data. The display device includes: a substrate defining a display area comprising a first region and a second region, and a non-display area surrounding one side of the display area; sub-pixels disposed in the display area; dummy pixels disposed in the non-display area; and repair lines provided together to the display area and the non-display area, and extending in a first direction. The repair lines include: a first repair line and a second repair line disposed in the first region between a first pixel row and a second pixel row of the substrate. The dummy pixels include a first dummy pixel and a second dummy pixel respectively arranged to correspond to the first pixel row and the second pixel row. Each of the first dummy pixels and the second dummy pixels includes a dummy pixel circuit and a first capacitor electrically connected to the dummy pixel circuit. The first capacitor of each of the first dummy pixels and the second dummy pixels is disposed between the dummy pixel circuit of the first dummy pixel and the dummy pixel circuit of the second dummy pixel.

[0027] The first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel can be set as a single entity. The first dummy pixel and the second dummy pixel share the first capacitor. Attached Figure Description

[0028] The above and other features of the embodiments of this disclosure will become more apparent from the description of the embodiments of this disclosure in more detail with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic block diagram illustrating an implementation of the display device.

[0030] Figure 2 This is a schematic plan view illustrating an embodiment of the display device.

[0031] Figure 3 It is shown Figure 2 A schematic diagram illustrating the implementation of one of the sub-pixels.

[0032] Figure 4 It is shown Figure 2 A schematic diagram illustrating an implementation of one of the dummy pixels.

[0033] Figure 5 It is shown Figure 2 A schematic plan view of an implementation of one pixel of the pixels.

[0034] Figure 6 It is along Figure 5 A schematic cross-sectional view of line I-I' in the diagram.

[0035] Figure 7This is a schematic plan view illustrating an embodiment of sub-pixels arranged in the first and second rows within a portion of the first area of ​​the display area of ​​a display device.

[0036] Figure 8 It only shows those included Figure 7 A schematic plan view of the arrangement of the first to seventh transistors and the first conductive layer.

[0037] Figure 9 It only shows those included Figure 7 A schematic plan view of the configuration in the second conductive layer.

[0038] Figure 10 It only shows those included Figure 7 A schematic plan view of the configuration in the third conductive layer.

[0039] Figure 11 It only shows those included Figure 7 A schematic plan view of the configuration in the fourth conductive layer.

[0040] Figure 12 It only shows those included Figure 7 A schematic plan view of the configuration in the fifth conductive layer.

[0041] Figure 13 yes Figure 7 A schematic enlarged plan view of part of EA2.

[0042] Figure 14 It is along Figure 13 A schematic cross-sectional view of line II-II'.

[0043] Figure 15 It is the first region and Figure 7 A schematic enlarged plan view of the part corresponding to EA2.

[0044] Figure 16 It is the first region and Figure 7 A schematic enlarged plan view of the part corresponding to EA2.

[0045] Figure 17 It is along Figure 16 A schematic cross-sectional view of line III-III'.

[0046] Figure 18 This is a schematic plan view illustrating an embodiment of dummy pixels arranged in the first row and the second row in the first region of the first non-display area of ​​a display device.

[0047] Figure 19 Is only shown Figure 18A schematic plan view of the configuration of the first to sixth transistors, the eighth transistor, and the ninth transistor, and the first conductive layer.

[0048] Figure 20 It only shows those included Figure 18 A schematic plan view of the configuration in the second conductive layer.

[0049] Figure 21 It only shows those included Figure 18 A schematic plan view of the configuration in the third conductive layer.

[0050] Figure 22 It only shows those included Figure 18 A schematic plan view of the configuration in the fourth conductive layer.

[0051] Figure 23 It is only included Figure 18 A schematic plan view of the configuration in the fifth conductive layer.

[0052] Figure 24 It is used to indicate sub-pixels in a first region and dummy pixels in a first non-display region of a display device. Figure 2 A schematic diagram of a partial implementation of EA1.

[0053] Figure 25 This is a schematic flowchart illustrating an implementation of a method for repairing a display device.

[0054] Figure 26 It is used to show the repair and Figure 2 A schematic diagram of the method for dealing with bad sub-pixels corresponding to EA1.

[0055] Figure 27 yes Figure 26 A partial schematic diagram of EA3.

[0056] Figure 28 It shows the arrangement in Figure 26 A schematic circuit diagram of the electrical connection between the first sub-pixel and the second dummy pixel in the first row.

[0057] Figure 29 It is used to show the repair and Figure 2 A schematic diagram of the method for dealing with bad sub-pixels corresponding to EA1.

[0058] Figure 30 The display device in the implementation method and Figure 2 A schematic diagram of the implementation method for a region corresponding to part EA1.

[0059] Figure 31 It is used to show the repair and Figure 2 A schematic diagram of the method for dealing with bad sub-pixels corresponding to EA1.

[0060] Figure 32 This is a schematic block diagram illustrating an implementation of an electronic device.

[0061] Figure 33 It is shown that Figure 32 The electronic device is a schematic diagram illustrating an implementation of a smartphone.

[0062] Figure 34 It is shown that Figure 32 The electronic device is a schematic diagram illustrating an implementation of a tablet PC. Detailed Implementation

[0063] This disclosure will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, this disclosure may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0064] In describing the accompanying drawings, similar reference numerals are used for similar elements. In the drawings, the dimensions of structures are enlarged compared to their actual dimensions to clearly illustrate the present disclosure. It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element discussed below may be referred to as a second element. Similarly, a second element may also be referred to as a first element.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprises” and / or “comprising” or “includes” and / or “including” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0066] In the following description, when the first part is “connected” to the second part, this includes not only the case where the first part is directly connected to the second part, but also the case where the third part is inserted between them and they are connected to each other.

[0067] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying images. It will be understood that, in addition to the orientation depicted in the accompanying images, the relative terms are intended to encompass different orientations of the device. For example, if a device in one of the accompanying images is flipped, an element described as being “below” the other elements will subsequently be oriented “above” the other elements. Thus, depending on the specific orientation of the image, the term “below” can encompass both “below” and “above” orientations. Similarly, when a device in one of the accompanying images is flipped, an element described as being “below” or “under” the other elements will subsequently be oriented “above” the other elements. Thus, the term “below” or “under” can encompass both “above” and “below” orientations.

[0068] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0069] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0070] Figure 1 This is a schematic block diagram illustrating an embodiment of the display device DD.

[0071] refer to Figure 1 The display device DD may include a display panel PNL, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0072] The display panel PNL may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm (where m is a natural number greater than 0). Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn (where n is a natural number greater than 0).

[0073] Each of the sub-pixels SP can include at least one light-emitting element for generating light. Therefore, each of the sub-pixels SP can generate light of a specific color, such as red, green, blue, cyan, magenta, yellow, etc. Two or more sub-pixels SP can constitute a single pixel PXL. In an implementation, as... Figure 1 As shown, for example, three sub-pixels SP can form a single pixel PXL.

[0074] The gate driver 120 can be connected to a sub-pixel SP arranged in the row direction via a first gate line GL1 to the m-th gate line GLm. The gate driver 120 can output gate signals to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. The gate driver 120 can be arranged on one side of the display panel PNL, but is not limited thereto.

[0075] In one implementation, a first emission control line EL1 to an m-th emission control line ELm connected to the sub-pixel SP in the row direction may be further provided. The gate driver 120 may include an emission control driver that controls the first emission control line EL1 to the m-th emission control line ELm. The emission control driver may be operable under the control of the controller 150.

[0076] The data driver 130 can be connected to sub-pixels SP arranged in the column direction via the first data line DL1 to the nth data line DLn. The data driver 130 can receive image data DATA and data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS.

[0077] The data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn via a voltage from the voltage generator 140. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the first data lines DL1 to the nth data line DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel PNL.

[0078] In one implementation, gate driver 120 and data driver 130 may include complementary metal-oxide-semiconductor (“CMOS”) circuit elements.

[0079] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can generate multiple voltages and provide the generated voltages to components of display device DD. In an embodiment, for example, voltage generator 140 can receive an input voltage from outside display device DD, control the input voltage, and adjust the controlled voltage to generate multiple voltages.

[0080] Voltage generator 140 can generate a first power supply voltage ELVDD and a second power supply voltage ELVSS, and the generated first power supply voltage ELVDD and second power supply voltage ELVSS can be supplied to the sub-pixel SP. The first power supply voltage ELVDD can have a relatively high voltage level, and the second power supply voltage ELVSS can have a lower voltage level than the first power supply voltage ELVDD. In other embodiments, the first power supply voltage ELVDD or the second power supply voltage ELVSS can be supplied to the display device DD by an external device.

[0081] Furthermore, voltage generator 140 can generate various voltages. In one embodiment, for example, voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. In another embodiment, for example, a predetermined reference voltage can be applied to the first data line DL1 to the nth data line DLn during sensing operation to sense the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, and voltage generator 140 can generate the reference voltage.

[0082] The controller 150 can control various operations of the display device DD. The controller 150 can receive a control signal CTRL from an external source to control the input image data IMG and its display. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0083] The controller 150 can convert the input image data IMG into a format suitable for a display device DD or a display panel PNL to output image data DATA. In one embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to matching subpixels SP on a row-by-row basis.

[0084] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be configured (e.g., mounted) on a single integrated circuit. Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). The data driver 130, voltage generator 140, and controller 150 may be functionally distinct components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a separate component within the driver integrated circuit (DIC).

[0085] The display device DD may include at least one temperature sensor 160. The temperature sensor 160 can sense the temperature in its vicinity and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be arranged adjacent to the display panel PNL and / or the driver integrated circuit DIC.

[0086] The controller 150 can control various operations of the display device DD in response to the temperature data TEP. In one embodiment, the controller 150 can adjust the brightness of the image output from the display panel PNL in response to the temperature data TEP.

[0087] Figure 2 This is a schematic plan view illustrating an embodiment of the display device DD. For convenience, Figure 2 The structure of the display area DA of the display device DD is schematically shown, for example, the structure of the display panel PNL provided in the display device DD.

[0088] refer to Figure 2 The display device DD (or display panel PNL) may include a substrate SUB and sub-pixels SP.

[0089] The display device DD can have various shapes, such as, but not limited to, quadrilaterals, such as a rectangular plate with two pairs of parallel sides. The implementation is applicable when the display device DD is an electronic device such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop personal computer (“PC”), laptop PC, network book computer, workstation, server, personal digital assistant (“PDA”), portable multimedia player (“PMP”), Moving Picture Experts Group Audio Layer III (“MP3”) player, medical device, camera, or wearable device having a display surface on at least one side.

[0090] The substrate SUB may include a transparent insulating material that allows light to pass through it. The substrate SUB may be a rigid substrate or a flexible substrate.

[0091] The rigid substrate can be, for example, a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate.

[0092] The flexible substrate can be a film substrate or a plastic substrate comprising a polymeric organic material. In embodiments, for example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0093] Subpixels SP can be arranged on the substrate SUB in the display area DA. The subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of the subpixels SP is not limited to this. In one embodiment, for example, the subpixels SP can be arranged in a sawtooth pattern along the first direction DR1 and the second direction DR2. In another embodiment, for example, the subpixels SP can be arranged in a pentiline pattern. ® Arrangement structure. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0094] Two or more sub-pixels SP can form a single pixel PXL.

[0095] One area of ​​the substrate SUB can be provided as a display area DA on which sub-pixels SP are placed, and the remaining area of ​​the substrate SUB can be provided as a non-display area NDA.

[0096] On the substrate SUB, in the non-display area NDA, components for controlling the sub-pixel SP can be arranged. In an implementation, for example, wiring associated with the sub-pixel SP (such as...) Figure 1The first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn shown can be arranged in the non-display area NDA.

[0097] In an implementation, the display area DA may include a first area DA1 (or a first display area) and a second area DA2 (or a second display area) adjacent to each other in the first direction DR1. The display area DA can be divided into a first area DA1 and a second area DA2 by bisecting the display area DA around an imaginary line located at its center. When viewed in a plane, the first area DA1 may be located on the upper left, and the second area DA2 may be located on the upper right.

[0098] The non-display area NDA may include a first non-display area NDA1 surrounding at least one side of the first area DA1 and a second non-display area NDA2 surrounding at least one side of the second area DA2.

[0099] In each of the first non-display area NDA1 and the second non-display area NDA2, two dummy pixels DP corresponding to each pixel row can be arranged. In an embodiment, for example, the non-display area NDA may have two dummy pixels DP corresponding to each pixel row. The dummy pixels DP may include a first dummy pixel DP1 and a second dummy pixel DP2 arranged in the first non-display area NDA1, and a third dummy pixel DP3 and a fourth dummy pixel DP4 arranged in the second non-display area NDA2.

[0100] The first dummy pixel DP1 and the second dummy pixel DP2 can be arranged adjacent to each other in the first non-display area NDA1 along the first direction DR1. The third dummy pixel DP3 and the fourth dummy pixel DP4 can be arranged adjacent to each other in the second non-display area NDA2 along the first direction DR1. The second dummy pixel DP2 can be arranged closer to the first region DA1 than the first dummy pixel DP1, and the third dummy pixel DP3 can be arranged closer to the second region DA2 than the fourth dummy pixel DP4, but this disclosure is not limited thereto. According to an embodiment, the first dummy pixel DP1 can be arranged closer to the first region DA1 than the second dummy pixel DP2, and the fourth dummy pixel DP4 can be arranged closer to the second region DA2 than the third dummy pixel DP3.

[0101] The pad PD can be arranged on the substrate SUB in the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via wiring. In an embodiment, for example, the pad PD can be arranged as described above. Figure 1 The first data line DL1 to the nth data line DLn are connected to the sub-pixel SP.

[0102] The pads (PD) can connect the display panel (PNL) to other components of the display device (DD). In this implementation, the pads (PD) can connect from... Figure 1 The driver integrated circuit (DIC) provides the voltages and signals required to operate the components included in the display panel PNL.

[0103] In this embodiment, the display device DD may include a repair line RPL that is shared across the display area DA and the non-display area NDA. The repair line RPL may include a first repair line RPL1, a second repair line RPL2, a third repair line RPL3, and a fourth repair line RPL4. The first repair line RPL1 and the second repair line RPL2 may be shared across the first area DA1 and the first non-display area NDA1. The third repair line RPL3 and the fourth repair line RPL4 may be shared across the second area DA2 and the second non-display area NDA2.

[0104] In the first region DA1, the first repair line RPL1 and the second repair line RPL2 can be arranged between two sub-pixels SP that face each other on the second direction DR2. In the first non-display region NDA1, the first repair line RPL1 and the second repair line RPL2 can be arranged between two first dummy pixels DP1 and two second dummy pixels DP2 that face each other on the second direction DR2, respectively.

[0105] In the second region DA2, the third repair line RPL3 and the fourth repair line RPL4 can be arranged between two sub-pixels SP that face each other on the second direction DR2. In the second non-display region NDA2, the third repair line RPL3 and the fourth repair line RPL4 can be arranged between two third dummy pixels DP3 and two fourth dummy pixels DP4 that face each other on the second direction DR2, respectively.

[0106] Figure 3 It is shown as Figure 2 A schematic diagram illustrating the implementation of a sub-pixel SPij in the sub-pixels. Here, i is a natural number equal to or less than m and greater than 0, and j is a natural number equal to or less than n and greater than 0. For ease of description, Figure 3 The sub-pixel SPij is shown as being located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj.

[0107] refer to Figure 2 and Figure 3 Sub-pixels SPij can be arranged on the i-th horizontal line.

[0108] Sub-pixel SPij may include a light-emitting element LED and a pixel circuit PXC. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a storage capacitor Cst.

[0109] A first transistor T1 may be electrically connected between a first power line PL1 and the anode electrode AE ​​of a light-emitting element (LED). The first transistor T1 may include a gate electrode electrically connected to a first node N1. The first transistor T1 may control the amount of current (or drive current) flowing from the first power line PL1 through the LED to the third power line PL3 based on the voltage at the first node N1. The first power line PL1 is supplied with a first power supply voltage ELVDD, and the third power line PL3 is supplied with a second power supply voltage ELVSS, wherein the first power supply voltage ELVDD may be set to a voltage higher than the second power supply voltage ELVSS.

[0110] The second transistor T2 can be electrically connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 can be connected to the 1i-th scan line S1i (or the first scan line). When the first scan signal GW[i] (e.g., a low-level first scan signal) is provided to the 1i-th scan line S1i, the second transistor T2 can be turned on to electrically connect the j-th data line Dj and the second node N2. When each of the first transistor T1 and the third transistor T3 is in the on state, the second transistor T2 can transmit the data signal of the j-th data line Dj to the second node N2 in response to the first scan signal GW[i].

[0111] The third transistor T3 can be electrically connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 can be electrically connected to the first scan line S1i. When the first scan signal GW[i] is provided to the first scan line S1i, the third transistor T3 can be turned on. When the third transistor T3 is turned on, the first transistor T1 can be a diode connected.

[0112] A fourth transistor T4 can be electrically connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 can be electrically connected to the 2i scan line S2i (the second scan line). The second power line PL2 can be supplied with a first initialization power supply voltage Vint1. The fourth transistor T4 can be turned on by a second scan signal GI[i] supplied to the 2i scan line S2i. When the fourth transistor T4 is turned on, the first initialization power supply voltage Vint1 can be supplied to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0113] The fifth transistor T5 can be electrically connected between the first power line PL1 and the second node N2. The gate electrode of the fifth transistor T5 can be electrically connected to the i-th emitter control line Ei. The sixth transistor T6 can be electrically connected between the third node N3 and the light-emitting element LED (or the fourth node N4). The gate electrode of the sixth transistor T6 can be electrically connected to the i-th emitter control line Ei. When the emitter control signal EM[i] (e.g., a high-level emitter control signal EM[i]) is provided to the i-th emitter control line Ei, the fifth transistor T5 and the sixth transistor T6 can be turned off; otherwise, they can be turned on.

[0114] The seventh transistor T7 can be electrically connected between the anode electrode AE ​​(i.e., the fourth node N4) of the light-emitting element LED and the fourth power line PL4. The gate electrode of the seventh transistor T7 can be electrically connected to the 3i scan line S3i. The fourth power line PL4 can be supplied with a second initialization power supply voltage Vint2. The seventh transistor T7 can be turned on by a third scan signal GB[i] provided to the 3i scan line S3i to provide the second initialization power supply voltage Vint2 to the anode electrode AE ​​of the light-emitting element LED. The second initialization power supply voltage Vint2 can be the same as, but is not limited to, the first initialization power supply voltage Vint1.

[0115] The storage capacitor Cst can be connected or formed between the first power line PL1 and the first node N1.

[0116] The light-emitting element (LED) may include an anode electrode AE ​​and a cathode electrode CE. The anode electrode AE ​​may be connected to a fourth node N4, and the cathode electrode CE may be connected to a third power line PL3. The cathode electrode CE of the LED may be supplied with a second power supply voltage ELVSS. The LED may receive a drive current from a first transistor T1 and emit light.

[0117] In one embodiment, the pixel circuit PXC may include a P-type transistor. In another embodiment, for example, the first transistor T1 through the seventh transistor T7 may include polysilicon transistors comprising silicon semiconductors, and may include a polysilicon semiconductor layer as an active layer. In yet another embodiment, the active layer may be formed using a low-temperature polysilicon process (e.g., a low-temperature polysilicon (“LTPS”) process).

[0118] Figure 4 It is shown as Figure 2 A schematic diagram illustrating an implementation of a dummy pixel DPi1, one of the dummy pixels. For ease of description, Figure 4 It is shown in the first non-display area (reference) Figure 2 The dummy pixel DPi1 is set on the i-th horizontal line (or the i-th pixel row) and connected to the first dummy data line DD1 in “NDA1”.

[0119] refer to Figure 4 For ease of description, overlapping descriptions with the above embodiments will be omitted.

[0120] refer to Figure 2 and Figure 4 The dummy pixel DPi1 can be arranged on the i-th horizontal line.

[0121] The dummy pixel DPi1 may include a dummy pixel circuit DPC and a repair modulation circuit RM. The dummy pixel circuit DPC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a storage capacitor Cst. In other words, except for the seventh transistor T7, the dummy pixel circuit DPC may be connected to a reference... Figure 3 The pixel circuitry PXC described includes essentially the same configuration.

[0122] The repair modulation circuit RM may include an eighth transistor T8, a ninth transistor T9, and a first capacitor C1. The repair modulation circuit RM is connected to the repair line RPL, the i-th transmit control line Ei, and the 3i-th scan line S3i.

[0123] The eighth transistor T8 can be electrically connected between the fourth node N4 and the connection node P1. The gate electrode of the eighth transistor T8 can be electrically connected to the i-th emission control line Ei. The first input / output terminal of the eighth transistor T8 can be electrically connected to the fourth node N4 (or the node electrically connected to the repair line RPL and the light-emitting element of the defective sub-pixel), and the second input / output terminal of the eighth transistor T8 can be electrically connected to the first capacitor C1 and the connection node P1 of the ninth transistor T9.

[0124] The ninth transistor T9 can be electrically connected between the eighth transistor T8 and the second power line PL2. The gate electrode of the ninth transistor T9 can be electrically connected to the 3i scan line S3i. The first input / output terminal of the ninth transistor T9 can be electrically connected to the connection node P1, and the second input / output terminal of the ninth transistor T9 can be electrically connected to the second power line PL2.

[0125] One terminal of the first capacitor C1 is connected to the connection node P1 (or between the second input / output terminal of the eighth transistor T8 and the first input / output terminal of the ninth transistor T9), and the remaining (other) terminal of the first capacitor C1 can be electrically connected to the first power line PL1.

[0126] In the dummy pixel DPi1, the fourth node N4 can be electrically connected to the repair line RPL. When the sub-pixel SP of the display area DA fails, the wiring between the anode electrode of the light-emitting element of the defective sub-pixel and the sixth transistor T6 can be disconnected, and the anode electrode and the repair line RPL can be connected, allowing the light-emitting element of the defective sub-pixel to emit light normally. A detailed description of the repair method for the defective sub-pixel will be described below.

[0127] Figure 5 It is shown Figure 2 A schematic plan view of an implementation of one of the pixels, PXL.

[0128] refer to Figure 2 and Figure 5 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged on the first direction DR1.

[0129] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA surrounding the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA surrounding the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA surrounding the third emission region EMA3.

[0130] The first emission region EMA1 can be a light-emitting element corresponding to the first sub-pixel SP1 (see reference). Figure 3 The second emission region EMA2 can be the region that emits light from the light-emitting element LED corresponding to the second sub-pixel SP2. The third emission region EMA3 can be the region that emits light from the light-emitting element LED corresponding to the third sub-pixel SP3.

[0131] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have substantially the same area, but are not limited thereto. In some embodiments, the second sub-pixel SP2 may have a larger area than the first sub-pixel SP1, and the third sub-pixel SP3 may have a larger area than the second sub-pixel SP2.

[0132] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have polygonal shapes. In an implementation, for example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have square or hexagonal shapes, but are not limited thereto.

[0133] Figure 6 It is along Figure 5 A schematic cross-sectional view of line I-I' in the diagram.

[0134] exist Figure 6 In this diagram, for ease of description, the cross-sectional structure or stacked structure of the display device DD is briefly shown, mainly based on the pixel PXL included in the display device DD, and the thickness direction of the substrate SUB is shown as the third direction DR3.

[0135] refer to Figure 5 and Figure 6 The display device DD may include one or more pixels PXL arranged in the display area DA.

[0136] Pixel PXL may include one or more subpixels SP. In an embodiment, for example, pixel PXL may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. In an embodiment, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 may be a green subpixel, and the third subpixel SP3 may be a blue subpixel, but this disclosure is not limited thereto. Hereinafter, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 are collectively referred to as subpixels SP and / or (multiple) subpixels SP.

[0137] Each of the first sub-pixel SP1 to the third sub-pixel SP3 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a thin film encapsulation layer TFE, and a window WD.

[0138] The substrate SUB may include a transparent insulating material that allows light to pass through it. The substrate SUB may be a rigid substrate or a flexible substrate.

[0139] The pixel circuit layer (PCL) of the sub-pixel SP can be disposed on the substrate SUB. One or more insulating layers can be disposed in the pixel circuit layer PCL. The insulating layers may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, a fifth insulating layer INS5, a sixth insulating layer INS6, and a seventh insulating layer INS7, which are sequentially stacked on the substrate SUB on the third-direction DR3. The insulating layers disposed in the pixel circuit layer PCL are not limited to the above embodiments, and other insulating layers may be added or some insulating layers may be omitted.

[0140] The first insulating layer INS1 can be disposed on the substrate SUB. The first insulating layer INS1 can prevent impurities from diffusing into the pixel circuitry (reference). Figure 3 The first insulating layer INS1 is an inorganic layer comprising an inorganic material (or substance). The first insulating layer INS1 may include silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon nitride oxide (SiO)x N y ) and aluminum oxide (AlO) x At least one of the following. The first insulating layer INS1 can be a single layer, but it can also be a multilayer with at least two or more layers. Depending on the material and process conditions of the substrate SUB, the first insulating layer INS1 can be omitted.

[0141] A second insulating layer INS2 may be disposed on a first insulating layer INS1. The second insulating layer INS2 may comprise the same material as the first insulating layer INS1, or may comprise a suitable (or selected) material from the components exemplified by the first insulating layer INS1. In embodiments, for example, the second insulating layer INS2 may be an inorganic layer comprising inorganic materials.

[0142] The third insulating layer INS3 may be disposed on the second insulating layer INS2. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials from the composition of the first insulating layer INS1.

[0143] The fourth insulating layer INS4 can be disposed on the third insulating layer INS3. The fourth insulating layer INS4 can be an inorganic layer including inorganic materials or an organic layer including organic materials.

[0144] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4. The fifth insulating layer INS5 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials from the composition of the first insulating layer INS1.

[0145] The sixth insulating layer INS6 (or the first via layer) can be disposed on the fifth insulating layer INS5. The sixth insulating layer INS6 can be an inorganic layer comprising inorganic materials or an organic layer comprising organic materials. The inorganic layer can include, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon nitride oxide (SiO) x N y ) and aluminum oxide (AlO) x At least one of the following: . The organic layer may be, for example, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. In an embodiment, the sixth insulating layer INS6 may be an organic layer comprising organic materials.

[0146] A seventh insulating layer INS7 (or a second via layer) may be disposed on the sixth insulating layer INS6. The seventh insulating layer INS7 may comprise the same material as the sixth insulating layer INS6, or may comprise one or more suitable (or selected) materials from the composition exemplified by the sixth insulating layer INS6. In embodiments, for example, the seventh insulating layer INS7 may be an organic layer comprising an organic material.

[0147] The pixel circuit layer (PCL) may include one or more conductive layers disposed between the aforementioned insulating layers. In an embodiment, for example, the conductive layers may include a first conductive layer disposed between the second insulating layer INS2 and the third insulating layer INS3, a second conductive layer disposed between the third insulating layer INS3 and the fourth insulating layer INS4, a third conductive layer disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5, a fourth conductive layer disposed between the fifth insulating layer INS5 and the sixth insulating layer INS6, and a fifth conductive layer disposed between the sixth insulating layer INS6 and the seventh insulating layer INS7. However, the insulating and conductive layers are not limited to the above embodiments, and in embodiments, other insulating and conductive layers besides the aforementioned insulating and conductive layers may be disposed in the pixel circuit layer (PCL).

[0148] The pixel circuit layer (PCL) may include circuit elements (or driving elements) for each of the first sub-pixels SP1 to the third sub-pixels SP3. In an embodiment, for example, the PCL may include a transistor T_SP1 for the first sub-pixel SP1, a transistor T_SP2 for the second sub-pixel SP2, and a transistor T_SP3 for the third sub-pixel SP3. The transistor T_SP1 for the first sub-pixel SP1 is one of the transistors included in the pixel circuit PXC of the first sub-pixel SP1. The transistor T_SP2 for the second sub-pixel SP2 is one of the transistors included in the pixel circuit PXC of the second sub-pixel SP2. The transistor T_SP3 for the third sub-pixel SP3 is one of the transistors included in the pixel circuit PXC of the third sub-pixel SP3. Figure 6 For clarity and simplicity, only one transistor of each sub-pixel SP is shown, and the remaining (other) circuit elements are omitted.

[0149] The transistor T_SP1 of the first sub-pixel SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal EL1, and a second terminal EL2.

[0150] The gate electrode GE can be disposed on the second insulating layer INS2 and covered by the third insulating layer INS3. In an embodiment, for example, the gate electrode GE can be a first conductive layer (or a first gate conductive layer) disposed between the second insulating layer INS2 and the third insulating layer INS3. The gate electrode GE can overlap with a portion of the semiconductor pattern SCP. In an embodiment, for example, the gate electrode GE can overlap with the active pattern of the semiconductor pattern SCP.

[0151] The pixel circuit layer PCL may include a first pattern PT1 disposed between a third insulating layer INS3 and a fourth insulating layer INS4. The first pattern PT1 may be formed of a second conductive layer (or a second gate conductive layer). In an embodiment, the first pattern PT1 may overlap with the gate electrode GE, and the third insulating layer INS3 may be interposed therebetween to form a capacitor. Furthermore, the pixel circuit layer PCL may include a second pattern PT2 disposed between a fourth insulating layer INS4 and a fifth insulating layer INS5. The second pattern PT2 may be formed of a third conductive layer (or a third gate conductive layer). In an embodiment, the second pattern PT2 may be used as a signal line, connection means, etc., electrically connected to a transistor.

[0152] A semiconductor pattern SCP can be disposed on a first insulating layer INS1 and covered by a second insulating layer INS2. The semiconductor pattern SCP can be a semiconductor layer including polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The semiconductor pattern SCP can include an active pattern, a first contact region, and a second contact region. The active pattern, the first contact region, and the second contact region can include undoped or impurity-doped semiconductor layers. In an embodiment, for example, the first and second contact regions can include impurity-doped semiconductor layers, and the active pattern can be a region doped at a lower concentration than the first and second contact regions. Therefore, the conductivity of the first and second contact regions can be greater than the conductivity of the active pattern. The first and second contact regions can be the source / drain regions (or source / drain electrodes) of the transistor T_SP1 of the first sub-pixel SP1.

[0153] The active pattern of the semiconductor pattern SCP can be the channel region of the transistor T_SP1 of the first sub-pixel SP1 that overlaps with the gate electrode GE. The first contact area of ​​the semiconductor pattern SCP can contact one end of the active pattern. The first contact area can be electrically connected to the first terminal EL1. The second contact area of ​​the semiconductor pattern SCP can contact the opposite end of the active pattern. The second contact area can be electrically connected to the second terminal EL2.

[0154] The first terminal EL1 may be disposed on and / or formed on the fifth insulating layer INS5. In an embodiment, for example, the first terminal EL1 may be formed by a fourth conductive layer (or a first source-drain conductive layer) formed between the fifth insulating layer INS5 and the sixth insulating layer INS6. The first terminal EL1 may contact the first contact area of ​​the semiconductor pattern SCP through a contact hole passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0155] The second terminal EL2 may be disposed on and / or formed on the fifth insulating layer INS5. The second terminal EL2 may be formed by a fourth conductive layer formed between the fifth insulating layer INS5 and the sixth insulating layer INS6. The second terminal EL2 may contact the second contact area of ​​the semiconductor pattern SCP through contact holes passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0156] The second terminal EL2 can be electrically connected to the connection line CNL disposed on the sixth insulating layer INS6. The connection line CNL can be the fifth conductive layer (or the second source-drain conductive layer) disposed between the sixth insulating layer INS6 and the seventh insulating layer INS7.

[0157] In this embodiment, the bottom metal pattern BML can be disposed on the underside of the transistor T_SP1 of the first sub-pixel SP1 as described above. The bottom metal pattern BML can be a dummy conductive layer disposed between the substrate SUB and the first insulating layer INS1.

[0158] When the gate electrode GE, the first terminal EL1, and the second terminal EL2 are electrically connected to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be configured as one of the transistors in the pixel circuit PXC that constitutes the first sub-pixel SP1.

[0159] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be configured to be substantially the same as the transistor T_SP1 of the first sub-pixel SP1.

[0160] As described above, the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0161] The display element layer (DPL) can be arranged on the pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements (see reference). Figure 3The light-emitting element (LED) includes an anode electrode, a light-emitting layer, and a cathode electrode (CE). The LED can be disposed in each of the first sub-pixels SP1 to SP3. The LED disposed in the first sub-pixel SP1 can be the first light-emitting element LED1, the LED disposed in the second sub-pixel SP2 can be the second light-emitting element LED2, and the LED disposed in the third sub-pixel SP3 can be the third light-emitting element LED3.

[0162] The first anode electrode AE1 can be disposed on the pixel circuit layer PCL (or the seventh insulating layer INS7) of the first sub-pixel SP1, the second anode electrode AE2 can be disposed on the pixel circuit layer PCL of the second sub-pixel SP2, and the third anode electrode AE3 can be disposed on the pixel circuit layer PCL of the third sub-pixel SP3. Each of the first anode electrodes AE1 to the third anode electrode AE3 can be electrically connected to a circuit element disposed on the pixel circuit layer PCL through a via penetrating the seventh insulating layer INS7. In an embodiment, for example, the first anode electrode AE1 is electrically connected to the transistor T_SP1 of the first sub-pixel SP1 through a first via VIH1 penetrating the seventh insulating layer INS7, the second anode electrode AE2 is electrically connected to the transistor T_SP2 of the second sub-pixel SP2 through a second via VIH2 penetrating the seventh insulating layer INS7, and the third anode electrode AE3 is electrically connected to the transistor T_SP3 of the third sub-pixel SP3 through a third via VIH3 penetrating the seventh insulating layer INS7.

[0163] When viewed from a third party towards DR3, each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may have the same... Figure 5 The first emitting region EMA1, the second emitting region EMA2, and the third emitting region EMA3 each have similar shapes. In an embodiment, for example, when viewed from a third party to DR3, the first anode electrode AE1 may have a shape similar to that of the first emitting region EMA1, the second anode electrode AE2 may have a shape similar to that of the second emitting region EMA2, and the third anode electrode AE3 may have a shape similar to that of the third emitting region EMA3. However, this disclosure is not limited thereto.

[0164] Each of the first anode electrodes AE1 to the third anode electrodes AE3 can be electrically connected to the corresponding pixel circuit PXC and receive a drive current. Each of the first anode electrodes AE1 to the third anode electrodes AE3 can be, but is not limited to, an opaque conductive material capable of reflecting light. By way of implementation, the first anode electrodes AE1 to the third anode electrodes AE3 can include a transparent conductive material.

[0165] A pixel defining layer (PDL) may be disposed on the first anode electrode AE1 to the third anode electrode AE3. The PDL may define an opening OP that exposes a portion of the first anode electrode AE1, a portion of the second anode electrode AE2, and a portion of the third anode electrode AE3. The PDL may be a structure that defines (or separates) the light-emitting region of each of the first sub-pixels SP1 to the third sub-pixels SP3. In an embodiment, for example, the PDL may define a first emission region EMA1 of the first sub-pixel SP1, a second emission region EMA2 of the second sub-pixel SP2, and a third emission region EMA3 of the third sub-pixel SP3.

[0166] The pixel defining layer (PDL) may include an organic insulating layer comprising organic materials. Organic materials (or organic substances) may include, for example, acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, etc. In embodiments, the pixel defining layer (PDL) may include a light-absorbing material or light absorber that can be applied thereto, such that the pixel defining layer (PDL) can absorb light from an external source. In embodiments, for example, the pixel defining layer (PDL) may include a carbon-based black pigment. However, this disclosure is not limited thereto.

[0167] A first light-emitting layer EML1 may be disposed on a first anode electrode AE1 exposed by an opening OP in the pixel-defining layer PDL, a second light-emitting layer EML2 may be disposed on a second anode electrode AE2 exposed by another opening OP in the pixel-defining layer PDL, and a third light-emitting layer EML3 may be disposed on a third anode electrode AE3 exposed by another opening OP in the pixel-defining layer PDL. Each of the first light-emitting layers EML1 to the third light-emitting layers EML3 may have a multilayer structure including a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer.

[0168] The first emissive layers EML1 to the third emissive layers EML3 may include at least one of luminescent materials that emit light of different colors according to the corresponding sub-pixels SP. In an embodiment, for example, the first emissive layer EML1 may include at least one of red luminescent materials, the second emissive layer EML2 may include at least one of green luminescent materials, and the third emissive layer EML3 may include at least one of blue luminescent materials. In an embodiment, each of the first emissive layers EML1 to the third emissive layers EML3 may emit white light overall by stacking multiple luminescent materials capable of generating light of different colors (such as red, green, blue, etc.). Color filters may be further arranged on each of the first emissive layers EML1 to the third emissive layers EML3. The color filters may include at least one of a red color filter, a green color filter, and a blue color filter.

[0169] The cathode electrode CE can be disposed on the first light-emitting layers EML1 to the third light-emitting layers EML3 and the pixel defining layer PDL. The cathode electrode CE can be a common layer provided together to the first sub-pixels SP1 to the third sub-pixels SP3. The cathode electrode CE can be provided integrally across the display area DA in the form of a plate. In an embodiment, the cathode electrode CE can be used as a semi-reflective mirror that partially transmits and partially reflects light emitted from the respective light-emitting layers.

[0170] The cathode electrode CE can be a thin metal layer with a thickness sufficient to transmit light emitted from the corresponding light-emitting layer. The cathode electrode CE can comprise a metallic material with a relatively small thickness or a transparent conductive material. In one embodiment, the cathode electrode CE can comprise at least one of various transparent conductive materials comprising indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide. In other embodiments, the cathode electrode CE can comprise at least one of magnesium, silver, and any combination thereof. However, the material of the cathode electrode CE is not limited to the embodiments described above.

[0171] The portion of the first anode electrode AE1, the first light-emitting layer EML1, and the cathode electrode CE overlapping with the first anode electrode AE1 can constitute the first light-emitting element LED1. The portion of the second anode electrode AE2, the second light-emitting layer EML2, and the cathode electrode CE overlapping with the second anode electrode AE2 can constitute the second light-emitting element LED2. The portion of the third anode electrode AE3, the third light-emitting layer EML3, and the cathode electrode CE overlapping with the third anode electrode AE3 can constitute the third light-emitting element LED3.

[0172] A thin-film encapsulation layer (TFE) can be disposed on the cathode electrode (CE). The TFE can cover the display element layer (DPL). The TFE prevents oxygen and / or moisture from penetrating into the DPL. In embodiments, the TFE can comprise a structure in which one or more inorganic layers are alternately stacked with one or more organic layers. In embodiments, for example, the inorganic layers can comprise silicon nitride, silicon oxide, or silicon nitride. In embodiments, for example, the organic layers can comprise organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene sulfide resin, or benzocyclobutene. However, the materials of the organic and inorganic layers of the TFE are not limited thereto.

[0173] The touch sensor layer TS can be disposed on the thin-film encapsulation layer TFE. Alternatively, the touch sensor layer TS can be disposed directly on the thin-film encapsulation layer TFE.

[0174] A touch sensor layer TS can be disposed on the surface of the display device DD on which an image is projected, and can receive touch input from the user. The touch sensor layer TS can recognize touch events on the display device DD through the user's hand, a separate input unit, etc. In an embodiment, for example, the touch sensor layer TS can recognize touch events capacitively.

[0175] The window WD can be disposed on the touch sensor layer TS. The window WD can be a protective member disposed on top of the touch sensor layer TS to protect the display device DD. The window WD can be glass or plastic. When the window WD includes glass, ultra-thin glass (“UTG”) with a thickness of 0.1 mm or less can be used to obtain flexibility. However, this disclosure is not limited thereto.

[0176] In one embodiment, the display device DD may further include a polarizing layer POL disposed between the touch sensor layer TS and the window WD. The polarizing layer POL can be used to reduce external light reflection. The polarizing layer POL can be attached to the window WD using an optically transparent adhesive component or the like.

[0177] Figure 7 This is a schematic plan view showing an embodiment of sub-pixels arranged in the first row R1 and the second row R2 in a portion of the first region DA1 of the display area of ​​a display device. Figure 8 It only shows those included Figure 7 A schematic plan view of the first transistor T1 to the seventh transistor T7 and their arrangement in the first conductive layer. Figure 9 It is only included Figure 7 A schematic plan view of the configuration in the second conductive layer. Figure 10 It is only included Figure 7A schematic plan view of the configuration in the third conductive layer. Figure 11 It is only included Figure 7 A schematic plan view of the configuration in the fourth conductive layer. Figure 12 It is only included Figure 7 A schematic plan view of the configuration in the fifth conductive layer. Figure 13 yes Figure 7 A schematic enlarged plan view of part of EA2. Figure 14 It is along Figure 13 A schematic cross-sectional view of line II-II'. Figure 15 It is the first region and Figure 7 A schematic enlarged plan view of the part corresponding to EA2.

[0178] exist Figure 13 and Figure 15 For ease of explanation, the configuration included in the fifth conductive layer has been omitted.

[0179] The following is for reference. Figures 7 to 15 The differences from the above-described implementation are described in order to avoid redundancy.

[0180] refer to Figure 2 as well as Figures 7 to 15 Subpixel (reference) Figure 2 The “SP” in the first region DA1 can be arranged in the same column on the second direction DR2 in each of the first row R1 (or the first pixel row) and the second row R2 (or the second pixel row). In an implementation, for example, the 11th sub-pixel SP11 (or the first sub-pixel) can be arranged in the first row R1, and the 21st sub-pixel SP21 (or the first sub-pixel) can be arranged in the second row R2. The 11th sub-pixel SP11 may include the 11th pixel circuit PXC11, and the 21st sub-pixel SP21 may include the 21st pixel circuit PXC21.

[0181] In one embodiment, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 are arranged on the second direction DR2 and may face each other relative to the repair line RPL. In another embodiment, for example, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 may be symmetrical and substantially identical with respect to the repair line RPL. Alternatively, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 may be mirror symmetrical with respect to the repair line RPL.

[0182] The signal lines can be arranged in a first region DA1, which has an 11th sub-pixel SP11 and a 21st sub-pixel SP21. In an embodiment, for example, the first wiring line WL1 to the thirteenth wiring line WL13 can be arranged in the first region DA1.

[0183] The first wiring line WL1 may extend in the first direction DR1 and may be formed by a first conductive layer disposed between the second insulating layer INS2 and the third insulating layer INS3. The first wiring line WL1 may be as described above. Figure 3 The second scan line S2i is described. A region of the first wiring line WL1 may be the gate electrode (hereinafter also referred to as the "fourth gate electrode") of the fourth transistor T4 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0184] The second wiring line WL2 may extend along the first direction DR1 and be spaced apart from the first wiring line WL1. The second wiring line WL2 may be formed of the first conductive layer. The second wiring line WL2 may be as described above. Figure 3 The described first scan line S1i. One region of the second wiring line WL2 may be the gate electrode (hereinafter also referred to as the "second gate electrode") of the second transistor T2 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21. Furthermore, another region of the second wiring line WL2 may be the gate electrode (hereinafter also referred to as the "third gate electrode") of the third transistor T3 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0185] The third wiring line WL3 may extend in the first direction DR1 and be spaced apart from the first wiring line WL1 and the second wiring line WL2. The third wiring line WL3 may be formed of the first conductive layer. The third wiring line WL3 may be as shown in the reference. Figure 3 The i-th emission control line Ei is described. The region of the third wiring line WL3 can be the gate electrode (hereinafter also referred to as the "fifth gate electrode") of the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21. Furthermore, another region of the third wiring line WL3 can be the gate electrode (hereinafter also referred to as the "sixth gate electrode") of the sixth transistor T6 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0186] The fourth wiring line WL4 may extend along the first direction DR1 and be spaced apart from the first wiring lines WL1 to the third wiring lines WL3. The fourth wiring line WL4 may be formed of the first conductive layer. The fourth wiring line WL4 may be as shown in the reference. Figure 3 The 3i scan line S3i is described. A region of the fourth wiring line WL4 may be the gate electrode (hereinafter also referred to as the "seventh gate electrode") of the seventh transistor T7 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0187] The fifth wiring line WL5 extends in the first direction DR1 and can be formed by a second conductive layer disposed between the third insulating layer INS3 and the fourth insulating layer INS4. The fifth wiring line WL5 can be a reference. Figure 3 The fourth power line described is PL4.

[0188] The sixth wiring line WL6 extends in the first direction DR1 and can be formed by a third conductive layer disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5. The sixth wiring line WL6 can be as shown in the reference. Figure 3 The second power line PL2 is described.

[0189] The seventh wiring line WL7 extends in the first direction DR1 and may be formed by a fourth conductive layer disposed between the fifth insulating layer INS5 and the sixth insulating layer INS6. The seventh wiring line WL7 may be, but is not limited to, a dummy line overlapping the first wiring line WL1 formed by the first conductive layer. In an embodiment, the seventh wiring line WL7 may be electrically connected to the first wiring line WL1 to realize the first wiring line WL1 as a dual structure.

[0190] The eighth wiring line WL8 may extend in the first direction DR1 and be spaced apart from the seventh wiring line WL7. The eighth wiring line WL8 may be formed by a fourth conductive layer. The eighth wiring line WL8 may be a dummy line. In an embodiment, the eighth wiring line WL8 may be electrically connected to the second wiring line WL2 formed by the first conductive layer, thereby realizing the second wiring line WL2 as a dual structure.

[0191] The ninth wiring line WL9 may extend in the first direction DR1 and be spaced apart from the seventh wiring line WL7 and the eighth wiring line WL8. The ninth wiring line WL9 may be formed of a fourth conductive layer. The ninth wiring line WL9 may be as shown in the reference. Figure 3 The first electric line PL1 is described.

[0192] The tenth wiring line WL10 may extend in the first direction DR1 and be spaced apart from the seventh wiring lines WL7 to the ninth wiring lines WL9. The tenth wiring line WL10 may be formed of a fourth conductive layer. The tenth wiring line WL10 may be a dummy line overlapping with the third wiring line WL3 formed of a first conductive layer. In an embodiment, the tenth wiring line WL10 may be electrically connected to the third wiring line WL3 to realize the third wiring line WL3 as a dual structure.

[0193] The eleventh wiring line WL11 may extend in the first direction DR1 and be spaced apart from the seventh wiring lines WL7 to the tenth wiring lines WL10. The eleventh wiring line WL11 may be formed of a fourth conductive layer. The eleventh wiring line WL11 may be a dummy line overlapping with the fourth wiring line WL4 formed of a first conductive layer. In an embodiment, the eleventh wiring line WL11 may be electrically connected to the fourth wiring line WL4 through a corresponding contact hole CH to realize the fourth wiring line WL4 as a dual structure.

[0194] The twelfth wiring line WL12 may extend in the second direction DR2, which intersects the first direction DR1, and may be formed by a fifth conductive layer disposed between the sixth insulating layer INS6 and the seventh insulating layer INS7. The twelfth wiring line WL12 may be as shown in the reference. Figure 3 The j-th data line Dj is described. The twelfth wiring line WL12 can be electrically connected via the first conductive pattern CP1 to the second transistor T2 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0195] The first conductive pattern CP1 can be formed from the fourth conductive layer. The first conductive pattern CP1 can be electrically connected to the twelfth wiring line WL12 through the contact hole CH passing through the sixth insulating layer INS6. In addition, the first conductive pattern CP1 can be electrically connected to the semiconductor pattern SCP of the second transistor T2 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 through the contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0196] The thirteenth wiring line WL13 may extend in the second direction DR2 and may be spaced apart from the twelfth wiring line WL12. The thirteenth wiring line WL13 may be formed by a fifth conductive layer. The thirteenth wiring line WL13 may be electrically connected to the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 via the third conductive pattern CP3.

[0197] The third conductive pattern CP3 can be formed from the fourth conductive layer. The third conductive pattern CP3 can be electrically connected to the thirteenth wiring line WL13 through the contact hole CH passing through the sixth insulating layer INS6. In addition, the third conductive pattern CP3 can be electrically connected to the semiconductor pattern SCP of the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 through the contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3 and the second insulating layer INS2 in sequence.

[0198] The thirteenth wiring line WL13 can be referenced as follows. Figure 3 The first power line PL1 is described. The thirteenth wiring line WL13 can be a vertical power line of the first power line PL1, and the ninth wiring line WL9 can be a horizontal power line of the first power line PL1. The ninth wiring line WL9 and the thirteenth wiring line WL13 can be electrically connected to each other to form a mesh structure of the first power line PL1.

[0199] The connection pattern CNP, formed from the same layer as the thirteenth wiring line WL13 (e.g., the fifth conductive layer), can be arranged to be spaced apart from the thirteenth wiring line WL13. The connection pattern CNP can be a reference. Figure 6 The described connection line CNL. The connection pattern CNP can be electrically connected to the light-emitting element through the through-hole VIH passing through the seventh insulating layer INS7 (reference). Figure 3 The corresponding anode electrode of "LED" (reference) Figure 3 (referring to "AE" in the original text). Furthermore, the connecting pattern CNP can be electrically connected to the fourth conductive pattern CP4 via the contact hole CH passing through the sixth insulating layer INS6.

[0200] The 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 may have substantially similar or identical structures. In an embodiment, for example, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 may be mirror-symmetric based on an imaginary line VL extending in the first direction DR1 between the first row R1 and the second row R2. Hereinafter, for convenience, the description will primarily focus on the 11th pixel circuit PXC11, and overlapping descriptions will be omitted.

[0201] The 11th pixel circuit PXC11 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0202] The first transistor T1 may include a first active pattern ACT1 and a first gate electrode GE1.

[0203] The first active pattern ACT1 can be the region of the semiconductor pattern SCP that overlaps with the first gate electrode GE1. The first active pattern ACT1 can be the channel region of the first transistor T1.

[0204] The region of the semiconductor pattern SCP that does not overlap with the first gate electrode GE1 and is connected to one side of the first active pattern ACT1 (e.g., the left side of the first active pattern ACT1 in the plan view) can be a first input / output terminal. The region of the semiconductor pattern SCP that does not overlap with the first gate electrode GE1 and is connected to the opposite side of the first active pattern ACT1 (e.g., the right side of the first active pattern ACT1 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the first active pattern ACT1 and can be connected to each of the semiconductor pattern SCPs of the second transistor T2 and the fifth transistor T5. The second input / output terminal can be connected to the opposite side of the first active pattern ACT1 and can be connected to the semiconductor pattern SCP of the sixth transistor T6.

[0205] The first gate electrode GE1 overlaps with the first active pattern ACT1 and can be formed by the first conductive layer. The first gate electrode GE1 can be an island-shaped conductive pattern. The first gate electrode GE1 can be electrically connected to the third transistor T3 and the fourth transistor T4 through the second conductive pattern CP2.

[0206] The second conductive pattern CP2 can be formed from the fourth conductive layer. One end of the second conductive pattern CP2 can be electrically connected to the first gate electrode GE1 through a contact hole CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer INS3. The opposite end of the second conductive pattern CP2 can be electrically connected to the region of the semiconductor pattern SCP shared by the third transistor T3 and the fourth transistor T4 through a contact hole CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0207] The second transistor T2 may include a second active pattern ACT2 and a second gate electrode.

[0208] The second active pattern ACT2 can be the region of the semiconductor pattern SCP that overlaps with the second wiring line WL2. The second active pattern ACT2 can be the channel region of the second transistor T2.

[0209] The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring line WL2 and is connected to one side of the second active pattern ACT2 (e.g., the upper side of the second active pattern ACT2 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring line WL2 and is connected to the opposite side of the second active pattern ACT2 (e.g., the lower side of the second active pattern ACT2 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the second active pattern ACT2 and can be electrically connected to the first conductive pattern CP1. The first input / output terminal can be electrically connected to the twelfth wiring line WL12 (or data line) through the first conductive pattern CP1. The second input / output terminal can be connected to the opposite side of the second active pattern ACT2 and can be connected to the first input / output terminal of the first transistor T1.

[0210] The second gate electrode can be the region of the second wiring line WL2 that overlaps with the second active pattern ACT2.

[0211] A third transistor T3 can be configured to connect the sub-transistors in series to prevent leakage current. For ease of description, the third transistor T3, which is formed on the protrusion of the second wiring line WL2, will be described as an exemplary embodiment.

[0212] The third transistor T3 may include a third active pattern ACT3 and a third gate electrode.

[0213] The third active pattern ACT3 is the region where the semiconductor pattern SCP overlaps with the protrusion protruding from the second wiring line WL2 on the second direction DR2, and can form the channel region of the third transistor T3.

[0214] The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring line WL2 and is connected to one side of the third active pattern ACT3 (e.g., the right side of the third active pattern ACT3 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring line WL2 and is connected to the opposite side of the third active pattern ACT3 (e.g., the left side of the third active pattern ACT3 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the third active pattern ACT3 and can be electrically connected to the semiconductor pattern SCPs of the first transistor T1 and the sixth transistor T6. The second input / output terminal can be connected to the opposite side of the third active pattern ACT3 and is electrically connected to the semiconductor pattern SCP of the fourth transistor T4.

[0215] The third gate electrode can be the area where the second wiring line WL2 overlaps with the third active pattern ACT3.

[0216] The fourth transistor T4 may be configured with sub-transistors connected in series to prevent leakage current. For ease of description, the fourth transistor T4, which is arranged closest to the third transistor T3, will be described as an exemplary embodiment.

[0217] The fourth transistor T4 may include a fourth active pattern ACT4 and a fourth gate electrode.

[0218] The fourth active pattern ACT4 is the region of the semiconductor pattern SCP that overlaps with the first wiring line WL1, and can form the channel region of the fourth transistor T4.

[0219] The area of ​​the semiconductor pattern SCP that does not overlap with the first wiring line WL1 and is connected to one side of the fourth active pattern ACT4 (e.g., the lower side of the fourth active pattern ACT4 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the first wiring line WL1 and is connected to the opposite side of the fourth active pattern ACT4 (e.g., the upper side of the fourth active pattern ACT4 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the fourth active pattern ACT4 and can be connected to the semiconductor pattern SCP of the third transistor T3. The second input / output terminal can be connected to the opposite side of the fourth active pattern ACT4 and is electrically connected to the sixth wiring line WL6 through the contact hole CH passing through the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0220] The fourth gate electrode can be the area of ​​the first wiring line WL1 that overlaps with the fourth active pattern ACT4.

[0221] The fifth transistor T5 may include a fifth active pattern ACT5 and a fifth gate electrode.

[0222] The fifth active pattern ACT5 is the region of the semiconductor pattern SCP that overlaps with the third wiring line WL3, and can form the channel region of the fifth transistor T5.

[0223] The area of ​​the semiconductor pattern SCP in the plan view that does not overlap with the third wiring line WL3 and is connected to the side of the fifth active pattern ACT5 (e.g., the area below the fifth active pattern ACT5) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring line WL3 and is connected to the opposite side of the fifth active pattern ACT5 (e.g., the upper side of the fifth active pattern ACT5 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the fifth active pattern ACT5 and electrically connected to the first conductive pattern CP1 through a corresponding contact hole CH. The second input / output terminal can be connected to the opposite side of the fifth active pattern ACT5 and can be connected to the semiconductor pattern SCP of each of the first transistor T1 and the second transistor T2.

[0224] The fifth gate electrode can be the area of ​​the third wiring line WL3 that overlaps with the fifth active pattern ACT5.

[0225] The sixth transistor T6 may include a sixth active pattern ACT6 and a sixth gate electrode.

[0226] The sixth active pattern ACT6 is the region of the semiconductor pattern SCP that overlaps with the third wiring line WL3, and may be the channel region of the sixth transistor T6.

[0227] The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring line WL3 and is connected to one side of the sixth active pattern ACT6 (e.g., the upper side of the sixth active pattern ACT6 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring line WL3 and is connected to the opposite side of the sixth active pattern ACT6 (e.g., the lower side of the sixth active pattern ACT6 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the sixth active pattern ACT6 and the semiconductor pattern SCP of the first transistor T1. The second input / output terminal can be connected to the opposite side of the sixth active pattern ACT6 and the semiconductor pattern SCP of the seventh transistor T7. Furthermore, the second input / output terminal can be electrically connected to the fourth conductive pattern CP4 through a corresponding contact hole CH.

[0228] The fourth conductive pattern CP4 (or the first contact electrode CNE1) can be formed from the fourth conductive layer. The fourth conductive pattern CP4 can be electrically connected to the second input / output terminal of the sixth transistor T6 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the fourth conductive pattern CP4 can be electrically connected to the connection pattern CNP through corresponding contact holes CH. The fourth conductive pattern CP4 can be electrically connected to the anode electrode AE ​​of the light-emitting element LED.

[0229] The sixth gate electrode can be the area of ​​the third wiring line WL3 that overlaps with the sixth active pattern ACT6.

[0230] The seventh transistor T7 may include a seventh active pattern ACT7 and a seventh gate electrode.

[0231] The seventh active pattern ACT7 is the region of the semiconductor pattern SCP that overlaps with the fourth wiring line WL4, and can be the channel region of the seventh transistor T7.

[0232] The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring line WL4 and is connected to one side of the seventh active pattern ACT7 (e.g., the upper side of the seventh active pattern ACT7 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring line WL4 and is connected to the opposite side of the seventh active pattern ACT7 (e.g., the lower side of the seventh active pattern ACT7 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the semiconductor pattern SCP of the seventh active pattern ACT7 and the sixth transistor T6. The second input / output terminal can be connected to the opposite side of the seventh active pattern ACT7 and the fifth conductive pattern CP5.

[0233] The fifth conductive pattern CP5 can be formed from the fourth conductive layer. The fifth conductive pattern CP5 can be electrically connected to the semiconductor pattern SCP of the seventh transistor T7 via contact holes CH that sequentially penetrate the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the fifth conductive pattern CP5 can be connected to the fifth wiring line WL5 via contact holes CH that pass through the fifth insulating layer INS5 and the fourth insulating layer INS4.

[0234] The seventh gate electrode can be the region of the fourth wiring line WL4 that overlaps with the seventh active pattern ACT7.

[0235] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE.

[0236] The lower electrode LE can be integrated with the first gate electrode GE1. The lower electrode LE can be formed from the first conductive layer.

[0237] The upper electrode UE overlaps with the lower electrode LE and can be formed by a second conductive layer. The upper electrode UE can define an opening OPN by removing a portion of it. The area of ​​the lower electrode LE that overlaps with the upper electrode UE can be exposed by the opening OPN. The upper electrode UE can be electrically connected to the thirteenth wiring line WL13 through contact holes CH that sequentially penetrate the sixth insulating layer INS6, the fifth insulating layer INS5, and the fourth insulating layer INS4.

[0238] In the first region DA1, repair lines RPL can be arranged between the first row R1 and the second row R2. Repair lines RPL can include a first repair line RPL1 and a second repair line RPL2 spaced apart relative to an imaginary line VL extending in the first direction DR1. The first repair line RPL1 can be positioned above the imaginary line VL, and the second repair line RPL2 can be positioned below the imaginary line VL. The first repair line RPL1 and the second repair line RPL2 can be spaced apart from each other and can be electrically insulated from each other.

[0239] The first repair line RPL1 and the second repair line RPL2 may extend in the first direction DR1. The first repair line RPL1 and the second repair line RPL2 may be formed of a third conductive layer. The first repair line RPL1 and the second repair line RPL2 may be formed using the same process as the sixth wiring line WL6. The first repair line RPL1 and the second repair line RPL2 may be disposed in the same layer as the sixth wiring line WL6 and may comprise the same material as the sixth wiring line WL6.

[0240] The first repair line RPL1 may be electrically connected to the first bridging pattern BRP1. The first bridging pattern BRP1 may be integral with the first repair line RPL1. The first bridging pattern BRP1 may extend in the second direction DR2 and may protrude from the first repair line RPL1 in a direction toward the second repair line RPL2 (or the second row R2). In an embodiment, the first repair line RPL1 may be electrically connected to a first non-display area (reference) arranged immediately adjacent to (near) the first region DA1. Figure 2 The first dummy pixel and the second dummy pixel in each of the first row R1 and the second row R2 of “NDA1” (see reference) Figure 2 One of "DP1 and DP2" in the list.

[0241] The second repair line RPL2 can be electrically connected to the second bridging pattern BRP2. The second bridging pattern BRP2 can be integral with the second repair line RPL2. The second bridging pattern BRP2 can extend in the second direction DR2 and can protrude from the second repair line RPL2 in a direction toward the first repair line RPL1 or the first row R1. In an embodiment, the second repair line RPL2 can be electrically connected to the remaining (another) dummy pixel in the first dummy pixel DP1 and the second dummy pixel DP2 arranged in the first row R1 and the second row R2 of the first non-display area NDA1.

[0242] The first bridging pattern BRP1 and the second bridging pattern BRP2 are spaced apart and face each other in the first direction DR1. The first bridging pattern BRP1 and the first repair line RPL1 can be electrically isolated from the second bridging pattern BRP2 and the second repair line RPL2, respectively.

[0243] The fourth conductive pattern CP4 (or the first contact electrode CNE1) and the connection pattern CNP can be set at the connection point (or the fourth node) of the anode electrode AE ​​of the 11th sub-pixel SP11 and the 11th pixel circuit PXC11, which electrically connects the 11th sub-pixel SP11. Figure 3 The connection point is located at "N4" in the diagram. Furthermore, the electrical connection between the sixth transistor T6 and the semiconductor pattern SCP of the fourth conductive pattern CP4 can be provided at the connection point. The fourth conductive pattern CP4 can be electrically connected to the semiconductor pattern SCP of the sixth transistor T6 through a contact hole CH passing through the insulating layer. In an embodiment, for example, the fourth conductive pattern CP4 can be electrically connected to the semiconductor pattern SCP of the sixth transistor T6 through a contact hole CH (or a first contact hole CH1) passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0244] In each of the first row R1 and the second row R2, a first bridging pattern BRP1 and a second bridging pattern BRP2 can be arranged based on the first contact hole CH1. In an embodiment, as... Figure 13 As shown, for example, based on the first contact hole CH1, the first bridging pattern BRP1 is disposed on one side of the first contact hole CH1 (e.g., to the left of the first contact hole CH1 in the plan view), and based on the first contact hole CH1, the second bridging pattern BRP2 can be disposed on the opposite side of the first contact hole CH1 (e.g., to the right of the first contact hole CH1 in the plan view). However, this disclosure is not limited thereto. In some embodiments, based on the first contact hole CH1, the second bridging pattern BRP2 can be disposed on one side of the first contact hole CH1 (e.g., to the left of the first contact hole CH1 in the plan view), and based on the first contact hole CH1, the first bridging pattern BRP1 can be disposed on the opposite side of the first contact hole CH1 (e.g., to the right of the first contact hole CH1 in the plan view).

[0245] When viewed in a plane, such as Figure 13 As shown, the first contact hole CH1 can overlap with the semiconductor pattern SCP and the fourth conductive pattern CP4 of the sixth transistor T6 disposed above the first repair line RPL1. In the embodiment, as... Figure 15 As shown, the first contact hole CH1 may overlap with the semiconductor pattern SCP and the fourth conductive pattern CP4 (or the first contact electrode CNE1) of the sixth transistor T6 disposed below the first repair line RPL1.

[0246] In an embodiment, one end of each of the first bridging pattern BRP1 and the second bridging pattern BRP2 disposed between the first row R1 and the second row R2 may overlap with the fourth conductive pattern CP4 of the 11th sub-pixel SP11 of the first row R1, and the opposite end of each of the first bridging pattern BRP1 and the second bridging pattern BRP2 may overlap with the fourth conductive pattern CP4 of the 21st sub-pixel SP21 of the second row R2.

[0247] The corresponding repair line RPL in the first repair line RPL1 and the second repair line RPL2, the first bridging pattern BRP1, and the second bridging pattern BRP2 can overlap with the fourth conductive pattern CP4 of each of the 11th sub-pixel SP11 and the 21st sub-pixel SP21. The first repair line RPL1 and the second repair line RPL2, the first bridging pattern BRP1, and the second bridging pattern BRP2 can be electrically isolated from the fourth conductive pattern CP4.

[0248] When a dark spot fault occurs in the 11th sub-pixel SP11, the electrical connection between the semiconductor pattern SCP shared by the sixth transistor T6 and the seventh transistor T7 of the 11th sub-pixel SP11 and the anode electrode AE ​​of the light-emitting element LED can be broken, and the fourth conductive pattern CP4 (or the first contact electrode CNE1) can be electrically connected to one of the first bridging pattern BRP1 and the second bridging pattern BRP2 of the 11th sub-pixel SP11, thereby allowing the light-emitting element LED of the 11th sub-pixel SP11 to operate normally.

[0249] Figure 16 It is the first region DA1 and Figure 7 A schematic enlarged plan view of the part corresponding to EA2. Figure 17 It is along Figure 16 A schematic cross-sectional view of line III-III'.

[0250] Now for reference Figure 16 and Figure 17 For ease of explanation, overlapping descriptions with the above embodiments will be omitted.

[0251] refer to Figure 7 , Figure 16 and Figure 17Based on the first contact hole CH1 of the semiconductor pattern SCP and the fourth conductive pattern CP4 (first contact electrode CNE1) electrically connecting the sixth transistor T6, the first bridging pattern BRP1 and the second bridging pattern BRP2 can be disposed on one side of the first contact hole CH1. In an embodiment, for example, when viewed in a plane and cross section, the first bridging pattern BRP1 and the second bridging pattern BRP2 can be disposed on the right side of the first contact hole CH1. However, this disclosure is not limited thereto. In some embodiments, based on the first contact hole CH1, the first bridging pattern BRP1 and the second bridging pattern BRP2 can be disposed on the left side of the first contact hole CH1.

[0252] Figure 18 This is a schematic plan view illustrating an embodiment of a dummy pixel arranged in the first row R1 and the second row R2 in a region of the first non-display area NDA1 of a display device. Figure 19 It only shows those included Figure 18 A schematic plan view of the configuration of the first transistor T1 to the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 in the first conductive layer. Figure 20 It is only included Figure 18 A schematic plan view of the configuration in the second conductive layer. Figure 21 It is only included Figure 18 A schematic plan view of the configuration in the third conductive layer. Figure 22 It is only included Figure 18 A schematic plan view of the configuration in the fourth conductive layer. Figure 23 It is only included Figure 18 A schematic plan view of the configuration in the fifth conductive layer.

[0253] Main reference Figures 18 to 23 The differences from the above-described embodiments are described in order to avoid redundant descriptions.

[0254] refer to Figure 2 , Figure 4 as well as Figures 18 to 23 Virtual pixels (reference) Figure 2The "DP" in the first non-display area NDA1 can be arranged in the same column in the second direction DR2, in each of the first row R1 and the second row R2. In an embodiment, for example, the 11th dummy pixel DP11 (or the first dummy pixel) and the 12th dummy pixel DP12 (or the second dummy pixel) can be arranged in the first row R1, and the 21st dummy pixel DP21 (or the first dummy pixel) and the 22nd dummy pixel DP22 (or the second dummy pixel) can be arranged in the second row R2. The 11th dummy pixel DP11 and the 12th dummy pixel DP12 can be adjacent to each other in the first direction DR1, and the 21st dummy pixel DP21 and the 22nd dummy pixel DP22 can be adjacent to each other in the first direction DR1. The 11th dummy pixel DP11 in the first row R1 and the 21st dummy pixel DP21 in the second row R2 can be placed in the same column, and the 12th dummy pixel DP12 in the first row R1 and the 22nd dummy pixel DP22 in the second row R2 can also be placed in the same column. The 12th dummy pixel DP12 can be compared with the reference... Figure 7 The 11th sub-pixel SP11 described is directly adjacent (neighboring), and the 22nd dummy pixel DP22 can be related to, as referenced Figure 7 The 21st sub-pixel SP21 described is directly adjacent (neighboring).

[0255] A dummy pixel DP may include a dummy pixel circuit and a repair modulation circuit. In an embodiment, for example, the 11th dummy pixel DP11 includes the 11th dummy pixel circuit DPC11 and the 11th repair modulation circuit RM11, the 12th dummy pixel DP12 includes the 12th dummy pixel circuit DPC12 and the 12th repair modulation circuit RM12, the 21st dummy pixel DP21 includes the 21st dummy pixel circuit DPC21 and the 21st repair modulation circuit RM21, and the 22nd dummy pixel DP22 may include the 22nd dummy pixel circuit DPC22 and the 22nd repair modulation circuit RM22.

[0256] In this embodiment, the 11th dummy pixel DP11 and the 21st dummy pixel DP21 are arranged on the second direction DR2 and can face each other relative to the repair line RPL. The 12th dummy pixel DP12 and the 22nd dummy pixel DP22 are arranged on the second direction DR2 and can face each other relative to the repair line RPL. The 11th dummy pixel circuit DPC11 and the 21st dummy pixel circuit DPC21 can be symmetrical and substantially identical with respect to the repair line RPL, but are not limited thereto. The 11th dummy pixel circuit DPC11 and the 21st dummy pixel circuit DPC21 can be mirror symmetrical with respect to the repair line RPL. The 12th dummy pixel circuit DPC12 and the 22nd dummy pixel circuit DPC22 can be mirror symmetrical with respect to the repair line RPL.

[0257] Signal lines connected to the 11th dummy pixel DP11, the 12th dummy pixel DP12, the 21st dummy pixel DP21, and the 22nd dummy pixel DP22 can be arranged in the first non-display area NDA1. In an embodiment, for example, the first wiring line WL1 to the eleventh wiring line WL11 can be arranged in the first non-display area NDA1. The first wiring line WL1 to the eleventh wiring line WL11 can be as shown in the reference... Figures 7 to 12 The first cabling line WL1 to the eleventh cabling line WL11 are described.

[0258] Furthermore, the first dummy line DML1 and the second dummy line DML2 can be arranged in the first non-display area NDA1. The first dummy line DML1 extends in the second direction DR2 and can be arranged in the sixth insulating layer (reference). Figure 6 "INS6" and the seventh insulating layer (reference) Figure 6 A fifth conductive layer is formed between "INS7" and the first dummy line DML1, as shown in the reference. Figure 4 The first dummy data line DD1 is described. The second dummy line DML2 may extend in the second direction DR2 and may be formed by a fifth conductive layer. The second dummy line DML2 may be as described in the reference. Figures 7 to 15 The thirteenth wiring line WL13 is described. The second dummy line DML2 can be electrically connected via the third conductive pattern CP3 to the fifth transistor T5 of each of the 11th dummy pixel circuit DPC11, the 12th dummy pixel circuit DPC12, the 21st dummy pixel circuit DPC21, and the 22nd dummy pixel circuit DPC22.

[0259] The 11th dummy pixel circuit DPC11, the 12th dummy pixel circuit DPC12, the 21st dummy pixel circuit DPC21, and the 22nd dummy pixel circuit DPC22 may have substantially similar or identical structures. For convenience, the following description will primarily focus on the 12th dummy pixel DP12, and overlapping descriptions will be omitted.

[0260] The 12th dummy pixel DP12 may include the 12th dummy pixel circuit DPC12 and the 12th repair modulation circuit RM12.

[0261] The 12th dummy pixel circuit DPC12 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a storage capacitor Cst. The first transistor T1 through the sixth transistor T6 are connected to a reference... Figures 7 to 15The first transistor T1 through the sixth transistor T6 are identical and therefore will not be described again herein. The storage capacitor Cst may include a first lower electrode LE1 and a first upper electrode UE1. The storage capacitor Cst may be related to the reference... Figures 7 to 15 The storage capacitor Cst described is the same. The first lower electrode LE1 can be as referenced. Figures 7 to 15 The lower electrode LE is described, and the first upper electrode UE1 can be as referenced. Figures 7 to 15 The described upper electrode UE. The first upper electrode UE1 can define a first opening OPN1 by removing a first portion of it. An area of ​​the first lower electrode LE1 that overlaps with the first upper electrode UE1 can be exposed by the first opening OPN1. The first upper electrode UE1 can be electrically connected to the second dummy line DML2 through a contact hole CH passing through the sixth insulating layer INS6, the fifth insulating layer INS5, and the fourth insulating layer INS4.

[0262] The 12th repair modulation circuit RM12 may include an eighth transistor T8, a ninth transistor T9, and a first capacitor C1.

[0263] The eighth transistor T8 may include an eighth active pattern ACT8 and an eighth gate electrode.

[0264] The eighth active pattern ACT8 can be the region of the semiconductor pattern SCP that overlaps with the third wiring line WL3. The eighth active pattern ACT8 can be the channel region of the eighth transistor T8.

[0265] The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring line WL3 and is connected to one side of the eighth active pattern ACT8 (e.g., to the left of the eighth active pattern ACT8 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring line WL3 and is connected to the opposite side of the eighth active pattern ACT8 (e.g., to the right of the eighth active pattern ACT8 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the eighth active pattern ACT8 and the sixth conductive pattern CP6. The second input / output terminal can be connected to the opposite side of the eighth active pattern ACT8 and the semiconductor pattern SCP of the ninth transistor T9.

[0266] The sixth conductive pattern CP6 can be formed from the fourth conductive layer. The sixth conductive pattern CP6 can be formed by passing through the fifth insulating layer (see reference). Figure 6 "INS5" in the text), the fourth insulating layer (refer to...) Figure 6 "INS4" in the text), the third insulating layer (refer to...) Figure 6 "INS3" in the middle) and the second insulating layer (reference) Figure 6The contact hole CH of “INS2” is electrically connected to the first input / output terminal of the eighth transistor T8. Furthermore, the sixth conductive pattern CP6 can be electrically connected to the first repair line RPL1 through the contact hole CH passing through the fifth insulating layer INS5.

[0267] The sixth conductive pattern CP6 can be electrically connected to the second lower electrode LE2 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer INS3. Furthermore, the sixth conductive pattern CP6 can be electrically connected to the semiconductor pattern SCP shared by the eighth transistor T8 and the ninth transistor T9 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0268] The eighth gate electrode can be the area of ​​the third wiring line WL3 that overlaps with the eighth active pattern ACT8.

[0269] The ninth transistor T9 may include a ninth active pattern ACT9 and a ninth gate electrode.

[0270] The ninth active pattern ACT9 can be the region of the semiconductor pattern SCP that overlaps with the fourth wiring line WL4. The ninth active pattern ACT9 can be the channel region of the ninth transistor T9.

[0271] The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring line WL4 and is connected to one side of the ninth active pattern ACT9 (e.g., the upper side of the ninth active pattern ACT9 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring line WL4 and is connected to the opposite side of the ninth active pattern ACT9 (e.g., the lower side of the ninth active pattern ACT9 in the plan view) can be a second input / output terminal. The first input / output terminal can be electrically connected to one side of the ninth active pattern ACT9 and the semiconductor pattern SCP of the eighth transistor T8. The second input / output terminal can be electrically connected to the opposite side of the ninth active pattern ACT9 and the seventh conductive pattern CP7.

[0272] The seventh conductive pattern CP7 can be formed from the fourth conductive layer. The seventh conductive pattern CP7 can be electrically connected to the semiconductor pattern SCP of the ninth transistor T9 via contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the seventh conductive pattern CP7 can be electrically connected to the fifth wiring line WL5 via contact holes CH passing through the fifth insulating layer INS5 and the fourth insulating layer INS4. First initialization power supply voltage (reference) Figure 4 The “Vint1” in the reference can provide access to the fifth cabling line WL5. The fifth cabling line WL5 can be as described above. Figure 4 The second power line PL2 or the fourth power line PL4 are described. The fifth wiring line WL5 can be electrically connected to the area of ​​the semiconductor pattern SCP of the ninth transistor T9 (e.g., the second input / output terminal) via the seventh conductive pattern CP7.

[0273] The ninth gate electrode can be the area of ​​the fourth wiring line WL4 that overlaps with the ninth active pattern ACT9.

[0274] The first capacitor C1 may include a second lower electrode LE2 and a second upper electrode UE2.

[0275] The second lower electrode LE2 may be spaced apart from the first lower electrode LE1. The second lower electrode LE2 may be formed from the first conductive layer. In an embodiment, for example, the second lower electrode LE2 may be formed using the same process as the first lower electrode LE1 (or the first gate electrode GE1), may be disposed in the same layer as the first lower electrode LE1, and may comprise the same material as the first lower electrode LE1. The second lower electrode LE2 may be electrically connected via the sixth conductive pattern CP6 to the semiconductor pattern SCP shared by the eighth transistor T8 and the ninth transistor T9.

[0276] The second upper electrode UE2 may overlap with the second lower electrode LE2 and may be formed of a second conductive layer. The second upper electrode UE2 may define a second opening OPN2 by removing a portion of it. A region of the second lower electrode LE2 that overlaps with the second upper electrode UE2 may be exposed by the second opening OPN2. The second upper electrode UE2 may be integral with the first upper electrode UE1 and electrically connected to the second dummy line DML2.

[0277] In one embodiment, the 11th dummy pixel DP11 and the 12th dummy pixel DP12, arranged adjacent to each other on the first direction DR1, may include the same repair modulation circuit. In other words, the repair modulation circuit of the 11th dummy pixel DP11 and the repair modulation circuit of the 12th dummy pixel DP12 may be configured as a single unit. In another embodiment, for example, the 11th repair modulation circuit RM11 of the 11th dummy pixel DP11 and the 12th repair modulation circuit RM12 of the 12th dummy pixel DP12 may be configured as a single unit. The 11th dummy pixel DP11 and the 12th dummy pixel DP12 may share the same first capacitor C1. The first capacitor C1 may be arranged in the boundary region between the 11th dummy pixel circuit DPC11 of the 11th dummy pixel DP11 and the 12th dummy pixel circuit DPC12 of the 12th dummy pixel DP12.

[0278] The second lower electrode LE2 of the first capacitor C1 in each of the 11th repair modulation circuit RM11 and the 12th repair modulation circuit RM12 can be spaced apart from the first lower electrode LE1 of the storage capacitor Cst in each of the 11th dummy pixel circuit DPC11 and the 12th dummy pixel circuit DPC12. The second upper electrode UE2 of the first capacitor C1 in each of the 11th repair modulation circuit RM11 and the 12th repair modulation circuit RM12 can be integrally formed with the first upper electrode UE1 of the storage capacitor Cst in each of the 11th dummy pixel circuit DPC11 and the 12th dummy pixel circuit DPC12. The second upper electrode UE2 can be electrically connected to the ninth wiring line WL9 arranged on the 11th dummy pixel DP11 through the contact hole CH passing through the fifth insulating layer INS5 and the fourth insulating layer INS4.

[0279] As described above, the first capacitor C1 can be arranged between the 11th dummy pixel circuit DPC11 and the 12th dummy pixel circuit DPC12, so that the 11th dummy pixel DP11 and the 12th dummy pixel DP12 can share the first capacitor C1. The area occupied by the first capacitor C1 of each dummy pixel DP in the first non-display area NDA1 can be reduced. Therefore, the dead space of the first non-display area NDA1 can be reduced.

[0280] Furthermore, the 21st dummy pixel DP21 and the 22nd dummy pixel DP22, which are adjacent to each other in the first direction DR1 in the second row R2, can share the first capacitor C1. In an embodiment, for example, the 21st dummy pixel DP21 and the 22nd dummy pixel DP22 can share the same first capacitor C1. The first capacitor C1 can be arranged between the 21st dummy pixel circuit DPC21 of the 21st dummy pixel DP21 and the 22nd dummy pixel circuit DPC22 of the 22nd dummy pixel DP22.

[0281] In the first non-display area NDA1, a repair line RPL can be arranged between the first row R1 and the second row R2. The repair line RPL can include a first repair line RPL1 and a second repair line RPL2 spaced apart from an imaginary line VL extending in the first direction DR1. The first repair line RPL1 can be positioned above the imaginary line VL, and the second repair line RPL2 can be positioned below the imaginary line VL. The first repair line RPL1 and the second repair line RPL2 can be spaced apart from each other and can be electrically insulated from each other.

[0282] The first repair line RPL1 and the second repair line RPL2 can be formed by a third conductive layer disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5. The first repair line RPL1 and the second repair line RPL2 can be connected to a reference... Figures 7 to 15The first repair line RPL1 and the second repair line RPL2 are described as identical. In other words, the first repair line RPL1 and the second repair line RPL2 can be common lines provided to the first non-display area NDA1 and the first area DA1.

[0283] Each of the first repair line RPL1 and the second repair line RPL2 can be electrically connected to the dummy pixel circuit of the dummy pixel DP. In an embodiment, for example, the 11th dummy pixel circuit DPC11 of the 11th dummy pixel DP11 in the first row R1 can be electrically connected to the second repair line RPL2, and the 12th dummy pixel circuit DPC12 of the 12th dummy pixel DP12 in the first row R1 can be electrically connected to the first repair line RPL1. Similarly, the 21st dummy pixel circuit DPC21 of the 21st dummy pixel DP21 in the second row R2 can be electrically connected to the first repair line RPL1, and the 22nd dummy pixel circuit DPC22 of the 22nd dummy pixel DP22 in the second row R2 can be electrically connected to the second repair line RPL2.

[0284] The first bridging pattern BRP1 and the second bridging pattern BRP2 can be arranged between the first repair line RPL1 and the second repair line RPL2. The first bridging pattern BRP1 and the second bridging pattern BRP2 can be spaced apart from each other.

[0285] The first bridging pattern BRP1 may be integrally formed with the first repair suture RPL1. The first bridging pattern BRP1 may be electrically and / or physically connected to the first repair suture RPL1. The first bridging pattern BRP1 may extend in the second direction DR2 and may protrude from the first repair suture RPL1 in the direction toward the second repair suture RPL2. The second bridging pattern BRP2 may be integral with the second repair suture RPL2. The second bridging pattern BRP2 may be electrically and / or physically connected to the second repair suture RPL2. The second bridging pattern BRP2 may extend in the second direction DR2 and may protrude from the second repair suture RPL2 in the direction toward the first repair suture RPL1.

[0286] The first bridging pattern BRP1 and the second bridging pattern BRP2 are spaced apart and can face each other in the first direction DR1. The first bridging pattern BRP1 and the first repair line RPL1 can be electrically isolated from the second bridging pattern BRP2 and the second repair line RPL2, respectively.

[0287] In this embodiment, one end of the first repair line RPL1, one end of the first bridging pattern BRP1, and one end of the second bridging pattern BRP2 may overlap with the fourth conductive pattern CP4 of each of the 11th dummy pixel DP11 and the 12th dummy pixel DP12 arranged in the first row R1. The first repair line RPL1, the first bridging pattern BRP1, and the second bridging pattern BRP2 may be electrically isolated from the fourth conductive pattern CP4 of each of the 11th dummy pixel DP11 and the 12th dummy pixel DP12.

[0288] The opposite ends of the second repair line RPL2, the first bridging pattern BRP1, and the second bridging pattern BRP2 may overlap with the fourth conductive pattern CP4 (or the second contact electrode CNE2) of each of the 21st dummy pixel DP21 and the 22nd dummy pixel DP22 arranged in the second row R2. The second repair line RPL2, the first bridging pattern BRP1, and the second bridging pattern BRP2 may be electrically isolated from the fourth conductive pattern CP4 of each of the 21st dummy pixel DP21 and the 22nd dummy pixel DP22.

[0289] The dummy pixels DP in the first row R1 and the second row R2, located in the same column, can be electrically connected to different bridging patterns (or repair lines). In an embodiment, for example, the fourth conductive pattern CP4 of the 11th dummy pixel DP11 in the first row R1 can be electrically connected to the second bridging pattern BRP2 (or the second repair line RPL2) through a corresponding contact hole CH, and the fourth conductive pattern CP4 of the 21st dummy pixel DP21 in the second row R2 can be electrically connected to the first bridging pattern BRP1 (or the first repair line RPL1) through a corresponding contact hole CH. Furthermore, the fourth conductive pattern CP4 of the 12th dummy pixel DP12 in the first row R1 can be electrically connected to the first repair line RPL1 (or the first bridging pattern BRP1) through a corresponding contact hole CH, and the fourth conductive pattern CP4 of the 22nd dummy pixel DP22 in the second row R2 can be electrically connected to the second repair line RPL2 (or the second bridging pattern BRP2) through a corresponding contact hole CH.

[0290] Figure 24 It is used to show the sub-pixels in the first region DA1 and the dummy pixels in the first non-display region NDA1 in the display device. Figure 2 A schematic diagram of a partial implementation of EA1.

[0291] exist Figure 24 For ease of description, only the first repair line RPL1 and the second repair line RPL2 arranged between the first row R1 and the second row R2 of the signal wiring lines in each of the first region DA1 and the first non-display region NDA1 are shown.

[0292] refer to Figure 24 This section primarily describes the differences from the embodiments described above in order to avoid overlapping descriptions.

[0293] refer to Figure 2 and Figure 24 In the first region DA1, each of the first row R1 and the second row R2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged in the first direction DR1. The first sub-pixel SP1, including the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21, may be arranged in the first pixel column PC1; the second sub-pixel SP2, including the 12th pixel circuit PXC12 and the 22nd pixel circuit PXC22, may be arranged in the second pixel column PC2; and the third sub-pixel SP3, including the 13th pixel circuit PXC13 and the 23rd pixel circuit PXC23, may be arranged in the third pixel column PC3. Each of the first sub-pixels SP1 to SP3 may include a pixel circuit, and a light-emitting element LED is electrically connected to the pixel circuit. The pixel circuit of each of the first sub-pixels SP1 to SP3 may include a first contact electrode CNE1. The first contact electrode CNE1 may be electrically connected to the light-emitting element LED. The first contact electrode CNE1 may be as shown in the reference. Figures 7 to 15 The fourth conductive pattern CP4 is described.

[0294] The first contact electrode CNE1 can electrically connect the light-emitting element LED and the pixel circuit in some configurations. In an embodiment, for example, the first contact electrode CNE1 can electrically connect the light-emitting element LED and the pixel circuit through a corresponding contact hole CH (see reference). Figure 3 The sixth transistor of “PXC” (reference) Figure 7 (T6 in the text). The first contact electrode CNE1 can be set at the connection point (or...) in each sub-pixel where the light-emitting element LED and the pixel circuit PXC are electrically connected. Figure 3 The fourth node (N4) is located therein. In the following text, for ease of description, the contact hole CH that electrically connects the light-emitting element LED of the pixel circuit PXC, the first contact electrode CNE1, and the sixth transistor T6 will also be referred to as the first contact hole CH1.

[0295] In the first non-display area NDA1, each of the first row R1 and the second row R2 may include a first dummy pixel DP1 and a second dummy pixel DP2. The first dummy pixel DP1 may be arranged in a first dummy column DC1, and the second dummy pixel DP2 may be arranged in a second dummy column DC2. Each of the first dummy pixel DP1 and the second dummy pixel DP2 may include a dummy pixel circuit. In an embodiment, for example, the first dummy pixel circuit DPC1 may be arranged in the first dummy pixel DP1, and the second dummy pixel circuit DPC2 may be arranged in the second dummy pixel DP2. The dummy pixel circuit of each of the first dummy pixel DP1 and the second dummy pixel DP2 may include a second contact electrode CNE2 electrically connected to the repair line RPL. The second contact electrode CNE2 may be as referenced. Figures 18 to 23 The fourth conductive pattern CP4 is described.

[0296] The second contact electrode CNE2 can be electrically connected to the repair line RPL through a corresponding contact hole CH. The contact hole CH can be set at the connection point (or connection node) of the electrical connection repair line RPL and the second contact electrode CNE2 at each dummy pixel.

[0297] In each of the first non-display area NDA1 and the first area DA1, a first repair line RPL1 and a second repair line RPL2 may be arranged between the first row R1 and the second row R2. The first repair line RPL1 may be integrally formed with the first bridging pattern BRP1, and the second repair line RPL2 may be integrally formed with the second bridging pattern BRP2.

[0298] In the first region DA1, the first bridging pattern BRP1 and the second bridging pattern BRP2 can extend along the second direction DR2 between sub-pixels in the first row R1 and sub-pixels in the second row R2. In an embodiment, for example, the first bridging pattern BRP1 and the second bridging pattern BRP2 can extend along the second direction DR2 between the first sub-pixel SP1 in the first row R1 and the first sub-pixel SP1 in the second row R2, between the second sub-pixel SP2 in the first row R1 and the second sub-pixel SP2 in the second row R2, and between the third sub-pixel SP3 in the first row R1 and the third sub-pixel SP3 in the second row R2.

[0299] In the first region DA1, the first bridging pattern BRP1 and the second bridging pattern BRP2 may overlap with the first contact electrode CNE1 of each sub-pixel. Each of the first bridging pattern BRP1 and the second bridging pattern BRP2 may be electrically isolated from the first contact electrode CNE1. The first bridging pattern BRP1 and the second bridging pattern BRP2, spaced apart from each other between sub-pixels in the first row R1 and the second row R2 of the same pixel column, may be disposed on one side and the opposite side of the first contact hole CH1, respectively, relative to the first contact hole CH1. In an embodiment, for example, between the first row R1 and the second row R2 of each of the first pixel columns PC1 to the third pixel column PC3, based on the first contact hole CH1 of the sub-pixels in each of the first row R1 and the second row R2, the second bridging pattern BRP2 may be disposed on the left side of the first contact hole CH1, and the first bridging pattern BRP1 may be disposed on the right side of the first contact hole CH1.

[0300] In one embodiment, the first repair line RPL1 can be electrically connected to the dummy pixel circuit of one of the first dummy pixel DP1 and the second dummy pixel DP2, and the second repair line RPL2 can be electrically connected to the dummy pixel circuit of the remaining dummy pixels among the first dummy pixel DP1 and the second dummy pixel DP2. In another embodiment, for example, each of the second dummy pixel DP2 (or second dummy pixel circuit DPC2) in the first row R1 and the first dummy pixel DP1 (or first dummy pixel circuit DPC1) in the second row R2 is electrically connected to the first repair line RPL1 via a corresponding second contact electrode CNE2. Each of the first dummy pixel DP1 (or first dummy pixel circuit DPC1) in the first row R1 and the second dummy pixel DP2 (or second dummy pixel circuit DPC2) in the second row R2 can be electrically connected to the second repair line RPL2 via a corresponding second contact electrode CNE2.

[0301] The first repair line RPL1 and the second repair line RPL2 can be electrically isolated from the pixel circuit of each of the first sub-pixels SP1 to SP3 located in the first region DA1.

[0302] Typically, display devices (reference) Figure 2 The “DD” in the text can be used to specify the area to be placed in the display area (see reference). Figure 2 Subpixels in “DA” (reference) Figure 2 The light-emitting element (LED) of the sub-pixel SP performs an illumination check. When the illumination check indicates that some of the LEDs are not lit and the sub-pixel SP is dimmed, a repair process can be performed to drive the LEDs by electrically connecting the unlit LEDs to the first dummy pixel DP1 and the second dummy pixel DP2.

[0303] The following section describes a method for repairing defective subpixels SP in the first region DA1.

[0304] Figure 25 This is a schematic flowchart illustrating an implementation of a method for repairing a display device. Figure 26 This is used to illustrate the method of repairing defective subpixels. Figure 2 The diagram below shows the part corresponding to EA1. Figure 27 yes Figure 26 A partial schematic diagram of EA3. Figure 28 It shows the arrangement in Figure 26 A schematic circuit diagram showing the electrical connection of the first sub-pixel SP1 and the second dummy pixel DP2 in the first row R1.

[0305] Main reference Figures 25 to 28 The implementation method described herein differs from the implementation method described above in order to avoid overlapping descriptions.

[0306] refer to Figures 25 to 28 In operation S100, dummy pixels (see reference) can be provided. Figure 2 "DP" in the reference and sub-pixels (reference) Figure 2 The display device of "SP" in (reference) Figure 2 (DD in the text).

[0307] Using this repair method, during operation S200, the first area DA1 (or the first display area) and the second area (refer to) can be detected. Figure 2 Dark spot defects in each subpixel SP in “DA2” (or the second display area).

[0308] When two sub-pixels in the first row R1 of the first region DA1 have a dark spot fault, in operation S300, the first dummy pixel (refer to) arranged in the first row R1 of the first non-display region NDA1 can be removed. Figure 2 "DP1" in the reference and the second dummy pixel (reference) Figure 2 The “DP2” in the diagram is electrically connected to two sub-pixels to repair the dark spot faults of those two sub-pixels.

[0309] The repair process may include, for example, using a laser to disconnect the electrical connection between the light-emitting element and the pixel circuitry in the sub-pixel with the dark spot fault, and performing a bonding process using a laser to electrically connect the light-emitting element via a repair line (“RPL”) to a dummy pixel DP arranged in the same row as the sub-pixel with the dark spot fault, so that the light-emitting element can operate normally.

[0310] like Figure 26As shown, when a dark spot fault occurs simultaneously in the first sub-pixel SP1 and the third sub-pixel SP3 arranged in the first row R1, a repair process can be performed in which the first sub-pixel SP1 is electrically connected to the second dummy pixel DP2 arranged in the first row R1 and the third sub-pixel SP3 is electrically connected to the first dummy pixel DP1 arranged in the first row R1. The dark spot fault in each of the first sub-pixel SP1 and the third sub-pixel SP3 may be caused by, for example, a defect in the pixel circuitry.

[0311] When the 11th pixel circuit PXC11 of the first sub-pixel SP1 is defective, a laser can be used to disconnect the anode electrode AE ​​of the light-emitting element LED (hereinafter also referred to as the "first light-emitting element") electrically connected to the 11th pixel circuit PXC11 from the sixth transistor T6 and the seventh transistor T7 of the 11th pixel circuit PXC11. As a result, the anode electrode AE ​​can be electrically disconnected from the sixth transistor T6 and the seventh transistor T7. A contact hole CH (or a second contact hole CH2) can be formed between the first contact electrode CNE1 and the first bridging pattern BRP1 electrically connected to the anode electrode AE ​​(or the first light-emitting element LED) through the first contact hole CH1 by using a laser bonding process to break the insulating layer. In a plan view, based on the first contact hole CH1, the contact hole CH (or the second contact hole CH2) can be disposed on the right side of the first contact hole CH1.

[0312] Through contact hole CH (or second contact hole CH2), first contact electrode CNE1, and first contact hole CH1, the first bridging pattern BRP1 (or first repair line RPL1) and anode electrode AE ​​(or first light-emitting element LED) can be electrically connected. The first repair line RPL1 is electrically connected to the second dummy pixel DP2 arranged in the first row R1 of the first non-display area NDA1, allowing the second dummy pixel circuit DPC2 of the second dummy pixel DP2 and the first light-emitting element LED of the first sub-pixel SP1 to be electrically connected. Therefore, the first repair line RPL1 forms an electrical path from the second dummy pixel DP2 to the first light-emitting element LED of the first sub-pixel SP1, enabling the first light-emitting element LED to operate normally and repairing the first sub-pixel SP1 with dark spot defects.

[0313] When a dark spot fault occurs in the third sub-pixel SP3, which is arranged in the same row as the first sub-pixel SP1, the light-emitting element LED (hereinafter referred to as the "second light-emitting element") of the 13th pixel circuit PXC13 of the third sub-pixel SP3, which is electrically connected to the anode electrode (see reference), can be used. Figure 3 The “AE” in the text refers to the sixth and seventh transistors of the 13th pixel circuit PXC13 (see reference). Figure 3The transistors T6 and T7 are disconnected. As a result, the anode electrode AE ​​of the second light-emitting element LED can be electrically disconnected from each other by the sixth transistor T6 and the seventh transistor T7. The contact hole CH (or the second contact hole CH2) can be formed by laser bonding between the first contact electrode CNE1 and the second bridging pattern BRP2, which is electrically connected to the anode electrode AE ​​of the second light-emitting element LED through the first contact hole CH1, by breaking the insulating layer. In the plan view, based on the first contact hole CH1, the first contact hole CH (or the second contact hole CH2) can be disposed on the left side of the first contact hole CH1.

[0314] The second bridging pattern BRP2 (or the second repair line RPL2) and the anode electrode AE ​​of the second light-emitting element LED can be electrically connected through the contact hole CH, the first contact electrode CNE1, and the first contact hole CH1. The second repair line RPL2 is electrically connected to the first dummy pixel DP1 arranged in the first row R1 of the first non-display area NDA1, so that the first dummy pixel circuit DPC1 of the first dummy pixel DP1 and the second light-emitting element LED of the third sub-pixel SP3 can be electrically connected. Therefore, the second repair line RPL2 forms an electrical path from the first dummy pixel DP1 to the second light-emitting element LED of the third sub-pixel SP3, so that the second light-emitting element LED can operate normally and the third sub-pixel SP3 with dark spot defects can be repaired.

[0315] As described above, when a dark spot fault occurs in two sub-pixels arranged in the first row R1 of the first region DA1, the light-emitting element (LED) of one of the two sub-pixels for a horizontal time is electrically connected to the dummy pixel circuit of one of the first dummy pixels DP1 and the second dummy pixel DP2 arranged in the first row R1 of the first non-display region NDA1, and the light-emitting element (LED) of the remaining (other) sub-pixel can be electrically connected to the dummy pixel circuit of the other of the first dummy pixel DP1 and the second dummy pixel DP2. Therefore, the dark spot defect of two sub-pixels in a row (or a pixel row) of the first region DA1 can be repaired.

[0316] In the above embodiments, for ease of description, the first region DA1 is mainly described; however, this disclosure is not limited thereto, and any sub-pixel with dark spot defects can also be repaired in the second region (see reference). Figure 2 (Referring to "DA2" in the second region DA2). In an implementation, for example, when two sub-pixels in the first row of the second region DA2 (or the second display area) have a dark spot fault, the light-emitting element (LED) of one of the two sub-pixels is electrically connected to a second non-display area (see reference). Figure 2 The third and fourth dummy pixels in the first row of “NDA2” (see reference) Figure 2The dummy pixel circuit of one of the "DP3" and "DP4" in the third dummy pixel and the dummy pixel circuit of the fourth dummy pixel DP4 can be electrically connected to the dummy pixel circuit of the remaining (other) dummy pixel. Therefore, the dark spot defect of two sub-pixels in a row (or a pixel row) in the second region DA2 can be repaired.

[0317] According to the above implementation, by simultaneously repairing the dark spot defects of two sub-pixels in a row (or a pixel row) of each of the first region DA1 (or the first display area) and the second region DA2 (or the second display area), the number of repairable sub-pixels for a horizontal time can be increased, thereby improving product yield.

[0318] Figure 29 This is used to illustrate the method of repairing bad sub-pixels. Figure 2 A partial diagram corresponding to EA1. Specifically, Figure 29 The electrical paths relative to dummy pixels and bad sub-pixels are shown. Figure 26 Modified implementation method.

[0319] Compared to Figure 29 To avoid redundancy, the implementation method described below will primarily focus on the differences from the implementation method described above.

[0320] refer to Figure 2 and Figure 29 In the first row R1, when the 11th pixel circuit PXC11 of the first sub-pixel SP1 and the 13th pixel circuit PXC13 of the third sub-pixel SP3 are defective, the light-emitting element LED of the first sub-pixel SP1 (hereinafter also referred to as the "first light-emitting element") is electrically connected to the first dummy pixel DP1 arranged in the first row R1, and the light-emitting element LED of the third sub-pixel SP3 (hereinafter also referred to as the "second light-emitting element") is electrically connected to the second dummy pixel DP2 arranged in the first row R1. The first dummy pixel circuit DPC1 of the first dummy pixel DP1 can be electrically connected to the second repair line RPL2, and the second dummy pixel circuit DPC2 of the second dummy pixel DP2 can be electrically connected to the first repair line RPL1.

[0321] More specifically, the electrical connection between the first light-emitting element (LED) and the 11th pixel circuit PXC11 is released in one configuration, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 of the first sub-pixel SP1 and the second bridging pattern BRP2 to electrically connect the first light-emitting element (LED) to the second repair line RPL2 connected to the second bridging pattern BRP2, so that the first light-emitting element (LED) can be electrically connected to the first dummy pixel circuit DPC1 of the first dummy pixel DP1. Based on the first contact hole CH1, the contact hole CH (or the second contact hole CH2) can be disposed on the left side of the first contact hole CH1 of the first sub-pixel SP1.

[0322] Furthermore, the electrical connection between the second light-emitting element (LED) and some configurations of the 13th pixel circuit PXC13 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 and the first bridging pattern BRP1 of the third sub-pixel SP3 to electrically connect the second light-emitting element (LED) to the first repair line RPL1 connected to the first bridging pattern BRP1, so that the second light-emitting element (LED) can be electrically connected to the second dummy pixel circuit DPC2 of the second dummy pixel DP2. Based on the first contact hole CH1 of the third sub-pixel SP3, the contact hole CH (or the second contact hole CH2) can be disposed on the right side of the first contact hole CH1.

[0323] As described above, the second repair line RPL2 forms an electrical path from the first dummy pixel DP1 to the first light-emitting element LED of the first sub-pixel SP1 with a dark spot defect, and the first repair line RPL1 forms an electrical path from the second dummy pixel DP2 to the second light-emitting element LED of the third sub-pixel SP3 with a dark spot defect. Therefore, signal delay caused by the difference in electrical paths between the dummy pixel and the sub-pixel with the dark spot defect can be reduced or prevented. In other words, signal delay caused by the difference in length between the first repair line RPL1 and the second repair line RPL2 that electrically connects the dummy pixel and the defective sub-pixel can be reduced or prevented.

[0324] Figure 30 Is with Figure 2 A schematic diagram of an implementation of a region of the display device corresponding to part of EA1.

[0325] about Figure 30 To avoid redundancy, the implementation method described below will primarily focus on the differences from the implementation method described above.

[0326] refer to Figure 2 and Figure 30 In the first region DA1 (or the first display region), sub-pixels in the first row R1 (refer to...) Figure 2A bridging pattern BRP is arranged between the sub-pixel SP in the first row R1 and the second sub-pixel SP2 in the second row R2, between the second sub-pixel SP2 in the first row R1 and the second sub-pixel SP2 in the second row R2, and between the third sub-pixel SP3 in the first row R1 and the third sub-pixel SP3 in the second row R2.

[0327] In each of the first pixel columns PC1 to the third pixel columns PC3, one end of the bridging pattern BRP may overlap with some configuration of the sub-pixel SP of the first row R1 (e.g., the first contact electrode CNE1), and the opposite end of the bridging pattern BRP may overlap with some configuration of the sub-pixel SP of the second row R2 (e.g., the first contact electrode CNE1).

[0328] In the first pixel column PC1, the bridging pattern BRP may be integral with the first repair line RPL1 and electrically and / or physically connected to the first repair line RPL1. In the second pixel column PC2, the bridging pattern BRP may be integral with the second repair line RPL2 and electrically and / or physically connected to the second repair line RPL2. In the third pixel column PC3, the bridging pattern BRP may be integral with the first repair line RPL1 and electrically and / or physically connected to the first repair line RPL1. However, the electrical connection between the bridging pattern BRP and the repair line RPL in each pixel column is not limited to the above-described embodiments.

[0329] Figure 31 Is with Figure 2 The diagram corresponding to part EA1 illustrates a method for repairing bad sub-pixels.

[0330] Compared to Figure 31 To avoid redundancy, the implementation method described below will primarily focus on the differences from the implementation method described above.

[0331] refer to Figure 2 , Figure 30 and Figure 31When the 11th pixel circuit PXC11 of the first sub-pixel SP1 and the 12th pixel circuit PXC12 of the second sub-pixel SP2 in the first row R1 are defective, the light-emitting element LED of the first sub-pixel SP1 (hereinafter also referred to as the "first light-emitting element") is electrically connected to the second dummy pixel DP2 (or the second dummy pixel circuit DPC2) arranged in the first row R1, and the light-emitting element LED of the second sub-pixel SP2 (hereinafter also referred to as the "second light-emitting element") is electrically connected to the first dummy pixel DP1 (or the first dummy pixel circuit DPC1) arranged in the first row R1. The first dummy pixel circuit DPC1 may be electrically connected to the second repair line RPL2, and the second dummy pixel circuit DPC2 may be electrically connected to the first repair line RPL1.

[0332] More specifically, the electrical connection between the first light-emitting element (LED) and some configurations of the 11th pixel circuit PXC11 is released, and a contact hole CH (or a second contact hole CH2) is formed between one end of the bridging pattern BRP disposed in the first pixel column PC1 and the first contact electrode CNE1 of the first sub-pixel SP1, thereby electrically connecting the first light-emitting element (LED) and the first repair line RPL1 connected to the bridging pattern BRP, so that the first light-emitting element (LED) and the second dummy pixel DP2 of the second dummy pixel circuit DPC2 can be electrically connected. Therefore, an electrical path from the second dummy pixel DP2 to the first sub-pixel SP1 is formed through the first repair line RPL1, so that the first light-emitting element (LED) can operate normally and the first sub-pixel SP1 with dark spot defects can be repaired. Subsequently, the portion of the first repair line RPL1 between the second sub-pixel SP2 and the third sub-pixel SP3 in the first row R1 is removed to electrically disconnect the bridging pattern BRP disposed in the third pixel column PC3 from the first repair line RPL1 connected to the first light-emitting element (LED). The first repair line RPL1, which is electrically disconnected from the first light-emitting element LED and connected to the bridging pattern BRP arranged in the third pixel column PC3, can be electrically connected as shown in the reference. Figure 3 The second initialization power supply voltage Vint2 described is applied to its fourth electric field line (reference). Figure 3 "PL4" (or the fifth wiring line (see reference)) Figure 7 (WL5 in the text).

[0333] Furthermore, the electrical connection between the second light-emitting element (LED) and some configurations of the twelfth pixel circuit PXC12 is released, and a contact hole CH (or a second contact hole CH2) is formed between one end of the bridging pattern BRP disposed in the second pixel column PC2 and the first contact electrode CNE1 of the second sub-pixel SP2 to electrically connect the second light-emitting element (LED) and the second repair line RPL2 connected to the bridging pattern BRP, so that the second light-emitting element (LED) and the first dummy pixel circuit DPC1 of the first sub-pixel SP1 can be electrically connected. Therefore, an electrical path from the first dummy pixel DP1 of the second sub-pixel SP2 to the second light-emitting element (LED) is formed through the second repair line RPL2, so that the second light-emitting element (LED) can operate normally and the second sub-pixel SP2 with dark spot faults can be repaired.

[0334] Figure 32 This is a schematic block diagram illustrating an embodiment of the electronic device 1000. Figure 33 It is shown that Figure 32 The electronic device 1000 is a schematic diagram illustrating an implementation of a smartphone. Figure 34 It is shown that Figure 32 The electronic device 1000 is a schematic diagram of an implementation of a tablet PC.

[0335] refer to Figures 32 to 34 Electronic device 1000 may include processor 1010, memory device 1020, storage device 1030, input / output (“I / O”) device 1040, power supply 1050, and display device 1060. Display device 1060 may be… Figure 1 and Figure 2 The display device DD. Electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, or other systems. In embodiments, such as Figure 33 As shown, the electronic device 1000 can be a smartphone. In an implementation, as... Figure 34 As shown, electronic device 1000 may be a tablet computer. However, the foregoing example is exemplary, and electronic device 1000 is not necessarily limited to the foregoing example. In implementations, for example, electronic device 1000 may be a cellular phone, video phone, smartboard, smartwatch, navigation device for a vehicle, computer monitor, laptop computer, head-mounted display device, etc.

[0336] Processor 1010 can perform predetermined calculations or tasks. In embodiments, processor 1010 may be a microprocessor, central processing unit, application processor, etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In embodiments, processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (“PCI”) bus.

[0337] The memory device 1020 can store data required for performing operations of the electronic device 1000. In embodiments, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (“EPROM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory devices, phase-change random access memory (“PRAM”), resistive random access memory (“RRAM”), nanofloating gate memory (“NFGM”), polymer random access memory (“PoRAM”), magnetic random access memory (“MRAM”), and ferroelectric random access memory (“FRAM”) devices, and / or volatile memory devices such as dynamic random access memory (“DRAM”), static random access memory (“SRAM”), and mobile DRAM devices.

[0338] Storage device 1030 may include solid-state drives (“SSDs”), hard disk drives (“HDDs”), optical disc read-only memory (“CD-ROMs”), etc.

[0339] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touchscreen, and mouse, as well as output devices such as speakers and printers. In one embodiment, display device 1060 may be included in I / O device 1040.

[0340] The power supply 1050 can provide the power required to perform the operation of the electronic device 1000. In an embodiment, for example, the power supply 1050 may include a power management integrated circuit (“PMIC”).

[0341] Display device 1060 can display images in response to control signals or data from processor 1010. Display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but this disclosure is not limited to these. Display device 1060 can be connected to other components via a bus or other communication links.

[0342] The display device and its repair method described in the implementation can improve the reliability of the display device by easily repairing dark spot faults that occur simultaneously in four sub-pixels in a pixel row.

[0343] By implementing the method, product yield can be improved by increasing the number of repairable subpixels.

[0344] Furthermore, in the embodiments, an electronic device including the above-described display device may be provided.

[0345] The effects of this disclosure are not limited to the foregoing, and various other effects are anticipated herein.

Claims

1. A display device, comprising: A substrate, wherein a display area comprising a first region and a second region and a non-display area surrounding one side of the display area are defined; Sub-pixels are arranged in the display area; Dummy pixels are arranged in the non-display area, and the dummy pixels include: A first dummy pixel and a second dummy pixel, each of the first dummy pixel and the second dummy pixel comprising: Virtual pixel circuit; and A first capacitor is electrically connected to the dummy pixel circuit; and A repair line, provided together to the display area and the non-display area, and extending in a first direction, the repair line includes: A first repair line and a second repair line are arranged in the first region between the first pixel row and the second pixel row of the substrate. Wherein, the first dummy pixel and the second dummy pixel are arranged in each of the first pixel row and the second pixel row, and The first capacitor of each of the first dummy pixel and the second dummy pixel is disposed between the dummy pixel circuit of the first dummy pixel and the dummy pixel circuit of the second dummy pixel.

2. The display device according to claim 1, wherein, The first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel are configured as a single entity, and The first dummy pixel and the second dummy pixel share the first capacitor.

3. The display device according to claim 2, wherein, The first repair line and the second repair line extend in the first direction, are spaced apart from each other in a second direction that intersects the first direction, and are electrically insulated from each other.

4. The display device according to claim 3, further comprising: A first bridging pattern extends in the second direction and is electrically connected to the first repair line; as well as The second bridging pattern extends in the second direction and is electrically connected to the second repair line.

5. The display device according to claim 4, wherein, The sub-pixels include: Transistors are disposed on the substrate; A light-emitting element, electrically connected to the transistor and emitting light; and The contact electrode electrically connects the light-emitting element and the transistor.

6. The display device according to claim 5, wherein, The contact electrode is disposed on the semiconductor pattern of the transistor, and an insulating layer is inserted between the contact electrode and the semiconductor pattern of the transistor, and the contact electrode is electrically connected to the semiconductor pattern of the transistor through a first contact hole passing through the insulating layer.

7. The display device according to claim 6, wherein, In the plan view, based on the first contact hole, the first bridging pattern is disposed on one side of the first contact hole, and the second bridging pattern is disposed on the opposite side of the first contact hole that is opposite to the side of the first contact hole.

8. The display device according to claim 6, wherein, In the plan view, based on the first contact hole, the first bridging pattern and the second bridging pattern are disposed on one side of the first contact hole.

9. The display device according to claim 6, wherein, The contact electrode overlaps with the first bridging pattern and the second bridging pattern, and The contact electrode, the first bridging pattern, and the second bridging pattern are electrically insulated from each other.

10. The display device according to claim 3, wherein, The first dummy pixel is electrically connected to one of the first repair line and the second repair line, and The second dummy pixel is electrically connected to the remaining repair lines in the first repair line and the second repair line.

11. The display device according to claim 3, wherein, The sub-pixel includes pixel circuitry, and In this context, the pixel circuits of two sub-pixels in the first region that face each other in the second direction and have the first repair line and the second repair line inserted between them are mirror-symmetrical with respect to each other.

12. The display device according to claim 3, wherein, The sub-pixel includes a transistor disposed on the substrate, a light-emitting element electrically connected to the transistor and emitting light, and a contact electrode electrically connected to the light-emitting element and the transistor. The display device further includes a bridging pattern disposed between the sub-pixels arranged in the first pixel row and the sub-pixels arranged in the second pixel row, and the bridging pattern is connected to corresponding repair lines in the first repair line and the second repair line. Wherein, the contact electrode of the sub-pixel arranged in the first pixel row overlaps with one end of the bridging pattern, and The contact electrode of the sub-pixel arranged in the second pixel row overlaps with the other end of the bridging pattern opposite to one end of the bridging pattern.

13. The display device according to claim 12, wherein, In each of the first pixel row and the second pixel row, the sub-pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged in the first direction. The bridging pattern disposed between the first sub-pixel arranged in the first pixel row and the first sub-pixel arranged in the second pixel row is connected to the first repair line. The bridging pattern disposed between the second sub-pixel arranged in the first pixel row and the second sub-pixel arranged in the second pixel row is connected to the second repair line, and The bridging pattern disposed between the third sub-pixel arranged in the first pixel row and the third sub-pixel arranged in the second pixel row is connected to the first repair line.

14. The display device according to claim 3, wherein, The non-display area includes a first non-display area adjacent to the first area and a second non-display area adjacent to the second area, and The first repair line and the second repair line are arranged in the first non-display area between the first dummy pixel and the second dummy pixel arranged in the first pixel row and between the first dummy pixel and the second dummy pixel arranged in the second pixel row.

15. A display device, comprising: A substrate, wherein a display area and a non-display area are defined on one side surrounding the display area; A sub-pixel is arranged in the display area and includes a transistor, a light-emitting element electrically connected to the transistor, and a contact electrode electrically connected to the light-emitting element and the transistor; The first repair line and the second repair line extend in a first direction and are arranged between the first pixel row and the second pixel row on the substrate. A first dummy pixel and a second dummy pixel are arranged in the non-display area and in each of the first pixel row and the second pixel row; as well as A first bridging pattern and a second bridging pattern are disposed between the first repair line and the second repair line and extend in a second direction intersecting the first direction. Wherein, the first bridging pattern is connected to the first repair line, and the second bridging pattern is connected to the second repair line. The contact electrode is disposed on the semiconductor pattern of the transistor, and an insulating layer is interposed between the contact electrode and the semiconductor pattern of the transistor. The contact electrode is electrically connected to the semiconductor pattern through a first contact hole passing through the insulating layer. Wherein, based on the first contact hole, the first bridging pattern is disposed on one side of the first contact hole, and the second bridging pattern is disposed on the opposite side of the first contact hole that is opposite to the side of the first contact hole.

16. The display device according to claim 15, wherein, The contact electrode overlaps with the first bridging pattern and the second bridging pattern, and The contact electrode, the first bridging pattern, and the second bridging pattern are electrically insulated from each other.

17. The display device according to claim 15, wherein, Each of the first dummy pixel and the second dummy pixel includes a dummy pixel circuit containing a first capacitor, and The dummy pixel circuit of the first dummy pixel and the dummy pixel circuit of the second dummy pixel share the first capacitor.

18. The display device according to claim 15, wherein, The first dummy pixel is electrically connected to one of the first repair line and the second repair line, and The second dummy pixel is electrically connected to the remaining repair lines in the first repair line and the second repair line.

19. An electronic device comprising: The processor provides input image data to the display device; as well as The display device displays an image based on the input image data. The display device includes: A substrate, wherein a display area comprising a first region and a second region and a non-display area surrounding one side of the display area are defined; Sub-pixels are arranged in the display area; Dummy pixels are arranged in the non-display area, the dummy pixels including a first dummy pixel and a second dummy pixel; and A repair line, provided together to the display area and the non-display area, and extending in a first direction, the repair line includes: A first repair line and a second repair line are arranged in the first region between the first pixel row and the second pixel row of the substrate. The first dummy pixel and the second dummy pixel are arranged in each of the first pixel row and the second pixel row. Each of the first dummy pixel and the second dummy pixel includes a dummy pixel circuit and a first capacitor electrically connected to the dummy pixel circuit. The first capacitor of each of the first dummy pixel and the second dummy pixel is disposed between the dummy pixel circuit of the first dummy pixel and the dummy pixel circuit of the second dummy pixel.

20. The electronic device according to claim 19, wherein, The first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel are configured as a single entity, and The first dummy pixel and the second dummy pixel share the first capacitor.

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