Display device, repair method thereof, and electronic device having display device

Abstract

The invention relates to a display device, a method of repairing the display device, and an electronic device including the display device. The display device includes: a substrate in which a display area including a first area and a second area and a non-display area surrounding at least one side of the display area are defined; sub-pixels arranged in the display area; dummy pixels arranged in the non-display area; and a repair line commonly disposed in the display area and the non-display area, and extending in the first direction. The non-display area includes a first non-display area adjacent to the first area and a second non-display area adjacent to the second area. The repair lines include a first repair line and a second repair line arranged between a first pixel row and a second pixel row of the substrate in the first region. Each of the first pixel row and the second pixel row extends in a first direction. The first repair line and the second repair line face each other in a second direction crossing the first direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0157061, filed on November 7, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present invention relate to a display device, a method for repairing a display device, and an electronic device including a display device. Background Technology

[0004] With the recent increase in interest in information display, research and development of display devices are underway. Summary of the Invention

[0005] This disclosure provides a display device, a repair method thereof, and an electronic device including the display device, which can improve reliability by preventing pixel dark spot failures.

[0006] Some embodiments of this disclosure include a display device comprising: a substrate defining a display area including a first region and a second region, and a non-display area surrounding at least one side of the display area; sub-pixels disposed in the display area; dummy pixels disposed in the non-display area; and repair lines commonly disposed in the display area and the non-display area, and extending in a first direction. The non-display area includes a first non-display area adjacent to the first region and a second non-display area adjacent to the second region. The repair lines include a first repair line and a second repair line disposed in the first region between a first pixel row and a second pixel row on the substrate. Each of the first pixel row and the second pixel row extends in the first direction. The first repair line and the second repair line face each other in a second direction intersecting the first direction.

[0007] According to some implementations, a dummy pixel may include a first dummy pixel and a second dummy pixel, which correspond to each arrangement in a first pixel row and a second pixel row in a first non-display area. The first dummy pixel and the second dummy pixel are arranged adjacent to each other in a first direction.

[0008] According to some implementations, the first dummy pixel may be electrically connected to one of the first repair line and the second repair line, and the second dummy pixel may be electrically connected to the other of the first repair line and the second repair line.

[0009] According to some implementations, the first repair wire and the second repair wire can be electrically insulated from each other.

[0010] According to some implementations, in the first non-display area, the first repair line and the second repair line may be arranged between the first dummy pixel and the second dummy pixel arranged corresponding to the first pixel row and the first dummy pixel and the second dummy pixel arranged corresponding to the second pixel row.

[0011] According to some implementations, there may be multiple sub-pixels, and each of the multiple sub-pixels may include pixel circuitry. The pixel circuitry of two sub-pixels facing each other in a second direction in a first region may be mirror-symmetrical with respect to each other, and a first repair line and a second repair line are located between the two sub-pixels.

[0012] According to some embodiments, the display device may further include: a plurality of first bridging patterns extending in a second direction and electrically connected to the first repair line; and a plurality of second bridging patterns extending in the second direction, electrically connected to the second repair line, and spaced apart from the plurality of first bridging patterns.

[0013] According to some embodiments, in the first region, a plurality of first bridging patterns are integrally formed with the first repair line and protrude from the first repair line in a direction toward the second repair line. In the first region, a plurality of second bridging patterns are integrally formed with the second repair line and protrude from the second repair line in a direction toward the first repair line.

[0014] According to some embodiments, the sub-pixel may further include: a light-emitting element electrically connected to the pixel circuit and used for emitting light; and a contact electrode electrically connected to the anode electrode of the light-emitting element. The contact electrode is electrically insulated from the first repair line and the second repair line.

[0015] According to some implementations, the contact electrode may overlap with a first bridging pattern and a second bridging pattern in a first region of a planar diagram.

[0016] According to some implementations, each of the first dummy pixel and the second dummy pixel may include a dummy pixel circuit. The dummy pixel circuits of two dummy pixels facing each other in a second direction in a first non-display area may be mirror-symmetrical with respect to each other, and a first repair line and a second repair line are located between the two dummy pixels.

[0017] According to some embodiments, the dummy pixel circuit may include a capacitor. The capacitor may include a first electrode and a second electrode disposed on the first electrode, with an insulating layer between the first and second electrodes. At least one of a first repair line and a second repair line may be disposed on the first and second electrodes.

[0018] According to some embodiments, each of the first dummy pixel and the second dummy pixel may further include a dummy anode electrode located in the non-display area and overlapping with the dummy pixel circuitry. The dummy anode electrode may be electrically connected to the anode electrode of a sub-pixel arranged in the display area adjacent to the non-display area.

[0019] According to some embodiments, the repair lines may further include third and fourth repair lines disposed in the second region between the first and second pixel rows. The dummy pixels also include third and fourth dummy pixels, which correspond to each arrangement in the first and second pixel rows in the second non-display region. The third and fourth repair lines may face each other in a second direction. The third and fourth dummy pixels may be disposed adjacent to each other in a first direction.

[0020] According to some implementations, the third dummy pixel may be electrically connected to one of the third and fourth repair lines, and the fourth dummy pixel may be electrically connected to the other of the third and fourth repair lines. The third and fourth repair lines may be electrically insulated from each other.

[0021] According to some implementations, the pixel circuits of two sub-pixels facing each other in the second direction in the second region can be mirror-symmetrical relative to each other, and the third repair line and the fourth repair line are between the two sub-pixels.

[0022] According to some embodiments, the display device may further include: a plurality of third bridging patterns extending in a second direction and electrically connected to a third repair line; and a plurality of fourth bridging patterns extending in the second direction, electrically connected to a fourth repair line, and spaced apart from the plurality of third bridging patterns. In the second region, the plurality of third bridging patterns are integrally formed with the third repair line and protrude from the third repair line in a direction toward the fourth repair line. In the second region, the plurality of fourth bridging patterns are integrally formed with the fourth repair line and protrude from the fourth repair line in a direction toward the third repair line.

[0023] Some embodiments of this disclosure include a display device that may include: a substrate defining a display area including a first region and a second region, and a non-display area surrounding at least one side of the display area; sub-pixels disposed in the display area and including pixel circuitry; dummy pixels disposed in the non-display area; and repair lines commonly disposed in the display area and the non-display area, and extending in a first direction. The non-display area includes a first non-display area surrounding one side of the first region and a second non-display area surrounding one side of the second region. The repair lines include: a first repair line and a second repair line disposed in the first region between a first pixel row and a second pixel row of the substrate; and a third repair line and a fourth repair line disposed in the second region between the first pixel row and the second pixel row of the substrate. Each of the first pixel row and the second pixel row extends in the first direction, and a plurality of sub-pixels are disposed, and each of the plurality of sub-pixels includes pixel circuitry. In the first region, the pixel circuitry of two sub-pixels facing each other in a second direction intersecting the first direction are mirror-symmetrical with respect to each other, and the first repair line and the second repair line are between the two sub-pixels. In the second region, the pixel circuits of two sub-pixels facing each other in the second direction are mirror symmetrical with respect to each other, and the third and fourth repair lines are between the two sub-pixels.

[0024] According to some embodiments, a dummy pixel may include: a first dummy pixel and a second dummy pixel, corresponding to each arrangement in the first pixel row and the second pixel row in a first non-display area; and a third dummy pixel and a fourth dummy pixel, corresponding to each arrangement in the first pixel row and the second pixel row in a second non-display area. The first dummy pixel may be electrically connected to one of the first repair line and the second repair line, and the second dummy pixel may be electrically connected to the other of the first repair line and the second repair line. The third dummy pixel may be electrically connected to one of the third repair line and the fourth repair line, and the fourth dummy pixel may be electrically connected to the other of the third repair line and the fourth repair line.

[0025] According to some implementations, the first repair wire and the second repair wire can be electrically insulated from each other, and the third repair wire and the fourth repair wire can be electrically insulated from each other.

[0026] According to some embodiments, the display device may further include: a plurality of first bridging patterns extending in a second direction and electrically connected to a first repair line; a plurality of second bridging patterns extending in a second direction, electrically connected to a second repair line, and spaced apart from the plurality of first bridging patterns; a plurality of third bridging patterns extending in a second direction and electrically connected to a third repair line; and a plurality of fourth bridging patterns extending in a second direction, electrically connected to a fourth repair line, and spaced apart from the plurality of third bridging patterns.

[0027] Some aspects of embodiments of this disclosure include a method for repairing a display device, the display device comprising: a substrate defining a display area including a first region and a second region, and a non-display area surrounding at least one side of each of the first region and the second region; a sub-pixel disposed in the display area and including pixel circuitry, a light-emitting element, and a contact electrode electrically connected to an anode electrode of the light-emitting element; a first repair line and a second repair line disposed in the display area between and spaced apart from each other from a first pixel row and a second pixel row; a dummy pixel including a first dummy pixel and a second dummy pixel disposed in the non-display area corresponding to each of the first pixel row and the second pixel row and respectively connected to the first repair line and the second repair line; a first bridging pattern electrically connected to the first repair line; and a second bridging pattern electrically connected to the second repair line. The method includes: separating a first defective pixel circuit arranged in a first pixel column of a first pixel row from a first light-emitting element corresponding to the first defective pixel circuit; electrically connecting the anode of the first light-emitting element to a dummy pixel circuit of a first dummy pixel by electrically connecting a contact electrode electrically connected to the anode electrode of the first light-emitting element to a corresponding first bridging pattern in a first bridging pattern; separating a second defective pixel circuit arranged in a third pixel column of the first pixel row from a second light-emitting element corresponding to the second defective pixel circuit; and electrically connecting the anode of the second light-emitting element to a dummy pixel circuit of a second dummy pixel by electrically connecting a contact electrode electrically connected to the anode electrode of the second light-emitting element to a corresponding second bridging pattern in a second bridging pattern.

[0028] According to some implementations, the first repair wire and the second repair wire can be electrically insulated from each other.

[0029] Some aspects of embodiments of this disclosure include an electronic device comprising: a processor for providing input image data to a display device; and a display device for displaying an image based on the input image data, wherein the display device comprises: a substrate defining a display area including a first region and a second region and a non-display area surrounding at least one side of the display area; subpixels disposed in the display area; dummy pixels disposed in the non-display area; and repair lines commonly disposed in the display area and the non-display area and extending in a first direction, wherein the non-display area includes a first non-display area adjacent to the first region and a second non-display area adjacent to the second region, wherein the repair lines include a first repair line and a second repair line disposed in the first region between a first pixel row and a second pixel row on the substrate, each of the first pixel row and the second pixel row extending in the first direction, and the first repair line and the second repair line facing each other in a second direction intersecting the first direction.

[0030] According to some implementations, a dummy pixel may include a first dummy pixel and a second dummy pixel, which correspond to each arrangement in a first pixel row and a second pixel row in a first non-display area, and the first dummy pixel may be electrically connected to one of a first repair line and a second repair line, and the second dummy pixel may be electrically connected to the other of the first repair line and the second repair line. Attached Figure Description

[0031] The above and other features of the embodiments of the present invention will become more apparent from the further detailed description of the embodiments of the present invention with reference to the accompanying drawings.

[0032] Figure 1 This is a schematic block diagram illustrating a display device according to one embodiment.

[0033] Figure 2 This is a schematic plan view showing a display device according to one embodiment.

[0034] Figure 3 It is shown Figure 2 A schematic diagram illustrating the implementation of one sub-pixel of a sub-pixel.

[0035] Figure 4 It is shown Figure 2 A schematic diagram illustrating an implementation of a virtual pixel in a set of virtual pixels.

[0036] Figure 5 It is shown Figure 2 A schematic plan view of an implementation of one pixel in a pixel.

[0037] Figure 6 It is along Figure 5 A schematic cross-sectional view taken by line I-I' in the diagram.

[0038] Figure 7 This is a schematic plan view showing sub-pixels arranged in a first row and a second row in a portion of a first area of ​​a display area of ​​a display device, according to one embodiment.

[0039] Figure 8 It only shows those included Figure 7 A schematic plan view of the arrangement of the first to seventh transistors and the first conductive layer.

[0040] Figure 9 It only shows those included Figure 7 A schematic plan view of the configuration in the second conductive layer.

[0041] Figure 10 It only shows those included Figure 7 A schematic plan view of the configuration in the third conductive layer.

[0042] Figure 11 It only shows those included Figure 7 A schematic plan view of the configuration in the fourth conductive layer.

[0043] Figure 12 It only shows those included Figure 7 A schematic plan view of the configuration in the fifth conductive layer.

[0044] Figure 13 This is a schematic plan view showing dummy pixels arranged in a first row and a second row in a first region located in a first non-display area of ​​a display device, according to one embodiment.

[0045] Figure 14 Is only shown Figure 13 A schematic plan view of the configuration of the first to sixth transistors, the eighth transistor, and the ninth transistor, and the first conductive layer.

[0046] Figure 15 It only shows those included Figure 13 A schematic plan view of the configuration in the second conductive layer.

[0047] Figure 16 It only shows those included Figure 13 A schematic plan view of the configuration in the third conductive layer.

[0048] Figure 17 It only shows those included Figure 13 A schematic plan view of the configuration in the fourth conductive layer.

[0049] Figure 18 It only shows those included Figure 13 A schematic plan view of the configuration in the fifth conductive layer.

[0050] Figure 19 According to one implementation method Figure 2 A schematic diagram of part of EA1 is used to illustrate sub-pixels in a first region and dummy pixels in a first non-display region of the display device.

[0051] Figure 20 This is a schematic flowchart illustrating a method for repairing a display device according to one embodiment.

[0052] Figure 21 It is used to show the repair and Figure 2 A schematic diagram of the method for dealing with bad sub-pixels corresponding to EA1.

[0053] Figure 22 It shows the arrangement in Figure 21A schematic circuit diagram of the electrical connection between the first sub-pixel and the second dummy pixel in the first row of the first group.

[0054] Figure 23 It is used to show the repair and Figure 2 A schematic diagram of the method for dealing with bad sub-pixels corresponding to EA1.

[0055] Figure 24 The corresponding display device according to one embodiment Figure 2 A schematic diagram of a region of EA1.

[0056] Figure 25 According to one implementation method Figure 2 A schematic diagram of part of EA2 is used to illustrate sub-pixels in the second region and dummy pixels in the second non-display region of the display device.

[0057] Figure 26 It is used to show the repair and Figure 2 A schematic diagram of the method for dealing with bad sub-pixels corresponding to EA2.

[0058] Figure 27 This is a schematic block diagram illustrating an electronic device according to an embodiment.

[0059] Figure 28 It is shown that Figure 27 The electronic device shown is a schematic diagram of an example of a smartphone.

[0060] Figure 29 It is shown that Figure 27 The electronic device is a schematic diagram of an example of a tablet PC. Detailed Implementation

[0061] The invention will now be described more fully with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0062] In describing the accompanying drawings, the same reference numerals are used for the same elements. In the drawings, the dimensions of structures are enlarged beyond their actual dimensions to clearly explain the invention. It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the scope of the invention. Similarly, a second element may also be referred to as a first element.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” will not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” or “containing” and / or “comprising” specify the presence of the described features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0064] In the following description, when the first part is “connected” to the second part, this includes not only the case where the first part is directly connected to the second part, but also the case where the third part is inserted between them and they are connected to each other.

[0065] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are intended to also include different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” to the other element will be oriented to be “up” to the other element. Thus, the term “down” can include both “down” and “up” orientations, depending on the specific orientation of the drawing. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other element will be oriented to be “above” the other element. Thus, the term “below” or “under” can include both “up” and “down” orientations.

[0066] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the same meaning as they have in the context of the relevant technology and this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0067] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0068] Figure 1This is a schematic block diagram illustrating a display device DD according to one embodiment.

[0069] refer to Figure 1 The display device DD may include a display panel PNL, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0070] The display panel PNL may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to the m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to the n-th data line DLn. Here, m and n are integers greater than 1.

[0071] Each of the subpixels SP can include at least one light-emitting element configured to generate light. Therefore, each of the subpixels SP can produce light of a specific color, such as red, green, blue, cyan, magenta, yellow, etc. Two or more subpixels SP can constitute a single pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form a single pixel PXL.

[0072] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signals GCS received from controller 150. Gate driver 120 can be arranged on one side of display panel PNL, but is not limited thereto.

[0073] In one implementation, first emission control lines EL1 to m-th emission control lines ELm connected to sub-pixels SP in the row direction may also be provided. Gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to m-th emission control lines ELm. The emission control driver may be operable under the control of controller 150.

[0074] The data driver 130 can be connected to sub-pixels SP arranged in the column direction via the first data line DL1 to the nth data line DLn. The data driver 130 can receive image data DATA and data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS.

[0075] The data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn by using a voltage from the voltage generator 140. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel PNL.

[0076] In one implementation, the gate driver 120 and the data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0077] Voltage generator 140 is operable in response to a voltage control signal VCS from controller 150. Voltage generator 140 can generate multiple voltages and supply the generated voltages to components of display device DD. For example, voltage generator 140 can receive an input voltage from outside display device DD, control the input voltage, and regulate the controlled voltage to generate multiple voltages.

[0078] Voltage generator 140 can generate a first power supply voltage ELVDD and a second power supply voltage ELVSS, and the generated first power supply voltage ELVDD and second power supply voltage ELVSS can be provided to sub-pixels SP. The first power supply voltage ELVDD can have a relatively high voltage level, and the second power supply voltage ELVSS can have a lower voltage level than the first power supply voltage ELVDD. In other embodiments, the first power supply voltage ELVDD or the second power supply voltage ELVSS can be provided to the display device DD by an external device.

[0079] Furthermore, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to sub-pixel SP. For example, a predetermined reference voltage can be applied to the first data lines DL1 to the nth data lines DLn during sensing operation to sense the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, and voltage generator 140 can generate a reference voltage.

[0080] The controller 150 can control various operations of the display device DD. The controller 150 can receive a control signal CTRL from an external source to control the input image data IMG and its display. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0081] The controller 150 can convert the input image data IMG into image data DATA suitable for use in a display device DD or a display panel PNL. In one embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to match the sub-pixels SP in the row unit.

[0082] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1 As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). The data driver 130, voltage generator 140, and controller 150 may be functionally distinct components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be provided as a separate component within the driver integrated circuit (DIC).

[0083] The display device DD may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature in its vicinity and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be arranged adjacent to the display panel PNL and / or the driver integrated circuit DIC.

[0084] The controller 150 can control various operations of the display device DD in response to the temperature data TEP. In one embodiment, the controller 150 can adjust the brightness of the image output from the display panel PNL in response to the temperature data TEP.

[0085] Figure 2 This is a schematic plan view showing a display device DD according to one embodiment. For convenience, Figure 2 The structure of the display area DA of the display device DD is schematically shown, for example, the structure of the display panel PNL provided in the display device DD. As used herein, a “plan view” is a view in the thickness direction (i.e., third direction DR3) of the display device DD (or substrate SUB).

[0086] refer to Figure 2 The display device DD (or display panel PNL) may include a substrate SUB and sub-pixels SP.

[0087] The display device DD can have various shapes, such as, but not limited to, a rectangular plate shape with two pairs of parallel sides. The implementation may be applicable when the display device DD is an electronic device having a display surface on at least one side, such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, notebook computer, workstation, server, PDA, portable multimedia player (PMP), MP3 player, medical device, camera, or wearable device.

[0088] The substrate SUB can include a transparent insulating material that allows light to pass through. The substrate SUB can be a rigid substrate or a flexible substrate.

[0089] The rigid substrate can be, for example, a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate.

[0090] The flexible substrate can be one of plastic substrates and film substrates, including polymeric organic materials. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0091] Subpixels SP can be arranged on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of subpixels SP is not limited to this. For example, subpixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, subpixels SP can be arranged in a pentiline pattern. ® Arrangement structure. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0092] Two or more sub-pixels SP can form a single pixel PXL.

[0093] One area of ​​the substrate SUB can be set as a display area DA in which sub-pixels SP are disposed, and the remaining area of ​​the substrate SUB can be set as a non-display area NDA.

[0094] In the non-display area NDA of the substrate SUB, components for controlling the sub-pixel SP can be arranged. For example, wiring associated with the sub-pixel SP (such as...) Figure 1 The first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn shown can be arranged in the non-display area NDA.

[0095] In an implementation, the display area DA may include a first area DA1 (or a first display area) and a second area DA2 (or a second display area) adjacent in the first direction DR1. The display area DA can be divided into a first area DA1 and a second area DA2 by dividing it equally around a center. When viewed in a plane, the first area DA1 may be located on the upper left, and the second area DA2 may be located on the upper right.

[0096] The non-display area NDA may include a first non-display area NDA1 surrounding at least one side of the first area DA1 and a second non-display area NDA2 surrounding at least one side of the second area DA2.

[0097] In each of the first non-display area NDA1 and the second non-display area NDA2, two dummy pixels DP corresponding to each pixel row can be arranged. For example, the non-display area NDA can have two dummy pixels DP corresponding to each pixel row. The dummy pixels DP may include a first dummy pixel DP1 and a second dummy pixel DP2 arranged in the first non-display area NDA1, and a third dummy pixel DP3 and a fourth dummy pixel DP4 arranged in the second non-display area NDA2.

[0098] The first dummy pixel DP1 and the second dummy pixel DP2 can be arranged adjacently in the first non-display area NDA1 along the first direction DR1. The third dummy pixel DP3 and the fourth dummy pixel DP4 can be arranged adjacently in the second non-display area NDA2 along the first direction DR1. The second dummy pixel DP2 can be arranged closer to the first region DA1 than the first dummy pixel DP1, and the third dummy pixel DP3 can be arranged closer to the second region DA2 than the fourth dummy pixel DP4, but this disclosure is not limited thereto. According to an embodiment, the first dummy pixel DP1 can be arranged closer to the first region DA1 than the second dummy pixel DP2, and the fourth dummy pixel DP4 can be arranged closer to the second region DA2 than the third dummy pixel DP3.

[0099] The pads (PDs) can be arranged on the substrate (SUB) within the non-display area (NDA). The pads (PDs) can be electrically connected to the sub-pixels (SPs) via wiring. For example, the pads (PDs) can be arranged as shown in the reference above. Figure 1 The first data line DL1 to the nth data line DLn are connected to the sub-pixel SP.

[0100] The pads PD can connect the display panel PNL to other components of the display device DD. In an embodiment, the voltages and signals required to operate the components included in the display panel PNL can be transmitted from the display device DD via the pads PD. Figure 1 The driver integrated circuit DIC is provided.

[0101] In one embodiment, the display device DD may include a repair line RPL that is disposed across a common area of ​​the display area DA and the non-display area NDA. The repair line RPL may include a first repair line RPL1, a second repair line RPL2, a third repair line RPL3, and a fourth repair line RPL4. The first repair line RPL1 and the second repair line RPL2 may be disposed across a common area of ​​the first area DA1 and the first non-display area NDA1. The third repair line RPL3 and the fourth repair line RPL4 may be disposed across a common area of ​​the second area DA2 and the second non-display area NDA2.

[0102] In the first region DA1, the first repair line RPL1 and the second repair line RPL2 can be arranged between two sub-pixels SP that face each other in the second direction DR2. In the first non-display region NDA1, the first repair line RPL1 and the second repair line RPL2 can be arranged between two first dummy pixels DP1 that face each other in the second direction DR2 and between two second dummy pixels DP2 that face each other in the second direction DR2.

[0103] In the second region DA2, the third repair line RPL3 and the fourth repair line RPL4 can be arranged between two sub-pixels SP that face each other in the second direction DR2. In the second non-display region NDA2, the third repair line RPL3 and the fourth repair line RPL4 can be arranged between two third dummy pixels DP3 that face each other in the second direction DR2 and between two fourth dummy pixels DP4 that face each other in the second direction DR2.

[0104] Figure 3 It is shown as Figure 2 A schematic diagram illustrating an implementation of a sub-pixel SPij in sub-pixel SP. For ease of description, Figure 3 The sub-pixel SPij is shown as being located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj.

[0105] refer to Figure 2 and Figure 3 Sub-pixels SPij can be arranged on the i-th horizontal line.

[0106] Subpixel SPij may include a light-emitting element LED and a pixel circuit PXC. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a storage capacitor Cst.

[0107] A first transistor T1 may be electrically connected between a first power line PL1 and the anode electrode AE ​​of a light-emitting element (LED). The first transistor T1 may include a gate electrode electrically connected to a first node N1. The first transistor T1 may control the amount of current (or drive current) flowing from the first power line PL1 through the LED to the third power line PL3 based on the voltage at the first node N1. A first power supply voltage ELVDD is provided to the first power line PL1, and a second power supply voltage ELVSS is provided to the third power line PL3. The first power supply voltage ELVDD may be set to a voltage higher than the second power supply voltage ELVSS.

[0108] The second transistor T2 can be electrically connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 can be connected to the 1i-th scan line S1i (or the first scan line). When the first scan signal GW[i] (e.g., a low-level first scan signal GW[i]) is provided to the 1i-th scan line S1i, the second transistor T2 can be turned on to electrically connect the j-th data line Dj and the second node N2. When each of the first transistor T1 and the third transistor T3 is in the on state, the second transistor T2 can transmit the data signal of the j-th data line Dj to the second node N2 in response to the first scan signal GW[i].

[0109] The third transistor T3 can be electrically connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 can be electrically connected to the first scan line S1i. When the first scan signal GW[i] is provided to the first scan line S1i, the third transistor T3 can be turned on. When the third transistor T3 is turned on, the first transistor T1 can be connected as a diode.

[0110] A fourth transistor T4 can be electrically connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 can be electrically connected to the 2i scan line S2i (the second scan line). A first initialization power supply voltage Vint1 can be provided to the second power line PL2. The fourth transistor T4 can be turned on by a second scan signal GI[i] provided to the 2i scan line S2i. When the fourth transistor T4 is turned on, the first initialization power supply voltage Vint1 can be provided to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0111] The fifth transistor T5 can be electrically connected between the first power line PL1 and the second node N2. The gate electrode of the fifth transistor T5 can be electrically connected to the i-th emitter control line Ei. The sixth transistor T6 can be electrically connected between the third node N3 and the light-emitting element LED (or the fourth node N4). The gate electrode of the sixth transistor T6 can be electrically connected to the i-th emitter control line Ei. When the emitter control signal EM[i] (e.g., a high-level emitter control signal EM[i]) is provided to the i-th emitter control line Ei, the fifth transistor T5 and the sixth transistor T6 can be turned off, and conversely, they can be turned on.

[0112] The seventh transistor T7 can be electrically connected between the anode electrode AE ​​(i.e., the fourth node N4) of the light-emitting element LED and the fourth power line PL4. The gate electrode of the seventh transistor T7 can be electrically connected to the 3i scan line S3i. A second initialization power supply voltage Vint2 can be provided to the fourth power line PL4. The seventh transistor T7 can be turned on by the third scan signal GB[i] provided to the 3i scan line S3i to provide the second initialization power supply voltage Vint2 to the anode electrode AE ​​of the light-emitting element LED. The second initialization power supply voltage Vint2 can be the same as, but is not limited to, the first initialization power supply voltage Vint1.

[0113] The storage capacitor Cst can be connected or formed between the first power line PL1 and the first node N1.

[0114] The light-emitting element (LED) may include an anode electrode AE ​​and a cathode electrode CE. The anode electrode AE ​​may be connected to a fourth node N4, and the cathode electrode CE may be connected to a third power line PL3. A second power supply voltage ELVSS may be provided to the cathode electrode CE of the LED. The LED may receive a drive current from a first transistor T1 and emit light.

[0115] In this implementation, the pixel circuit PXC may include P-type transistors. For example, the first transistor T1 to the seventh transistor T7 may include polysilicon transistors containing silicon semiconductors, and may include a polysilicon semiconductor layer as an active layer. For example, the active layer may be formed using a low-temperature polysilicon process (e.g., a low-temperature polysilicon (LTPS) process).

[0116] Figure 4 It is shown as Figure 2 A schematic diagram illustrating an implementation of a dummy pixel DPi1 in a dummy pixel DP. For ease of description, Figure 4 The dummy pixel DPi1 is shown on the i-th horizontal line (or i-th pixel row) located in the first non-display area and connected to the first dummy data line DD1.

[0117] refer to Figure 4For ease of description, overlapping descriptions with the above embodiments will be omitted.

[0118] refer to Figure 2 and Figure 4 The dummy pixel DPi1 can be arranged on the i-th horizontal line.

[0119] The dummy pixel DPi1 may include a dummy pixel circuit DPC. The dummy pixel circuit DPC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, and a ninth transistor T9, a storage capacitor Cst, and a first capacitor C1. In other words, except for the seventh transistor T7, the dummy pixel circuit DPC may include components related to the reference transistor. Figure 3 The pixel circuitry described is essentially the same configuration as that of the PXC.

[0120] The eighth transistor T8 can be electrically connected between the fourth node N4 and the connection node P1. The gate electrode of the eighth transistor T8 can be electrically connected to the i-th emission control line Ei. The first input / output terminal of the eighth transistor T8 can be electrically connected to the fourth node N4 (or the node electrically connected to the repair line RPL and the light-emitting element of the defective sub-pixel), and the second input / output terminal of the eighth transistor T8 can be electrically connected to the first capacitor C1 and the ninth transistor T9.

[0121] The ninth transistor T9 can be electrically connected between the eighth transistor T8 and the second power line PL2. The gate electrode of the ninth transistor T9 can be electrically connected to the 3i scan line S3i. The first input / output terminal of the ninth transistor T9 can be electrically connected to the connection node P1, and the second input / output terminal of the ninth transistor T9 can be electrically connected to the second power line PL2.

[0122] One terminal of the first capacitor C1 is connected to the connection node P1 (or between the second input / output terminal of the eighth transistor T8 and the first input / output terminal of the ninth transistor T9), and the other terminal of the first capacitor C1 can be electrically connected to the first power line PL1.

[0123] In the dummy pixel DPi1, the fourth node N4 can be electrically connected to the repair line RPL. When the sub-pixel SP of the display area DA fails, the wiring between the anode electrode of the light-emitting element of the defective sub-pixel and the sixth transistor T6 can be disconnected, and the anode electrode and the repair line RPL can be connected, allowing the light-emitting element of the defective sub-pixel to emit light normally. A detailed description of the repair method for the defective sub-pixel is described below.

[0124] Figure 5 It is shown Figure 2A schematic plan view of an implementation of a pixel PXL in pixel PXL.

[0125] refer to Figure 2 and Figure 5 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged on the first direction DR1.

[0126] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA surrounding the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA surrounding the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA surrounding the third emission region EMA3.

[0127] The first emission region EMA1 can be a light-emitting element corresponding to the first sub-pixel SP1 (see [link]). Figure 3 The second emission region EMA2 can be the region that emits light from the light-emitting element LED corresponding to the second sub-pixel SP2. The third emission region EMA3 can be the region that emits light from the light-emitting element LED corresponding to the third sub-pixel SP3.

[0128] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have substantially the same area, but are not limited thereto. In some embodiments, the second sub-pixel SP2 may have a larger area than the first sub-pixel SP1, and the third sub-pixel SP3 may have a larger area than the second sub-pixel SP2.

[0129] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have polygonal shapes. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have square or hexagonal shapes, but are not limited to these.

[0130] Figure 6 It is along Figure 5 A schematic cross-sectional view taken by line I-I' in the diagram.

[0131] exist Figure 6 For ease of description, the main cross-sectional or stacked structure of the display device DD based on the pixel PXL included in the display device DD is briefly shown, and the thickness direction of the substrate SUB is shown as the third direction DR3.

[0132] refer to Figure 5 and Figure 6 The display device DD may include one or more pixels PXL arranged in the display area DA.

[0133] Pixel PXL may include one or more subpixels SP. For example, pixel PXL may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. In an embodiment, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 may be a green subpixel, and the third subpixel SP3 may be a blue subpixel, but this disclosure is not limited thereto. Hereinafter, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 are collectively referred to as subpixels SP and / or multiple subpixels SP.

[0134] Each of the first sub-pixel SP1 to the third sub-pixel SP3 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a thin film encapsulation layer TFE, and a window WD.

[0135] The substrate SUB can include a transparent insulating material that allows light to pass through. The substrate SUB can be a rigid substrate or a flexible substrate.

[0136] The pixel circuit layer (PCL) of the sub-pixel SP can be disposed on the substrate SUB. One or more insulating layers can be disposed in the pixel circuit layer PCL. The insulating layers may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, a fifth insulating layer INS5, a sixth insulating layer INS6, and a seventh insulating layer INS7, which are sequentially stacked on the substrate SUB on the third-direction DR3. The insulating layers disposed in the pixel circuit layer PCL are not limited to the above embodiments, and other insulating layers may be added or some insulating layers may be omitted.

[0137] The first insulating layer INS1 can be disposed on the substrate SUB. The first insulating layer INS1 can prevent impurities from diffusing into the pixel circuitry (see [link]). Figure 3 In circuit elements (or driving elements) of “PXC”, for example, to prevent impurities from diffusing into transistors. The first insulating layer INS1 may be an inorganic layer comprising an inorganic material (or substance). The first insulating layer INS1 may include silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO) x At least one of the following. The first insulating layer INS1 can be a single layer, but it can also be a multilayer consisting of two or more layers. Depending on the material and process conditions of the substrate SUB, the first insulating layer INS1 can be omitted.

[0138] The second insulating layer INS2 may be disposed on the first insulating layer INS1. The second insulating layer INS2 may include the same material as the first insulating layer INS1, or may include suitable (or selected) materials listed as constituent materials of the first insulating layer INS1. For example, the second insulating layer INS2 may be an inorganic layer comprising inorganic materials.

[0139] The third insulating layer INS3 may be disposed on the second insulating layer INS2. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials listed as constituent materials of the first insulating layer INS1.

[0140] The fourth insulating layer INS4 can be disposed on the third insulating layer INS3. The fourth insulating layer INS4 can be an inorganic layer including inorganic materials or an organic layer including organic materials.

[0141] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4. The fifth insulating layer INS5 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials listed as constituent materials of the first insulating layer INS1.

[0142] The sixth insulating layer INS6 (or the first via layer) can be disposed on the fifth insulating layer INS5. The sixth insulating layer INS6 can be an inorganic layer comprising inorganic materials or an organic layer comprising organic materials. The inorganic layer can include, for example, silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO) x At least one of the following: . The organic layer may be, for example, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin. In an embodiment, the sixth insulating layer INS6 may be an organic layer comprising organic materials.

[0143] A seventh insulating layer INS7 (or a second via layer) may be disposed on a sixth insulating layer INS6. The seventh insulating layer INS7 may comprise the same material as the sixth insulating layer INS6, or may comprise one or more suitable (or selected) materials listed as constituent materials of the sixth insulating layer INS6. For example, the seventh insulating layer INS7 may be an organic layer comprising organic materials.

[0144] The pixel circuit layer (PCL) may include one or more conductive layers disposed between the aforementioned insulating layers. For example, the conductive layers may include a first conductive layer disposed between the second insulating layer INS2 and the third insulating layer INS3, a second conductive layer disposed between the third insulating layer INS3 and the fourth insulating layer INS4, a third conductive layer disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5, a fourth conductive layer disposed between the fifth insulating layer INS5 and the sixth insulating layer INS6, and a fifth conductive layer disposed between the sixth insulating layer INS6 and the seventh insulating layer INS7. However, the insulating and conductive layers are not limited to the above embodiments, and according to embodiments, other insulating and conductive layers besides the aforementioned insulating and conductive layers may also be disposed in the pixel circuit layer (PCL).

[0145] The pixel circuit layer (PCL) may include circuit elements (or driving elements) for each of the first sub-pixels SP1 to the third sub-pixels SP3. For example, the PCL may include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 is one of the transistors included in the pixel circuit PXC of the first sub-pixel SP1. Transistor T_SP2 for the second sub-pixel SP2 is one of the transistors included in the pixel circuit PXC of the second sub-pixel SP2. Transistor T_SP3 for the third sub-pixel SP3 is one of the transistors included in the pixel circuit PXC of the third sub-pixel SP3. Figure 6 For clarity and simplicity, only one transistor of each sub-pixel SP is shown, and other circuit elements are omitted.

[0146] The transistor T_SP1 of the first sub-pixel SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal EL1, and a second terminal EL2.

[0147] The gate electrode GE can be disposed on the second insulating layer INS2 and covered by the third insulating layer INS3. For example, the gate electrode GE can be a first conductive layer (or a first gate conductive layer) located between the second insulating layer INS2 and the third insulating layer INS3. In a plan view, the gate electrode GE can overlap with a portion of the semiconductor pattern SCP. For example, the gate electrode GE can overlap with the active pattern of the semiconductor pattern SCP.

[0148] The pixel circuit layer PCL may include a first pattern PT1 disposed between a third insulating layer INS3 and a fourth insulating layer INS4. The first pattern PT1 may include a second conductive layer (or a second gate conductive layer). According to an embodiment, in a plan view, the first pattern PT1 may overlap with the gate electrode GE, and the third insulating layer INS3 is interposed between them to form a capacitor. Furthermore, the pixel circuit layer PCL may include a second pattern PT2 disposed between a fourth insulating layer INS4 and a fifth insulating layer INS5. The second pattern PT2 may include a third conductive layer (or a third gate conductive layer). According to an embodiment, the second pattern PT2 can be used as a signal line electrically connected to a transistor, a connection device, etc.

[0149] A semiconductor pattern SCP can be disposed on a first insulating layer INS1 and covered by a second insulating layer INS2. The semiconductor pattern SCP can be a semiconductor layer including polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The semiconductor pattern SCP can include an active pattern, a first contact region, and a second contact region. The active pattern, the first contact region, and the second contact region can include undoped semiconductor layers or doped semiconductor layers. For example, the first contact region and the second contact region can include doped semiconductor layers, and the active pattern can be a region doped at a lower concentration than the first contact region and the second contact region. Therefore, the conductivity of the first contact region and the second contact region can be greater than the conductivity of the active pattern. The first contact region and the second contact region can be the source / drain region (or source electrode / drain electrode) of the transistor T_SP1 of the first sub-pixel SP1.

[0150] The active pattern of the semiconductor pattern SCP can be the channel region of the transistor T_SP1 of the first sub-pixel SP1, which overlaps with the gate electrode GE in the planar view. A first contact region of the semiconductor pattern SCP can contact one end of the active pattern. The first contact region can be electrically connected to a first terminal EL1. A second contact region of the semiconductor pattern SCP can contact the other end of the active pattern. The second contact region can be electrically connected to a second terminal EL2.

[0151] The first terminal EL1 may be disposed on and / or formed on the fifth insulating layer INS5. For example, the first terminal EL1 may include a fourth conductive layer (or a first source-drain conductive layer) formed between the fifth insulating layer INS5 and the sixth insulating layer INS6. The first terminal EL1 may contact the first contact area of ​​the semiconductor pattern SCP through a contact hole passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0152] The second terminal EL2 may be disposed on and / or formed on the fifth insulating layer INS5. The second terminal EL2 may include a fourth conductive layer formed between the fifth insulating layer INS5 and the sixth insulating layer INS6. The second terminal EL2 may contact the second contact area of ​​the semiconductor pattern SCP through a contact hole passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0153] The second terminal EL2 can be electrically connected to the connection line CNL disposed on the sixth insulating layer INS6. The connection line CNL can be the fifth conductive layer (or the second source-drain conductive layer) disposed between the sixth insulating layer INS6 and the seventh insulating layer INS7.

[0154] According to the embodiment, the bottom metal pattern BML can be arranged on the underside of the transistor T_SP1 of the first sub-pixel SP1 as described above. The bottom metal pattern BML can be a dummy conductive layer located between the substrate SUB and the first insulating layer INS1.

[0155] Since the gate electrode GE, the first terminal EL1, and the second terminal EL2 are electrically connected to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be set as one of the transistors in the pixel circuit PXC that constitutes the first sub-pixel SP1.

[0156] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be configured to be substantially the same as the transistor T_SP1 of the first sub-pixel SP1.

[0157] As described above, the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0158] The display element layer (DPL) can be arranged on the pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements (see...). Figure 3 The light-emitting element (LED) in the text refers to the LED and the pixel definition layer (PDL). The LED may include an anode electrode, a light-emitting layer, and a cathode electrode (CE). The LED may be disposed in each of the first sub-pixels SP1 to SP3. Each of the first sub-pixels SP1 to SP3 may be equipped with a light-emitting element (LED). The LED disposed in the first sub-pixel SP1 may be a first light-emitting element LED1, the LED disposed in the second sub-pixel SP2 may be a second light-emitting element LED2, and the LED disposed in the third sub-pixel SP3 may be a third light-emitting element LED3.

[0159] The first anode electrode AE1 can be disposed on the pixel circuit layer PCL (or the seventh insulating layer INS7) of the first sub-pixel SP1, the second anode electrode AE2 can be disposed on the pixel circuit layer PCL of the second sub-pixel SP2, and the third anode electrode AE3 can be disposed on the pixel circuit layer PCL of the third sub-pixel SP3. Each of the first anode electrodes AE1 to the third anode electrode AE3 can be electrically connected to a circuit element disposed in the pixel circuit layer PCL through a via through the seventh insulating layer INS7. In one example, the first anode electrode AE1 is electrically connected to the transistor T_SP1 of the first sub-pixel SP1 through a first via VIH1 through the seventh insulating layer INS7, the second anode electrode AE2 is electrically connected to the transistor T_SP2 of the second sub-pixel SP2 through a second via VIH2 through the seventh insulating layer INS7, and the third anode electrode AE3 is electrically connected to the transistor T_SP3 of the third sub-pixel SP3 through a third via VIH3 through the seventh insulating layer INS7.

[0160] When viewed from a third party towards DR3, each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may have the same... Figure 5 The first emitting region EMA1, the second emitting region EMA2, and the third emitting region EMA3 each have similar shapes. For example, when viewed from a third party to DR3, the first anode electrode AE1 may have a shape similar to that of the first emitting region EMA1, the second anode electrode AE2 may have a shape similar to that of the second emitting region EMA2, and the third anode electrode AE3 may have a shape similar to that of the third emitting region EMA3. However, this disclosure is not limited thereto.

[0161] Each of the first anode electrodes AE1 to the third anode electrodes AE3 can be electrically connected to the corresponding pixel circuit PXC and receive a drive current. Each of the first anode electrodes AE1 to the third anode electrodes AE3 can be, but is not limited to, an opaque conductive material capable of reflecting light. According to an embodiment, the first anode electrodes AE1 to the third anode electrodes AE3 can include a transparent conductive material.

[0162] A pixel defining layer (PDL) may be located on first anode electrodes AE1 to third anode electrodes AE3. The PDL may include an opening OP exposing a portion of the first anode electrode AE1, a portion of the second anode electrode AE2, and a portion of the third anode electrode AE3. The PDL may be a structure that defines (or divides) the light-emitting region of each of the first sub-pixels SP1 to the third sub-pixels SP3. For example, the PDL may define a first emission region EMA1 of the first sub-pixel SP1, a second emission region EMA2 of the second sub-pixel SP2, and a third emission region EMA3 of the third sub-pixel SP3.

[0163] The pixel defining layer (PDL) may include an organic insulating layer comprising organic materials. Organic materials (or organic substances) may include, for example, acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, etc. According to embodiments, the pixel defining layer (PDL) may include a light-absorbing material, or a light-absorbing agent may be applied thereto, such that the pixel defining layer (PDL) can absorb light from an external source. For example, the pixel defining layer (PDL) may include a carbon-based black pigment. However, this disclosure is not limited thereto.

[0164] The first light-emitting layer EML1 can be disposed on the portion of the first anode electrode AE1 exposed by the opening OP in the pixel-defining layer PDL, the second light-emitting layer EML2 can be disposed on the portion of the second anode electrode AE2 exposed by another opening OP in the pixel-defining layer PDL, and the third light-emitting layer EML3 can be disposed on the portion of the third anode electrode AE3 exposed by another opening OP in the pixel-defining layer PDL. Each of the first light-emitting layers EML1 to the third light-emitting layers EML3 can have a multilayer structure including a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer.

[0165] The first emissive layer EML1 to the third emissive layer EML3 may include at least one of a light-emitting material that emits light of different colors according to the corresponding sub-pixel SP. For example, the first emissive layer EML1 may include at least one of a red light-emitting material, the second emissive layer EML2 may include at least one of a green light-emitting material, and the third emissive layer EML3 may include at least one of a blue light-emitting material. According to an embodiment, each of the first emissive layer EML1 to the third emissive layer EML3 may emit white light overall by stacking multiple light-emitting materials capable of producing light of different colors (such as red light, green light, blue light, etc.). A color filter may also be arranged on each of the first emissive layer EML1 to the third emissive layer EML3. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter.

[0166] The cathode electrode CE can be disposed on the first light-emitting layer EML1 to the third light-emitting layer EML3 and the pixel defining layer PDL. The cathode electrode CE can be commonly disposed on a common layer of the first sub-pixels SP1 to the third sub-pixels SP3. The cathode electrode CE can be disposed in the form of a plate spanning the entire area of ​​the display area DA. According to an embodiment, the cathode electrode CE can be used as a semi-reflective mirror that partially transmits and partially reflects light emitted from the respective light-emitting layer.

[0167] The cathode electrode CE can be a thin metal layer, thick enough to transmit light emitted from the corresponding light-emitting layer. The cathode electrode CE can comprise a metallic material with relatively small thickness or a transparent conductive material. In one embodiment, the cathode electrode CE can comprise at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode electrode CE can comprise at least one of magnesium, silver, and mixtures thereof. However, the material of the cathode electrode CE is not limited to the embodiments described above.

[0168] The portions of the first anode electrode AE1, the first light-emitting layer EML1, and the cathode electrode CE that overlap with the first anode electrode AE1 in a planar view can constitute the first light-emitting element LED1. The portions of the second anode electrode AE2, the second light-emitting layer EML2, and the cathode electrode CE that overlap with the second anode electrode AE2 in a planar view can constitute the second light-emitting element LED2. The portions of the third anode electrode AE3, the third light-emitting layer EML3, and the cathode electrode CE that overlap with the third anode electrode AE3 in a planar view can constitute the third light-emitting element LED3.

[0169] A thin-film encapsulation layer (TFE) can be disposed on the cathode electrode (CE). The TFE can cover the display element layer (DPL). The TFE can be configured to prevent oxygen and / or moisture from penetrating into the display element layer (DPL). In embodiments, the TFE can include a structure in which one or more inorganic layers are alternately stacked with one or more organic layers. For example, the inorganic layers can include silicon nitride, silicon oxide, or silicon oxynitride. For example, the organic layers can include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polystyrene resin, polyphenylene sulfide resin, or benzocyclobutene. However, the materials of the organic and inorganic layers of the TFE are not limited thereto.

[0170] The touch sensor layer TS can be disposed on the thin-film encapsulation layer TFE. Alternatively, the touch sensor layer TS can be disposed directly on the thin-film encapsulation layer TFE.

[0171] A touch sensor layer (TS) can be disposed on the surface of the display device (DD) on which the image is projected, and can receive touch input from the user. The touch sensor layer (TS) can recognize touch events on the display device (DD) through the user's hand, individual input units, etc. For example, the touch sensor layer (TS) can recognize touch events capacitively.

[0172] The window WD can be disposed on the touch sensor layer TS. The window WD can be a protective element disposed on top of the touch sensor layer TS to protect the configuration of the display device DD. The window WD can be glass or plastic. When the window WD includes glass, ultra-thin glass (UTG) with a thickness of 0.1 mm or less can be used to obtain flexibility. However, this disclosure is not limited thereto.

[0173] According to one embodiment, the display device DD may further include a polarizing layer POL disposed between the touch sensor layer TS and the window WD. The polarizing layer POL can be used to reduce external light reflection. The polarizing layer POL can be attached to the window WD using an optically transparent adhesive component or the like.

[0174] Figure 7 This is a schematic plan view showing sub-pixels arranged in a first row R1 and a second row R2 in a portion of a first region DA1 of the display area of ​​a display device, according to one embodiment. Figure 8 It only shows those included Figure 7 A schematic plan view of the first transistor T1 to the seventh transistor T7 and their arrangement in the first conductive layer. Figure 9 It only shows those included Figure 7 A schematic plan view of the configuration in the second conductive layer. Figure 10 It only shows those included Figure 7 A schematic plan view of the configuration in the third conductive layer. Figure 11 It only shows those included Figure 7 A schematic plan view of the configuration in the fourth conductive layer. Figure 12 It only shows those included Figure 7 A schematic plan view of the configuration in the fifth conductive layer.

[0175] The following is for reference. Figures 7 to 12 The differences from the above implementation are described to avoid redundancy.

[0176] refer to Figure 2 and Figures 7 to 12 Subpixels (see Figure 2The “SP” in the first region DA1 can be arranged in each of the first row R1 (or first pixel row) and the second row R2 (or second pixel row) in the same column on the second direction DR2. For example, the 11th sub-pixel SP11 (or first sub-pixel) can be arranged in the first row R1, and the 21st sub-pixel SP21 (or first sub-pixel) can be arranged in the second row R2. The 11th sub-pixel SP11 may include the 11th pixel circuit PXC11, and the 21st sub-pixel SP21 may include the 21st pixel circuit PXC21.

[0177] In one implementation, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 are arranged on the second direction DR2 and can face each other relative to the repair line RPL. For example, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 can be symmetrical to each other and substantially identical with respect to the repair line RPL. The 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 can be mirror symmetrical with respect to the repair line RPL.

[0178] Signal lines can be arranged in the first region DA1 where the 11th sub-pixel SP11 and the 21st sub-pixel SP21 are located. For example, the first wiring WL1 to the thirteenth wiring WL13 can be arranged in the first region DA1.

[0179] The first wiring WL1 may extend along the first direction DR1 and may include a second insulating layer (see [reference]). Figure 6 "INS2" in the text and the third insulating layer (see Figure 6 The first conductive layer between "INS3" and the first wiring WL1 can be as shown in the above reference. Figure 3 The second scan line S2i. A region of the first wiring WL1 may be the gate electrode (hereinafter referred to as the "fourth gate electrode") of the fourth transistor T4 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0180] The second wiring WL2 may extend along the first direction DR1 and be spaced apart from the first wiring WL1. The second wiring WL2 may include a first conductive layer. The second wiring WL2 may be as described above. Figure 3 The described first scan line S1i. One region of the second wiring WL2 may be the gate electrode (hereinafter referred to as "second gate electrode") of the second transistor T2 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21. Furthermore, another region of the second wiring WL2 may be the gate electrode (hereinafter referred to as "third gate electrode") of the third transistor T3 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0181] The third wiring WL3 may extend along the first direction DR1 and be spaced apart from the first wiring WL1 and the second wiring WL2. The third wiring WL3 may include a first conductive layer. The third wiring WL3 may be as shown in the reference. Figure 3 The i-th emission control line Ei is described. A region of the third wiring WL3 may be the gate electrode (hereinafter referred to as the "fifth gate electrode") of the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21. Furthermore, another region of the third wiring WL3 may be the gate electrode (hereinafter referred to as the "sixth gate electrode") of the sixth transistor T6 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0182] The fourth wiring WL4 may extend along the first direction DR1 and be spaced apart from the first wiring WL1 to the third wiring WL3. The fourth wiring WL4 may include a first conductive layer. The fourth wiring WL4 may be as shown in the reference. Figure 3 The 3i scan line S3i is described. A region of the fourth wiring WL4 may be the gate electrode (hereinafter referred to as the "seventh gate electrode") of the seventh transistor T7 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0183] The fifth wiring WL5 extends along the first direction DR1 and may include wiring disposed on the third insulation layer INS3 and the fourth insulation layer (see...). Figure 6 The second conductive layer between "INS4" and the fifth wiring WL5 can be a reference. Figure 3 The fourth power line described is PL4.

[0184] The sixth wiring WL6 extends along the first direction DR1 and may include wiring disposed on the fourth insulation layer INS4 and the fifth insulation layer (see...). Figure 6 The third conductive layer between "INS5" and the sixth wiring WL6 can be as shown in the reference. Figure 3 The second power line PL2 is described.

[0185] The seventh wiring WL7 extends along the first direction DR1 and may include wiring arranged on the fifth insulation layer INS5 and the sixth insulation layer (see...). Figure 6 The fourth conductive layer between "INS6" in the diagram. The seventh wiring WL7 may be, but is not limited to, a dummy line overlapping the first wiring WL1, which includes the first conductive layer. According to an embodiment, the seventh wiring WL7 may be electrically connected to the first wiring WL1 to realize the first wiring WL1 as a dual structure.

[0186] The eighth wiring WL8 may extend in the first direction DR1 and be spaced apart from the seventh wiring WL7. The eighth wiring WL8 may include a fourth conductive layer. The eighth wiring WL8 may be a dummy line. In an embodiment, the eighth wiring WL8 may be electrically connected to the second wiring WL2, which includes a first conductive layer, thereby realizing the second wiring WL2 as a dual-structure.

[0187] The ninth wiring WL9 may extend along the first direction DR1 and be spaced apart from the seventh wiring WL7 and the eighth wiring WL8. The ninth wiring WL9 may include a fourth conductive layer. The ninth wiring WL9 may be as shown in the reference. Figure 3 The first electric line PL1 is described.

[0188] The tenth wiring WL10 may extend in the first direction DR1 and be spaced apart from the seventh wiring WL7 to the ninth wiring WL9. The tenth wiring WL10 may include a fourth conductive layer. The tenth wiring WL10 may be a dummy line overlapping the third wiring WL3, which includes a first conductive layer, in a plan view. According to an embodiment, the tenth wiring WL10 may be electrically connected to the third wiring WL3 to realize the third wiring WL3 as a dual structure.

[0189] The eleventh wiring WL11 may extend in the first direction DR1 and be spaced apart from the seventh wiring WL7 to the tenth wiring WL10. The eleventh wiring WL11 may include a fourth conductive layer. The eleventh wiring WL11 may be a dummy line overlapping with the fourth wiring WL4, which includes a first conductive layer. According to an embodiment, the eleventh wiring WL11 may be electrically connected to the fourth wiring WL4 through a corresponding contact hole CH to realize the fourth wiring WL4 as a dual structure.

[0190] The twelfth wiring WL12 may extend along a second direction DR2 that intersects with the first direction DR1, and may include wiring disposed on the sixth insulating layer INS6 and the seventh insulating layer (see...). Figure 6 The fifth conductive layer between "INS7" and the twelfth wiring WL12 can be as shown in the reference. Figure 3 The j-th data line Dj is described. The twelfth wiring WL12 can be electrically connected via the first conductive pattern CP1 to the second transistor T2 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0191] The first conductive pattern CP1 may include a fourth conductive layer. The first conductive pattern CP1 can be electrically connected to the twelfth wiring WL12 through a contact hole CH passing through the sixth insulating layer INS6. In addition, the first conductive pattern CP1 can be electrically connected to the semiconductor pattern SCP of the second transistor T2 in each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0192] The thirteenth wiring WL13 may extend in the second direction DR2 and may be spaced apart from the twelfth wiring WL12. The thirteenth wiring WL13 may include a fifth conductive layer. The thirteenth wiring WL13 may be electrically connected via a third conductive pattern CP3 to the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0193] The third conductive pattern CP3 may include a fourth conductive layer. The third conductive pattern CP3 can be electrically connected to the thirteenth wiring WL13 through a contact hole CH passing through the sixth insulating layer INS6. In addition, the third conductive pattern CP3 can be electrically connected to the semiconductor pattern SCP of the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 through contact holes CH sequentially passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0194] The thirteenth wiring, WL13, can be referenced as follows. Figure 3 The first power line PL1 is described. The thirteenth wiring WL13 can be a vertical power line of the first power line PL1, and the ninth wiring WL9 can be a horizontal power line of the first power line PL1. The ninth wiring WL9 and the thirteenth wiring WL13 can be electrically connected to each other to form a mesh structure of the first power line PL1.

[0195] The connection pattern CNP, including the same layer as the thirteenth wiring WL13 (e.g., the fifth conductive layer), can be arranged spaced apart from the thirteenth wiring WL13. The connection pattern CNP can be a reference. Figure 6 The described connection line CNL. The connection pattern CNP can be electrically connected to the corresponding anode electrode through the through-hole VIH passing through the seventh insulating layer INS7 (see...). Figure 3 (referring to "AE" in the original text). Furthermore, the connecting pattern CNP can be electrically connected to the fourth conductive pattern CP4 via the contact hole CH passing through the sixth insulating layer INS6.

[0196] The 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 can have substantially similar or identical structures. For example, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 can be mirror-symmetric based on an imaginary line VL extending in the first direction DR1 between the first row R1 and the second row R2. In the following description, for convenience, we will focus primarily on the 11th pixel circuit PXC11, and overlapping descriptions will be omitted.

[0197] The 11th pixel circuit PXC11 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0198] The first transistor T1 may include a first active pattern ACT1 and a first gate electrode GE1.

[0199] The first active pattern ACT1 can be the region of the semiconductor pattern SCP that overlaps with the first gate electrode GE1 in a planar view. The first active pattern ACT1 can be the channel region of the first transistor T1.

[0200] The region of the semiconductor pattern SCP that does not overlap with the first gate electrode GE1 and is connected to one side of the first active pattern ACT1 (e.g., the left side of the first active pattern ACT1 in a plan view) can be a first input / output terminal. The region of the semiconductor pattern SCP that does not overlap with the first gate electrode GE1 and is connected to the other side of the first active pattern ACT1 (e.g., the right side of the first active pattern ACT1 in a plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the first active pattern ACT1 and can be connected to the semiconductor pattern SCP of the second transistor T2 and the semiconductor pattern SCP of the fifth transistor T5. The second input / output terminal can be connected to the other side of the first active pattern ACT1 and can be connected to the semiconductor pattern SCP of the sixth transistor T6.

[0201] The first gate electrode GE1 overlaps with the first active pattern ACT1 in the plan view and may include a first conductive layer. The first gate electrode GE1 may be an island-shaped conductive pattern. The first gate electrode GE1 may be electrically connected to the third transistor T3 and the fourth transistor T4 through the second conductive pattern CP2.

[0202] The second conductive pattern CP2 may include a fourth conductive layer. One end of the second conductive pattern CP2 can be electrically connected to the first gate electrode GE1 through a contact hole CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer INS3. The other end of the second conductive pattern CP2 can be electrically connected to a region of the semiconductor pattern SCP shared by the third transistor T3 and the fourth transistor T4 through a contact hole CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0203] The second transistor T2 may include a second active pattern ACT2 and a second gate electrode.

[0204] The second active pattern ACT2 can be the region of the semiconductor pattern SCP that overlaps with the second wiring WL2. The second active pattern ACT2 can be the channel region of the second transistor T2.

[0205] The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring WL2 in the plan view and is connected to one side of the second active pattern ACT2 (e.g., the upper side of the second active pattern ACT2 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring WL2 in the plan view and is connected to the other side of the second active pattern ACT2 (e.g., the lower side of the second active pattern ACT2 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the second active pattern ACT2 and can be electrically connected to the first conductive pattern CP1. The first input / output terminal can be electrically connected to the twelfth wiring WL12 (or data line) through the first conductive pattern CP1. The second input / output terminal can be connected to the other side of the second active pattern ACT2 and can be connected to the first input / output terminal of the first transistor T1.

[0206] The second gate electrode can be the area of ​​the second wiring WL2 that overlaps with the second active pattern ACT2 in the plan view.

[0207] The third transistor T3 can be configured such that its sub-transistors are connected in series to prevent leakage current. For ease of description, the third transistor T3, which is formed on the protrusion of the second wiring WL2, is described above as a representative example.

[0208] The third transistor T3 may include a third active pattern ACT3 and a third gate electrode.

[0209] The third active pattern ACT3 is the region where the semiconductor pattern SCP overlaps with the protrusion protruding from the second wiring WL2 on the second direction DR2, and can form the channel region of the third transistor T3.

[0210] The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring WL2 in the plan view and is connected to one side of the third active pattern ACT3 (e.g., the right side of the third active pattern ACT3 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring WL2 in the plan view and is connected to the other side of the third active pattern ACT3 (e.g., the left side of the third active pattern ACT3 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the third active pattern ACT3 and can be electrically connected to the semiconductor pattern SCPs of the first transistor T1 and the sixth transistor T6. The second input / output terminal can be connected to the other side of the third active pattern ACT3 and is electrically connected to the semiconductor pattern SCP of the fourth transistor T4.

[0211] The third gate electrode can be the area of ​​the second wiring WL2 that overlaps with the third active pattern ACT3 in the planar diagram.

[0212] The fourth transistor T4 may be configured with sub-transistors connected in series to prevent leakage current. For ease of description, the fourth transistor T4, which is arranged closest to the third transistor T3 among the sub-transistors described above, is taken as a representative example.

[0213] The fourth transistor T4 may include a fourth active pattern ACT4 and a fourth gate electrode.

[0214] The fourth active pattern ACT4 is the region of the semiconductor pattern SCP that overlaps with the first wiring WL1, and can form the channel region of the fourth transistor T4.

[0215] The area of ​​the semiconductor pattern SCP that does not overlap with the first wiring WL1 and is connected to one side of the fourth active pattern ACT4 (e.g., the lower side of the fourth active pattern ACT4 in a plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the first wiring WL1 in a plan view and is connected to the other side of the fourth active pattern ACT4 (e.g., the upper side of the fourth active pattern ACT4 in a plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the fourth active pattern ACT4 and can be connected to the semiconductor pattern SCP of the third transistor T3. The second input / output terminal can be connected to the other side of the fourth active pattern ACT4 and electrically connected to the sixth wiring WL6 through the contact hole CH passing through the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0216] The fourth gate electrode can be the region of the first wiring WL1 that overlaps with the fourth active pattern ACT4.

[0217] The fifth transistor T5 may include a fifth active pattern ACT5 and a fifth gate electrode.

[0218] The fifth active pattern ACT5 is the area of ​​the semiconductor pattern SCP that overlaps with the third wiring WL3 in the planar diagram, and can form the channel region of the fifth transistor T5.

[0219] The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 in the plan view and is connected to one side of the fifth active pattern ACT5 (e.g., the lower side of the fifth active pattern ACT5 in the plan view may be the first input / output terminal). The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 in the plan view and is connected to the other side of the fifth active pattern ACT5 (e.g., the upper side of the fifth active pattern ACT5 in the plan view) may be the second input / output terminal. The first input / output terminal may be connected to one side of the fifth active pattern ACT5 and electrically connected to the first conductive pattern CP1 through a corresponding contact hole CH. The second input / output terminal may be connected to the other side of the fifth active pattern ACT5 and may be connected to the semiconductor pattern SCP of each of the first transistor T1 and the second transistor T2.

[0220] The fifth gate electrode can be the region of the third wiring WL3 that overlaps with the fifth active pattern ACT5.

[0221] The sixth transistor T6 may include a sixth active pattern ACT6 and a sixth gate electrode.

[0222] The sixth active pattern ACT6 is the region of the semiconductor pattern SCP that overlaps with the third wiring WL3 in the planar diagram, and may be the channel region of the sixth transistor T6.

[0223] The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 and is connected to one side of the sixth active pattern ACT6 (e.g., the upper side of the sixth active pattern ACT6 in a plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 and is connected to the other side of the sixth active pattern ACT6 (e.g., the lower side of the sixth active pattern ACT6 in a plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the sixth active pattern ACT6 and the semiconductor pattern SCP of the first transistor T1. The second input / output terminal can be connected to the other side of the sixth active pattern ACT6 and the semiconductor pattern SCP of the seventh transistor T7. Furthermore, the second input / output terminal can be electrically connected to the fourth conductive pattern CP4 through a corresponding contact hole CH.

[0224] The fourth conductive pattern CP4 may include a fourth conductive layer. The fourth conductive pattern CP4 can be electrically connected to the second input / output terminal of the sixth transistor T6 via contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the fourth conductive pattern CP4 can be electrically connected to the connection pattern CNP via corresponding contact holes CH.

[0225] The sixth gate electrode can be the area of ​​the third wiring WL3 that overlaps with the sixth active pattern ACT6 in the planar diagram.

[0226] The seventh transistor T7 may include a seventh active pattern ACT7 and a seventh gate electrode.

[0227] The seventh active pattern ACT7 is the region of the semiconductor pattern SCP that overlaps with the fourth wiring WL4, and can be the channel region of the seventh transistor T7.

[0228] The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring WL4 in the plan view and is connected to one side of the seventh active pattern ACT7 (e.g., the upper side of the seventh active pattern ACT7 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring WL4 in the plan view and is connected to the other side of the seventh active pattern ACT7 (e.g., the lower side of the seventh active pattern ACT7 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the seventh active pattern ACT7 and the semiconductor pattern SCP of the sixth transistor T6. The second input / output terminal can be connected to the other side of the seventh active pattern ACT7 and the fifth conductive pattern CP5.

[0229] The fifth conductive pattern CP5 may include a fourth conductive layer. The fifth conductive pattern CP5 can be electrically connected to the semiconductor pattern SCP of the seventh transistor T7 via contact holes CH that sequentially penetrate the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the fifth conductive pattern CP5 can be connected to the fifth wiring WL5 via contact holes CH that pass through the fifth insulating layer INS5 and the fourth insulating layer INS4.

[0230] The seventh gate electrode can be the region of the fourth wiring WL4 that overlaps with the seventh active pattern ACT7.

[0231] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE.

[0232] The lower electrode LE can be integrally formed with the first gate electrode GE1. The lower electrode LE may include a first conductive layer.

[0233] The upper electrode UE overlaps with the lower electrode LE in the plan view and may include a second conductive layer. The upper electrode UE may include an opening OPN by removing a portion of it. The area of ​​the lower electrode LE that overlaps with the upper electrode UE in the plan view may be exposed by the opening OPN. The upper electrode UE can be electrically connected to the thirteenth wiring WL13 via contact holes CH that sequentially penetrate the sixth insulating layer INS6, the fifth insulating layer INS5, and the fourth insulating layer INS4.

[0234] In the first region DA1, repair lines RPL can be arranged between the first row R1 and the second row R2. Repair lines RPL can include a first repair line RPL1 and a second repair line RPL2 spaced apart relative to an imaginary line VL extending in the first direction DR1. The first repair line RPL1 can be located above the imaginary line VL, and the second repair line RPL2 can be located below the imaginary line VL. The first repair line RPL1 and the second repair line RPL2 can be spaced apart from each other and can be electrically insulated from each other.

[0235] The first repair line RPL1 and the second repair line RPL2 may extend in the first direction DR1. The first repair line RPL1 and the second repair line RPL2 may include a third conductive layer. The first repair line RPL1 and the second repair line RPL2 may be formed using the same process as the sixth wiring WL6. The first repair line RPL1 and the second repair line RPL2 may be disposed in the same layer as the sixth wiring WL6 and may include the same material as the sixth wiring WL6.

[0236] The first repair line RPL1 may be electrically connected to the first bridging pattern BRP1. The first bridging pattern BRP1 may be integrally formed with the first repair line RPL1. The first bridging pattern BRP1 may extend in the second direction DR2 and may protrude from the first repair line RPL1 in a direction toward the second repair line RPL2 (or the second row R2). In an embodiment, the first repair line RPL1 may be electrically connected to a first non-display area arranged adjacent to the first region DA1 (see [link to relevant documentation]). Figure 2 The first and second dummy pixels in the first row R1 of “NDA1” (see Figure 2 One of "DP1 and DP2" in the list.

[0237] The second repair line RPL2 can be electrically connected to the second bridging pattern BRP2. The second bridging pattern BRP2 can be integrally formed with the second repair line RPL2. The second bridging pattern BRP2 can extend in the second direction DR2 and can protrude from the second repair line RPL2 in a direction toward the first repair line RPL1 or the first row R1. In an embodiment, the second repair line RPL2 can be electrically connected to another dummy pixel arranged between the first dummy pixel DP1 and the second dummy pixel DP2 in the first row R1 of the first non-display area NDA1.

[0238] The first bridging pattern BRP1 and the second bridging pattern BRP2 are spaced apart in the first direction DR1 and face each other. The first bridging pattern BRP1 and the second bridging pattern BRP2 can be electrically insulated from each other.

[0239] In the implementation, in the plan view, the first repair line RPL1, the first bridging pattern BRP1, and the second bridging pattern BRP2 can overlap with the fourth conductive pattern CP4 (or the first contact electrode CNE1) of the 11th sub-pixel SP11 (or the 11th pixel circuit PXC11). The first repair line RPL1, the first bridging pattern BRP1, and the second bridging pattern BRP2 can be electrically separated from the fourth conductive pattern CP4. In the plan view, the second repair line RPL2, the second bridging pattern BRP2, and the first bridging pattern BRP1 can overlap with the fourth conductive pattern CP4 (or the first contact electrode CNE1) of the 21st sub-pixel SP21 or the 21st pixel circuit PXC21. The second repair line RPL2, the second bridging pattern BRP2, and the first bridging pattern BRP1 can be electrically separated from the fourth conductive pattern CP4.

[0240] When a dark spot fault occurs in the 11th sub-pixel SP11, the semiconductor pattern SCP shared by the sixth transistor T6 and the seventh transistor T7 of the 11th sub-pixel SP11 can be disconnected from the light-emitting element (see [link]). Figure 3 The electrical connection between the anode electrode AE ​​of the "LED" in the 11th sub-pixel SP11 and the fourth conductive pattern CP4 (or the first contact electrode CNE1) and the first bridging pattern BRP1 of the 11th sub-pixel SP11 can be electrically connected to each other, so that the light-emitting element LED of the 11th sub-pixel SP11 can operate normally.

[0241] Figure 13 This is a schematic plan view showing dummy pixels arranged in a first row R1 and a second row R2 in a region of a first non-display area NDA1 of a display device, according to one embodiment. Figure 14 It only shows those included Figure 13 A schematic plan view of the configuration of the first transistor T1 to the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 in the first conductive layer. Figure 15 It only shows those included Figure 13 A schematic plan view of the configuration in the second conductive layer. Figure 16 It only shows those included Figure 13 A schematic plan view of the configuration in the third conductive layer. Figure 17 It only shows those included Figure 13 A schematic plan view of the configuration in the fourth conductive layer. Figure 18 It only shows those included Figure 13 A schematic plan view of the configuration in the fifth conductive layer.

[0242] Main reference Figures 13 to 18 To describe the differences from the above implementation, in order to avoid redundant description.

[0243] refer to Figure 2 , Figure 4 and Figures 13 to 18 dummy pixels (see) Figure 2 The "DP" in the first non-display area NDA1 can be arranged in each of the first row R1 and the second row R2 in the same column on the second direction DR2. For example, the 12th dummy pixel DP12 (or the second dummy pixel) can be arranged in the first row R1, and the 22nd dummy pixel DP22 (or the second dummy pixel) can be arranged in the second row R2. The 12th dummy pixel DP12 can be directly connected to the reference. Figure 7 The 11th sub-pixel SP11 is adjacent, and the 22nd dummy pixel DP22 can be directly connected to the reference. Figure 7 The 21st sub-pixel SP21 is adjacent to each other. The 12th dummy pixel DP12 and the 11th sub-pixel SP11 can be arranged in the first row R1, and the 22nd dummy pixel DP22 and the 21st sub-pixel SP21 can be arranged in the second row R2. The 12th dummy pixel DP12 may include the 12th dummy pixel circuit DPC12, and the 22nd dummy pixel DP22 may include the 22nd dummy pixel circuit DPC22.

[0244] In this embodiment, the 12th dummy pixel circuit DPC12 and the 22nd dummy pixel circuit DPC22 are arranged on the second direction DR2 and can face each other relative to the repair line RPL. For example, the 12th dummy pixel circuit DPC12 and the 22nd dummy pixel circuit DPC22 can be symmetrical to each other and substantially identical with respect to the repair line RPL. The 12th dummy pixel circuit DPC12 and the 22nd dummy pixel circuit DPC22 can be mirror symmetrical with respect to the repair line RPL.

[0245] Signal lines can be arranged in the first non-display area NDA1 where the 12th dummy pixel DP12 and the 22nd dummy pixel DP22 are located. For example, the first wiring WL1 to the eleventh wiring WL11 can be arranged in the first non-display area NDA1. The first wiring WL1 to the eleventh wiring WL11 can be as shown in the reference. Figures 7 to 12 The first wiring WL1 to the eleventh wiring WL11.

[0246] Furthermore, the first dummy line DML1 and the second dummy line DML2 can be arranged in the first non-display area NDA1.

[0247] The first dummy line DML1 extends in the second direction DR2 and may include a line arranged in... Figure 6 The sixth insulating layer (see Figure 6 The fifth conductive layer between “INS6” and the seventh insulating layer (see “INS7”). The first dummy line DML1 can be as shown in the reference. Figure 4 The first dummy data line DD1 is described.

[0248] The second dummy line DML2 may extend along the second direction DR2 and include a fifth conductive layer. The second dummy line DML2 may be as shown in the reference. Figures 7 to 12 The thirteenth wiring WL13 is described. The second dummy line DML2 can be electrically connected to the fifth transistor T5 of each of the 12th dummy pixel circuit DPC12 and the 22nd dummy pixel circuit DPC22 via the third conductive pattern CP3.

[0249] The 12th dummy pixel circuit DPC12 and the 22nd dummy pixel circuit DPC22 may have substantially similar or identical structures. For example, the 12th dummy pixel circuit DPC12 and the 22nd dummy pixel circuit DPC22 may be mirror-symmetrical with respect to an imaginary line VL extending in the first direction DR1 between the first row R1 and the second row R2. In the following description, for convenience, we will focus primarily on the 12th dummy pixel circuit DPC12, and overlapping descriptions will be omitted.

[0250] The 12th dummy pixel circuit DPC12 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, an eighth transistor T8, and a ninth transistor T9, a storage capacitor Cst, and a first capacitor C1. The first transistor T1 to the sixth transistor T6 are connected to a reference... Figures 7 to 12 The first transistor T1 through the sixth transistor T6 are the same as described, and therefore will not be described again here.

[0251] The eighth transistor T8 may include an eighth active pattern ACT8 and an eighth gate electrode.

[0252] The eighth active pattern ACT8 can be the region of the semiconductor pattern SCP that overlaps with the third wiring WL3 in the planar diagram. The eighth active pattern ACT8 can be the channel region of the eighth transistor T8.

[0253] The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 in the plan view and is connected to one side of the eighth active pattern ACT8 (e.g., the left side of the eighth active pattern ACT8 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 in the plan view and is connected to the other side of the eighth active pattern ACT8 (e.g., the right side of the eighth active pattern ACT8 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the eighth active pattern ACT8 and the sixth conductive pattern CP6. The second input / output terminal can be connected to the other side of the eighth active pattern ACT8 and the semiconductor pattern SCP of the ninth transistor T9.

[0254] The sixth conductive pattern CP6 may include the fourth conductive layer. The sixth conductive pattern CP6 can be transmitted through the fifth insulating layer (see...). Figure 6 "INS5" in the text), the fourth insulating layer (see Figure 6 "INS4" in the text), the third insulating layer (see Figure 6 "INS3" in the middle) and the second insulating layer (see Figure 6 The contact hole CH of “INS2” is electrically connected to the first input / output terminal of the eighth transistor T8. Furthermore, the sixth conductive pattern CP6 can be electrically connected to the first repair line RPL1 through the contact hole CH passing through the fifth insulating layer INS5.

[0255] The sixth conductive pattern CP6 can be electrically connected to the second lower electrode LE2 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer INS3. Furthermore, the sixth conductive pattern CP6 can be electrically connected to the semiconductor pattern SCP shared by the eighth transistor T8 and the ninth transistor T9 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0256] The eighth gate electrode can be the area of ​​the third wiring WL3 that overlaps with the eighth active pattern ACT8 in the planar diagram.

[0257] The ninth transistor T9 may include a ninth active pattern ACT9 and a ninth gate electrode.

[0258] The ninth active pattern ACT9 can be the region of the semiconductor pattern SCP that overlaps with the fourth wiring WL4. The ninth active pattern ACT9 can be the channel region of the ninth transistor T9.

[0259] The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring WL4 in the plan view and is connected to one side of the ninth active pattern ACT9 (e.g., the upper side of the ninth active pattern ACT9 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring WL4 in the plan view and is connected to the other side of the ninth active pattern ACT9 (e.g., the lower side of the ninth active pattern ACT9 in the plan view) can be a second input / output terminal. The first input / output terminal can be electrically connected to one side of the ninth active pattern ACT9 and the semiconductor pattern SCP of the eighth transistor T8. The second input / output terminal can be electrically connected to the other side of the ninth active pattern ACT9 and the seventh conductive pattern CP7.

[0260] The seventh conductive pattern CP7 may include a fourth conductive layer. The seventh conductive pattern CP7 can be electrically connected to the semiconductor pattern SCP of the ninth transistor T9 via contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the seventh conductive pattern CP7 can be electrically connected to the fifth wiring WL5 via contact holes CH passing through the fifth insulating layer INS5 and the fourth insulating layer INS4. The fifth wiring WL5 may be as described above. Figure 3 and Figure 4 The fourth power line PL4 (or the second power line PL2) is described above. The fifth wiring WL5 can be electrically connected to the area of ​​the semiconductor pattern SCP of the ninth transistor T9 (e.g., the second input / output terminal) via the seventh conductive pattern CP7.

[0261] The ninth gate electrode can be the area of ​​the fourth wiring WL4 that overlaps with the ninth active pattern ACT9 in the planar diagram.

[0262] The storage capacitor Cst may include a first lower electrode LE1 and a first upper electrode UE1. The storage capacitor Cst may be connected to a reference electrode. Figures 7 to 12 The storage capacitor Cst described is the same. The first lower electrode LE1 can be as referenced. Figures 7 to 12 The lower electrode LE, and the first upper electrode UE1, can be as referenced. Figures 7 to 12 The aforementioned upper electrode UE.

[0263] By removing a first portion of the first upper electrode UE1, the first upper electrode UE1 may include a first opening OPN1. A region of the first lower electrode LE1 that overlaps with the first upper electrode UE1 in a plan view may be exposed by the first opening OPN1. The first upper electrode UE1 may be electrically connected to the second dummy line DML2 through a contact hole CH passing through the sixth insulating layer INS6, the fifth insulating layer INS5, and the fourth insulating layer INS4.

[0264] The first capacitor C1 may include a second lower electrode LE2 and a second upper electrode UE2.

[0265] The second lower electrode LE2 may be spaced apart from the first lower electrode LE1. The second lower electrode LE2 may include a first conductive layer. For example, the second lower electrode LE2 may be formed using the same process as the first lower electrode LE1 (or the first gate electrode GE1), may be disposed in the same layer as the first lower electrode LE1, and may include the same material as the first lower electrode LE1. The second lower electrode LE2 may be electrically connected to the semiconductor pattern SCP shared by the eighth transistor T8 and the ninth transistor T9 via the sixth conductive pattern CP6.

[0266] The second upper electrode UE2 may overlap with the second lower electrode LE2 and may include a second conductive layer. By removing a portion of the second upper electrode UE2, the second upper electrode UE2 may include a second opening OPN2. A region of the second lower electrode LE2 that overlaps with the second upper electrode UE2 in a plan view may be exposed by the second opening OPN2. The second upper electrode UE2 may be integrally formed with the first upper electrode UE1 and electrically connected to the second dummy line DML2.

[0267] In the first non-display area NDA1, a repair line RPL can be arranged between the first row R1 and the second row R2. The repair line RPL can include a first repair line RPL1 and a second repair line RPL2 spaced apart relative to an imaginary line VL extending in the first direction DR1. The first repair line RPL1 can be positioned above the imaginary line VL, and the second repair line RPL2 can be positioned below the imaginary line VL. The first repair line RPL1 and the second repair line RPL2 can be spaced apart from each other and can be electrically insulated from each other.

[0268] The first repair line RPL1 and the second repair line RPL2 may include a third conductive layer disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5. The first repair line RPL1 and the second repair line RPL2 may be related to a reference... Figures 7 to 12 The first repair line RPL1 and the second repair line RPL2 are the same. In other words, the first repair line RPL1 and the second repair line RPL2 can be common lines commonly set in the first non-display area NDA1 and the first area DA1.

[0269] The first repair line RPL1 may be electrically connected to the first bridging pattern BRP1. The first bridging pattern BRP1 may be integrally formed with the first repair line RPL1. The first bridging pattern BRP1 may extend in the second direction DR2 and may protrude from the first repair line RPL1 in the direction toward the second repair line RPL2. In an embodiment, the first repair line RPL1 may be electrically connected to the sixth conductive pattern CP6.

[0270] The second repair line RPL2 can be electrically connected to the second bridging pattern BRP2. The second bridging pattern BRP2 can be integrally formed with the second repair line RPL2. The second bridging pattern BRP2 can extend in the second direction DR2 and can protrude from the second repair line RPL2 in the direction toward the first repair line RPL1. In an embodiment, the second repair line RPL2 can be electrically connected to the sixth conductive pattern CP6 of the 22nd dummy pixel circuit DPC22 (or the 22nd dummy pixel DP22).

[0271] The first bridging pattern BRP1 and the second bridging pattern BRP2 are spaced apart in the first direction DR1 and can face each other. The first bridging pattern BRP1 and the second bridging pattern BRP2 can be electrically insulated from each other, and the first repair line RPL1 and the second repair line RPL2 can be electrically insulated from each other.

[0272] In the implementation, in the plan view, the first repair line RPL1, the first bridging pattern BRP1, and the second bridging pattern BRP2 may overlap with the fourth conductive pattern CP4 (or the second contact electrode CNE2) of the 12th dummy pixel circuit DPC12 or the 12th dummy pixel DP12. The first repair line RPL1, the first bridging pattern BRP1, and the second bridging pattern BRP2 may be electrically insulated from the fourth conductive pattern CP4. In the plan view, the second repair line RPL2, the second bridging pattern BRP2, and the first bridging pattern BRP1 may overlap with the fourth conductive pattern CP4 (or the second contact electrode CNE2) of the 22nd dummy pixel DP22 or the 22nd dummy pixel circuit DPC22. The second repair line RPL2, the second bridging pattern BRP2, and the first bridging pattern BRP1 may be electrically insulated from the fourth conductive pattern CP4.

[0273] Figure 19 According to one implementation method Figure 2 A schematic diagram of part of EA1 is used to illustrate sub-pixels in the first region DA1 and dummy pixels in the first non-display region NDA1 in the display device.

[0274] exist Figure 19For ease of description, only the first repair line RPL1 and the second repair line RPL2 arranged in the signal wiring in each of the first display area DA1 and the first non-display area NDA1 are shown.

[0275] refer to Figure 19 This section primarily describes the differences from the embodiments described above, in order to avoid overlapping descriptions.

[0276] refer to Figure 2 and Figure 19 The first region DA1 and the first non-display region NDA1 may include a first group of GR1 and a second group of GR2 arranged alternately on the second direction DR2. For example, in each of the first region DA1 and the first non-display region NDA1, the first group of GR1, the second group of GR2, the first group of GR1, the second group of GR2, the first group of GR1, the second group of GR2, the first group of GR1, the second group of GR2... may be arranged in this order on the second direction DR2.

[0277] Each of the first group GR1 and the second group GR2 may include the first row R1 and the second row R2.

[0278] In the first region DA1, each of the first row R1 and the second row R2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1 may be arranged in the first pixel column PC1, the second sub-pixel SP2 may be arranged in the second pixel column PC2, and the third sub-pixel SP3 may be arranged in the third pixel column PC3. Each of the first sub-pixels SP1 to the third sub-pixel SP3 may include pixel circuitry, and a light-emitting element (LED) is electrically connected to the pixel circuitry. As used herein, the pixel row extends in the first direction DR1, and the pixel column extends in the second direction DR2.

[0279] In the first row R1, the first sub-pixel SP1 includes the 11th pixel circuit PXC11 and a light-emitting element LED electrically connected to the 11th pixel circuit PXC11; the second sub-pixel SP2 may include the 12th pixel circuit PXC12 and a light-emitting element LED electrically connected to the 12th pixel circuit PXC12; and the third sub-pixel SP3 may include the 13th pixel circuit PXC13 and a light-emitting element LED electrically connected to the 13th pixel circuit PXC13.

[0280] In the second row R2, the first sub-pixel SP1 includes the 21st pixel circuit PXC21 and a light-emitting element LED electrically connected to the 21st pixel circuit PXC21, the second sub-pixel SP2 may include the 22nd pixel circuit PXC22 and a light-emitting element LED electrically connected to the 22nd pixel circuit PXC22, and the third sub-pixel SP3 may include the 23rd pixel circuit PXC23 and a light-emitting element LED electrically connected to the 23rd pixel circuit PXC23.

[0281] The pixel circuit of each of the first sub-pixels SP1 to the third sub-pixels SP3 may include a first contact electrode CNE1. The first contact electrode CNE1 may be electrically connected to a light-emitting element (LED). The first contact electrode CNE1 may be as shown in the reference. Figures 7 to 12 The fourth conductive pattern CP4.

[0282] The first contact electrode CNE1 can be electrically connected to the light-emitting element LED and the pixel circuit through a corresponding contact hole CH in some configurations. The first contact electrode CNE1 can be a connection device for connecting the light-emitting element LED and the pixel circuit. The first contact electrode CNE1 can be located at the connection point (or...) where the light-emitting element LED and the pixel circuit are electrically connected in each sub-pixel. Figure 3 The fourth node (N4) is located therein. In the following text, for ease of description, the contact hole CH of some configuration that electrically connects the light-emitting element LED, the first contact electrode CNE1, and the pixel circuit will be referred to as the first contact hole CH1.

[0283] In the first non-display area NDA1, each of the first row R1 and the second row R2 may include a first dummy pixel DP1 and a second dummy pixel DP2. The first dummy pixel DP1 may be arranged in the first dummy column DC1, and the second dummy pixel DP2 may be arranged in the second dummy column DC2. Each of the first dummy pixel DP1 and the second dummy pixel DP2 may include dummy pixel circuitry. For example, the first dummy pixel circuitry DPC1 may be arranged in the first dummy pixel DP1, and the second dummy pixel circuitry DPC2 may be arranged in the second dummy pixel DP2. The dummy pixel circuitry of each of the first dummy pixel DP1 and the second dummy pixel DP2 may include a second contact electrode CNE2 electrically connected to the repair line RPL. The second contact electrode CNE2 may be as described in the reference... Figures 13 to 18 The fourth conductive pattern CP4 is described.

[0284] The second contact electrode CNE2 can be electrically connected to the repair line RPL through a corresponding contact hole CH. The contact hole CH can be located at the connection point (or connection node) between the repair line RPL and the second contact electrode CNE2 at each dummy pixel.

[0285] In each of the first non-display area NDA1 and the first area DA1, a first repair line RPL1 and a second repair line RPL2 may be arranged between the first row R1 and the second row R2. The first repair line RPL1 may be integrally formed with a first bridging pattern BRP1, and the second repair line RPL2 may be integrally formed with a second bridging pattern BRP2. The first bridging pattern BRP1 may be configured as multiple bridging patterns spanning the first non-display area NDA1 and the first area DA1. The second bridging pattern BRP2 may be configured as multiple bridging patterns spanning the first non-display area NDA1 and the first area DA1.

[0286] In the first region DA1, the first bridging pattern BRP1 and the second bridging pattern BRP2 can extend along the second direction DR2 between sub-pixels in the first row R1 and the second row R2. For example, the first bridging pattern BRP1 and the second bridging pattern BRP2 can extend along the second direction DR2 between the first sub-pixel SP1 in the first row R1 and the first sub-pixel SP1 in the second row R2, between the second sub-pixel SP2 in the first row R1 and the second sub-pixel SP2 in the second row R2, and between the third sub-pixel SP3 in the first row R1 and the third sub-pixel SP3 in the second row R2.

[0287] In the first region DA1, the first bridging pattern BRP1 and the second bridging pattern BRP2 may overlap with the first contact electrode CNE1 of each sub-pixel in the planar diagram. Each of the first bridging pattern BRP1 and the second bridging pattern BRP2 may be electrically insulated from the first contact electrode CNE1.

[0288] In an implementation, the first repair line RPL1 can be electrically connected to the dummy pixel circuit of one of the first dummy pixel DP1 and the second dummy pixel DP2, and the second repair line RPL2 can be electrically connected to the dummy pixel circuits of the remaining dummy pixels in each dummy column. For example, in each of the first group GR1 and the second group GR2, each of the second dummy pixel DP2 (or second dummy pixel circuit DPC2) in the first row R1 and the first dummy pixel DP1 (or first dummy pixel circuit DPC1) in the second row R2 is electrically connected to the first repair line RPL1 via a corresponding second contact electrode CNE2. In each of the first group GR1 and the second group GR2, each of the first dummy pixel DP1 (or first dummy pixel circuit DPC1) in the first row R1 and the second dummy pixel DP2 (or second dummy pixel circuit DPC2) in the second row R2 can be electrically connected to the second repair line RPL2 via a corresponding second contact electrode CNE2. The first repair line RPL1 and the second repair line RPL2 can be electrically insulated from the pixel circuit of each of the first sub-pixels SP1 to SP3 located in the first region DA1.

[0289] Typically, display devices (see...) Figure 2 The “DD” in the text can be used to specify the area to be placed in the display area (see [link]). Figure 2 Subpixels in “DA” (see Figure 2 The light-emitting element (LED) of the sub-pixel SP performs an illumination check. When the illumination check indicates that some of the LEDs are not lit and the sub-pixel SP is dimmed, a repair process can be performed by electrically connecting the unlit LEDs to the first dummy pixel DP1 and the second dummy pixel DP2 to drive the LEDs.

[0290] The following describes a method for repairing defective subpixels SP in the first region DA1.

[0291] Figure 20 This is a schematic flowchart illustrating a method for repairing a display device according to one embodiment. Figure 21 It corresponds to Figure 2 A schematic diagram of part of EA1 is used to illustrate a method for repairing defective subpixels. Figure 22 It shows the arrangement in Figure 21 A schematic circuit diagram showing the electrical connection of the first sub-pixel SP1 and the second dummy pixel DP2 in the first row R1 of the first group GR1.

[0292] Main reference Figures 20 to 22 The implementation method described herein differs from the implementation method described above in order to avoid overlapping descriptions.

[0293] refer to Figures 20 to 22In step S100, dummy pixels (see...) can be provided. Figure 2 "DP" in the text) and sub-pixels (see Figure 2 The display device for "SP" in (see Figure 2 (DD in the text).

[0294] This repair method allows for the detection of the first region DA1 (or the first display region) and the second region (see [reference]) at step S200. Figure 2 Dark spot defects (or dark spot faults) in each of the sub-pixels SP in “DA2” (or the second display area).

[0295] When two sub-pixels in the first row R1 of the first region DA1 have a dark spot fault, in step S300, the first dummy pixel arranged in the first row R1 of the first non-display region NDA1 (see...) can be removed. Figure 2 and Figure 21 "DP1" in the second dummy pixel (see "DP1") and the second dummy pixel (see Figure 2 and Figure 21 The “DP2” in the diagram is electrically connected to the two sub-pixels respectively to repair the dark spot faults of the two sub-pixels.

[0296] Repair processes may include, for example, using a laser to disconnect the electrical connections between the light-emitting elements and pixel circuitry in a subpixel with a dark spot defect and the pixel circuitry, and using a laser through a repair line (see...). Figure 19 The “RPL” in the text refers to the process of electrically connecting the light-emitting element to a dummy pixel DP arranged in the same row as the sub-pixel with a dark spot fault to perform a bonding process, so that the light-emitting element can operate normally.

[0297] like Figure 21 As shown, when a dark spot fault occurs simultaneously in the first sub-pixel SP1 and the third sub-pixel SP3 arranged in the first row R1 of the first group GR1, a repair process can be performed in which the first sub-pixel SP1 is electrically connected to the second dummy pixel DP2 arranged in the first row R1, and the third sub-pixel SP3 is electrically connected to the first dummy pixel DP1 arranged in the first row R1. The dark spot fault in each of the first sub-pixel SP1 and the third sub-pixel SP3 can be caused, for example, by a defect in the pixel circuitry.

[0298] When the 11th pixel circuit PXC11 of the first sub-pixel SP1 is defective, a laser can be used to disconnect the anode electrode AE ​​of the light-emitting element LED (hereinafter referred to as "(1-1) light-emitting element") electrically connected to the 11th pixel circuit PXC11 from the sixth transistor T6 and the seventh transistor T7 of the 11th pixel circuit PXC11. Therefore, the anode electrode AE ​​can be electrically disconnected from the sixth transistor T6 and the seventh transistor T7. A contact hole CH (or a second contact hole CH2) can be formed between the first bridging pattern BRP1 and the first contact electrode CNE1, which are electrically connected to the anode electrode AE ​​(or the (1-1) light-emitting element LED) through the first contact hole CH1, by destroying the insulating layer using a laser bonding process. Through the contact hole CH, the first contact electrode CNE1, and the first contact hole CH1, the first bridging pattern BRP1 (or the first repair line RPL1) and the anode electrode AE ​​(or the (1-1) light-emitting element LED) can be electrically connected. The first repair line RPL1 is electrically connected to the second dummy pixel DP2 arranged in the first row R1 of the first non-display area NDA1, so that the second dummy pixel circuit DPC2 of the second dummy pixel DP2 and the first (1-1) light-emitting element LED of the first sub-pixel SP1 can be electrically connected. Therefore, an electrical path is formed from the second dummy pixel DP2 to the first (1-1) light-emitting element LED of the first sub-pixel SP1, so that the first (1-1) light-emitting element LED can operate normally and the first sub-pixel SP1 with dark spot defects can be repaired.

[0299] When a dark spot fault occurs in the third sub-pixel SP3, which is arranged in the same row as the first sub-pixel SP1, the anode electrode of the light-emitting element LED (hereinafter referred to as the "3-1 light-emitting element") of the 13th pixel circuit PXC13 of the third sub-pixel SP3 (see [reference needed]) can be electrically connected to the third sub-pixel SP3. Figure 21 The “AE” in the text refers to the sixth and seventh transistors of the 13th pixel circuit PXC13 (see...). Figure 21The transistors T6 and T7 are disconnected. Therefore, the anode AE ​​of the (3-1) light-emitting element LED can be electrically disconnected from the sixth transistor T6 and the seventh transistor T7. A contact hole CH (or a second contact hole CH2) can be formed between the second bridging pattern BRP2 and the first contact electrode CNE1, which are electrically connected to the anode AE ​​of the (3-1) light-emitting element LED through the first contact hole CH1, by using a laser bonding process to break the insulating layer. The second bridging pattern BRP2 (or the second repair line RPL2) and the anode AE ​​of the (3-1) light-emitting element LED can be electrically connected through the contact hole CH, the first contact electrode CNE1, and the first contact hole CH1. The second repair line RPL2 is electrically connected to the first dummy pixel DP1 arranged in the first row R1 of the first non-display area NDA1, so that the first dummy pixel circuit DPC1 of the first dummy pixel DP1 and the (3-1) light-emitting element LED of the third sub-pixel SP3 can be electrically connected. Therefore, an electrical path is formed from the first dummy pixel DP1 to the third sub-pixel SP3, so that the (3-1) light-emitting element LED can operate normally and the third sub-pixel SP3 with dark spot defects can be repaired.

[0300] As described above, when a dark spot fault occurs in two sub-pixels arranged in the first row R1 of the first region DA1, the light-emitting element (LED) of one of the two sub-pixels for a horizontal time is electrically connected to the dummy pixel circuit of one of the first dummy pixels DP1 and the second dummy pixel DP2 arranged in the first row R1 of the first non-display region NDA1, and the light-emitting element (LED) of the other sub-pixel can be electrically connected to the dummy pixel circuit of the other of the first dummy pixel DP1 and the second dummy pixel DP2. Therefore, the dark spot defect of two sub-pixels in one row (or one pixel row) of the first region DA1 can be repaired.

[0301] In addition, such as Figure 21 As shown, when a dark spot fault occurs simultaneously in the first sub-pixel SP1 and the third sub-pixel SP3 arranged in the second row R2 of the second group GR2, a repair process can be performed in which the first sub-pixel SP1 is electrically connected to the second dummy pixel DP2 arranged in the second row R2, and the third sub-pixel SP3 is electrically connected to the first dummy pixel DP1 arranged in the second row R2. For example, some configurations of the 21st pixel circuit PXC21 that releases the first sub-pixel SP1 (e.g., the sixth transistor and the seventh transistor (see...)) Figure 21The electrical connection between the light-emitting element LED (hereinafter referred to as the "first (1-2) light-emitting element") of the first sub-pixel SP1 and the second bridging pattern BRP2 (or the second repair line RPL2) of the first sub-pixel SP1 is formed by forming a contact hole CH (or a second contact hole CH2), thereby electrically connecting the first (1-2) light-emitting element LED of the first sub-pixel SP1 and the second dummy pixel circuit DPC2 of the second dummy pixel DP2. Therefore, an electrical path can be formed from the second dummy pixel DP2 to the first (1-2) light-emitting element LED of the first sub-pixel SP1. Furthermore, some configurations of the 23rd pixel circuit PXC23 of the third sub-pixel SP3 (e.g., the sixth transistor and the seventh transistor (see...)) can be released. Figure 21 The electrical connection between "T6 and T7" in the diagram and the light-emitting element LED of the third sub-pixel SP3 (hereinafter referred to as "the (3-2) light-emitting element") is established, and the (3-2) light-emitting element LED and the first bridging pattern BRP1 (or the first repair line RPL1) can be electrically connected through the formation of contact hole CH (or second contact hole CH2), so that the (3-2) light-emitting element LED of the third sub-pixel SP3 and the first dummy pixel circuit DPC1 of the first dummy pixel DP1 can be electrically connected to each other. Therefore, an electrical path can be formed from the first dummy pixel DP1 to the (3-2) light-emitting element LED of the third sub-pixel SP3.

[0302] In the above embodiments, for ease of description, the first region DA1 is mainly described; however, this disclosure is not limited thereto, and any sub-pixel with a dark spot defect in the second region DA2 can also be repaired. For example, when two sub-pixels in the first row R1 of the second region DA2 (or the second display area) have a dark spot defect, the light-emitting element (LED) of one of the two sub-pixels is electrically connected to a second non-display area (see [link to documentation]). Figure 2 The third and fourth dummy pixels in the first row R1 of “NDA2” (see Figure 2 The dummy pixel circuit of one of the "DP3 and DP4" in the second region DA2 can be connected to the dummy pixel circuit of another dummy pixel in the third dummy pixel DP3 and the fourth dummy pixel DP4. Therefore, the dark spot defect of two sub-pixels in a row (or a pixel row) in the second region DA2 can be repaired.

[0303] According to the above implementation, by simultaneously repairing the dark spot defects of two sub-pixels in a row (or a pixel row) of each of the first region DA1 (or the first display area) and the second region DA2 (or the second display area), the number of repairable sub-pixels for a horizontal time can be increased, thereby improving product yield.

[0304] Figure 23 It corresponds to Figure 2 A schematic diagram of part of EA1 is provided to illustrate a method for repairing bad sub-pixels. Specifically, Figure 23 The electrical paths for dummy pixels and bad sub-pixels are shown. Figure 21 Example of modification.

[0305] about Figure 23 To avoid redundancy, the implementation method described below will primarily focus on the differences from the implementation method described above.

[0306] refer to Figure 2 and Figure 23 In the first row R1 of the first group GR1, when the 11th pixel circuit PXC11 of the first sub-pixel SP1 and the 13th pixel circuit PXC13 of the third sub-pixel SP3 are defective, the light-emitting element LED of the first sub-pixel SP1 (hereinafter referred to as "the (1-1) light-emitting element") is electrically connected to the first dummy pixel DP1 arranged in the first row R1, and the light-emitting element LED of the third sub-pixel SP3 (hereinafter referred to as "the (3-1) light-emitting element") is electrically connected to the second dummy pixel DP2 arranged in the first row R1. The first dummy pixel circuit DPC1 of the first dummy pixel DP1 can be electrically connected to the second repair line RPL2, and the second dummy pixel circuit DPC2 of the second dummy pixel DP2 can be electrically connected to the first repair line RPL1.

[0307] More specifically, the electrical connection between the (1-1) light-emitting element LED and some configurations of the 11th pixel circuit PXC11 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 of the first sub-pixel SP1 and the second bridging pattern BRP2 to electrically connect the (1-1) light-emitting element LED and the second repair line RPL2 connected to the second bridging pattern BRP2, so that the (1-1) light-emitting element LED can be electrically connected to the first dummy pixel circuit DPC1 of the first dummy pixel DP1. Furthermore, by releasing the electrical connection between the (3-1) light-emitting element LED and some configurations of the 13th pixel circuit PXC13, and forming a contact hole CH (or a second contact hole CH2) between the second contact electrode CNE2 of the third sub-pixel SP3 and the first bridging pattern BRP1 to electrically connect the (3-1) light-emitting element LED and the first repair line RPL1 connected to the first bridging pattern BRP1, the (3-1) light-emitting element LED can be electrically connected to the second dummy pixel circuit DPC2 of the second dummy pixel DP2.

[0308] As described above, the second repair line RPL2 forms an electrical path from the first dummy pixel DP1 to the first sub-pixel SP1 with a dark spot defect, specifically the (1-1)th light-emitting element LED, and the first repair line RPL1 forms an electrical path from the second dummy pixel DP2 to the third sub-pixel SP3 with a dark spot defect, specifically the (3-1)th light-emitting element LED. Therefore, signal delay caused by the difference in electrical paths between the dummy pixel and the sub-pixel with the dark spot defect can be reduced or prevented. In other words, signal delay caused by the length difference between the first repair line RPL1 and the second repair line RPL2, which electrically connect the dummy pixel and the defective sub-pixel, can be reduced or prevented.

[0309] When the 21st pixel circuit PXC21 of the first sub-pixel SP1 and the 23rd pixel circuit PXC23 of the third sub-pixel SP3 in the second row R2 of the second group GR2 are defective, the light-emitting element LED of the first sub-pixel SP1 (hereinafter referred to as "the (1-2) light-emitting element") is electrically connected to the first dummy pixel DP1 arranged in the second row R2, and the light-emitting element LED of the third sub-pixel SP3 (hereinafter referred to as "the (3-2) light-emitting element") is electrically connected to the second dummy pixel DP2 arranged in the second row R2. The first dummy pixel circuit DPC1 of the first dummy pixel DP1 can be electrically connected to the first repair line RPL1, and the second dummy pixel circuit DPC2 of the second dummy pixel DP2 can be electrically connected to the second repair line RPL2.

[0310] More specifically, the electrical connection between the (1-2) light-emitting element LED and some configurations of the 21st pixel circuit PXC21 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 of the first sub-pixel SP1 and the first bridging pattern BRP1, thereby electrically connecting the (1-2) light-emitting element LED to the first repair line RPL1 connected to the first bridging pattern BRP1, so that the (1-2) light-emitting element LED and the first dummy pixel circuit DPC1 of the first dummy pixel DP1 can be electrically connected. Furthermore, the electrical connection between the (3-2) light-emitting element LED and some configurations of the 23rd pixel circuit PXC23 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 of the third sub-pixel SP3 and the second bridging pattern BRP2 to electrically connect the (3-2) light-emitting element LED and the second repair line RPL2 connected to the second bridging pattern BRP2, so that the (3-2) light-emitting element LED and the second dummy pixel circuit DPC2 of the second dummy pixel DP2 can be electrically connected.

[0311] As described above, an electrical path is formed via the first repair line RPL1 from the first dummy pixel DP1 to the (1-2)th light-emitting element LED of the first sub-pixel SP1 with a dark spot defect, and an electrical path is formed via the second repair line RPL2 from the second dummy pixel DP2 to the (3-2)th light-emitting element LED of the third sub-pixel SP3 with a dark spot defect. This reduces or prevents signal delay caused by the difference in electrical paths between the dummy pixel and the sub-pixel where the dark spot defect occurs. In other words, it reduces or prevents signal delay caused by the length difference between the first repair line RPL1 and the second repair line RPL2 that electrically connects the dummy pixel and the defective sub-pixel.

[0312] Figure 24 The corresponding display device according to one embodiment Figure 2 A schematic diagram of a region of EA1.

[0313] about Figure 24 To avoid redundancy, the implementation method described below will primarily focus on the differences from the implementation method described above.

[0314] refer to Figure 2 and Figure 24 The dummy pixels arranged in the first non-display area NDA1 may include dummy anode electrodes (DAEs). A portion of the dummy anode electrode (DAE) may be arranged in the first area DA1. The dummy anode electrode (DAE) may include a first dummy anode electrode (DAE1), a second dummy anode electrode (DAE2), and a third dummy anode electrode (DAE3).

[0315] The anode electrode AE ​​can be disposed in a first region DA1 (or a first display region) adjacent to the first non-display region NDA1. The anode electrode AE ​​can include a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3. The first anode electrode AE1 can be electrically connected to the pixel circuit of the first sub-pixel SP1, the second anode electrode AE2 can be electrically connected to the pixel circuit of the second sub-pixel SP2, and the third anode electrode AE3 can be electrically connected to the pixel circuit of the third sub-pixel SP3.

[0316] Each of the first anode electrode AE1 to the third anode electrode AE3 may be spaced apart from the dummy anode electrode DAE. For example, the first anode electrode AE1 may be spaced apart from each of the first dummy anode electrodes DAE1 to the third dummy anode electrode DAE3, the second anode electrode AE2 may be spaced apart from each of the first dummy anode electrodes DAE1 to the third dummy anode electrode DAE3, and the third anode electrode AE3 may be spaced apart from each of the first dummy anode electrodes DAE1 to the third dummy anode electrode DAE3.

[0317] In this embodiment, the dummy anode electrode DAE can be electrically connected to the anode electrode AE. The first dummy anode electrode DAE1 can be electrically connected to the first anode electrode AE1 via a first additional conductive wiring ACL1. The second dummy anode electrode DAE2 can be electrically connected to the second anode electrode AE2 via a second additional conductive wiring ACL2. The third dummy anode electrode DAE3 can be electrically connected to the third anode electrode AE3 via a third additional conductive wiring ACL3.

[0318] The light-emitting layer EML can be disposed on each of the dummy anode electrode DAE and the anode electrode AE. The first light-emitting layer EML1 can be disposed on the first anode electrode AE1 and the first dummy anode electrode DAE1, the second light-emitting layer EML2 can be disposed on the second anode electrode AE2 and the second dummy anode electrode DAE2, and the third light-emitting layer EML3 can be disposed on the third anode electrode AE3 and the third dummy anode electrode DAE3.

[0319] Cathode electrode (see Figure 6 The cathode electrode (CE) can be arranged on the light-emitting layer (EML). The cathode electrode (CE) can be arranged in the form of a plate spanning the first non-display area (NDA1) and the first area (DA1).

[0320] The first dummy anode electrode DAE1, the first light-emitting layer EML1, and the cathode electrode CE, arranged in the first non-display area NDA1, can constitute a first dummy light-emitting element. The first dummy light-emitting element can be electrically connected to the pixel circuit of the first sub-pixel SP1 via the first additional conductive wiring ACL1. Therefore, the light-emitting element of the first sub-pixel SP1 (see...) Figure 19 The “LED” in the image and the first dummy light-emitting element can be turned on or off simultaneously through the same pixel circuit.

[0321] The second dummy anode electrode DAE2, the second light-emitting layer EML2, and the cathode electrode CE arranged in the first non-display area NDA1 can constitute a second dummy light-emitting element. The second dummy light-emitting element can be electrically connected to the pixel circuit of the second sub-pixel SP2 through the second additional conductive wiring ACL2. Therefore, the light-emitting element LED of the second sub-pixel SP2 and the second dummy light-emitting element can be simultaneously turned on or off through the same pixel circuit.

[0322] The third dummy anode electrode DAE3, the third light-emitting layer EML3, and the cathode electrode CE arranged in the first non-display area NDA1 can constitute a third dummy light-emitting element. The third dummy light-emitting element can be electrically connected to the pixel circuit of the third sub-pixel SP3 through the third additional conductive wiring ACL3. Therefore, the light-emitting element LED of the third sub-pixel SP3 and the third dummy light-emitting element can be simultaneously turned on or off through the same pixel circuit.

[0323] As described above, since the first to third dummy light-emitting elements are arranged in the first non-display area NDA1 and electrically connected to the pixel circuit of the corresponding sub-pixel to emit light, the display area of ​​the displayed image can be increased (see [link]). Figure 2 The size of "DA" in the figure is reduced to decrease the size of the display device (see Figure 2 The dead zone of “DD” in the middle.

[0324] Figure 25 According to one implementation method Figure 2 A schematic diagram of part of EA2 is used to illustrate the sub-pixels of the second region DA2 and the dummy pixels of the second non-display region NDA2 in the display device.

[0325] about Figure 25 To avoid redundancy, the implementation method described below will primarily focus on the differences from the implementation method described above.

[0326] refer to Figure 2 and Figure 25 The second region DA2 and the second non-display region NDA2 may include a first group of GR1 and a second group of GR2 arranged alternately on the second direction DR2. Each of the first group of GR1 and the second group of GR2 may include a first row R1 and a second row R2.

[0327] In the second region DA2, each of the first row R1 and the second row R2 may include a third sub-pixel SP3, a second sub-pixel SP2, and a first sub-pixel SP1 arranged in the first direction DR1. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged sequentially based on the boundaries of the second region DA2 and the second non-display region NDA2. For example, in the direction opposite to the first direction DR1, the first sub-pixel SP1 may be arranged in the first pixel column PC1, the second sub-pixel SP2 may be arranged in the second pixel column PC2, and the third sub-pixel SP3 may be arranged in the third pixel column PC3. The first sub-pixel SP1 includes an 11th pixel circuit PXC11 and a light-emitting element LED electrically connected to the 11th pixel circuit PXC11. The second sub-pixel SP2 includes a 12th pixel circuit PXC12 and a light-emitting element LED electrically connected to the 12th pixel circuit PXC12. The third sub-pixel SP3 may include a 13th pixel circuit PXC13 and a light-emitting element LED electrically connected to the 13th pixel circuit PXC13. The pixel circuit of each of the first sub-pixels SP1 to the third sub-pixels SP3 may include a first contact electrode CNE1. The first contact electrode CNE1 may be electrically connected to the light-emitting element LED through a corresponding contact hole CH.

[0328] In the second non-display area NDA2, each of the first row R1 and the second row R2 may include a third dummy pixel DP3 and a fourth dummy pixel DP4. The third dummy pixel DP3 may be arranged in the third dummy column DC3, and the fourth dummy pixel DP4 may be arranged in the fourth dummy column DC4. A third dummy pixel circuit DPC3 may be arranged in the third dummy pixel DP3, and a fourth dummy pixel circuit DPC4 may be arranged in the fourth dummy pixel DP4. The dummy pixel circuit of each of the third dummy pixel DP3 and the fourth dummy pixel DP4 may include a second contact electrode CNE2 electrically connected to the repair line RPL. The second contact electrode CNE2 may be electrically connected to the repair line RPL through a corresponding contact hole CH.

[0329] In each of the second non-display area NDA2 and the second area DA2, a third repair line RPL3 and a fourth repair line RPL4 may be arranged between the first row R1 and the second row R2. The third repair line RPL3 may be integrally formed with the third bridging pattern BRP3, and the fourth repair line RPL4 may be integrally formed with the fourth bridging pattern BRP4.

[0330] In the second region DA2, the third bridging pattern BRP3 and the fourth bridging pattern BRP4 can extend along the second direction DR2 between sub-pixels in the first row R1 and the second row R2. For example, the third bridging pattern BRP3 and the fourth bridging pattern BRP4 can extend along the second direction DR2 between the first sub-pixel SP1 in the first row R1 and the first sub-pixel SP1 in the second row R2, between the second sub-pixel SP2 in the first row R1 and the second sub-pixel SP2 in the second row R2, and between the third sub-pixel SP3 in the first row R1 and the third sub-pixel SP3 in the second row R2.

[0331] In the second region DA2, the third bridging pattern BRP3 and the fourth bridging pattern BRP4 can overlap with the first contact electrode CNE1 of each sub-pixel in the planar diagram. Each of the third bridging pattern BRP3 and the fourth bridging pattern BRP4 can be electrically insulated from the first contact electrode CNE1.

[0332] In this implementation, the third repair line RPL3 can be electrically connected to one of the third dummy pixel DP3 and the fourth dummy pixel DP4, and the fourth repair line RPL4 can be electrically connected to the other dummy pixel of the third dummy pixel DP3 and the fourth dummy pixel DP4. For example, the third repair line RPL3 can be electrically connected to the third dummy pixel DP3 through a corresponding second contact electrode CNE2, and the fourth repair line RPL4 can be electrically connected to the fourth dummy pixel DP4 through a corresponding second contact electrode CNE2.

[0333] The third repair line RPL3 and the fourth repair line RPL4 can be electrically insulated from the pixel circuits of each of the first sub-pixels SP1 to SP3 located in the second region DA2.

[0334] Typically, display devices (see...) Figure 2 The “DD” in the text can be used to specify the area to be placed in the display area (see [link]). Figure 2 The LEDs of the sub-pixels in “DA” are used to perform an illumination check. When the illumination check indicates that some of the LEDs are not lit, causing the sub-pixel to darken, a repair process can be performed by electrically connecting the unlit LEDs to the third dummy pixel DP3 and the fourth dummy pixel DP4 to drive the LEDs.

[0335] In the following text, see references Figure 26 This will describe a method for repairing defective subpixels in the second region DA2.

[0336] Figure 26 It is used to show the repair and Figure 2 A schematic diagram of the method for dealing with bad sub-pixels corresponding to EA2.

[0337] about Figure 26 To avoid redundancy, the implementation method described below will primarily focus on the differences from the implementation method described above.

[0338] refer to Figure 2 and Figure 26 When the 11th pixel circuit PXC11 of the first sub-pixel SP1 and the 13th pixel circuit PXC13 of the third sub-pixel SP3 in the first row R1 of the first group GR1 are defective, the light-emitting element LED of the first sub-pixel SP1 (hereinafter referred to as "(1-1) light-emitting element") is electrically connected to the fourth dummy pixel DP4 arranged in the first row R1, and the light-emitting element LED of the third sub-pixel SP3 (hereinafter referred to as "(3-1) light-emitting element") is electrically connected to the third dummy pixel DP3 arranged in the first row R1. The third dummy pixel circuit DPC3 of the third dummy pixel DP3 can be electrically connected to the third repair line RPL3, and the fourth dummy pixel circuit DPC4 of the fourth dummy pixel DP4 can be electrically connected to the fourth repair line RPL4.

[0339] More specifically, the electrical connection between the (1-1) light-emitting element LED and some configurations of the 11th pixel circuit PXC11 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 of the first sub-pixel SP1 and the fourth bridging pattern BRP4 to electrically connect the (1-1) light-emitting element LED and the fourth repair line RPL4 connected to the fourth bridging pattern BRP4, so that the (1-1) light-emitting element LED and the fourth dummy pixel circuit DPC4 of the fourth dummy pixel DP4 can be electrically connected. Therefore, an electrical path is formed from the fourth dummy pixel DP4 to the (1-1) light-emitting element LED of the first sub-pixel SP1, so that the (1-1) light-emitting element LED can operate normally and the first sub-pixel SP1 with dark spot defects can be repaired.

[0340] Furthermore, the electrical connection between the (3-1) light-emitting element LED and some configurations of the 13th pixel circuit PXC13 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 of the third sub-pixel SP3 and the third bridging pattern BRP3 to electrically connect the (3-1) light-emitting element LED and the third repair line RPL3 connected to the third bridging pattern BRP3, so that the (3-1) light-emitting element LED and the third dummy pixel circuit DPC3 of the third dummy pixel DP3 can be electrically connected. Therefore, an electrical path is formed from the third dummy pixel DP3 to the third sub-pixel SP3, so that the (3-1) light-emitting element LED can operate normally and the third sub-pixel SP3 with dark spot defects can be repaired.

[0341] When the 21st pixel circuit PXC21 of the first sub-pixel SP1 and the 23rd pixel circuit PXC23 of the third sub-pixel SP3 in the second row R2 of the second group GR2 are defective, the light-emitting element LED of the first sub-pixel SP1 (hereinafter referred to as "the (1-2) light-emitting element") is electrically connected to the fourth dummy pixel DP4 arranged in the second row R2. The light-emitting element LED of the third sub-pixel SP3 (hereinafter referred to as "the (3-2) light-emitting element") is electrically connected to the third dummy pixel DP3 arranged in the second row R2. The third dummy pixel circuit DPC3 of the third dummy pixel DP3 can be electrically connected to the fourth repair line RPL4, and the fourth dummy pixel circuit DPC4 of the fourth dummy pixel DP4 can be electrically connected to the third repair line RPL3.

[0342] More specifically, the electrical connection between the (1-2) light-emitting elements LED and some configurations of the 21st pixel circuit PXC21 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 of the first sub-pixel SP1 and the third bridging pattern BRP3 to electrically connect the (1-2) light-emitting elements LED and the third repair line RPL3 connected to the third bridging pattern BRP3, so that the (1-2) light-emitting elements LED can be electrically connected to the fourth dummy pixel circuit DPC4 of the fourth dummy pixel DP4. Therefore, an electrical path is formed from the fourth dummy pixel DP4 to the first sub-pixel SP1, so that the (1-2) light-emitting elements LED can operate normally and the first sub-pixel SP1 with dark spot defects can be repaired.

[0343] Furthermore, the electrical connection between the (3-2) light-emitting element LED and some configurations of the 23rd pixel circuit PXC23 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 of the third sub-pixel SP3 and the fourth bridging pattern BRP4 to electrically connect the (3-2) light-emitting element LED and the fourth repair line RPL4 connected to the fourth bridging pattern BRP4, so that the (3-2) light-emitting element LED and the third dummy pixel circuit DPC3 of the third dummy pixel DP3 can be electrically connected. Therefore, an electrical path is formed from the third dummy pixel DP3 to the third sub-pixel SP3, so that the (3-2) light-emitting element LED can operate normally and the third sub-pixel SP3 with dark spot defects can be repaired.

[0344] As described above, when a dark spot fault occurs in two sub-pixels in the first row R1 of the second region DA2, the light-emitting element (LED) of one of the two sub-pixels for a horizontal time is electrically connected to the dummy pixel circuit of one of the third dummy pixels DP3 and the fourth dummy pixels DP4 arranged in the first row R1 of the second non-display region NDA2. Similarly, the light-emitting element (LED) of the other sub-pixel can be electrically connected to the dummy pixel circuit of the other dummy pixel in the third dummy pixel DP3 and the fourth dummy pixel DP4. Therefore, the dark spot defect in two sub-pixels in one row (or one pixel row) of the second region DA2 can be repaired.

[0345] Figure 27 This is a schematic block diagram showing an electronic device 1000 according to an embodiment. Figure 28 It is shown that Figure 27 The electronic device 1000 is a schematic diagram of an example of a smartphone. Figure 29 It is shown that Figure 27The electronic device 1000 is a schematic diagram of an example of a tablet PC.

[0346] refer to Figures 27 to 29 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 and Figure 2 The display device DD. The electronic device 1000 may also include various ports for communicating with a graphics card, sound card, memory card, USB device, or other systems. In embodiments, such as Figure 28 As shown, the electronic device 1000 can be a smartphone. In an implementation, as... Figure 29 As shown, electronic device 1000 may be a tablet computer. However, the above examples are illustrative, and electronic device 1000 is not necessarily limited to the examples described above. For example, electronic device 1000 may be a cellular phone, video phone, smart tablet, smartwatch, navigation device for vehicle, computer monitor, laptop computer, head-mounted display device, etc.

[0347] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 can be a microprocessor, central processing unit, application processor, etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In embodiments, processor 1010 can be connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0348] The memory device 1020 can store data required to perform the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano-floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) and ferroelectric random access memory (FRAM) devices, and / or volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices and mobile DRAM devices.

[0349] Storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc.

[0350] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touch screen, and mouse, as well as output devices such as speakers and printers. In some embodiments, display device 1060 may be included in I / O device 1040.

[0351] The power supply 1050 can provide the power required to operate the electronic device 1000. For example, the power supply 1050 may include a power management integrated circuit (PMIC).

[0352] The display device 1060 can display images in response to control signals or data from the processor 1010. The display device 1060 may be an organic light-emitting display device or a quantum dot light-emitting display device, but this disclosure is not limited to these. The display device 1060 can be connected to other components via a bus or other communication links.

[0353] The display device and its repair method according to the embodiments can improve the reliability of the display device by simultaneously and easily repairing dark spot faults occurring in four sub-pixels in a pixel row.

[0354] According to the implementation method, the product yield can be increased by increasing the number of repairable subpixels.

[0355] Furthermore, according to the embodiments, an electronic device including the above-described display device can be provided.

[0356] The effects of this disclosure are not limited to the foregoing, and various other effects are anticipated herein.

Claims

1. A display device, comprising: A substrate, wherein a display area comprising a first region and a second region and a non-display area surrounding at least one side of the display area; Sub-pixels are arranged in the display area; Dummy pixels are arranged in the non-display area; as well as The repair line is commonly located in both the display area and the non-display area, and extends in a first direction. The non-display area includes a first non-display area adjacent to the first area and a second non-display area adjacent to the second area. The repair line includes a first repair line and a second repair line, which are arranged in the first region between the first pixel row and the second pixel row of the substrate. Wherein, each of the first pixel row and the second pixel row extends in the first direction, and The first repair line and the second repair line face each other in a second direction that intersects with the first direction.

2. The display device according to claim 1, wherein, The dummy pixels include a first dummy pixel and a second dummy pixel, the first dummy pixel and the second dummy pixel corresponding to each arrangement in the first pixel row and the second pixel row in the first non-display area, and The first dummy pixel and the second dummy pixel are arranged adjacent to each other in the first direction.

3. The display device according to claim 2, wherein, The first dummy pixel is electrically connected to one of the first repair line and the second repair line, and the second dummy pixel is electrically connected to the other of the first repair line and the second repair line.

4. The display device according to claim 3, wherein, The first repair wire and the second repair wire are electrically insulated from each other.

5. The display device according to claim 4, wherein, In the first non-display area, the first repair line and the second repair line are arranged between the first dummy pixel and the second dummy pixel arranged corresponding to the first pixel row and the first dummy pixel and the second dummy pixel arranged corresponding to the second pixel row.

6. The display device according to claim 2, wherein, The sub-pixels are configured in multiple ways, and each of the multiple sub-pixels includes pixel circuitry, and In this context, the pixel circuits of two sub-pixels facing each other in the second direction in the first region are mirror-symmetrical with respect to each other, and the first repair line and the second repair line are between the two sub-pixels.

7. The display device according to claim 6, further comprising: Multiple first bridging patterns extend in the second direction and are electrically connected to the first repair line; as well as A plurality of second bridging patterns extend in the second direction, are electrically connected to the second repair line, and are spaced apart from the plurality of first bridging patterns.

8. The display device according to claim 7, wherein, In the first region, the plurality of first bridging patterns are integrally formed with the first repair line and protrude from the first repair line in the direction toward the second repair line, and In the first region, the plurality of second bridging patterns are integrally formed with the second repair line and protrude from the second repair line in the direction toward the first repair line.

9. The display device according to claim 7, wherein, The sub-pixel also includes: A light-emitting element, electrically connected to the pixel circuit and configured to emit light; and The contact electrode is electrically connected to the anode electrode of the light-emitting element, and The contact electrode is electrically insulated from the first repair line and the second repair line.

10. The display device according to claim 9, wherein, The contact electrode overlaps with the first bridging pattern and the second bridging pattern in the first region in the plan view.

11. The display device according to claim 9, wherein, Each of the first dummy pixel and the second dummy pixel includes a dummy pixel circuit, and In this context, the dummy pixel circuits of two dummy pixels facing each other in the second direction in the first non-display area are mirror-symmetrical with respect to each other, and the first repair line and the second repair line are between the two dummy pixels.

12. The display device according to claim 11, wherein, The dummy pixel circuit includes a capacitor. The capacitor includes a first electrode and a second electrode disposed on the first electrode, and an insulating layer is located between the first electrode and the second electrode. At least one of the first repair line and the second repair line is arranged on the first electrode and the second electrode.

13. The display device according to claim 11, wherein, Each of the first dummy pixel and the second dummy pixel further includes a dummy anode electrode, the dummy anode electrode being located in the non-display area and overlapping with the dummy pixel circuitry. The dummy anode electrode is electrically connected to the anode electrode of the sub-pixel arranged in the display area adjacent to the non-display area.

14. The display device according to claim 2, wherein, The repair lines also include a third repair line and a fourth repair line, which are arranged in the second region between the first pixel row and the second pixel row. The dummy pixels further include a third dummy pixel and a fourth dummy pixel, which are arranged in the second non-display area corresponding to each of the first pixel row and the second pixel row. Wherein, the third repair line and the fourth repair line face each other in the second direction, and The third dummy pixel and the fourth dummy pixel are arranged adjacent to each other in the first direction.

15. The display device according to claim 14, wherein, The third dummy pixel is electrically connected to one of the third and fourth repair lines, and the fourth dummy pixel is electrically connected to the other of the third and fourth repair lines. The third repair line and the fourth repair line are electrically insulated from each other.

16. The display device according to claim 15, wherein, The sub-pixels are configured in multiple ways, and each of the multiple sub-pixels includes pixel circuitry, and In this context, the pixel circuits of two sub-pixels facing each other in the second direction in the second region are mirror-symmetrical with respect to each other, and the third repair line and the fourth repair line are between the two sub-pixels.

17. The display device according to claim 15, further comprising: Multiple third bridging patterns extend in the second direction and are electrically connected to the third repair line; as well as Multiple fourth bridging patterns extend in the second direction, are electrically connected to the fourth repair line, and are spaced apart from the multiple third bridging patterns. In the second region, the plurality of third bridging patterns are integrally formed with the third repair line and protrude from the third repair line in the direction toward the fourth repair line. In the second region, the plurality of fourth bridging patterns are integrally formed with the fourth repair line and protrude from the fourth repair line in the direction toward the third repair line.

18. A method for repairing a display device, The display device includes: A substrate, wherein a display area comprising a first region and a second region and a non-display area surrounding at least one side of each of the first region and the second region; A sub-pixel is arranged in the display area and includes a pixel circuit, a light-emitting element, and a contact electrode, wherein the contact electrode is electrically connected to the anode electrode of the light-emitting element; The first repair line and the second repair line are arranged in the display area between the first pixel row and the second pixel row and are spaced apart from each other. The dummy pixel includes a first dummy pixel and a second dummy pixel, which are arranged in the non-display area corresponding to each of the first pixel row and the second pixel row and respectively connected to the first repair line and the second repair line; The first bridging pattern is electrically connected to the first repair line; as well as The second bridging pattern is electrically connected to the second repair line. The method includes: The first defective pixel circuit arranged in the first pixel column of the first pixel row is separated from the first light-emitting element corresponding to the first defective pixel circuit; The anode of the first light-emitting element is electrically connected to the dummy pixel circuit of the first dummy pixel by electrically connecting the contact electrode electrically connected to the anode electrode of the first light-emitting element to the corresponding first bridging pattern in the first bridging pattern. Separate the second defective pixel circuit arranged in the third pixel column of the first pixel row from the second light-emitting element corresponding to the second defective pixel circuit; and The anode of the second light-emitting element is electrically connected to the dummy pixel circuit of the second dummy pixel by electrically connecting the contact electrode electrically connected to the anode electrode of the second light-emitting element to the corresponding second bridging pattern in the second bridging pattern.

19. The method according to claim 18, wherein, The first repair wire and the second repair wire are electrically insulated from each other.

20. An electronic device comprising: A processor, used to provide input image data to a display device; as well as The display device is used to display an image based on the input image. The display device includes: A substrate, wherein a display area comprising a first region and a second region and a non-display area surrounding at least one side of the display area; Sub-pixels are arranged in the display area; Dummy pixels are arranged in the non-display area; and The repair line is commonly located in both the display area and the non-display area, and extends in a first direction. The non-display area includes a first non-display area adjacent to the first area and a second non-display area adjacent to the second area. The repair line includes a first repair line and a second repair line, which are arranged in the first region between the first pixel row and the second pixel row of the substrate. Wherein, each of the first pixel row and the second pixel row extends in the first direction, and The first repair line and the second repair line face each other in a second direction that intersects with the first direction.

Images