Display device, repair method thereof, and electronic device having display device

Abstract

The invention relates to a display device, a method of repairing the display device, and an electronic device including the display device. The display device includes: a substrate in which a display area including a first area and a second area and a non-display area surrounding at least one side of the display area are defined; sub-pixels arranged in the display area; a first dummy pixel and a second dummy pixel arranged in the non-display area; and a repair line commonly disposed in the display area and the non-display area, and extending in the first direction. The non-display area includes a first non-display area and a second non-display area. The repair lines include a first repair line and a second repair line arranged between the first pixel row and the second pixel row in the first region. Each of the first dummy pixel and the second dummy pixel includes a first capacitor electrically connected to the dummy pixel circuit. The first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel have different sizes.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0157066, filed on November 7, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present invention relate to a display device, a method for repairing a display device, and an electronic device including a display device. Background Technology

[0004] With the recent increase in interest in information display, research and development of display devices continues. Summary of the Invention

[0005] This disclosure provides a display device capable of improving reliability by preventing pixel dark spot defects, a method for repairing the device, and an electronic device including the display device.

[0006] Some embodiments of this disclosure include a display device comprising: a substrate defining a display region including a first region and a second region, and a non-display region surrounding at least one side of the display region; sub-pixels disposed in the display region; a first dummy pixel and a second dummy pixel disposed in the non-display region; and repair lines commonly disposed in the display region and the non-display region, and extending in a first direction. The non-display region includes a first non-display region adjacent to the first region and a second non-display region adjacent to the second region. The repair lines include a first repair line and a second repair line, which are disposed in the first region between a first pixel row and a second pixel row of the substrate. Each of the first dummy pixel and the second dummy pixel includes dummy pixel circuitry and a first capacitor electrically connected to the dummy pixel circuitry. The first capacitors of the first dummy pixel and the second dummy pixel have different dimensions.

[0007] According to some implementations, the second dummy pixel can be positioned closer to the first region than the first dummy pixel in the first non-display region, and the first capacitor of the first dummy pixel can have a larger size than the first capacitor of the second dummy pixel.

[0008] According to some embodiments, the first capacitor in each of the first dummy pixel and the second dummy pixel may include a lower electrode disposed on a substrate and an upper electrode disposed on the lower electrode, with an insulating layer interposed between the upper and lower electrodes. The overlap area between the lower and upper electrodes in the first dummy pixel may be greater than the overlap area between the lower and upper electrodes in the second dummy pixel.

[0009] According to some implementations, the dummy pixel circuit of the first dummy pixel can be arranged in a plan view between the first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel.

[0010] According to some implementations, the first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel can be arranged adjacent to each other in a plan view.

[0011] According to some implementations, the upper electrode of the first capacitor of the first dummy pixel and the upper electrode of the first capacitor of the second dummy pixel can be commonly disposed on the common electrode of the first dummy pixel and the second dummy pixel.

[0012] According to some embodiments, the first repair line and the second repair line may extend in a first direction. The first repair line and the second repair line may be spaced apart from each other in a second direction and may be electrically isolated from each other.

[0013] According to some implementations, the dummy pixel circuit of the first dummy pixel can be electrically connected to one of the first repair line and the second repair line. The dummy pixel circuit of the second dummy pixel can be electrically connected to the other of the first repair line and the second repair line.

[0014] According to some implementations, the dummy pixel circuit of the first dummy pixel can be electrically connected to the second repair line. The dummy pixel circuit of the second dummy pixel can be electrically connected to the first repair line.

[0015] According to some embodiments, the display device may further include: a first bridging pattern located between the first repair line and the second repair line, extending in a second direction and electrically connected to the first repair line; and a second bridging pattern located between the first repair line and the second repair line, extending in a second direction and electrically connected to the second repair line.

[0016] According to some embodiments, a sub-pixel may include: a pixel circuit including at least one transistor disposed on a substrate; a light-emitting element electrically connected to the transistor and emitting light; and a first contact electrode electrically connected to the light-emitting element and the transistor. The first contact electrode may overlap with a first bridging pattern and a second bridging pattern. The first contact electrode, the first bridging pattern, and the second bridging pattern may be electrically isolated from each other.

[0017] According to some implementations, the pixel circuits of two sub-pixels facing each other in a second direction can be mirror-symmetrical to each other, with a first repair line and a second repair line interposed between them in a first region.

[0018] According to some embodiments, each of the first dummy pixel and the second dummy pixel may further include a second contact electrode, the second contact electrode electrically connecting the dummy pixel circuitry to a corresponding repair line among the first repair line and the second repair line. The second contact electrode may overlap with the first bridging pattern and the second bridging pattern. The second contact electrode may be electrically connected to one of the first bridging pattern and the second bridging pattern.

[0019] According to some embodiments, the repair lines may further include a third repair line and a fourth repair line, which are arranged in the second region between the first pixel row and the second pixel row. Dummy pixels may further include a third dummy pixel and a fourth dummy pixel arranged in each of the first pixel row and the second pixel row in the second non-display region. The third dummy pixel may be electrically connected to one of the third and fourth repair lines. The fourth dummy pixel may be electrically connected to the other of the third and fourth repair lines.

[0020] According to some implementations, each of the third dummy pixel and the fourth dummy pixel may include a dummy pixel circuit and a first capacitor electrically connected to the dummy pixel circuit. The first capacitor of the third dummy pixel and the first capacitor of the fourth dummy pixel may have different sizes.

[0021] According to some implementations, the third dummy pixel can be positioned closer to the second region than the fourth dummy pixel in the second non-display region. The first capacitor of the fourth dummy pixel can have a larger size than the first capacitor of the third dummy pixel.

[0022] Some embodiments of this disclosure include a display device comprising: a substrate defining a display area including a first region and a second region, and a non-display area surrounding at least one side of the display area; sub-pixels disposed in the display area; dummy pixels disposed in the non-display area; and repair lines commonly disposed in the display area and the non-display area, and extending in a first direction. The repair lines include two repair lines disposed between a first pixel row and a second pixel row on the substrate and electrically isolated from each other. The non-display area includes a first non-display area adjacent to the first region and a second non-display area adjacent to the second region. The dummy pixels include a first dummy pixel and a second dummy pixel disposed in each of the first pixel row and the second pixel row in the first non-display area, and a third dummy pixel and a fourth dummy pixel disposed in each of the first pixel row and the second pixel row in the second non-display area. Each of the first to fourth dummy pixels includes a dummy pixel circuit comprising at least one transistor and a first capacitor electrically connected to the dummy pixel circuit. The first capacitors of the first and second dummy pixels have different dimensions. The first capacitors of the third and fourth dummy pixels have different dimensions.

[0023] According to some implementations, a second dummy pixel may be positioned closer to the first region than the first dummy pixel in the first non-display region. A third dummy pixel may be positioned closer to the second region than the fourth dummy pixel in the second non-display region. The first capacitor of the first dummy pixel may have a larger size than the first capacitor of the second dummy pixel. The first capacitor of the fourth dummy pixel may have a larger size than the first capacitor of the third dummy pixel.

[0024] Some embodiments of this disclosure include a method for repairing a display device, the display device comprising: a substrate defining a display region including a first region and a second region, and a non-display region surrounding at least one side of the first region and the second region; sub-pixels disposed in the display region and including pixel circuitry, a light-emitting element, and a contact electrode electrically connected to a positive electrode of the light-emitting element; a first repair line and a second repair line disposed in the display region between a first pixel row and a second pixel row, and spaced apart from each other; a first dummy pixel and a second dummy pixel disposed in each of the first pixel row and the second pixel row in the non-display region, and respectively connected to one of the first repair line and the second repair line; a first bridging pattern electrically connected to the first repair line; and a second bridging pattern. The method of electrically connecting to a second repair line includes: separating a first defective pixel circuit arranged in a first pixel column of a first pixel row from a first light-emitting element corresponding to the first defective pixel circuit; electrically connecting the anode of the first light-emitting element to a dummy pixel circuit of the first light-emitting element by electrically connecting a contact electrode electrically connected to the anode of the first light-emitting element to a corresponding first bridging pattern in a first bridging pattern; separating a second defective pixel circuit arranged in a third pixel column of the first pixel row from a second light-emitting element corresponding to the second defective pixel circuit; and electrically connecting the anode of the second light-emitting element to a dummy pixel circuit of the second dummy pixel by electrically connecting a contact electrode electrically connected to the anode of the second light-emitting element to a corresponding second bridging pattern in a second bridging pattern. Each of the first dummy pixel and the second dummy pixel includes a first capacitor electrically connected to the dummy pixel circuit. The first capacitors of the first dummy pixel and the second dummy pixel have different sizes.

[0025] According to some implementations, the second dummy pixel can be positioned in a non-display area closer to the display area than the first dummy pixel. The first capacitor of the first dummy pixel can have a larger size than the first capacitor of the second dummy pixel.

[0026] Some embodiments of this disclosure include an electronic device comprising: a processor for providing input image data to a display device; and a display device for displaying an image based on the input image data, wherein the display device may include: a substrate defining a display area including a first region and a second region, and a non-display area surrounding at least one side of the display area; sub-pixels disposed in the display area; dummy pixels disposed in the non-display area; and repair lines commonly disposed in the display area and the non-display area, and extending in a first direction. The non-display area includes a first non-display area adjacent to the first region and a second non-display area adjacent to the second region. The repair lines include a first repair line and a second repair line, which are disposed in the first region between a first pixel row and a second pixel row of the substrate. The dummy pixels include a first dummy pixel and a second dummy pixel disposed in each of the first pixel row and the second pixel row in the first non-display area. Each of the first dummy pixel and the second dummy pixel includes dummy pixel circuitry and a first capacitor electrically connected to the dummy pixel circuitry. The first capacitors of the first dummy pixel and the second dummy pixel have different dimensions.

[0027] According to some implementations, the second dummy pixel may be positioned closer to the first region than the first dummy pixel in the first non-display region. The first capacitor of the first dummy pixel may have a larger size than the first capacitor of the second dummy pixel. Attached Figure Description

[0028] The above and other features of the present invention will become more apparent from the description of embodiments of the invention in more detail with reference to the accompanying drawings.

[0029] Figure 1 This is a schematic block diagram illustrating a display device according to one embodiment.

[0030] Figure 2 This is a schematic plan view showing a display device according to one embodiment.

[0031] Figure 3 It is shown Figure 2 A schematic diagram illustrating the implementation of one of the sub-pixels.

[0032] Figure 4 It is shown Figure 2 A schematic diagram illustrating an implementation of one of the dummy pixels.

[0033] Figure 5 It is shown Figure 2 A schematic plan view of an implementation of one pixel of the pixels.

[0034] Figure 6 It is along Figure 5 A schematic cross-sectional view of line I-I' in the diagram.

[0035] Figure 7 It is a schematic plan view showing sub-pixels arranged in the first and second rows in a portion of the first area of ​​the display area of ​​a display device according to one embodiment.

[0036] Figure 8 It only shows those included Figure 7 A schematic plan view of the arrangement of the first to seventh transistors and the first conductive layer.

[0037] Figure 9 It only shows those included Figure 7 A schematic plan view of the configuration in the second conductive layer.

[0038] Figure 10 It only shows those included Figure 7 A schematic plan view of the configuration in the third conductive layer.

[0039] Figure 11 It only shows those included Figure 7 A schematic plan view of the configuration in the fourth conductive layer.

[0040] Figure 12 It only shows those included Figure 7 A schematic plan view of the configuration in the fifth conductive layer.

[0041] Figure 13 This is a schematic plan view showing dummy pixels arranged in the first row and the second row in the first region of the first non-display area of ​​a display device according to one embodiment.

[0042] Figure 14 Is only shown Figure 13 A schematic plan view of the configuration of the first to sixth transistors, the eighth transistor, and the ninth transistor, and the first conductive layer.

[0043] Figure 15 It only shows those included Figure 13 A schematic plan view of the configuration in the second conductive layer.

[0044] Figure 16 It only shows those included Figure 13 A schematic plan view of the configuration in the third conductive layer.

[0045] Figure 17 It only shows those included Figure 13 A schematic plan view of the configuration in the fourth conductive layer.

[0046] Figure 18 It only shows those included Figure 13 A schematic plan view of the configuration in the fifth conductive layer.

[0047] Figure 19 This is a schematic plan view showing dummy pixels arranged in the first and second rows in a portion of the first non-display area of ​​a display device according to one embodiment.

[0048] Figure 20 It only shows those included Figure 19 A schematic diagram of the configuration of the first to sixth transistors, the eighth transistor, and the ninth transistor in the first conductive layer.

[0049] Figure 21 It only shows those included Figure 19 A schematic plan view of the configuration in the second conductive layer.

[0050] Figure 22 It is used to illustrate sub-pixels in a first region and dummy pixels in a first non-display region in a display device according to one embodiment. Figure 2 The view of part of EA1.

[0051] Figure 23 This is a schematic flowchart illustrating a method for repairing a display device according to one embodiment.

[0052] Figure 24 Is with Figure 2 The diagram corresponding to part EA1 illustrates a method for repairing defective sub-pixels.

[0053] Figure 25 It shows the arrangement in Figure 24 A schematic circuit diagram showing the electrical connection between the first sub-pixel and the second dummy pixel in the first row.

[0054] Figure 26 Is with Figure 2 The diagram corresponding to part EA1 illustrates a method for repairing defective sub-pixels.

[0055] Figure 27 It is used to illustrate sub-pixels in a second region and dummy pixels in a second non-display region in a display device according to one embodiment. Figure 2 A partial schematic diagram of EA2.

[0056] Figure 28 Is with Figure 2 The diagram corresponding to EA2 shows a method for repairing defective sub-pixels.

[0057] Figure 29 This is a schematic block diagram illustrating an electronic device according to an embodiment.

[0058] Figure 30 It is shown Figure 29 The image shows a 3D representation of an electronic device, specifically a smartphone.

[0059] Figure 31 It is shown Figure 29 The electronic device is a three-dimensional diagram of an example of a tablet PC.

[0060] Figure 32 This is a flowchart illustrating a method for repairing a display device according to one embodiment. Detailed Implementation

[0061] The invention will be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0062] In describing the accompanying drawings, the same reference numerals are used for the same elements. In the drawings, the dimensions of the structures are exaggerated beyond their actual dimensions for clarity of explanation. It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element discussed below may be referred to as a second element without departing from the scope of the invention. Similarly, a second element may also be referred to as a first element.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprises” and / or “comprising” or “includes” and / or “including” specify the presence of the stated features, areas, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integers, steps, operations, elements, components, and / or groups thereof.

[0064] In the following description, when the first part is “connected” to the second part, this includes not only the case where the first part is directly connected to the second part, but also the case where the third part is inserted between the first part and the second part and they are connected to each other.

[0065] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientations depicted in the drawings, the relative terms are intended to encompass different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” to the other elements will subsequently be oriented “up” to the other elements. Thus, based on the specific orientation of the drawing, the term “down” can encompass both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other elements will subsequently be oriented “above” the other elements. Thus, the term “below” or “under” can encompass both “up” and “down” orientations.

[0066] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in common dictionaries, shall be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0067] In the following, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0068] Figure 1 This is a schematic block diagram illustrating a display device DD according to one embodiment.

[0069] refer to Figure 1 The display device DD may include a display panel PNL, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0070] The display panel PNL may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn.

[0071] Each of the subpixels SP can include at least one light-emitting element configured to generate light. Therefore, each of the subpixels SP can generate light of a specific color, such as red, green, blue, cyan, magenta, yellow, etc. Two or more subpixels SP can constitute a single pixel PXL. For example, as... Figure 1 As shown, three sub-pixels SP can form a single pixel PXL.

[0072] The gate driver 120 can be connected to the sub-pixels SP arranged in the row direction via the first gate line GL1 to the m-th gate line GLm. The gate driver 120 can output gate signals to the first gate line GL1 to the m-th gate line GLm in response to the gate control signal GCS. The gate driver 120 can be arranged on one side of the display panel PNL, but is not limited thereto.

[0073] In one implementation, first emission control lines EL1 to m-th emission control lines ELm may also be provided connected to sub-pixels SP in the row direction. Gate driver 120 may include emission control drivers configured to control the first emission control lines EL1 to m-th emission control lines ELm. The emission control drivers may be operable under the control of controller 150.

[0074] The data driver 130 can be connected to the sub-pixels SP arranged in the column direction via the first data line DL1 to the nth data line DLn. The data driver 130 can receive image data DATA and data control signal DCS from the controller 150. The data driver 130 can operate in response to the data control signal DCS.

[0075] The data driver 130 can apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, a data signal corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel PNL.

[0076] In one embodiment, the gate driver 120 and the data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0077] Voltage generator 140 can operate in response to a voltage control signal VCS from controller 150. Voltage generator 140 can generate multiple voltages and supply the generated voltages to components of display device DD. For example, voltage generator 140 can receive an input voltage from outside display device DD, control the input voltage, and regulate the controlled voltage to generate multiple voltages.

[0078] Voltage generator 140 can generate a first power supply voltage ELVDD and a second power supply voltage ELVSS, and the generated first power supply voltage ELVDD and second power supply voltage ELVSS can be provided to sub-pixel SP. The first power supply voltage ELVDD can have a relatively high voltage level, and the second power supply voltage ELVSS can have a lower voltage level than the first power supply voltage ELVDD. In other embodiments, the first power supply voltage ELVDD or the second power supply voltage ELVSS can be provided to the display device DD by an external device.

[0079] Furthermore, voltage generator 140 can generate various voltages. For example, voltage generator 140 can generate an initialization voltage applied to sub-pixel SP. For example, a predetermined reference voltage can be applied to the first data lines DL1 to the nth data lines DLn during sensing operation to sense the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, and voltage generator 140 can generate this reference voltage.

[0080] The controller 150 can control various operations of the display device DD. The controller 150 can receive input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from an external source. The controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0081] The controller 150 can convert the input image data IMG into a format suitable for a display device DD or a display panel PNL to output image data DATA. In one embodiment, the controller 150 can output image data DATA by aligning the input image data IMG to sub-pixels SP of matching row units.

[0082] Two or more of the components—data driver 130, voltage generator 140, and controller 150—can be mounted on a single integrated circuit. For example... Figure 1As shown, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). The data driver 130, voltage generator 140, and controller 150 may be functionally different components within a single driver integrated circuit (DIC). In other embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a separate component within the driver integrated circuit (DIC).

[0083] The display device DD may include at least one temperature sensor 160. The temperature sensor 160 may be configured to sense the temperature in the vicinity of the temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be arranged adjacent to the display panel PNL and / or the driver integrated circuit DIC.

[0084] The controller 150 can control various operations of the display device DD in response to the temperature data TEP. In one embodiment, the controller 150 can adjust the brightness of the image output from the display panel PNL in response to the temperature data TEP.

[0085] Figure 2 This is a schematic plan view showing a display device DD according to one embodiment. For convenience, Figure 2 The schematic diagram illustrates the structure of the display area DA of the display device DD, for example, the structure of the display panel PNL disposed in the display device DD. As used herein, a “plan view” is a view of the display device DD (or substrate SUB) in the thickness direction (i.e., the third direction DR3).

[0086] refer to Figure 2 The display device DD (or display panel PNL) may include a substrate SUB and sub-pixels SP.

[0087] The display device DD can have various shapes, such as, but not limited to, a rectangular plate shape with two pairs of parallel sides. This embodiment is applicable when the display device DD is an electronic device (such as a smartphone, television, tablet PC, mobile phone, video phone, e-book reader, desktop PC, laptop PC, netbook computer, workstation, server, PDA, portable multimedia player (PMP), MP3 player, medical device, camera, or wearable device) having a display surface on at least one side.

[0088] The substrate SUB may include a transparent insulating material that allows light to pass through it. The substrate SUB may be a rigid substrate or a flexible substrate.

[0089] The rigid substrate can be, for example, a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystalline glass substrate.

[0090] The flexible substrate can be one of polymeric organic materials, film substrates, and plastic substrates. For example, the flexible substrate can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate, as well as one or more combinations thereof.

[0091] Subpixels SP can be arranged on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of subpixels SP is not limited to this. For example, subpixels SP can be arranged in a zigzag pattern along the first direction DR1 and the second direction DR2. For example, subpixels SP can be arranged in a pentiline pattern. ® Arrange the structural layout. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0092] Two or more sub-pixels SP can form a single pixel PXL.

[0093] One area of ​​the substrate SUB can be set as the display area DA in which the sub-pixels SP are placed, and the remaining area of ​​the substrate SUB can be set as the non-display area NDA.

[0094] In the non-display area NDA of the substrate SUB, components for controlling the sub-pixel SP can be arranged. For example, wiring associated with the sub-pixel SP (such as...) Figure 1 The first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn shown can be arranged in the non-display area NDA.

[0095] In an implementation, the display area DA may include a first area DA1 (or a first display area) and a second area DA2 (or a second display area) adjacent in the first direction DR1. The display area DA can be divided into a first area DA1 and a second area DA2 by bisecting the display area DA around an imaginary line located at the center. When viewed in a plane, the first area DA1 may be located on the upper left, and the second area DA2 may be located on the upper right.

[0096] The non-display area NDA may include a first non-display area NDA1 that surrounds or is adjacent to at least one side of the edge of the first area DA1 or extends toward the edge along at least one side of the edge of the first area DA1, and a second non-display area NDA2 that surrounds or is adjacent to at least one side of the edge of the second area DA2 or extends toward the edge along at least one side of the edge of the second area DA2.

[0097] In each of the first non-display area NDA1 and the second non-display area NDA2, two dummy pixels DP corresponding to each pixel row can be arranged. For example, the non-display area NDA can have two dummy pixels DP corresponding to each pixel row. The dummy pixels DP may include a first dummy pixel DP1 and a second dummy pixel DP2 arranged in the first non-display area NDA1, and a third dummy pixel DP3 and a fourth dummy pixel DP4 arranged in the second non-display area NDA2.

[0098] The first dummy pixel DP1 and the second dummy pixel DP2 can be arranged adjacent to each other in the first non-display area NDA1 along the first direction DR1. The third dummy pixel DP3 and the fourth dummy pixel DP4 can be arranged adjacent to each other in the second non-display area NDA2 along the first direction DR1. The second dummy pixel DP2 can be arranged closer to the first area DA1 (or display area DA) than the first dummy pixel DP1, and the third dummy pixel DP3 can be arranged closer to the second area DA2 (or display area DA) than the fourth dummy pixel DP4.

[0099] The pads (PDs) can be arranged on the substrate (SUB) within the non-display area (NDA). The pads (PDs) can be electrically connected to the sub-pixels (SPs) via wiring. For example, as referenced above. Figure 1 As described, the pad PD can be connected to the sub-pixel SP via the first data line DL1 to the nth data line DLn.

[0100] The pad PD can interface with other components of the display device DD via the display panel PNL. In this embodiment, the voltages and signals required to operate the components included in the display panel PNL can be obtained from... Figure 1 The driver integrated circuit (DIC) is provided via pad PD.

[0101] In one embodiment, the display device DD may include a repair line RPL that is commonly disposed across the display area DA and the non-display area NDA. The repair line RPL may include a first repair line RPL1, a second repair line RPL2, a third repair line RPL3, and a fourth repair line RPL4. The first repair line RPL1 and the second repair line RPL2 may be commonly disposed and extend parallel to each other across the first area DA1 and the first non-display area NDA1. The third repair line RPL3 and the fourth repair line RPL4 may be commonly disposed and extend parallel to each other across the second area DA2 and the second non-display area NDA2.

[0102] In the first region DA1, the first repair line RPL1 and the second repair line RPL2 can be arranged between two sub-pixels SP that face each other in the second direction DR2. In the first non-display region NDA1, the first repair line RPL1 and the second repair line RPL2 can be arranged between two first dummy pixels DP1 that face each other in the second direction DR2 and between two second dummy pixels DP2 that face each other in the second direction DR2.

[0103] In the second region DA2, the third repair line RPL3 and the fourth repair line RPL4 can be arranged between two sub-pixels SP that face each other in the second direction DR2. In the second non-display region NDA2, the third repair line RPL3 and the fourth repair line RPL4 can be arranged between two third dummy pixels DP3 that face each other in the second direction DR2 and between two fourth dummy pixels DP4 that face each other in the second direction DR2.

[0104] Figure 3 It is shown as Figure 2 A schematic diagram illustrating an implementation of a sub-pixel SPij within a sub-pixel. For ease of description, Figure 3 The sub-pixel SPij is shown as being located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj.

[0105] refer to Figure 2 and Figure 3 Sub-pixels SPij can be arranged on the i-th horizontal line.

[0106] Subpixel SPij may include a light-emitting element LED and a pixel circuit PXC. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, as well as a storage capacitor Cst.

[0107] A first transistor T1 may be electrically connected between a first power line PL1 and the anode AE ​​of a light-emitting element (LED). The first transistor T1 may include a gate electrode electrically connected to a first node N1. The first transistor T1 may control the amount of current (or drive current) flowing from the first power line PL1 through the LED to the third power line PL3 based on the voltage at the first node N1. The first power line PL1 is supplied with a first power supply voltage ELVDD, and the third power line PL3 is supplied with a second power supply voltage ELVSS, wherein the first power supply voltage ELVDD may be set to a voltage higher than the second power supply voltage ELVSS.

[0108] The second transistor T2 can be electrically connected between the j-th data line Dj and the second node N2. The gate electrode of the second transistor T2 can be connected to the 1i-th scan line S1i (or the first scan line). When the first scan signal GW[i] (e.g., a low-level first scan signal GW[i]) is supplied to the 1i-th scan line S1i, the second transistor T2 can be turned on to electrically connect the j-th data line Dj and the second node N2. When each of the first transistor T1 and the third transistor T3 is in the on state, the second transistor T2 can transmit the data signal of the j-th data line Dj to the first node N1 in response to the first scan signal GW[i].

[0109] The third transistor T3 can be electrically connected between the first node N1 and the third node N3. The gate electrode of the third transistor T3 can be electrically connected to the first scan line S1i. When the first scan signal GW[i] is supplied to the first scan line S1i, the third transistor T3 can be turned on. When the third transistor T3 is turned on, the first transistor T1 can be connected by a diode.

[0110] The fourth transistor T4 can be electrically connected between the first node N1 and the second power line PL2. The gate electrode of the fourth transistor T4 can be electrically connected to the 2i scan line S2i (the second scan line). The second power line PL2 can provide a first initial power supply voltage Vint1. The fourth transistor T4 can be turned on by the second scan signal GI[i] supplied to the 2i scan line S2i. When the fourth transistor T4 is turned on, the first initial power supply voltage Vint1 can be supplied to the first node N1 (i.e., the gate electrode of the first transistor T1).

[0111] The fifth transistor T5 can be electrically connected between the first power line PL1 and the second node N2. The gate electrode of the fifth transistor T5 can be electrically connected to the i-th emitter control line Ei. The sixth transistor T6 can be electrically connected between the third node N3 and the light-emitting element LED (or the fourth node N4). The gate electrode of the sixth transistor T6 can be electrically connected to the i-th emitter control line Ei. The fifth transistor T5 and the sixth transistor T6 can be turned off when the emitter control signal EM[i] (e.g., a high-level emitter control signal EM[i]) is supplied to the i-th emitter control line Ei, and can be turned on under other conditions.

[0112] The seventh transistor T7 can be electrically connected between the anode AE ​​(i.e., the fourth node N4) of the LED and the fourth power line PL4. The gate electrode of the seventh transistor T7 can be electrically connected to the 3i scan line S3i. The fourth power line PL4 can be supplied with a second initialization power supply voltage Vint2. The seventh transistor T7 can be turned on by the third scan signal GB[i] supplied to the 3i scan line S3i to supply the second initialization power supply voltage Vint2 to the anode AE ​​of the LED. The second initialization power supply voltage Vint2 can be the same as, but is not limited to, the first initialization power supply voltage Vint1.

[0113] The light-emitting element (LED) may include a positive electrode AE ​​and a negative electrode CE. The positive electrode AE ​​may be connected to a fourth node N4, and the negative electrode CE may be connected to a third power line PL3. The negative electrode CE of the LED may be supplied with a second power supply voltage ELVSS. The LED may receive drive current from a first transistor T1 and emit light.

[0114] In this implementation, the pixel circuit PXC may include P-type transistors. For example, the first transistor T1 to the seventh transistor T7 may include polysilicon transistors containing silicon semiconductors, and may include a polysilicon semiconductor layer as an active layer. For example, the active layer may be formed using a low-temperature polysilicon process (LTPS process).

[0115] Figure 4 It is shown as Figure 2 A schematic diagram illustrating an implementation of a dummy pixel DPi1, one of the dummy pixels. For ease of description, Figure 4 The dummy pixel DPi1 is shown on the i-th horizontal line (or i-th pixel row) in the first non-display area NDA1 and connected to the first dummy data line DD1.

[0116] refer to Figure 4 For ease of description, descriptions that overlap with the above embodiments will be omitted.

[0117] refer to Figure 2 and Figure 4The dummy pixel DPi1 can be arranged on the i-th horizontal line.

[0118] The dummy pixel DPi1 may include the dummy pixel circuit DPC and the repair modulation circuit RM.

[0119] The dummy pixel circuit (DPC) may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a storage capacitor Cst. In other words, except for the seventh transistor T7, the dummy pixel circuit (DPC) may include components related to the reference transistor. Figure 3 The pixel circuitry described is essentially the same configuration as that of the PXC.

[0120] The repair modulation circuit RM may include an eighth transistor T8, a ninth transistor T9, and a first capacitor C1. The repair modulation circuit RM is connected to the repair line RPL, the i-th transmit control line Ei, and the 3i-th scan line S3i.

[0121] The eighth transistor T8 can be electrically connected between the fourth node N4 and the connection node P1. The gate electrode of the eighth transistor T8 can be connected to the i-th emission control line Ei. The first input / output terminal of the eighth transistor T8 can be electrically connected to the fourth node N4 (or the node that electrically connects the repair line RPL and the light-emitting element of the defective sub-pixel), and the second input / output terminal of the eighth transistor T8 can be electrically connected to the connection node P1 (or between the first capacitor C1 and the ninth transistor T9).

[0122] The ninth transistor T9 can be electrically connected between the eighth transistor T8 and the second power line PL2. The gate electrode of the ninth transistor T9 can be electrically connected to the 3i scan line S3i. The first input / output terminal of the ninth transistor T9 can be electrically connected to the connection node P1, and the second input / output terminal of the ninth transistor T9 can be electrically connected to the second power line PL2.

[0123] One terminal of the first capacitor C1 is connected to the connection node P1 (or between the second input / output terminal of the eighth transistor T8 and the first input / output terminal of the ninth transistor T9), and the other terminal of the first capacitor C1 can be electrically connected to the first power line PL1.

[0124] In the dummy pixel DPi1, the fourth node N4 can be electrically connected to the repair line RPL. When the sub-pixel SP of the display area DA fails, the wiring between the anode of the light-emitting element of the defective sub-pixel and the sixth transistor T6 can be disconnected, and the anode and the repair line RPL can be connected, allowing the light-emitting element of the defective sub-pixel to emit light normally. The following is a detailed description of the repair method for the defective sub-pixel.

[0125] Figure 5It is shown Figure 2 A schematic plan view of an implementation of one of the pixels, PXL.

[0126] refer to Figure 2 and Figure 5 Pixel PXL may include a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3 arranged on the first direction DR1.

[0127] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA surrounding the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA surrounding the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA surrounding the third emission region EMA3.

[0128] The first emission region EMA1 can be a light-emitting element corresponding to the first sub-pixel SP1 (see [link]). Figure 3 The second emission region EMA2 can be the region that emits light from the light-emitting element LED corresponding to the second sub-pixel SP2. The third emission region EMA3 can be the region that emits light from the light-emitting element LED corresponding to the third sub-pixel SP3.

[0129] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have substantially the same area, but are not limited thereto. In some embodiments, the second sub-pixel SP2 may have a larger area than the first sub-pixel SP1, and the third sub-pixel SP3 may have a larger area than the second sub-pixel SP2.

[0130] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have polygonal shapes in the planar diagram. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can have quadrilateral or hexagonal shapes in the planar diagram, but are not limited to these.

[0131] Figure 6 It is along Figure 5 A schematic cross-sectional view of line I-I' in the diagram.

[0132] exist Figure 6 In this diagram, for ease of description, the cross-sectional structure or stacked structure of the display device DD is briefly shown based primarily on the pixels PXL included in the display device DD, and the thickness direction of the substrate SUB is shown as the third direction DR3.

[0133] refer to Figure 5 and Figure 6The display device DD may include one or more pixels PXL arranged in the display area DA.

[0134] Pixel PXL may include one or more subpixels SP. For example, pixel PXL may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. In an embodiment, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 may be a green subpixel, and the third subpixel SP3 may be a blue subpixel, but this disclosure is not limited thereto. Hereinafter, the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 are collectively referred to as subpixels SP and / or multiple subpixels SP.

[0135] Each of the first sub-pixel SP1 to the third sub-pixel SP3 may include a substrate SUB, a pixel circuit layer PCL, a display element layer DPL, a thin film encapsulation layer TFE, and a window WD.

[0136] The substrate SUB may include a transparent insulating material that allows light to pass through it. The substrate SUB may be a rigid substrate or a flexible substrate.

[0137] The pixel circuit layer (PCL) of the sub-pixel SP can be disposed on the substrate SUB. One or more insulating layers can be disposed on the pixel circuit layer PCL. The insulating layers may include a first insulating layer INS1, a second insulating layer INS2, a third insulating layer INS3, a fourth insulating layer INS4, a fifth insulating layer INS5, a sixth insulating layer INS6, and a seventh insulating layer INS7, which are sequentially stacked on the substrate SUB on the third-direction DR3. The insulating layers disposed on the pixel circuit layer PCL are not limited to the above embodiments, and other insulating layers may be added or some insulating layers may be omitted.

[0138] The first insulating layer INS1 can be disposed on the substrate SUB. The first insulating layer INS1 can prevent impurities from diffusing into the pixel circuitry (see [link]). Figure 3 The first insulating layer INS1 is an inorganic layer comprising an inorganic material (or substance). The first insulating layer INS1 may include silicon nitride (SiN). x ), silicon oxide (SiO) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO) x (and at least one of one or more combinations thereof.) The first insulating layer INS1 may be a single layer, but may also be a multilayer consisting of two or more layers. Based on the material and process conditions of the substrate SUB, the first insulating layer INS1 may be omitted.

[0139] A second insulating layer INS2 may be disposed on a first insulating layer INS1. The second insulating layer INS2 may comprise the same material as the first insulating layer INS1, or may comprise a suitable (or selected from) material among those exemplified as components of the first insulating layer INS1. For example, the second insulating layer INS2 may be an inorganic layer comprising inorganic materials.

[0140] The third insulating layer INS3 may be disposed on the second insulating layer INS2. The third insulating layer INS3 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials from those exemplified as components of the first insulating layer INS1.

[0141] The fourth insulating layer INS4 can be disposed on the third insulating layer INS3. The fourth insulating layer INS4 can be an inorganic layer including inorganic materials or an organic layer including organic materials.

[0142] The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4. The fifth insulating layer INS5 may include the same material as the first insulating layer INS1, or may include one or more suitable (or selected) materials from those materials exemplified as components of the first insulating layer INS1.

[0143] The sixth insulating layer INS6 (or the first via layer) can be disposed on the fifth insulating layer INS5. The sixth insulating layer INS6 can be an inorganic layer comprising inorganic materials or an organic layer comprising organic materials. The inorganic layer can include, for example, silicon oxide (SiO2). x ), silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y ) and aluminum oxide (AlO) x Organic layers may include, for example, polyacrylate resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polyphenylene ether resins, polyphenylene sulfide resins, and benzocyclobutene resins, as well as at least one of these and combinations thereof.

[0144] A seventh insulating layer INS7 (or a second via layer) may be disposed on a sixth insulating layer INS6. The seventh insulating layer INS7 may comprise the same material as the sixth insulating layer INS6, or may comprise one or more suitable (or selected from) materials exemplified as components of the sixth insulating layer INS6. For example, the seventh insulating layer INS7 may be an organic layer comprising an organic material.

[0145] The pixel circuit layer (PCL) may include one or more conductive layers disposed between the aforementioned insulating layers. For example, the conductive layers may include a first conductive layer disposed between the second insulating layer INS2 and the third insulating layer INS3, a second conductive layer disposed between the third insulating layer INS3 and the fourth insulating layer INS4, a third conductive layer disposed between the fourth insulating layer INS4 and the fifth insulating layer INS5, a fourth conductive layer disposed between the fifth insulating layer INS5 and the sixth insulating layer INS6, and a fifth conductive layer disposed between the sixth insulating layer INS6 and the seventh insulating layer INS7. However, the insulating and conductive layers are not limited to the above embodiments, and according to embodiments, other insulating and conductive layers besides the aforementioned insulating and conductive layers may be disposed in the pixel circuit layer (PCL).

[0146] The pixel circuit layer (PCL) may include circuit elements (or driving elements) for each of the first sub-pixels SP1 to the third sub-pixels SP3. For example, the PCL may include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 is one of the transistors included in the pixel circuit PXC of the first sub-pixel SP1. Transistor T_SP2 for the second sub-pixel SP2 is one of the transistors included in the pixel circuit PXC of the second sub-pixel SP2. Transistor T_SP3 for the third sub-pixel SP3 is one of the transistors included in the pixel circuit PXC of the third sub-pixel SP3. Figure 6 For clarity and brevity, only one transistor of each sub-pixel SP is shown, and other circuit elements are omitted.

[0147] The transistor T_SP1 of the first sub-pixel SP1 may include a semiconductor pattern SCP, a gate electrode GE, a first terminal EL1, and a second terminal EL2.

[0148] The gate electrode GE can be disposed on the second insulating layer INS2 and covered by the third insulating layer INS3. For example, the gate electrode GE can be a first conductive layer (or a first gate conductive layer) located between the second insulating layer INS2 and the third insulating layer INS3. The gate electrode GE can overlap with a portion of the semiconductor pattern SCP. For example, the gate electrode GE can overlap with the active pattern of the semiconductor pattern SCP.

[0149] The pixel circuit layer PCL may include a first pattern PT1 disposed between a third insulating layer INS3 and a fourth insulating layer INS4. The first pattern PT1 may include a second conductive layer (or a second gate conductive layer). According to an embodiment, the first pattern PT1 may overlap with the gate electrode GE in a planar view, with the third insulating layer INS3 interposed therebetween, to form a capacitor. Furthermore, the pixel circuit layer PCL may include a second pattern PT2 disposed between a fourth insulating layer INS4 and a fifth insulating layer INS5. The second pattern PT2 may include a third conductive layer (or a third gate conductive layer). According to an embodiment, the second pattern PT2 may be used as a signal line electrically connected to a transistor, a connection device, etc.

[0150] A semiconductor pattern SCP can be disposed on a first insulating layer INS1 and covered by a second insulating layer INS2. The semiconductor pattern SCP can be a semiconductor layer including polycrystalline silicon, amorphous silicon, oxide semiconductor, etc. The semiconductor pattern SCP can include an active pattern, a first contact region, and a second contact region. The active pattern, the first contact region, and the second contact region can include undoped or impurity-doped semiconductor layers. For example, the first and second contact regions can include impurity-doped semiconductor layers, and the active pattern can be a region doped at a lower concentration than the first and second contact regions. Therefore, the conductivity of the first and second contact regions can be greater than the conductivity of the active pattern. The first and second contact regions can be the source / drain regions (or source / drain electrodes) of the transistor T_SP1 of the first sub-pixel SP1.

[0151] The active pattern of the semiconductor pattern SCP can be a channel region overlapping the gate electrode GE. A first contact area of ​​the semiconductor pattern SCP can contact one end of the active pattern. The first contact area can be electrically connected to a first terminal EL1. A second contact area of ​​the semiconductor pattern SCP can contact the other end of the active pattern. The second contact area can be electrically connected to a second terminal EL2.

[0152] The first terminal EL1 may be disposed on and / or formed on the fifth insulating layer INS5. For example, the first terminal EL1 may include a fourth conductive layer (or a first source / drain conductive layer) formed between the fifth insulating layer INS5 and the sixth insulating layer INS6. The first terminal EL1 may contact the first contact area of ​​the semiconductor pattern SCP through a contact hole passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0153] The second terminal EL2 may be disposed on and / or formed on the fifth insulating layer INS5. The second terminal EL2 may include a fourth conductive layer formed between the fifth insulating layer INS5 and the sixth insulating layer INS6. The second terminal EL2 may contact the second contact area of ​​the semiconductor pattern SCP through a contact hole passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0154] The second terminal EL2 can be electrically connected to the connection line CNL disposed on the sixth insulating layer INS6. The connection line CNL can be the fifth conductive layer (or the second source / drain conductive layer) disposed between the sixth insulating layer INS6 and the seventh insulating layer INS7.

[0155] According to the embodiment, the bottom metal pattern BML can be arranged on the underside of the transistor T_SP1 of the first sub-pixel SP1 as described above. The bottom metal pattern BML can be a dummy conductive layer located between the substrate SUB and the first insulating layer INS1.

[0156] With the gate electrode GE, the first terminal EL1, and the second terminal EL2 electrically connected to other circuit elements and / or wiring, the transistor T_SP1 of the first sub-pixel SP1 can be configured as one of the transistors in the pixel circuit PXC that constitutes the first sub-pixel SP1.

[0157] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be configured in substantially the same way as the transistor T_SP1 of the first sub-pixel SP1.

[0158] As described above, the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0159] The display element layer (DPL) can be arranged on the pixel circuit layer (PCL). The display element layer (DPL) may include light-emitting elements (see...). Figure 3 The light-emitting element (LED) includes a pixel definition layer (PDL) and a cathode (CE). The LED can be disposed in each of the first sub-pixels SP1 to SP3. The LED disposed in the first sub-pixel SP1 can be the first light-emitting element LED1, the LED disposed in the second sub-pixel SP2 can be the second light-emitting element LED2, and the LED disposed in the third sub-pixel SP3 can be the third light-emitting element LED3.

[0160] The first anode AE1 can be disposed on the pixel circuit layer PCL (or the seventh insulating layer INS7) of the first sub-pixel SP1, the second anode AE2 can be disposed on the pixel circuit layer PCL of the second sub-pixel SP2, and the third anode AE3 can be disposed on the pixel circuit layer PCL of the third sub-pixel SP3. Each of the first anode AE1 to the third anode AE3 can be electrically connected to a circuit element disposed on the pixel circuit layer PCL through a via penetrating the seventh insulating layer INS7. For example, the first anode AE1 is electrically connected to the transistor T_SP1 of the first sub-pixel SP1 through the first via VIH1 penetrating the seventh insulating layer INS7, the second anode AE2 is electrically connected to the transistor T_SP2 of the second sub-pixel SP2 through the second via VIH2 penetrating the seventh insulating layer INS7, and the third anode AE3 is electrically connected to the transistor T_SP3 of the third sub-pixel SP3 through the third via VIH3 penetrating the seventh insulating layer INS7.

[0161] When viewed from a third party towards DR3, each of the first anode AE1, the second anode AE2, and the third anode AE3 can have the same... Figure 5 The first emitting region EMA1, the second emitting region EMA2, and the third emitting region EMA3 each have similar shapes. For example, when viewed from a third party to DR3, the first anode AE1 may have a shape similar to that of the first emitting region EMA1, the second anode AE2 may have a shape similar to that of the second emitting region EMA2, and the third anode AE3 may have a shape similar to that of the third emitting region EMA3. However, this disclosure is not limited thereto.

[0162] Each of the first anodes AE1 to the third anodes AE3 can be electrically connected to the corresponding pixel circuit PXC and receive a drive current. Each of the first anodes AE1 to the third anodes AE3 can be, but is not limited to, an opaque conductive material capable of reflecting light. According to an embodiment, the first anodes AE1 to the third anodes AE3 can include a transparent conductive material.

[0163] A pixel defining layer (PDL) may be located on first anodes AE1 to third anodes AE3. The PDL may include an opening OP that exposes a portion of the first anode AE1, a portion of the second anode AE2, and a portion of the third anode AE3. The PDL may be a structure that defines (or divides) the light-emitting region of each of the first anodes AE1 to the third anode AE3. For example, the PDL may define a first emission region EMA1 of the first sub-pixel SP1, a second emission region EMA2 of the second sub-pixel SP2, and a third emission region EMA3 of the third sub-pixel SP3.

[0164] The pixel-defining layer (PDL) may include an organic insulating layer comprising organic materials. Organic materials (or organic substances) may include, for example, acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, etc. According to embodiments, the pixel-defining layer (PDL) may include a light-absorbing material, or a light-absorbing agent may be applied to the pixel-defining layer (PDL) such that the pixel-defining layer (PDL) can absorb light from an external source. For example, the pixel-defining layer (PDL) may include a carbon-based black pigment. However, this disclosure is not limited thereto.

[0165] The first light-emitting layer EML1 can be disposed on a first anode AE1 exposed by an opening OP in the pixel-defining layer PDL, the second light-emitting layer EML2 can be disposed on a second anode AE2 exposed by another opening OP in the pixel-defining layer PDL, and the third light-emitting layer EML3 can be disposed on a third anode AE3 exposed by another opening OP in the pixel-defining layer PDL. Each of the first light-emitting layers EML1 to the third light-emitting layers EML3 can have a multilayer structure including a hole injection layer, a hole transport layer, an organic light-emitting layer, an electron transport layer, and an electron injection layer.

[0166] The first emissive layers EML1 to the third emissive layers EML3 may include at least one of luminescent materials that emit light of different colors, based on the respective sub-pixels SP. For example, the first emissive layer EML1 may include at least one of red luminescent materials, the second emissive layer EML2 may include at least one of green luminescent materials, and the third emissive layer EML3 may include at least one of blue luminescent materials. According to an embodiment, each of the first emissive layers EML1 to the third emissive layers EML3 may emit white light overall by stacking multiple luminescent materials capable of generating light of different colors (such as red, green, blue, etc.). Color filters may also be arranged on each of the first emissive layers EML1 to the third emissive layers EML3. The color filters may include at least one of a red color filter, a green color filter, and a blue color filter.

[0167] The cathode CE can be disposed on the first light-emitting layer EML1 to the third light-emitting layer EML3 and the pixel defining layer PDL. The cathode CE can be commonly disposed on a common layer of the first sub-pixels SP1 to the third sub-pixels SP3. The cathode CE can be disposed in the form of a plate spanning the entire area of ​​the display area DA. According to an embodiment, the cathode CE can be used as a semi-reflective mirror that partially transmits and partially reflects light emitted from the respective light-emitting layer.

[0168] The cathode CE can be a thin metal layer with sufficient thickness to allow light emitted from the corresponding light-emitting layer to pass through. The cathode CE can comprise a metallic material with a relatively small thickness, or it can comprise a transparent conductive material. In embodiments, the cathode CE can comprise at least one of a variety of transparent conductive materials, including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, or gallium tin oxide, and one or more combinations thereof. In other embodiments, the cathode CE can comprise at least one of magnesium, silver, and mixtures thereof. However, the material of the cathode CE is not limited to the embodiments described above.

[0169] The portion of the first anode AE1, the first light-emitting layer EML1, and the cathode CE overlapping with the first anode AE1 in the plan view can constitute the first light-emitting element LED1. The portion of the second anode AE2, the second light-emitting layer EML2, and the cathode CE overlapping with the second anode AE2 can constitute the second light-emitting element LED2. The portion of the third anode AE3, the third light-emitting layer EML3, and the cathode CE overlapping with the third anode AE3 can constitute the third light-emitting element LED3.

[0170] The thin-film encapsulation layer (TFE) can be disposed on the cathode (CE). The TFE can cover the display element layer (DPL). The TFE can be configured to prevent oxygen and / or moisture from penetrating into the DPL. In embodiments, the TFE can include a structure in which one or more inorganic layers are alternately stacked with one or more organic layers. For example, the inorganic layers can include silicon nitrides, silicon oxides, or silicon oxynitrides, or combinations thereof. For example, the organic layers can include organic insulating materials such as acrylic resins, epoxy resins, phenolic resins, polyamide resins, polyimide resins, unsaturated polyester resins, polystyrene resins, polyphenylene sulfide resins, or benzocyclobutene, or combinations thereof. However, the materials of the organic and inorganic layers of the TFE are not limited thereto.

[0171] The touch sensor layer TS can be disposed on the thin-film encapsulation layer TFE. Alternatively, the touch sensor layer TS can be disposed directly on the thin-film encapsulation layer TFE.

[0172] A touch sensor layer TS can be disposed on the surface on which the image of the display device DD is projected, and can receive touch input from the user. The touch sensor layer TS can recognize touch events on the display device DD via the user's hand, individual input units, etc. For example, the touch sensor layer TS can recognize touch events capacitively.

[0173] The window WD can be disposed on the touch sensor layer TS. The window WD can be a protective member disposed on top of the touch sensor layer TS to protect the configuration of the display device DD. The window WD can be glass or plastic. When the window WD includes glass, ultra-thin glass (UTG) with a thickness of 0.1 mm or less can be used to obtain flexibility. However, this disclosure is not limited thereto.

[0174] According to one embodiment, the display device DD may further include a polarizing layer POL disposed between the touch sensor layer TS and the window WD. The polarizing layer POL can be used to reduce external light reflection. The polarizing layer POL can be attached to the window WD using an optically transparent adhesive component or the like.

[0175] Figure 7 This is a schematic plan view showing sub-pixels arranged in the first row R1 and the second row R2 in a portion of the first region DA1 of the display area of ​​a display device according to one embodiment. Figure 8 It only shows those included Figure 7 A schematic plan view of the first transistor T1 to the seventh transistor T7 and their arrangement in the first conductive layer. Figure 9 It only shows those included Figure 7 A schematic plan view of the configuration in the second conductive layer. Figure 10 It only shows those included Figure 7 A schematic plan view of the configuration in the third conductive layer. Figure 11 It only shows those included Figure 7 A schematic plan view of the configuration in the fourth conductive layer. Figure 12 It only shows those included Figure 7 A schematic plan view of the configuration in the fifth conductive layer.

[0176] The following is for reference Figures 7 to 12 The differences from the above implementation are described to avoid redundancy.

[0177] refer to Figure 2 as well as Figures 7 to 12 Subpixels (see Figure 2The “SP” in the diagram can be arranged in each of the first row R1 (or the first pixel row) and the second row R2 (or the second pixel row), wherein the first row R1 (or the first pixel row) and the second row R2 (or the second pixel row) are located in the same column on the second direction DR2 in the first region DA1 (or the first display area). For example, the 11th sub-pixel SP11 (or the first sub-pixel) can be arranged in the first row R1, and the 21st sub-pixel SP21 (or the second sub-pixel) can be arranged in the second row R2. The 11th sub-pixel SP11 may include the 11th pixel circuit PXC11, and the 21st sub-pixel SP21 may include the 21st pixel circuit PXC21.

[0178] In this implementation, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 are arranged on the second direction DR2 and can face each other relative to the repair line RPL. For example, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 can be symmetrical and substantially identical with respect to the repair line RPL. The 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 can be mirror symmetrical with respect to the repair line RPL. In other words, the pixel circuits of two sub-pixels facing each other on the second direction DR2, with the first repair line RPL1 and the second repair line RPL2 interposed between them in the first region DA1, can be mirror symmetrical with respect to each other.

[0179] The signal lines can be arranged in a first region DA1 where the 11th sub-pixel SP11 and the 21st sub-pixel SP21 are located. For example, the first wiring WL1 to the fourteenth wiring WL14 can be arranged in the first region DA1.

[0180] The first wiring WL1 may extend along the first direction DR1 and may include a second insulating layer (see [reference]). Figure 6 "INS2" in the text and the third insulating layer (see Figure 6 The first conductive layer between "INS3" and the first wiring WL1 can be as shown in the above reference. Figure 3 The second scan line S2i is described. A region of the first wiring WL1 may be the gate electrode (hereinafter referred to as the "fourth gate electrode") of the fourth transistor T4 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0181] The second wiring WL2 may extend along the first direction DR1 and be spaced apart from the first wiring WL1. The second wiring WL2 may include a first conductive layer. The second wiring WL2 may be as described above. Figure 3The first scan line S1i is described. One region of the second wiring WL2 may be the gate electrode (hereinafter referred to as the "second gate electrode") of the second transistor T2 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21. Furthermore, another region of the second wiring WL2 may be the gate electrode (hereinafter referred to as the "third gate electrode") of the third transistor T3 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0182] The third wiring WL3 may extend along the first direction DR1 and be spaced apart from the first wiring WL1 and the second wiring WL2. The third wiring WL3 may include a first conductive layer. The third wiring WL3 may be as shown in the reference. Figure 3 The i-th emission control line Ei is described. One area of ​​the third wiring WL3 may be the gate electrode (hereinafter referred to as the "fifth gate electrode") of the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21. Furthermore, another area of ​​the third wiring WL3 may be the gate electrode (hereinafter referred to as the "sixth gate electrode") of the sixth transistor T6 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0183] The fourth wiring WL4 may extend along the first direction DR1 and be spaced apart from the first wiring WL1 to the third wiring WL3. The fourth wiring WL4 may include a first conductive layer. The fourth wiring WL4 may be as shown in the reference. Figure 3 The 3i scan line S3i is described. One area of ​​the fourth wiring WL4 may be the gate electrode (hereinafter referred to as the "seventh gate electrode") of the seventh transistor T7 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0184] The fifth wiring WL5 extends along the first direction DR1 and may include wiring disposed on the third insulation layer INS3 and the fourth insulation layer (see...). Figure 6 The second conductive layer between "INS4" and the fifth wiring WL5 can be a reference. Figure 3 The fourth power line described is PL4.

[0185] The sixth wiring WL6 extends along the first direction DR1 and may include wiring disposed on the fourth insulation layer INS4 and the fifth insulation layer (see...). Figure 6 The third conductive layer between "INS5" and the sixth wiring WL6 can be as shown in the reference. Figure 3 The second power line PL2 is described.

[0186] The seventh wiring WL7 extends along the first direction DR1 and may include wiring arranged on the fifth insulation layer INS5 and the sixth insulation layer (see...). Figure 6The fourth conductive layer between "INS6" in the diagram. The seventh wiring WL7 may be, but is not limited to, a dummy line overlapping the first wiring WL1, which includes the first conductive layer. According to an embodiment, the seventh wiring WL7 may be electrically connected to the first wiring WL1 to implement the first wiring WL1 as a dual structure.

[0187] The eighth wiring WL8 may extend in the first direction DR1 and be spaced apart from the seventh wiring WL7. The eighth wiring WL8 may include a fourth conductive layer. The eighth wiring WL8 may be a dummy line. In an embodiment, the eighth wiring WL8 may be electrically connected to the second wiring WL2, which includes a first conductive layer, thereby implementing the second wiring WL2 as a dual structure.

[0188] The ninth wiring WL9 may extend along the first direction DR1 and be spaced apart from the seventh wiring WL7 and the eighth wiring WL8. The ninth wiring WL9 may include a fourth conductive layer. The ninth wiring WL9 may be as shown in the reference. Figure 3 The first power line PL1 is described.

[0189] The tenth wiring WL10 may extend in the first direction DR1 and be spaced apart from the seventh wiring WL7 to the ninth wiring WL9. The tenth wiring WL10 may include a fourth conductive layer. The tenth wiring WL10 may be a dummy line overlapping the third wiring WL3, which includes a first conductive layer, in a plan view. According to an embodiment, the tenth wiring WL10 may be electrically connected to the third wiring WL3 to implement the third wiring WL3 as a dual structure.

[0190] The eleventh wiring WL11 may extend in the first direction DR1 and be spaced apart from the seventh wiring WL7 to the tenth wiring WL10. The eleventh wiring WL11 may include a fourth conductive layer. The eleventh wiring WL11 may be a dummy line overlapping with the fourth wiring WL4, which includes a first conductive layer. According to an embodiment, the eleventh wiring WL11 may be electrically connected to the fourth wiring WL4 through a corresponding contact hole CH to implement the fourth wiring WL4 as a dual structure.

[0191] The twelfth wiring WL12 may extend along the second direction DR2, which intersects with the first direction DR1, and may include wiring disposed on the sixth insulating layer INS6 and the seventh insulating layer (see...). Figure 6 The fifth conductive layer between "INS7" and the twelfth wiring WL12 can be as shown in the reference. Figure 3 The j-th data line Dj is described. The twelfth wiring WL12 can be electrically connected via the first conductive pattern CP1 to the second transistor T2 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0192] The first conductive pattern CP1 may include a fourth conductive layer. The first conductive pattern CP1 can be electrically connected to the twelfth wiring WL12 through a contact hole CH passing through the sixth insulating layer INS6. In addition, the first conductive pattern CP1 can be electrically connected to the semiconductor pattern SCP of the second transistor T2 in each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0193] The thirteenth wiring WL13 may extend in the second direction DR2 and may be spaced apart from the twelfth wiring WL12. The thirteenth wiring WL13 may include a fifth conductive layer. The thirteenth wiring WL13 may be electrically connected via a third conductive pattern CP3 to the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21.

[0194] The third conductive pattern CP3 may include a fourth conductive layer. The third conductive pattern CP3 can be electrically connected to the thirteenth wiring WL13 through a contact hole CH passing through the sixth insulating layer INS6. In addition, the third conductive pattern CP3 can be electrically connected to the semiconductor pattern SCP of the fifth transistor T5 of each of the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0195] The thirteenth wiring, WL13, can be referenced as follows. Figure 3 The first power line PL1 is described. The thirteenth wiring WL13 can be a vertical power line of the first power line PL1, and the ninth wiring WL9 can be a horizontal power line of the first power line PL1. The ninth wiring WL9 and the thirteenth wiring WL13 can be electrically connected to each other to form a mesh structure of the first power line PL1.

[0196] The fourteenth wiring WL14 extends in the second direction DR2 and is spaced apart from the twelfth wiring WL12 and the thirteenth wiring WL13. The fourteenth wiring WL14 may include a fifth conductive layer. The fourteenth wiring WL14 may be the (j+1)th data line adjacent to the j-th data line Dj.

[0197] The connection pattern CNP can be arranged between the thirteenth wiring WL13 and the fourteenth wiring WL14. The connection pattern CNP may include a fifth conductive layer. The connection pattern CNP may be a reference. Figure 6 The described connection line CNL. The connection pattern CNP can be electrically connected to the corresponding light-emitting element through the through-hole VIH passing through the seventh insulating layer INS7 (see...). Figure 3 The anode of the LED (see [reference]). Figure 3 (referring to "AE" in the original text). Furthermore, the connecting pattern CNP can be electrically connected to the fourth conductive pattern CP4 via the contact hole CH passing through the sixth insulating layer INS6.

[0198] The 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 can have substantially similar or identical structures. For example, the 11th pixel circuit PXC11 and the 21st pixel circuit PXC21 can be mirror-symmetric based on an imaginary line VL extending in the first direction DR1 between the first row R1 and the second row R2. In the following description, for convenience, we will focus primarily on the 11th pixel circuit PXC11, and overlapping descriptions will be omitted.

[0199] The 11th pixel circuit PXC11 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0200] The first transistor T1 may include a first active pattern ACT1 and a first gate electrode GE1.

[0201] The first active pattern ACT1 can be the region of the semiconductor pattern SCP that overlaps with the first gate electrode GE1 in a planar view. The first active pattern ACT1 can be the channel region of the first transistor T1.

[0202] The region of the semiconductor pattern SCP that does not overlap with the first gate electrode GE1 and is connected to one side of the first active pattern ACT1 (e.g., the first active pattern ACT1 is on the left side in the plan view) can be a first input / output terminal. The region of the semiconductor pattern SCP that does not overlap with the first gate electrode GE1 and is connected to the other side of the first active pattern ACT1 (e.g., the first active pattern ACT1 is on the right side in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the first active pattern ACT1, the semiconductor pattern SCP of the second transistor T2, and the semiconductor pattern SCP of the fifth transistor T5. The second input / output terminal can be connected to the other side of the first active pattern ACT1 and can be connected to the semiconductor pattern SCP of the sixth transistor T6.

[0203] The first gate electrode GE1 overlaps with the first active pattern ACT1 in the plan view and may include a first conductive layer. The first gate electrode GE1 may be an island-shaped conductive pattern. The first gate electrode GE1 may be electrically connected to the third transistor T3 and the fourth transistor T4 through the second conductive pattern CP2.

[0204] The second conductive pattern CP2 may include a fourth conductive layer. One end of the second conductive pattern CP2 may be electrically connected to the first gate electrode GE1 through a contact hole CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer INS3. The other end of the second conductive pattern CP2 may be electrically connected to the region of the semiconductor pattern SCP shared by the third transistor T3 and the fourth transistor T4 through a contact hole CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0205] The second transistor T2 may include a second active pattern ACT2 and a second gate electrode.

[0206] The second active pattern ACT2 can be the region of the semiconductor pattern SCP that overlaps with the second wiring WL2. The second active pattern ACT2 can be the channel region of the second transistor T2.

[0207] The region of the semiconductor pattern SCP that does not overlap with the second wiring WL2 in the plan view and is connected to one side of the second active pattern ACT2 (e.g., the second active pattern ACT2 is on the upper side of the plan view) can be a first input / output terminal. The region of the semiconductor pattern SCP that does not overlap with the second wiring WL2 and is connected to the other side of the second active pattern ACT2 (e.g., the second active pattern ACT2 is on the lower side of the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the second active pattern ACT2 and can be electrically connected to the first conductive pattern CP1. The first input / output terminal can be electrically connected to the twelfth wiring WL12 (or data line) through the first conductive pattern CP1. The second input / output terminal can be connected to the other side of the second active pattern ACT2 and can be connected to the first input / output terminal of the first transistor T1.

[0208] The second gate electrode can be the area of ​​the second wiring WL2 that overlaps with the second active pattern ACT2 in the plan view.

[0209] The third transistor T3 can be configured such that its sub-transistors are connected in series to prevent leakage current. For ease of description, the third transistor T3, which is formed on the bump of the second wiring WL2 among the sub-transistors described above, is taken as a representative example.

[0210] The third transistor T3 may include a third active pattern ACT3 and a third gate electrode.

[0211] The third active pattern ACT3 is the region of the semiconductor pattern SCP that overlaps with the protrusion protruding from the second wiring WL2 on the second direction DR2, and can form the channel region of the third transistor T3.

[0212] The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring WL2 in the plan view and is connected to one side of the third active pattern ACT3 (e.g., the third active pattern ACT3 is on the right side of the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the second wiring WL2 in the plan view and is connected to the other side of the third active pattern ACT3 (e.g., the third active pattern ACT3 is on the left side of the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the third active pattern ACT3 and can be electrically connected to the semiconductor pattern SCPs of the first transistor T1 and the sixth transistor T6. The second input / output terminal can be connected to the other side of the third active pattern ACT3 and is electrically connected to the semiconductor pattern SCP of the fourth transistor T4.

[0213] The third gate electrode can be the area of ​​the second wiring WL2 that overlaps with the third active pattern ACT3 in the planar diagram.

[0214] The fourth transistor T4 may be configured with sub-transistors connected in series to prevent leakage current. For ease of description, the fourth transistor T4, which is arranged closest to the third transistor T3 among the sub-transistors described above, is taken as a representative example.

[0215] The fourth transistor T4 may include a fourth active pattern ACT4 and a fourth gate electrode.

[0216] The fourth active pattern ACT4 is the region of the semiconductor pattern SCP that overlaps with the first wiring WL1, and can form the channel region of the fourth transistor T4.

[0217] The region of the semiconductor pattern SCP that does not overlap with the first wiring WL1 and is connected to one side of the fourth active pattern ACT4 (e.g., the fourth active pattern ACT4 is on the lower side in the plan view) can be a first input / output terminal. The region of the semiconductor pattern SCP that does not overlap with the first wiring WL1 in the plan view and is connected to the other side of the fourth active pattern ACT4 (e.g., the fourth active pattern ACT4 is on the upper side in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the fourth active pattern ACT4 and can be connected to the semiconductor pattern SCP of the third transistor T3. The second input / output terminal can be connected to the other side of the fourth active pattern ACT4 and electrically connected to the sixth wiring WL6 through the contact hole CH passing through the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0218] The fourth gate electrode can be the region of the first wiring WL1 that overlaps with the fourth active pattern ACT4.

[0219] The fifth transistor T5 may include a fifth active pattern ACT5 and a fifth gate electrode.

[0220] The fifth active pattern ACT5 is the area of ​​the semiconductor pattern SCP that overlaps with the third wiring WL3 in the planar diagram, and can form the channel region of the fifth transistor T5.

[0221] The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 and is connected to one side of the fifth active pattern ACT5 (e.g., the fifth active pattern ACT5 is on the lower side in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 in the plan view and is connected to the other side of the fifth active pattern ACT5 (e.g., the fifth active pattern ACT5 is on the upper side in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the fifth active pattern ACT5 and electrically connected to the third conductive pattern CP3 through a corresponding contact hole CH. The second input / output terminal can be connected to the other side of the fifth active pattern ACT5 and can be connected to the semiconductor pattern SCP of each of the first transistor T1 and the second transistor T2.

[0222] The sixth transistor T6 may include a sixth active pattern ACT6 and a sixth gate electrode.

[0223] The sixth active pattern ACT6 is the region of the semiconductor pattern SCP that overlaps with the third wiring WL3 in the planar diagram, and may be the channel region of the sixth transistor T6.

[0224] The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 and is connected to one side of the sixth active pattern ACT6 (e.g., the sixth active pattern ACT6 is on the upper side in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 and is connected to the other side of the sixth active pattern ACT6 (e.g., the sixth active pattern ACT6 is on the lower side in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the sixth active pattern ACT6 and the semiconductor pattern SCP of the first transistor T1. The second input / output terminal can be connected to the other side of the sixth active pattern ACT6 and the semiconductor pattern SCP of the seventh transistor T7. Furthermore, the second input / output terminal can be electrically connected to the fourth conductive pattern CP4 through a corresponding contact hole CH.

[0225] Fourth conductive pattern CP4 (or first contact electrode CNE1 (see...) Figure 22The device may include a fourth conductive layer. The fourth conductive pattern CP4 can be electrically connected to the second input / output terminal of the sixth transistor T6 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the fourth conductive pattern CP4 can be electrically connected to the connection pattern CNP through a corresponding contact hole CH. The second input / output terminal of the sixth transistor T6 can be electrically connected to the anode AE ​​of the light-emitting element LED through the fourth conductive pattern CP4 and the connection pattern CNP.

[0226] The sixth gate electrode can be the area of ​​the third wiring WL3 that overlaps with the sixth active pattern ACT6 in the planar diagram.

[0227] The seventh transistor T7 may include a seventh active pattern ACT7 and a seventh gate electrode.

[0228] The seventh active pattern ACT7 is the region of the semiconductor pattern SCP that overlaps with the fourth wiring WL4, and can be the channel region of the seventh transistor T7.

[0229] The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring WL4 and is connected to one side of the seventh active pattern ACT7 (e.g., the upper side of the seventh active pattern ACT7 in the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the fourth wiring WL4 in the plan view and is connected to the other side of the seventh active pattern ACT7 (e.g., the lower side of the seventh active pattern ACT7 in the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the seventh active pattern ACT7 and the semiconductor pattern SCP of the sixth transistor T6. The second input / output terminal can be connected to the other side of the seventh active pattern ACT7 and the fifth conductive pattern CP5.

[0230] The fifth conductive pattern CP5 may include a fourth conductive layer. The fifth conductive pattern CP5 can be electrically connected to the semiconductor pattern SCP of the seventh transistor T7 via contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the fifth conductive pattern CP5 can be connected to the fifth wiring WL5 via contact holes CH passing through the fifth insulating layer INS5 and the fourth insulating layer INS4.

[0231] The seventh gate electrode can be the region of the fourth wiring WL4 that overlaps with the seventh active pattern ACT7.

[0232] The storage capacitor Cst may include a lower electrode LE and an upper electrode UE.

[0233] The lower electrode LE can be integrally formed with the first gate electrode GE1. The lower electrode LE may include a first conductive layer.

[0234] The upper electrode UE overlaps with the lower electrode LE in the plan view and may include a second conductive layer. The upper electrode UE may include an opening region OPN by removing a portion of it. The area of ​​the lower electrode LE that overlaps with the upper electrode UE in the plan view may be exposed by the opening region OPN. The upper electrode UE can be electrically connected to the thirteenth wiring WL13 through contact holes CH that sequentially penetrate the sixth insulating layer INS6, the fifth insulating layer INS5, and the fourth insulating layer INS4.

[0235] In the first region DA1, repair lines RPL can be arranged between the first row R1 and the second row R2. Repair lines RPL can include a first repair line RPL1 and a second repair line RPL2 spaced apart relative to an imaginary line VL extending in the first direction DR1. The first repair line RPL1 can be located above the imaginary line VL, and the second repair line RPL2 can be located below the imaginary line VL. The first repair line RPL1 and the second repair line RPL2 can be spaced apart from each other and can be electrically isolated from each other.

[0236] The first repair line RPL1 and the second repair line RPL2 may extend in the first direction DR1. The first repair line RPL1 and the second repair line RPL2 may include a third conductive layer. The first repair line RPL1 and the second repair line RPL2 may be formed using the same process as the sixth wiring WL6. The first repair line RPL1 and the second repair line RPL2 may be disposed in the same layer as the sixth wiring WL6 and may include the same material as the sixth wiring WL6.

[0237] The first repair line RPL1 may be electrically connected to the first bridging pattern BRP1. The first bridging pattern BRP1 may be integrally formed with the first repair line RPL1. The first bridging pattern BRP1 may extend in the second direction DR2 and may protrude from the first repair line RPL1 in a direction toward the second repair line RPL2 (or the second row R2). In an embodiment, the first repair line RPL1 may be electrically connected to a first non-display area arranged adjacent to the first region DA1 (see [link to relevant documentation]). Figure 2 In the first row R1 and the second row R2 of “NDA1”, the first dummy pixel and the second dummy pixel (see Figure 2 One of "DP1 and DP2" in the list.

[0238] The second repair line RPL2 can be electrically connected to the second bridging pattern BRP2. The second bridging pattern BRP2 can be integrally formed with the second repair line RPL2. The second bridging pattern BRP2 can extend in the second direction DR2 and can protrude from the second repair line RPL2 in a direction toward the first repair line RPL1 or the first row R1. In an embodiment, the second repair line RPL2 can be electrically connected to another dummy pixel in the first dummy pixel DP1 and the second dummy pixel DP2 in each of the first row R1 and the second row R2 arranged in the first non-display area NDA1.

[0239] The first bridging pattern BRP1 and the second bridging pattern BRP2 are spaced apart and face each other in the first direction DR1. The first bridging pattern BRP1 and the first repair line RPL1 can be electrically isolated from the second bridging pattern BRP2 and the second repair line RPL2, respectively.

[0240] The fourth conductive pattern CP4 (or the first contact electrode CNE1) and the connection pattern CNP can be located at the connection point (or the fourth node, see [link to connection point]) that electrically connects the anode AE ​​of the 11th sub-pixel SP11 and the 11th pixel circuit PXC11. Figure 3 At point “N4” in the diagram. Furthermore, the semiconductor pattern SCP of each of the sixth transistor T6 and the seventh transistor T7, electrically connected to the fourth conductive pattern CP4, can be located at this connection point. The fourth conductive pattern CP4 can be electrically connected to the semiconductor pattern SCP of the sixth transistor T6 via a contact hole CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2.

[0241] In an embodiment, one end of each of the first bridging pattern BRP1 and the second bridging pattern BRP2 disposed between the first row R1 and the second row R2 may overlap with the fourth conductive pattern CP4 of the 11th sub-pixel SP11 of the first row R1, and the other end of each of the first bridging pattern BRP1 and the second bridging pattern BRP2 may overlap with the fourth conductive pattern CP4 of the 21st sub-pixel SP21 of the second row R2.

[0242] The corresponding repair lines RPL between the first repair line RPL1 and the second repair line RPL2, the first bridging pattern BRP1 and the second bridging pattern BRP2 may overlap with the fourth conductive pattern CP4 of each of the 11th sub-pixel SP11 and the 21st sub-pixel SP21. The first repair line RPL1 and the second repair line RPL2, the first bridging pattern BRP1 and the second bridging pattern BRP2 may be electrically isolated from the fourth conductive pattern CP4.

[0243] When a dark spot fault occurs in the 11th sub-pixel SP11, the semiconductor pattern SCP shared by the sixth transistor T6 and the seventh transistor T7 of the 11th sub-pixel SP11 and the light-emitting element (see...) Figure 3 The electrical connection between the anode AE ​​of the “LED” in the image can be broken, and the fourth conductive pattern CP4 and the first bridging pattern BRP1 of the 11th sub-pixel SP11 can be electrically connected to each other, so that the light-emitting element LED of the 11th sub-pixel SP11 can work normally.

[0244] Figure 13 This is a schematic plan view showing dummy pixels arranged in the first row R1 and the second row R2 in a region of the first non-display area NDA1 of a display device according to one embodiment. Figure 14 It only shows those included Figure 13 A schematic plan view of the configuration of the first transistor T1 to the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 in the first conductive layer. Figure 15 It only shows those included Figure 13 A schematic plan view of the configuration in the second conductive layer. Figure 16 It only shows those included Figure 13 A schematic plan view of the configuration in the third conductive layer. Figure 17 It only shows those included Figure 13 A schematic plan view of the configuration in the fourth conductive layer. Figure 18 It only shows those included Figure 13 A schematic plan view of the configuration in the fifth conductive layer.

[0245] Reference Figures 13 to 18 The main focus is on describing the differences from the embodiments described above, in order to avoid redundant descriptions.

[0246] refer to Figure 2 , Figure 4 as well as Figures 13 to 18 dummy pixels (see Figure 2The "DP" in the first non-display area NDA1 can be arranged in each of the first row R1 and the second row R2 in the same column on the second direction DR2. For example, the 11th dummy pixel DP11 (or the first dummy pixel) and the 12th dummy pixel DP12 (or the second dummy pixel) can be arranged in the first row R1, and the 21st dummy pixel DP21 (or the first dummy pixel) and the 22nd dummy pixel DP22 (or the second dummy pixel) can be arranged in the second row R2. The 11th dummy pixel DP11 and the 12th dummy pixel DP12 can be adjacent to each other on the first direction DR1, and the 21st dummy pixel DP21 and the 22nd dummy pixel DP22 can be adjacent to each other on the first direction DR1. The 11th dummy pixel DP11 in the first row R1 and the 21st dummy pixel DP21 in the second row R2 can be located in the same column, and the 12th dummy pixel DP12 in the first row R1 and the 22nd dummy pixel DP22 in the second row R2 can be located in the same column.

[0247] The 11th dummy pixel DP11 and the 12th dummy pixel DP12 can be arranged in relation to the reference. Figure 7 The 11th sub-pixel SP11 is described in the same row (e.g., the first row R1). The 21st dummy pixel DP21 and the 22nd dummy pixel DP22 can be arranged in the same row as the reference. Figure 7 In the same row as the 21st sub-pixel SP21 (e.g., the second row R2), the 12th dummy pixel DP12 can be directly adjacent to the 11th sub-pixel SP11, and the 22nd dummy pixel DP22 can be directly adjacent to the 21st sub-pixel SP21. In the first row R1, the 12th dummy pixel DP12 can be closer to the first region than the 11th dummy pixel DP11 (see [link to first row]). Figure 7 In the first region DA1 (or sub-pixel), the 22nd dummy pixel DP22 can be positioned closer to the first region DA1 (or sub-pixel) than the 21st dummy pixel DP21 in the second row R2.

[0248] A dummy pixel DP may include a dummy pixel circuit and a repair modulation circuit. For example, the 11th dummy pixel DP11 includes the 11th dummy pixel circuit DPC11 and the 11th repair modulation circuit RM11, and the 12th dummy pixel DP12 includes the 12th dummy pixel circuit DPC12 and the 12th repair modulation circuit RM12, the 21st dummy pixel DP21 includes the 21st dummy pixel circuit DPC21 and the 21st repair modulation circuit RM21, and the 22nd dummy pixel DP22 may include the 22nd dummy pixel circuit DPC22 and the 22nd repair modulation circuit RM22.

[0249] In this embodiment, the 11th dummy pixel DP11 and the 21st dummy pixel DP21 are arranged on the second direction DR2 and can face each other relative to the repair line RPL. The 12th dummy pixel DP12 and the 22nd dummy pixel DP22 are arranged on the second direction DR2 and can face each other relative to the repair line RPL. The 11th dummy pixel circuit DPC11 and the 21st dummy pixel circuit DPC21 can be symmetrical and substantially identical with respect to the repair line RPL, but are not limited thereto. The 11th dummy pixel circuit DPC11 and the 21st dummy pixel circuit DPC21 can be mirror symmetrical with respect to the repair line RPL. The 12th dummy pixel circuit DPC12 and the 22nd dummy pixel circuit DPC22 can be mirror symmetrical with respect to the repair line RPL.

[0250] Signal lines connected to the 11th dummy pixel DP11, the 12th dummy pixel DP12, the 21st dummy pixel DP21, and the 22nd dummy pixel DP22 can be arranged in the first non-display area NDA1. For example, the first wiring WL1 to the eleventh wiring WL11 can be arranged in the first non-display area NDA1. The first wiring WL1 to the eleventh wiring WL11 can be as shown in the reference. Figure 7 The first wiring WL1 to the eleventh wiring WL11 are described.

[0251] Furthermore, two first dummy lines DML1 and two second dummy lines DML2 may be arranged in the first non-display area NDA1. Each of the first dummy lines DML1 extends in the second direction DR2 and may include a arrangement in the sixth insulating layer (see [link to documentation]). Figure 6 "INS6" in the text and the seventh insulating layer (see Figure 6 The fifth conductive layer between "INS7" in the first dummy line DML1 can be as shown in the reference. Figure 4 The first dummy data line DD1 is described. Each of the first dummy lines DD1 can be electrically connected via a corresponding first conductive pattern CP1 to the second transistor T2 of each of the 11th dummy pixel circuit DPC11, the 12th dummy pixel circuit DPC12, the 21st dummy pixel circuit DPC21, and the 22nd dummy pixel circuit DPC22.

[0252] Each of the second dummy lines DML2 may extend in the second direction DR2 and may include a fifth conductive layer. Each of the second dummy lines DML2 may be as shown in the reference. Figures 7 to 12 The thirteenth wiring WL13 is described. Each of the second dummy lines DML2 can be electrically connected via the third conductive pattern CP3 to the fifth transistor T5 of each of the 11th dummy pixel circuit DPC11, the 12th dummy pixel circuit DPC12, the 21st dummy pixel circuit DPC21, and the 22nd dummy pixel circuit DPC22.

[0253] The 11th dummy pixel circuit DPC11, the 12th dummy pixel circuit DPC12, the 21st dummy pixel circuit DPC21, and the 22nd dummy pixel circuit DPC22 may have substantially similar or identical structures. For convenience, the following description will primarily focus on the 11th dummy pixel DP11, and overlapping descriptions will be omitted.

[0254] The 11th dummy pixel DP11 may include the 11th dummy pixel circuit DPC11 and the 11th repair modulation circuit RM11.

[0255] The 11th dummy pixel circuit DPC11 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, as well as a storage capacitor Cst. The first transistor T1 through the sixth transistor T6 are as shown in the reference... Figures 7 to 12 The first transistor T1 through the sixth transistor T6 are the same and therefore will not be described here.

[0256] The storage capacitor Cst may include a first lower electrode LE1 and a first upper electrode UE1. The first lower electrode LE1 may be as shown in the reference. Figures 7 to 12 The lower electrode LE is described, and the first upper electrode UE1 can be as referenced. Figures 7 to 12 The upper electrode UE is described. By removing a portion of the first upper electrode UE1, the first upper electrode UE1 may include a first opening region OPN1. A region of the first lower electrode LE1 that overlaps with the first upper electrode UE1 may be exposed by the first opening region OPN1. The first upper electrode UE1 may be exposed through the sixth insulating layer INS6, the fifth insulating layer (see...). Figure 6 "INS5" in the text and the fourth insulating layer (see Figure 6 The contact hole CH of “INS4” is electrically connected to the corresponding second dummy line DML2.

[0257] The 11th repair modulation circuit RM11 may include an eighth transistor T8, a ninth transistor T9, and a first capacitor C1.

[0258] The eighth transistor T8 may include an eighth active pattern ACT8 and an eighth gate electrode.

[0259] The eighth active pattern ACT8 can be the region of the semiconductor pattern SCP that overlaps with the third wiring WL3. The eighth active pattern ACT8 can be the channel region of the eighth transistor T8.

[0260] The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 in the plan view and is connected to one side of the eighth active pattern ACT8 (e.g., the eighth active pattern ACT8 is on the left side of the plan view) can be a first input / output terminal. The area of ​​the semiconductor pattern SCP that does not overlap with the third wiring WL3 in the plan view and is connected to the other side of the eighth active pattern ACT8 (e.g., the eighth active pattern ACT8 is on the right side of the plan view) can be a second input / output terminal. The first input / output terminal can be connected to one side of the eighth active pattern ACT8 and the sixth conductive pattern CP6. The second input / output terminal can be connected to the other side of the eighth active pattern ACT8 and the semiconductor pattern SCP of the ninth transistor T9.

[0261] The sixth conductive pattern CP6 may include the fourth conductive layer. The sixth conductive pattern CP6 can pass through the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer (see [link to documentation]). Figure 6 "INS3" in the middle) and the second insulating layer (see Figure 6 The contact hole CH of “INS2” is electrically connected to the first input / output terminal of the eighth transistor T8. Furthermore, the sixth conductive pattern CP6 can be electrically connected to the first additional conductive pattern ACP1 through the contact hole CH passing through the sixth insulating layer INS6.

[0262] The first additional conductive pattern ACP1 may include a fifth conductive layer disposed on the sixth insulating layer INS6. One end of the first additional conductive pattern ACP1 may be electrically connected to the sixth conductive pattern CP6 via a corresponding contact hole CH. The other end of the first additional conductive pattern ACP1 may be electrically connected to the second repair line RPL2 via a contact hole CH passing through the sixth insulating layer INS6, the fifth insulating layer INS5, and the fourth insulating layer INS4. The second repair line RPL2 may be electrically connected to the first input / output terminal of the eighth transistor T8 via the first additional conductive pattern ACP1 and the sixth conductive pattern CP6.

[0263] In this embodiment, the sixth conductive pattern CP6 can be electrically connected to the second lower electrode LE2 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, and the third insulating layer INS3. Furthermore, the sixth conductive pattern CP6 can be electrically connected to the first input / output terminal of the eighth transistor T8 through contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. The second input / output terminal of the eighth transistor T8 can be connected to the semiconductor pattern SCP of the ninth transistor T9.

[0264] The eighth gate electrode can be the area of ​​the third wiring WL3 that overlaps with the eighth active pattern ACT8 in the planar diagram.

[0265] The ninth transistor T9 may include a ninth active pattern ACT9 and a ninth gate electrode.

[0266] The ninth active pattern ACT9 can be the region of the semiconductor pattern SCP that overlaps with the fourth wiring WL4. The ninth active pattern ACT9 can be the channel region of the ninth transistor T9.

[0267] The region of the semiconductor pattern SCP that does not overlap with the fourth wiring WL4 and is connected to one side of the ninth active pattern ACT9 (e.g., the ninth active pattern ACT9 is on the upper side in the plan view) can be a first input / output terminal. The region of the semiconductor pattern SCP that does not overlap with the fourth wiring WL4 in the plan view and is connected to the other side of the ninth active pattern ACT9 (e.g., the ninth active pattern ACT9 is on the lower side in the plan view) can be a second input / output terminal. The first input / output terminal can be electrically connected to one side of the ninth active pattern ACT9 and the semiconductor pattern SCP of the eighth transistor T8. The second input / output terminal can be electrically connected to the other side of the ninth active pattern ACT9 and the seventh conductive pattern CP7.

[0268] The seventh conductive pattern CP7 may include a fourth conductive layer. The seventh conductive pattern CP7 can be electrically connected to the semiconductor pattern SCP of the ninth transistor T9 via contact holes CH passing through the fifth insulating layer INS5, the fourth insulating layer INS4, the third insulating layer INS3, and the second insulating layer INS2. Furthermore, the seventh conductive pattern CP7 can be electrically connected to the fifth wiring WL5 via contact holes CH passing through the fifth insulating layer INS5 and the fourth insulating layer INS4. First initialization power supply voltage (see...) Figure 4 The “Vint1” in the reference can be provided to the fifth routing WL5. The fifth routing WL5 can be as shown in the above reference. Figure 4 The second power line PL2 as described above or as referenced above Figure 3 The fourth power line PL4 is described. The fifth wiring WL5 can be electrically connected to the area of ​​the semiconductor pattern SCP of the ninth transistor T9 (e.g., the second input / output terminal) via the seventh conductive pattern CP7.

[0269] The ninth gate electrode can be the area of ​​the fourth wiring WL4 that overlaps with the ninth active pattern ACT9 in the planar diagram.

[0270] The first capacitor C1 may include a second lower electrode LE2 and a second upper electrode UE2.

[0271] The second lower electrode LE2 may be spaced apart from the first lower electrode LE1. The second lower electrode LE2 may include a first conductive layer. For example, the second lower electrode LE2 may be formed using the same process as the first lower electrode LE1 (or the first gate electrode GE1), may be disposed in the same layer as the first lower electrode LE1, and may include the same material as the first lower electrode LE1. The second lower electrode LE2 may be electrically connected to the semiconductor pattern SCP shared by the eighth transistor T8 and the ninth transistor T9 via the sixth conductive pattern CP6.

[0272] The second upper electrode UE2 may include a second conductive layer and overlaps with the second lower electrode LE2 while a third insulating layer INS3 is interposed therebetween. By removing a portion of the second upper electrode UE2, the second upper electrode UE2 may include a second opening region OPN2. A region of the second lower electrode LE2 that overlaps with the second upper electrode UE2 in a plan view may be exposed by the second opening region OPN2. The second upper electrode UE2 may be integrally formed with the first upper electrode UE1 and electrically connected to the second dummy line DML2.

[0273] In this implementation, the first and second dummy pixels arranged in the same row can be electrically connected to different repair lines RPL. For example, in the first row R1, the 11th dummy pixel DP11 can be electrically connected to the second repair line RPL2, and the 12th dummy pixel DP12 can be electrically connected to the first repair line RPL1. In the second row R2, the 21st dummy pixel DP21 can be electrically connected to the first repair line RPL1, and the 22nd dummy pixel DP22 can be electrically connected to the second repair line RPL2.

[0274] The 11th dummy pixel circuit DPC11 can be electrically connected to the second repair line RPL2 via the fourth conductive pattern CP4 of the second bridging pattern BRP2. The 11th repair modulation circuit RM11 can be electrically connected to the second repair line RPL2 via the first additional conductive pattern ACP1. The 12th dummy pixel circuit DPC12 can be electrically connected to the first repair line RPL1 via the fourth conductive pattern CP4. The 12th repair modulation circuit RM12 can be electrically connected to the first repair line RPL1 via the sixth conductive pattern CP6.

[0275] The 21st dummy pixel circuit DPC21 can be electrically connected to the first repair line RPL1 via the fourth conductive pattern CP4 of the first bridging pattern BRP1. The 21st repair modulation circuit RM21 can be electrically connected to the first repair line RPL1 via the second additional conductive pattern ACP2. The 22nd dummy pixel circuit DPC22 can be electrically connected to the second repair line RPL2 via the fourth conductive pattern CP4. The 22nd repair modulation circuit RM22 can be electrically connected to the second repair line RPL2 via the sixth conductive pattern CP6.

[0276] The second additional conductive pattern ACP2 may include a fifth conductive layer disposed on the sixth insulating layer INS6. One end of the second additional conductive pattern ACP2 may be electrically connected to the sixth conductive pattern CP6 of the 21st dummy pixel DP21 via a contact hole CH passing through the sixth insulating layer INS6. The other end of the second additional conductive pattern ACP2 may be electrically connected to the first repair line RPL1 via a contact hole CH passing through the sixth insulating layer INS6 and the fifth insulating layer INS5.

[0277] The dummy pixels DP in the first row R1 and the second row R2 in the same column can be electrically connected to different bridging patterns (or repair lines). For example, the fourth conductive pattern CP4 of the 11th dummy pixel DP11 in the first row R1 can be electrically connected to the second bridging pattern BRP2 (or the second repair line RPL2) through the corresponding contact hole CH, and the fourth conductive pattern CP4 of the 21st dummy pixel DP21 in the second row R2 can be electrically connected to the first bridging pattern BRP1 (or the first repair line RPL1) through the corresponding contact hole CH. Furthermore, the fourth conductive pattern CP4 of the 12th dummy pixel DP12 in the first row R1 can be electrically connected to the first repair line RPL1 (or the first bridging pattern BRP1) through the corresponding contact hole CH, and the fourth conductive pattern CP4 of the 22nd dummy pixel DP22 in the second row R2 can be electrically connected to the second repair line RPL2 (or the second bridging pattern BRP2) through the corresponding contact hole CH.

[0278] In the first row R1, the first capacitor C1 of the 11th dummy pixel DP11 and the first capacitor C1 of the 12th dummy pixel DP12 can be spaced apart from each other. For example, the 11th dummy pixel circuit DPC11 of the 11th dummy pixel DP11 can be arranged between the first capacitor C1 of the 11th dummy pixel DP11 and the first capacitor C1 of the 12th dummy pixel DP12. In the second row R2, the first capacitor C1 of the 21st dummy pixel DP21 and the first capacitor C1 of the 22nd dummy pixel DP22 can be spaced apart from each other. For example, the 21st dummy pixel circuit DPC21 of the 21st dummy pixel DP21 can be arranged between the first capacitor C1 of the 21st dummy pixel DP21 and the first capacitor C1 of the 22nd dummy pixel DP22. In the following text, for ease of explanation, the first capacitor C1 of the 11th dummy pixel DP11 is referred to as the 1-1 capacitor, the first capacitor C1 of the 12th dummy pixel DP12 is referred to as the 1-2 capacitor, the first capacitor C1 of the 21st dummy pixel DP21 is referred to as the 1-3 capacitor, and the first capacitor C1 of the 22nd dummy pixel DP22 is referred to as the 1-4 capacitor.

[0279] In an embodiment, the size of the first-1 capacitor C1 may be larger than that of the first-2 capacitor C1, and the size of the first-3 capacitor C1 may be larger than that of the first-4 capacitor C1.

[0280] Capacitors C1-1 and C1-3 may have the same dimensions, and capacitors C1-2 and C1-4 may have the same dimensions. However, this disclosure is not limited thereto. According to embodiments, capacitor C1-1 may be larger than capacitor C1-3, or vice versa, and capacitor C1-2 may be larger than capacitor C1-4, or vice versa.

[0281] In each of the first row R1 and the second row R2, the first capacitor C1 of the first dummy pixel located away from the first region DA1 (or sub-pixel) can have a larger size than the first capacitor C1 of the second dummy pixel located adjacent to the first region DA1 (or sub-pixel). Since the second dummy pixel is located closer to the first region DA1 (or sub-pixel) than the first dummy pixel, the load of the repair line RPL that electrically connects the sub-pixel with a dark spot fault in the first region DA1 (hereinafter referred to as the "defective sub-pixel") and the second dummy pixel can be smaller than the load of the repair line RPL that electrically connects the defective sub-pixel and the first dummy pixel. Therefore, in the above embodiment, the first capacitor C1 of the first dummy pixel can be designed to have a larger size than the first capacitor C1 of the second dummy pixel to compensate for the difference between the load of the repair line RPL connected to the first dummy pixel and the load of the repair line RPL connected to the second dummy pixel.

[0282] In the first row R1, the first-1 capacitor C1 of the 11th dummy pixel DP11, which is located further away from the first region DA1 than the 12th dummy pixel DP12, can have a larger size than the first-2 capacitor C1 of the 12th dummy pixel DP12. The overlapping area of ​​the second lower electrode LE2 and the second upper electrode UE2 constituting the first-1 capacitor C1 can be larger than the overlapping area of ​​the second lower electrode LE2 and the second upper electrode UE2 constituting the first-2 capacitor C1. Therefore, the capacitance of the first-1 capacitor C1 can be larger than the capacitance of the first-2 capacitor C1.

[0283] In the second row R2, the first-third capacitor C1 of the 21st dummy pixel DP21, which is located further away from the first region DA1 than the 22nd dummy pixel DP22, can have a larger size than the first-fourth capacitor C1 of the 22nd dummy pixel DP22. The overlapping area of ​​the second lower electrode LE2 and the second upper electrode UE2 constituting the first-third capacitor C1 can be larger than the overlapping area of ​​the second lower electrode LE2 and the second upper electrode UE2 constituting the first-fourth capacitor C1. Therefore, the capacitance of the first-third capacitor C1 can be greater than the capacitance of the first-fourth capacitor C1.

[0284] Figure 19 This is a schematic plan view showing dummy pixels arranged in the first row R1 and the second row R2 in a portion of the first non-display area NDA1 of a display device according to one embodiment. Figure 20 It only shows those included Figure 19 A schematic plan view of the configuration of the first transistor T1 to the sixth transistor T6, the eighth transistor T8 and the ninth transistor T9 in the first conductive layer. Figure 21 It only shows those included Figure 19 A schematic plan view of the configuration in the second conductive layer.

[0285] Reference Figures 19 to 21 The main focus is on describing the differences from the embodiments described above, in order to avoid redundant descriptions.

[0286] refer to Figure 2 as well as Figures 19 to 21 dummy pixels (see Figure 2 The "DP" in the first non-display area NDA1 can be arranged in each of the first row R1 and the second row R2. For example, the 11th dummy pixel DP11 (or the first dummy pixel) and the 12th dummy pixel DP12 (or the second dummy pixel) arranged on the first direction DR1 can be arranged in the first row R1 (or the first pixel row). The 21st dummy pixel DP21 (or the first dummy pixel) and the 22nd dummy pixel DP22 (or the second dummy pixel) arranged on the first direction DR1 can be arranged in the second row R2 (or the second pixel row).

[0287] In the implementation, the first capacitor C1 of the 11th dummy pixel DP11 and the first capacitor C1 of the 12th dummy pixel DP12 can be arranged adjacent to each other, and the first capacitor C1 of the 21st dummy pixel DP21 and the first capacitor C1 of the 22nd dummy pixel DP22 can be arranged adjacent to each other.

[0288] The first capacitor C1 of the 11th dummy pixel DP11 (hereinafter referred to as "capacitor 1-1") may include a second lower electrode LE2 and a second upper electrode UE2. The first capacitor C1 of the 12th dummy pixel DP12 (hereinafter referred to as "capacitor 1-2") may include a second lower electrode LE2 and a second upper electrode UE2. The second lower electrode LE2 of capacitor 1-1 and capacitor 1-2 may include a first conductive layer and may be spaced apart from each other. When viewed in a plane, the size of the second lower electrode LE2 of capacitor 1-1 may be larger than the size of the second lower electrode LE2 of capacitor 1-2.

[0289] In an embodiment, the second upper electrode UE2 of the first-1 capacitor C1 and the second upper electrode UE2 of the first-2 capacitor C1 can be integrally formed and connected to each other. The second upper electrode UE2 of the first-1 capacitor C1 and the second upper electrode UE2 of the first-2 capacitor C1 can be a first common electrode COM1 commonly disposed on the 11th dummy pixel DP11 and the 12th dummy pixel DP12. The first common electrode COM1 can be large enough to cover the second lower electrode LE2 of the first-1 capacitor C1 and the second lower electrode LE2 of the first-2 capacitor C1. The first common electrode COM1 can include a second conductive layer and overlap with the second lower electrode LE2 of the first-1 capacitor C1 and the second lower electrode LE2 of the first-2 capacitor C1, and a third insulating layer (see...) Figure 6 The "INS3" in the figure is inserted between the first common electrode COM1 and the second lower electrode LE2 of the first-1 capacitor C1 and the second lower electrode LE2 of the first-2 capacitor C1. The overlap area between the second lower electrode LE2 of the first-1 capacitor C1 and the first common electrode COM1 can be greater than the overlap area between the second lower electrode LE2 of the first-2 capacitor C1 and the first common electrode COM1. Therefore, the capacitance of the first capacitor C1 can be greater than the capacitance of the first capacitor C1. In other words, the capacitance of the first capacitor C1 of the 11th dummy pixel DP11 can be greater than the capacitance of the first capacitor C1 of the 12th dummy pixel DP12.

[0290] The first capacitor C1 of dummy pixel DP21 (hereinafter referred to as "capacitor 1-3") may include a second lower electrode LE2 and a second upper electrode UE2. The first capacitor C1 of dummy pixel DP22 (hereinafter referred to as "capacitor 1-4") may include a second lower electrode LE2 and a second upper electrode UE2. The second lower electrode LE2 of capacitor 1-3 and capacitor 1-4 may include a first conductive layer and are spaced apart from each other. When viewed in a plane, the size of the second lower electrode LE2 of capacitor 1-3 may be larger than the size of the second lower electrode LE2 of capacitor 1-4.

[0291] In this embodiment, the second upper electrode UE2 of the first-3 capacitors C1 and the second upper electrode UE2 of the first-4 capacitors C1 can be integrally formed and connected to each other. The second upper electrode UE2 of the first-3 capacitors C1 and the second upper electrode UE2 of the first-4 capacitors C1 can be commonly disposed on the second common electrode COM2 of the 21st dummy pixel DP21 and the 22nd dummy pixel DP22. The second common electrode COM2 can be large enough to cover the second lower electrode LE2 of the first-3 capacitors C1 and the second lower electrode LE2 of the first-4 capacitors C1. The second common electrode COM2 can include a second conductive layer and overlap with the second lower electrode LE2 of the first-3 capacitors C1 and the second lower electrode LE2 of the first-4 capacitors C1, and a third insulating layer INS3 is inserted between the second common electrode COM2 and the second lower electrode LE2 of the first-3 capacitors C1 and the second lower electrode LE2 of the first-4 capacitors C1. The overlapping area of ​​the second lower electrode LE2 and the second common electrode COM2 of capacitors C1-3 can be greater than the overlapping area of ​​the second lower electrode LE2 and the second common electrode COM2 of capacitors C1-4. Therefore, the capacitance of capacitor C1-3 can be greater than the capacitance of capacitor C1-4. For example, the capacitance of the first capacitor C1 of dummy pixel DP21 can be greater than the capacitance of the first capacitor C1 of dummy pixel DP22.

[0292] Figure 22 It is used to illustrate sub-pixels in a first region DA1 and dummy pixels in a first non-display region NDA1 in a display device according to one embodiment. Figure 2 A partial schematic diagram of EA1.

[0293] exist Figure 22 For ease of description, only the first repair line RPL1 and the second repair line RPL2 between the first row R1 and the second row R2 of the signal wiring arranged in each of the first display area DA1 and the first non-display area NDA1 are shown.

[0294] refer to Figure 22 This section primarily describes the differences from the embodiments described above, in order to avoid overlapping descriptions.

[0295] refer to Figure 2 and Figure 22 In the first region DA1 (or the first display area), each of the first row R1 and the second row R2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged on the first direction DR1. The first sub-pixel SP1 may be arranged in the first pixel column PC1, the second sub-pixel SP2 may be arranged in the second pixel column PC2, and the third sub-pixel SP3 may be arranged in the third pixel column PC3. Each of the first sub-pixel SP1 to the third sub-pixel SP3 may include pixel circuitry (see...). Figure 3 The first sub-pixel SP1 of the first row R1 may include the 11th pixel circuit PXC11 and the LED, the second sub-pixel SP2 of the first row R1 may include the 12th pixel circuit PXC12 and the LED, and the third sub-pixel SP3 of the first row R1 may include the 13th pixel circuit PXC13 and the LED. Similarly, the first sub-pixel SP1 of the second row R2 may include the 21st pixel circuit PXC21 and the LED, the second sub-pixel SP2 of the second row R2 may include the 22nd pixel circuit PXC22 and the LED, and the third sub-pixel SP3 of the second row R2 may include the 23rd pixel circuit PXC23 and the LED.

[0296] The pixel circuit PXC of each of the first sub-pixels SP1 to the third sub-pixels SP3 may include a first contact electrode CNE1. The first contact electrode CNE1 may be electrically connected to a light-emitting element (LED). The first contact electrode CNE1 may be as described above. Figures 7 to 12 The fourth conductive pattern CP4 is described.

[0297] The first contact electrode CNE1 can electrically connect the light-emitting element (LED) and the pixel circuit (PXC) in certain configurations. For example, the first contact electrode CNE1 can electrically connect the light-emitting element (LED) and the sixth transistor of the pixel circuit (PXC) through a corresponding contact hole CH (see...). Figure 3 (T6 in the text). The first contact electrode CNE1 can be located at the connection point in each sub-pixel that electrically connects the light-emitting element LED and the pixel circuit PXC (or... Figure 3 The fourth node (N4) is located at this point. In the following text, for ease of description, the contact hole CH (or connection device) that electrically connects the light-emitting element LED, the first contact electrode CNE1, and the sixth transistor T6 of the pixel circuit PXC will be referred to as the first contact hole CH1.

[0298] In the first non-display area NDA1, each of the first row R1 and the second row R2 may include a first dummy pixel DP1 and a second dummy pixel DP2. The first dummy pixel DP1 may be arranged in the first dummy column DC1, and the second dummy pixel DP2 may be arranged in the second dummy column DC2. Each of the first dummy pixel DP1 and the second dummy pixel DP2 may include a dummy pixel circuit and a first capacitor C1 electrically connected to each other. For example, the first dummy pixel DP1 may include a first dummy pixel circuit DPC1 and a first capacitor C1, and the second dummy pixel DP2 may include a second dummy pixel circuit DPC2 and a first capacitor C1. The first capacitor C1 of the first dummy pixel DP1 may have a larger size than the first capacitor C1 of the second dummy pixel DP2.

[0299] Each of the first dummy pixel circuit DPC1 and the second dummy pixel circuit DPC2 may include a second contact electrode CNE2 electrically connected to the repair line RPL. The second contact electrode CNE2 may be as shown in the reference. Figures 13 to 18 The fourth conductive pattern CP4 is described. The second contact electrode CNE2 can be electrically connected to the repair line RPL through a corresponding contact hole CH. The contact hole CH can be located at the connection point where the repair line RPL and the second contact electrode CNE2 are electrically connected at each dummy pixel. The second contact electrode CNE2 of each dummy pixel can overlap with the first bridging pattern BRP1 and the second bridging pattern BRP2. The second contact electrode CNE2 of each dummy pixel can be electrically connected to one of the first bridging pattern BRP1 and the second bridging pattern BRP2.

[0300] In an implementation, the size of the first capacitor C1 of the first dummy pixel DP1 can be larger than the size of the first capacitor C1 of the second dummy pixel DP2. To compensate for the difference in load of the repair line RPL based on the positions of the first dummy pixel DP1 and the second dummy pixel DP2, the first capacitor C1 of the first dummy pixel DP1 can be designed to have a larger size than the first capacitor C1 of the second dummy pixel DP2.

[0301] In each of the first non-display area NDA1 and the first area DA1, a first repair line RPL1 and a second repair line RPL2 may be arranged between the first row R1 and the second row R2. The first repair line RPL1 may be integrally formed with the first bridging pattern BRP1, and the second repair line RPL2 may be integrally formed with the second bridging pattern BRP2.

[0302] In the first region DA1, the first bridging pattern BRP1 and the second bridging pattern BRP2 can extend along the second direction DR2 between sub-pixels in the first row R1 and sub-pixels in the second row R2. For example, the first bridging pattern BRP1 and the second bridging pattern BRP2 can extend along the second direction DR2 between the first sub-pixel SP1 in the first row R1 and the first sub-pixel SP1 in the second row R2, between the second sub-pixel SP2 in the first row R1 and the second sub-pixel SP2 in the second row R2, and between the third sub-pixel SP3 in the first row R1 and the third sub-pixel SP3 in the second row R2.

[0303] In the first region DA1, the first bridging pattern BRP1 and the second bridging pattern BRP2 may overlap with the first contact electrode CNE1 of each sub-pixel. Each of the first bridging pattern BRP1 and the second bridging pattern BRP2 may be electrically isolated from the first contact electrode CNE1.

[0304] The first repair line RPL1 can be electrically connected to the dummy pixel circuit of one of the first dummy pixel DP1 and the second dummy pixel DP2, and the second repair line RPL2 can be electrically connected to the dummy pixel circuit of the remaining dummy pixels in the first dummy pixel DP1 and the second dummy pixel DP2. For example, each of the second dummy pixel DP2 (or second dummy pixel circuit DPC2) in the first row R1 and the first dummy pixel DP1 (or first dummy pixel circuit DPC1) in the second row R2 is electrically connected to the first repair line RPL1 through a corresponding second contact electrode CNE2. Each of the first dummy pixel DP1 (or first dummy pixel circuit DPC1) in the first row R1 and the second dummy pixel DP2 (or second dummy pixel circuit DPC2) in the second row R2 can be electrically connected to the second repair line RPL2 through a corresponding second contact electrode CNE2.

[0305] The first repair line RPL1 and the second repair line RPL2 can be electrically isolated from the pixel circuits of each of the first sub-pixels SP1 to SP3 located in the first region DA1.

[0306] Typically, display devices (see...) Figure 2 The “DD” in the text can be used to specify the area to be placed in the display area (see [link]). Figure 2 Subpixels in “DA” (see Figure 2 The light-emitting element LED (SP) in the text performs an illumination check. When the illumination check indicates that some of the light-emitting element LEDs are not lit and the sub-pixel SP is dimmed, a repair process can be performed by electrically connecting the unlit light-emitting element LEDs to the first dummy pixel DP1 and the second dummy pixel DP2 to drive the light-emitting element LEDs.

[0307] The following describes a method for repairing defective subpixels SP in the first region DA1.

[0308] Figure 23 This is a schematic flowchart illustrating a method for repairing a display device according to one embodiment. Figure 24 Is with Figure 2 The diagram corresponding to part EA1 illustrates the method for repairing defective sub-pixels. Figure 25 It shows the arrangement in Figure 24 A schematic circuit diagram showing the electrical connection of the first sub-pixel SP1 and the second dummy pixel DP2 in the first row.

[0309] Reference Figures 23 to 25 The implementation methods described herein mainly differ from those described above in order to avoid overlapping descriptions.

[0310] refer to Figures 23 to 25 In step S100, dummy pixels (see...) can be provided. Figure 2 "DP" in the text) and sub-pixels (see Figure 2 The display device for "SP" in (see Figure 2 (DD in the text).

[0311] In step S200, the repair method can detect the first area DA1 (or the first display area) and the second area (see...) Figure 2 Dark spot defects in each subpixel SP in “DA2” (or the second display area).

[0312] In step S300, when two sub-pixels in the first row R1 of the first region DA1 have a dark spot fault, the first dummy pixel arranged in the first row R1 of the first non-display region NDA1 (see...) can be removed. Figure 2 "DP1" in the second dummy pixel (see "DP1") and the second dummy pixel (see Figure 2 The “DP2” in the diagram is electrically connected to two sub-pixels to repair the dark spot faults of the two sub-pixels.

[0313] For example, the repair process may include using a laser to interrupt the electrical connection between the light source element and the pixel circuitry in a subpixel with a dark spot fault, and using a laser to perform a bonding process to electrically connect the light source element to a dummy pixel DP arranged in the same row as the subpixel with the dark spot fault via a repair line (“RPL”), so that the light source element can function normally.

[0314] like Figure 24As shown, when a dark spot fault occurs simultaneously in the first sub-pixel SP1 and the third sub-pixel SP3 arranged in the first row R1, a repair process can be performed to electrically connect the first sub-pixel SP1 to the second dummy pixel DP2 arranged in the first row R1 and to electrically connect the third sub-pixel SP3 to the first dummy pixel DP1 arranged in the first row R1. The dark spot fault in each of the first sub-pixel SP1 and the third sub-pixel SP3 may be caused by, for example, a defect in the pixel circuitry.

[0315] When the 11th pixel circuit PXC11 of the first sub-pixel SP1 is defective, a laser can be used to disconnect the anode AE ​​of the light-emitting element LED (hereinafter referred to as the "first light-emitting element") electrically connected to the 11th pixel circuit PXC11 from the sixth transistor T6 and the seventh transistor T7 of the 11th pixel circuit PXC11. Therefore, the anode AE ​​can be electrically disconnected from the sixth transistor T6 and the seventh transistor T7. A contact hole CH (or a second contact hole CH2) can be formed between the first contact electrode CNE1, which is electrically connected to the anode AE ​​(or the first light-emitting element LED) through the first contact hole CH1, and the first bridging pattern BRP1 by using a laser bonding process to destroy the insulating layer.

[0316] Through contact hole CH (or second contact hole CH2), first contact electrode CNE1, and first contact hole CH1, the first bridging pattern BRP1 (or first repair line RPL1) and the anode AE ​​(or first light-emitting element LED) can be electrically connected. The first repair line RPL1 is electrically connected to the second dummy pixel DP2 arranged in the first row R1 of the first non-display area NDA1, allowing the second dummy pixel circuit DPC2 of the second dummy pixel DP2 and the first light-emitting element LED of the first sub-pixel SP1 to be electrically connected. Therefore, the first repair line RPL1 forms an electrical path from the second dummy pixel DP2 to the first light-emitting element LED of the first sub-pixel SP1, enabling the first light-emitting element LED to operate normally and repairing the first sub-pixel SP1 with dark spot defects.

[0317] When a dark spot fault occurs in the third sub-pixel SP3, which is arranged in the same row as the first sub-pixel SP1, the anode AE ​​of the light-emitting element LED (hereinafter referred to as the "second light-emitting element") of the 13th pixel circuit PXC13, which is electrically connected to the third sub-pixel SP3, can be disconnected from the sixth transistor T6 and the seventh transistor T7 of the 13th pixel circuit PXC13. Therefore, the anode AE ​​of the second light-emitting element LED can be electrically disconnected from the sixth transistor T6 and the seventh transistor T7. A contact hole CH (or a second contact hole CH2) can be formed between the first contact electrode CNE1, which is electrically connected to the anode AE ​​of the second light-emitting element LED through the first contact hole CH1, and the second bridging pattern BRP2 by using a laser bonding process to break the insulating layer.

[0318] The second bridging pattern BRP2 (or the second repair line RPL2) and the anode AE ​​of the second light-emitting element LED can be electrically connected through the contact hole CH (or the second contact hole CH2), the first contact electrode CNE1, and the first contact hole CH1. The second repair line RPL2 is electrically connected to the first dummy pixel DP1 arranged in the first row R1 of the first non-display area NDA1, so that the first dummy pixel circuit DPC1 of the first dummy pixel DP1 and the second light-emitting element LED of the third sub-pixel SP3 can be electrically connected. Therefore, the second repair line RPL2 forms an electrical path from the first dummy pixel DP1 to the second light-emitting element LED of the third sub-pixel SP3, so that the second light-emitting element LED can operate normally and the third sub-pixel SP3 with dark spot defects can be repaired.

[0319] As described above, when a dark spot fault occurs in two sub-pixels arranged in the first row R1 of the first region DA1, the light-emitting element (LED) of one of the two sub-pixels is electrically connected to the dummy pixel circuit of one of the first dummy pixels DP1 and the second dummy pixel DP2 arranged in the first row R1 of the first non-display region NDA1 within a horizontal time. Similarly, the light-emitting element (LED) of the other sub-pixel can be electrically connected to the dummy pixel circuit of the other of the first dummy pixels DP1 and the second dummy pixel DP2. Therefore, the dark spot defect in two sub-pixels in one row (or one pixel row) of the first region DA1 can be repaired.

[0320] Furthermore, as described above, the first capacitor C1 of the first dummy pixel DP1, which is located far from the first region DA1 (or sub-pixel), can be designed to be larger than the first capacitor C1 of the second dummy pixel DP2, in order to reduce the load difference of the repair line RPL based on the positions of the first dummy pixel DP1 and the second dummy pixel DP2.

[0321] In the above embodiments, for ease of description, the first region DA1 is mainly described; however, this disclosure is not limited thereto, and it may also be in the second region (see...). Figure 2 In the "DA2" section, any sub-pixel with a dark spot defect is repaired. For example, when two sub-pixels in the first row of the second region DA2 (or the second display area) have a dark spot defect, the light-emitting element (LED) of one of the two sub-pixels is electrically connected to a sub-pixel arranged in the second non-display area (see...). Figure 2 The third and fourth dummy pixels in the first row of “NDA2” (see Figure 2 The dummy pixel circuit of one of the dummy pixels (DP3 and DP4) in the second region DA2 is connected to the dummy pixel circuit of another dummy pixel between the third dummy pixel DP3 and the fourth dummy pixel DP4. Therefore, dark spot defects of two sub-pixels in a row (or a pixel row) in the second region DA2 can be repaired.

[0322] According to the above implementation, by simultaneously repairing the dark spot defects of two sub-pixels in a row (or a pixel row) of each of the first region DA1 (or the first display area) and the second region DA2 (or the second display area), the number of repairable sub-pixels in a horizontal time period can be increased, thereby increasing product yield.

[0323] Figure 26 Is with Figure 2 The diagram corresponding to EA1 illustrates a method for repairing defective sub-pixels. Specifically, Figure 26 The electrical paths for dummy pixels and defective sub-pixels are shown. Figure 24 Example of modification.

[0324] about Figure 26 To avoid redundancy, the implementation method described below will primarily differ from the implementation method described above.

[0325] refer to Figure 2 and Figure 26 In the first row R1, when the 11th pixel circuit PXC11 of the first sub-pixel SP1 and the 13th pixel circuit PXC13 of the third sub-pixel SP3 are defective, the light-emitting element LED of the first sub-pixel SP1 (hereinafter referred to as the "1-1 light-emitting element") is electrically connected to the first dummy pixel DP1 arranged in the first row R1, and the light-emitting element LED of the third sub-pixel SP3 (hereinafter referred to as the "second light-emitting element") is electrically connected to the second dummy pixel DP2 arranged in the first row R1. The first dummy pixel circuit DPC1 of the first dummy pixel DP1 can be electrically connected to the second repair line RPL2, and the second dummy pixel circuit DPC2 of the second dummy pixel DP2 can be electrically connected to the first repair line RPL1.

[0326] More specifically, the electrical connection between the first light-emitting element LED and some configurations of the 11th pixel circuit PXC11 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 and the second bridging pattern BRP2 of the first sub-pixel SP1 to electrically connect the first light-emitting element LED to the second repair line RPL2 connected to the second bridging pattern BRP2, so that the first light-emitting element LED can be electrically connected to the first dummy pixel circuit DPC1 of the first dummy pixel DP1.

[0327] Furthermore, the electrical connection between the second light-emitting element LED and some configurations of the 13th pixel circuit PXC13 is released, and a contact hole CH (or a second contact hole CH2) is formed between the first contact electrode CNE1 and the first bridging pattern BRP1 of the third sub-pixel SP3 to electrically connect the second light-emitting element LED and the first repair line RPL1 connected to the first bridging pattern BRP1, so that the second light-emitting element LED can be electrically connected to the second dummy pixel circuit DPC2 of the second dummy pixel DP2.

[0328] As described above, the second repair line RPL2 forms an electrical path from the first dummy pixel DP1 to the first sub-pixel SP1 with a dark spot defect, and the first repair line RPL1 forms an electrical path from the second dummy pixel DP2 to the second sub-pixel SP3 with a dark spot defect, forming an electrical path for the second light-emitting element LED. Therefore, signal delay caused by the difference in electrical paths between the dummy pixel and the sub-pixel with the dark spot defect can be reduced or prevented. In other words, signal delay caused by the difference in length between the first repair line RPL1 and the second repair line RPL2 that electrically connects the dummy pixel and the defective sub-pixel can be reduced or prevented.

[0329] Figure 27 It is used to illustrate sub-pixels in the second region DA2 and dummy pixels in the second non-display region NDA2 in a display device according to one embodiment. Figure 2 A partial schematic diagram of EA2.

[0330] refer to Figure 27 This section primarily describes the differences from the embodiments described above, in order to avoid overlapping descriptions.

[0331] refer to Figure 2 and Figure 27In the second region DA2 (or the second display area), each of the first row R1 and the second row R2 may include a third sub-pixel SP3, a second sub-pixel SP2, and a first sub-pixel SP1 arranged in the first direction DR1. Based on the boundary between the second region DA2 and the second non-display area NDA2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be arranged sequentially in a direction opposite to the first direction DR1. Each of the first sub-pixel SP1 to the third sub-pixel SP3 may include pixel circuitry (see...). Figure 3 The pixel circuit PXC of each of the first sub-pixels SP1 to the third sub-pixels SP3 may include a first contact electrode CNE1. The first contact electrode CNE1 may be electrically connected to the light-emitting element LED through a corresponding contact hole CH.

[0332] The third dummy pixel DP3 and the fourth dummy pixel DP4 can be arranged in each of the first row R1 and the second row R2 of the second non-display area NDA2. The third dummy pixel DP3 can be arranged in the third dummy column DC3, and the fourth dummy pixel DP4 can be arranged in the fourth dummy column DC4. Each of the third dummy pixel DP3 and the fourth dummy pixel DP4 may include a dummy pixel circuit and a first capacitor C1 electrically connected to each other. For example, the third dummy pixel DP3 may include a third dummy pixel circuit DPC3 and a first capacitor C1, and the fourth dummy pixel DP4 may include a fourth dummy pixel circuit DPC4 and a first capacitor C1. The first capacitor C1 of the fourth dummy pixel DP4 may have a larger size than the first capacitor C1 of the third dummy pixel DP3.

[0333] Each of the third dummy pixel circuit DPC3 and the fourth dummy pixel circuit DPC4 may include a second contact electrode CNE2 electrically connected to the repair line RPL. The second contact electrode CNE2 may be electrically connected to the repair line RPL through a corresponding contact hole CH.

[0334] In an implementation, the first capacitor C1 of the fourth dummy pixel DP4 can have a larger size than the first capacitor C1 of the third dummy pixel DP3. In each of the first row R1 and the second row R2, the first capacitor C1 of the fourth dummy pixel DP4, located away from the second region DA2 (or sub-pixel), can have a larger size than the first capacitor C1 of the third dummy pixel DP3, located adjacent to the second region DA2 (or sub-pixel). Since the third dummy pixel DP3 is located closer to the second region DA2 than the fourth dummy pixel DP4, the load of the repair line RPL that electrically connects the sub-pixel with the dark spot fault in the second region DA2 and the third dummy pixel DP3 can be smaller than the load of the repair line RPL that electrically connects the sub-pixel with the dark spot fault and the fourth dummy pixel DP4. Therefore, in order to compensate for the difference between the load of the repair line RPL connected to the third dummy pixel DP3 and the load of the repair line RPL connected to the fourth dummy pixel DP4, the first capacitor C1 of the fourth dummy pixel DP4 can be designed to have a larger size than the first capacitor C1 of the third dummy pixel DP3.

[0335] In each of the second non-display area NDA2 and the second area DA2, a third repair line RPL3 and a fourth repair line RPL4 may be arranged between the first row R1 and the second row R2. The third repair line RPL3 may be integrally formed with the third bridging pattern BRP3, and the fourth repair line RPL4 may be integrally formed with the fourth bridging pattern BRP4.

[0336] In the second region DA2, the third bridging pattern BRP3 and the fourth bridging pattern BRP4 can extend along the second direction DR2 between sub-pixels in the first row R1 and sub-pixels in the second row R2. For example, the third bridging pattern BRP3 and the fourth bridging pattern BRP4 can extend along the second direction DR2 between the first sub-pixel SP1 in the first row R1 and the first sub-pixel SP1 in the second row R2, between the second sub-pixel SP2 in the first row R1 and the second sub-pixel SP2 in the second row R2, and between the third sub-pixel SP3 in the first row R1 and the third sub-pixel SP3 in the second row R2.

[0337] In the second region DA2, the third bridging pattern BRP3 and the fourth bridging pattern BRP4 can overlap with the first contact electrode CNE1 of each sub-pixel. Each of the third bridging pattern BRP3 and the fourth bridging pattern BRP4 can be electrically isolated from the first contact electrode CNE1.

[0338] The third repair line RPL3 can be electrically connected to one of the third dummy pixel DP3 and the fourth dummy pixel DP4, and the fourth repair line RPL4 can be electrically connected to another dummy pixel between the third dummy pixel DP3 and the fourth dummy pixel DP4. For example, each of the third dummy pixel DP3 (or third dummy pixel circuit DPC3) in the first row R1 and the fourth dummy pixel DP4 (or fourth dummy pixel circuit DPC4) in the second row R2 is electrically connected to the third repair line RPL3 through a corresponding second contact electrode CNE2, and each of the fourth dummy pixel DP4 (or fourth dummy pixel circuit DPC4) in the first row R1 and the third dummy pixel DP3 (or third dummy pixel circuit DPC3) in the second row R2 can be electrically connected to the second repair line RPL2 through a corresponding second contact electrode CNE2.

[0339] The third repair line RPL3 and the fourth repair line RPL4 can be electrically isolated from the pixel circuitry of each of the first sub-pixels SP1 to SP3 located in the second region DA2.

[0340] Typically, display devices (see...) Figure 2 The “DD” in the text can be used to specify the area to be placed in the display area (see [link]). Figure 2 The LEDs of the sub-pixels in “DA” are used for illumination checks. When the illumination check indicates that some of the LEDs are not lit, causing the sub-pixel to darken, a repair process can be performed by electrically connecting the unlit LEDs to the third dummy pixel DP3 and the fourth dummy pixel DP4 to drive the LEDs.

[0341] In the following text, see references Figure 28 This will describe a method for repairing defective subpixels in the second region DA2.

[0342] Figure 28 Is with Figure 2 The diagram corresponding to EA2 shows a method for repairing defective sub-pixels.

[0343] about Figure 28 In order to avoid redundant description, the implementation method will emphasize the differences from the implementation method described above.

[0344] refer to Figure 2 and Figure 28When a dark spot defect simultaneously occurs in the first sub-pixel SP1 and the third sub-pixel SP3 arranged in the first row R1, a repair process can be performed to electrically connect the first sub-pixel SP1 to the fourth dummy pixel DP4 arranged in the first row R1 and to electrically connect the third sub-pixel SP3 to the third dummy pixel DP3 arranged in the first row R1. The dark spot defect in each of the first sub-pixel SP1 and the third sub-pixel SP3 may be caused by, for example, a defect in the pixel circuitry.

[0345] When the 11th pixel circuit PXC11 of the first sub-pixel SP1 is defective, a laser can be used to electrically connect the anode of the light-emitting element LED (hereinafter referred to as the "first light-emitting element") of the 11th pixel circuit PXC11 (see [reference needed]). Figure 3 The “AE” in the text refers to the sixth and seventh transistors of the 11th pixel circuit PXC11 (see...). Figure 3 The electrical connection between “T6 and T7” is electrically disconnected from each other. Therefore, the anode AE ​​can be electrically disconnected from the sixth transistor T6 and the seventh transistor T7. A contact hole CH (or a second contact hole CH2) can be formed between the first contact electrode CNE1, which is electrically connected to the anode AE ​​(or the first light-emitting element LED) through the first contact hole CH1, and the fourth bridging pattern BRP4 by using a laser bonding process to destroy the insulating layer.

[0346] The fourth bridging pattern BRP4 (or fourth repair line RPL4) and the anode AE ​​(or first light-emitting element LED) can be electrically connected to each other through contact hole CH (or second contact hole CH2), first contact electrode CNE1, and first contact hole CH1. The fourth repair line RPL4 is electrically connected to the fourth dummy pixel DP4 arranged in the first row R1 of the second non-display area NDA2, so that the fourth dummy pixel circuit DPC4 of the fourth dummy pixel DP4 and the first light-emitting element LED of the first sub-pixel SP1 can be electrically connected to each other. Therefore, an electrical path from the fourth dummy pixel DP4 to the first light-emitting element LED of the first sub-pixel SP1 is formed through the fourth repair line RPL4, allowing the first light-emitting element LED to operate normally and repairing the first sub-pixel SP1 with dark spot defects.

[0347] When a dark spot fault also occurs in the third sub-pixel SP3, which is arranged in the same row as the first sub-pixel SP1, the electrical connection between the anode AE ​​of the light-emitting element LED (hereinafter referred to as the "second light-emitting element") of the 13th pixel circuit PXC13 of the third sub-pixel SP3 and the sixth transistor T6 and the seventh transistor T7 of the 13th pixel circuit PXC13 can be severed. Therefore, the anode AE ​​of the second light-emitting element LED can be electrically disconnected from the sixth transistor T6 and the seventh transistor T7. A contact hole CH (or a second contact hole CH2) can be formed between the first contact electrode CNE1, which is electrically connected to the anode AE ​​of the second light-emitting element LED through the first contact hole CH1, and the third bridging pattern BRP3 by using a laser bonding process to break the insulating layer.

[0348] The third bridging pattern BRP3 (or the third repair line RPL3) and the anode AE ​​of the second light-emitting element LED can be electrically connected to each other through contact hole CH (or second contact hole CH2), first contact electrode CNE1 and first contact hole CH1. The third repair line RPL3 is electrically connected to the third dummy pixel DP3 arranged in the first row R1 of the second non-display area NDA2, so that the third dummy pixel circuit DPC3 of the third dummy pixel DP3 and the second light-emitting element LED of the third sub-pixel SP3 can be electrically connected to each other. Therefore, the third repair line RPL3 forms an electrical path from the third dummy pixel DP3 to the second light-emitting element LED of the third sub-pixel SP3, so that the second light-emitting element LED can operate normally and the third sub-pixel SP3 with dark spot defects can be repaired.

[0349] As described above, when a dark spot fault occurs in two sub-pixels arranged in the first row R1 of the second region DA2, the light-emitting element (LED) of one of the two sub-pixels is electrically connected to the dummy pixel circuit of one of the third dummy pixel DP3 and the fourth dummy pixel DP4 arranged in the first row R1 of the second non-display region NDA2 within a horizontal time. Similarly, the light-emitting element (LED) of the other sub-pixel can be electrically connected to the dummy pixel circuit of the other of the third dummy pixel DP3 and the fourth dummy pixel DP4. Therefore, the dark spot defect in two sub-pixels in one row (or one pixel row) of the second region DA2 can be repaired.

[0350] Figure 29 This is a schematic block diagram showing an electronic device 1000 according to an embodiment. Figure 30 It is shown Figure 29 The electronic device 1000 is a schematic diagram of an example of a smartphone. Figure 31 It is shown Figure 29 The electronic device 1000 is a schematic diagram of an example of a tablet PC.

[0351] refer to Figures 29 to 31 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be... Figure 1 and Figure 2 The display device DD. The electronic device 1000 may also include various ports for communicating with video cards, sound cards, memory cards, USB devices, or other systems. In embodiments, such as Figure 30 As shown, the electronic device 1000 can be a smartphone. In an implementation, as... Figure 31 As shown, electronic device 1000 can be a tablet computer. However, the above example is illustrative, and electronic device 1000 is not necessarily limited to the above example. For example, electronic device 1000 can be a cellular phone, video phone, smart tablet, smartwatch, navigation device for vehicle, computer monitor, laptop computer, head-mounted display device, etc.

[0352] Processor 1010 can perform specific calculations or tasks. In embodiments, processor 1010 can be a microprocessor, central processing unit, application processor, etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In embodiments, processor 1010 can be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. Processor 1010 can provide input image data to display device 1060.

[0353] The memory device 1020 can store data required to perform the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (EEPROM) devices, flash memory devices, phase-change random access memory (PRAM) devices, resistive random access memory (RRAM) devices, nano-floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM) and ferroelectric random access memory (FRAM) devices, and / or volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices and mobile DRAM devices.

[0354] Storage device 1030 may include solid-state drive (SSD), hard disk drive (HDD), CD-ROM, etc.

[0355] I / O device 1040 may include input devices such as a keyboard, keypad, touchpad, touch screen, and mouse, and output devices such as a speaker and printer. In some embodiments, display device 1060 may be included in I / O device 1040.

[0356] The power supply 1050 can supply the power required to operate the electronic device 1000. For example, the power supply 1050 may include a power management integrated circuit (PMIC).

[0357] Display device 1060 can display images in response to control signals or data from processor 1010. For example, display device 1060 can display images based on input image data from processor 1010. Display device 1060 can be an organic light-emitting display device or a quantum dot light-emitting display device, but this disclosure is not limited to these. Display device 1060 can be connected to other components via a bus or other communication links.

[0358] Figure 32 This is a flowchart illustrating a method 3200 for repairing a display device according to one embodiment. (See also...) Figure 32 A method 3200 for repairing a display device is provided. As generally described above, the display device includes: a substrate defining a display area including a first region and a second region, and a non-display area surrounding at least one side of the first region and the second region; a sub-pixel disposed in the display area and including pixel circuitry, a light-emitting element, and a contact electrode electrically connected to a positive electrode of the light-emitting element; a first repair line and a second repair line disposed in the display area between and spaced apart from each other from a first pixel row and a second pixel row; a first dummy pixel and a second dummy pixel disposed in each of the first pixel row and the second pixel row in the non-display area and respectively connected to one of the first repair line and the second repair line; a first bridging pattern electrically connected to the first repair line; and a second bridging pattern electrically connected to the second repair line. Figure 32As shown, method 3200 includes: separating a first defective pixel circuit arranged in a first pixel column of a first pixel row from a first light-emitting element corresponding to the first defective pixel circuit (block 3201); electrically connecting the anode of the first light-emitting element to a dummy pixel circuit of a first dummy pixel by electrically connecting a contact electrode electrically connected to the anode of the first light-emitting element to a corresponding first bridging pattern in a first bridging pattern (block 3202); separating a second defective pixel circuit arranged in a third pixel column of the first pixel row from a second light-emitting element corresponding to the second defective pixel circuit (block 3203); and electrically connecting the anode of the second light-emitting element to a dummy pixel circuit of a second dummy pixel by electrically connecting a contact electrode electrically connected to the anode of the second light-emitting element to a corresponding second bridging pattern in a second bridging pattern (block 3204). According to method 3200, each of the first dummy pixel and the second dummy pixel includes a first capacitor electrically connected to the dummy pixel circuit, and the first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel have different sizes. Furthermore, according to method 3200, the second dummy pixel is positioned closer to the display area than the first dummy pixel in the non-display area, and the first capacitor of the first dummy pixel has a larger size than the first capacitor of the second dummy pixel.

[0359] The display device and its repair method according to the embodiments can improve the reliability of the display device by simultaneously and easily repairing dark spot faults that occur in four sub-pixels in a pixel row.

[0360] According to the implementation method, the production yield can be increased by increasing the number of repairable subpixels.

[0361] Furthermore, according to the embodiments, an electronic device including the above-described display device can be provided.

[0362] The effects of this disclosure are not limited to the foregoing, and various other effects are contemplated herein.

Claims

1. A display device, comprising: A substrate, wherein a display area comprising a first region and a second region and a non-display area surrounding at least one side of the display area; Sub-pixels are arranged in the display area; The first dummy pixel and the second dummy pixel are arranged in the non-display area; as well as The repair line is commonly located in both the display area and the non-display area, and extends in a first direction. The non-display area includes a first non-display area adjacent to the first area and a second non-display area adjacent to the second area. The repair line includes a first repair line and a second repair line, which are arranged in the first region between the first pixel row and the second pixel row of the substrate. Each of the first dummy pixel and the second dummy pixel includes a dummy pixel circuit and a first capacitor electrically connected to the dummy pixel circuit, and The first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel have different sizes.

2. The display device according to claim 1, wherein: The second dummy pixel is positioned closer to the first region than the first dummy pixel in the first non-display region, and The first capacitor of the first dummy pixel has a larger size than the first capacitor of the second dummy pixel.

3. The display device according to claim 2, wherein, The first capacitor of each of the first dummy pixel and the second dummy pixel includes: The lower electrode is disposed on the substrate; and An upper electrode is disposed on the lower electrode, and an insulating layer is inserted between the upper electrode and the lower electrode. Wherein, the overlap area between the lower electrode and the upper electrode in the first dummy pixel is greater than the overlap area between the lower electrode and the upper electrode in the second dummy pixel.

4. The display device according to claim 3, wherein, The dummy pixel circuit of the first dummy pixel is arranged in the plan view between the first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel.

5. The display device according to claim 3, wherein, The first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel are arranged adjacent to each other in the plan view.

6. The display device according to claim 5, wherein, The upper electrode of the first capacitor of the first dummy pixel and the upper electrode of the first capacitor of the second dummy pixel are commonly disposed on the common electrode of the first dummy pixel and the second dummy pixel.

7. The display device according to claim 2, wherein, The first repair line and the second repair line extend in the first direction, are spaced apart from each other in the second direction, and are electrically isolated from each other.

8. The display device according to claim 7, wherein: The dummy pixel circuit of the first dummy pixel is electrically connected to one of the first repair line and the second repair line, and The dummy pixel circuit of the second dummy pixel is electrically connected to another of the first repair line and the second repair line.

9. The display device according to claim 8, wherein: The dummy pixel circuit of the first dummy pixel is electrically connected to the second repair line, and The dummy pixel circuit of the second dummy pixel is electrically connected to the first repair line.

10. The display device according to claim 9, further comprising: A first bridging pattern is located between the first repair line and the second repair line, extends in the second direction, and is electrically connected to the first repair line; as well as A second bridging pattern is located between the first repair line and the second repair line, extends in the second direction, and is electrically connected to the second repair line.

11. The display device according to claim 10, wherein, The sub-pixels include: A pixel circuit, including at least one transistor disposed on the substrate; A light-emitting element, electrically connected to the transistor, and emitting light; and The first contact electrode is electrically connected to the light-emitting element and the transistor. Wherein, the first contact electrode overlaps with the first bridging pattern and the second bridging pattern, and The first contact electrode, the first bridging pattern, and the second bridging pattern are electrically isolated from each other.

12. The display device according to claim 11, wherein, The pixel circuits of two sub-pixels facing each other in the second direction are mirror-symmetrical, with the first repair line and the second repair line interposed between them in the first region.

13. The display device according to claim 10, wherein: Each of the first dummy pixel and the second dummy pixel further includes a second contact electrode, the second contact electrode electrically connecting the dummy pixel circuit to a corresponding repair line among the first repair line and the second repair line. The second contact electrode overlaps with both the first and second bridging patterns, and The second contact electrode is electrically connected to one of the first bridging pattern and the second bridging pattern.

14. The display device according to claim 1, wherein: The repair lines also include a third repair line and a fourth repair line, which are arranged in the second region between the first pixel row and the second pixel row. The third and fourth dummy pixels are arranged in each of the first and second pixel rows in the second non-display area. The third dummy pixel is electrically connected to one of the third repair line and the fourth repair line, and The fourth dummy pixel is electrically connected to the third repair line and another of the fourth repair lines.

15. The display device according to claim 14, wherein: Each of the third and fourth dummy pixels includes the dummy pixel circuit and the first capacitor electrically connected to the dummy pixel circuit, and The first capacitor of the third dummy pixel and the first capacitor of the fourth dummy pixel have different sizes.

16. The display device according to claim 15, wherein: The third dummy pixel is positioned closer to the second non-display area than the fourth dummy pixel, and The first capacitor of the fourth dummy pixel has a larger size than the first capacitor of the third dummy pixel.

17. A method for repairing a display device, the display device comprising: A substrate, wherein a display area comprising a first region and a second region and a non-display area surrounding at least one side of the first region and the second region are defined; Sub-pixels are arranged in the display area and include pixel circuitry, light-emitting elements, and contact electrodes electrically connected to the anode of the light-emitting elements; The first repair line and the second repair line are arranged in the display area between the first pixel row and the second pixel row and are spaced apart from each other. A first dummy pixel and a second dummy pixel are arranged in each of the first pixel row and the second pixel row in the non-display area, and are respectively connected to one of the first repair line and the second repair line; The first bridging pattern is electrically connected to the first repair line; And a second bridging pattern, electrically connected to the second repair line, the method comprising: Separate the first defective pixel circuit arranged in the first pixel column of the first pixel row from the first light-emitting element corresponding to the first defective pixel circuit; By electrically connecting the contact electrode electrically connected to the anode of the first light-emitting element to the corresponding first bridging pattern in the first bridging pattern, the anode of the first light-emitting element is electrically connected to the dummy pixel circuit of the first dummy pixel. Separate the second defective pixel circuit arranged in the third pixel column of the first pixel row from the second light-emitting element corresponding to the second defective pixel circuit; and By electrically connecting the contact electrode, which is electrically connected to the anode of the second light-emitting element, to a corresponding second bridging pattern in the second bridging pattern, the anode of the second light-emitting element is electrically connected to the dummy pixel circuit of the second dummy pixel. Each of the first dummy pixel and the second dummy pixel includes a first capacitor electrically connected to the dummy pixel circuit, and The first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel have different sizes.

18. The method of claim 17, wherein: The second dummy pixel is positioned closer to the display area than the first dummy pixel in the non-display area, and The first capacitor of the first dummy pixel has a larger size than the first capacitor of the second dummy pixel.

19. An electronic device comprising: The processor provides the input image data to the display device; as well as The display device displays an image based on the input image data. The display device includes: A substrate, wherein a display area comprising a first region and a second region is defined, and a non-display area surrounding at least one side of the display area; Sub-pixels are arranged in the display area; Dummy pixels are arranged in the non-display area; and The repair line is commonly located in both the display area and the non-display area, and extends in a first direction. The non-display area includes a first non-display area adjacent to the first area and a second non-display area adjacent to the second area. The repair line includes a first repair line and a second repair line, which are arranged in the first region between the first pixel row and the second pixel row of the substrate. The dummy pixels include a first dummy pixel and a second dummy pixel arranged in each of the first pixel row and the second pixel row in the first non-display area. Each of the first dummy pixel and the second dummy pixel includes a dummy pixel circuit and a first capacitor electrically connected to the dummy pixel circuit, and The first capacitor of the first dummy pixel and the first capacitor of the second dummy pixel have different sizes.

20. The electronic device according to claim 19, wherein: The second dummy pixel is positioned closer to the first region than the first dummy pixel in the first non-display region, and The first capacitor of the first dummy pixel has a larger size than the first capacitor of the second dummy pixel.

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