PSUB packaging substrate based on single-sided substrate process and manufacturing method thereof

Abstract

The embodiment of the invention provides a PSUB packaging substrate based on a single-sided substrate process and a manufacturing method thereof, and relates to the technical field of semiconductor advanced packaging, the PSUB packaging substrate comprises a metal substrate, the upper surface of the metal substrate is covered with a high-thermal-conductivity insulating film, the upper surface of the high-thermal-conductivity insulating film is covered with a metalized seed layer, and the metalized seed layer is arranged on the upper surface of the metal substrate. The upper surface of the metalized seed layer is covered with a plurality of layers of wiring structures, and each layer of wiring structure comprises a copper circuit, a conduction structure and an EMC filling layer. The invention has the effects of high-density wiring and large current.

Description

Technical Field

[0001] This invention relates to the field of advanced semiconductor packaging technology, and in particular to a PSUB packaging substrate based on single-sided substrate technology and its manufacturing method. Background Technology

[0002] As semiconductor devices iterate towards higher density and higher power, heat dissipation and signal interconnection in electronic systems have become core bottlenecks. Current electronic system packaging employs a four-stage separation structure: chip-SUB package carrier-PCB circuit board-metal heat sink. However, this four-stage heat dissipation structure has low thermal conductivity, failing to meet the heat dissipation requirements of high-power devices. Current PCB circuit board processes use copper etching, which cannot achieve chip-level wiring density. The SUB package carrier uses a semi-additive process, enabling high-density wiring, but it cannot meet the high current requirements of passive components.

[0003] In response to the above problems, the inventors believe that there is an urgent need for an integrated packaging substrate solution with high-density wiring and high current carrying capacity. Summary of the Invention

[0004] To address the issue that carrier boards cannot simultaneously handle high-density wiring and high current carrying capacity, this application provides a PSUB packaging substrate based on a single-sided substrate process and its manufacturing method.

[0005] This application provides a PSUB packaging substrate based on single-sided substrate technology and its manufacturing method, which adopts the following technical solution: A method for manufacturing a system-integrated PSUB metal PCB package heat dissipation substrate based on single-sided substrate technology includes the following steps: S1. A layer of highly thermally conductive insulating film is pressed onto a metal substrate by coating or lamination. S2. A metallization seed layer is formed on a high thermal conductivity insulating film or EMC filling layer by magnetron sputtering or chemical copper method. S3. A copper circuit and a conductive structure are formed on the metallized seed layer through two consecutive processes of exposure, development and RDL electroplating of photosensitive material, wherein the thickness of the copper circuit is 5μm-50μm. S4. Use a molding process to fill the wiring structure with EMC material to form an EMC filling layer. S5. The conductive structure is ground out using a grinding process; S6. Repeat steps S3-S5 several times to form a multi-layer wiring structure and realize the fabrication of the PSUB substrate.

[0006] Optionally, the multilayer wiring structure in steps S2-S5 is fabricated on a temporary carrier. The multilayer wiring structure is bonded to the metal substrate covered with a high thermal conductivity insulating film in step S2 by a hot pressing process. After peeling off the temporary carrier, the PSUB substrate fabrication is completed.

[0007] Optionally, the following packaging steps may also be included: S7. On the surface of the multilayer wiring structure of the PSUB substrate obtained in step S6, a copper pillar higher than the thickness of the chip to be packaged is formed, and the height of the copper pillar is 50-200μm. S8. The bottom chip with bumps is mounted in a positive mounting manner between the copper pillars on the surface of the PSUB substrate, and the bumps of the bottom chip are electrically connected to the multilayer wiring structure of the PSUB substrate. S9. Using a molding process, EMC material is covered onto the surface of the PSUB substrate, and the underlying chip and copper pillars are embedded to form an encapsulated EMC layer. S10. The EMC layer of the package is polished using a polishing process to expose the top connection port of the underlying chip. S11. The upper-layer chip is mounted on the top of the exposed lower-layer chip using a flip-chip process to connect to the port, thus completing the packaging structure fabrication based on the PSUB substrate. If a multilayer embedded chip structure needs to be fabricated in step S9, steps S7-S10 can be repeated. During the repetition, EMC materials with different CTEs should be used to address the warpage issue. The difference in the coefficient of thermal expansion of the EMC materials with different CTEs should be controlled within 5 × 10⁻⁶. -6 / ℃ or less.

[0008] A PSUB packaging substrate based on single-sided substrate technology and its manufacturing method are disclosed. The substrate includes a metal substrate, the upper surface of which is covered with a high thermal conductivity insulating film. At least one wiring structure is provided on the high thermal conductivity insulating film. Each wiring structure includes a metallization seed layer. From bottom to top, copper lines, conductive structures and EMC filling layers are provided on the metallization seed layer.

[0009] Optionally, the metal substrate is an aluminum plate or a copper plate.

[0010] Optionally, a packaging structure is also included, wherein the packaging structure is disposed on the side of the multilayer wiring structure of the PSUB substrate away from the high thermal conductivity insulating film; the packaging structure includes: copper pillars, a bottom chip, a packaging EMC layer, and a top chip; the copper pillars are vertically fixed to the surface of the multilayer wiring structure of the PSUB substrate, and the height of the copper pillars is greater than the thickness of the bottom chip; the bottom chip is embedded between the copper pillars in a positive mounting manner, and the bumps of the bottom chip are electrically connected to the multilayer wiring structure of the PSUB substrate; the packaging EMC layer covers the surface of the PSUB substrate, wraps the copper pillars and the bottom chip, and the top of the packaging EMC layer is ground to expose the top connection port of the bottom chip; the top chip is electrically connected to the top connection port of the bottom chip through a flip-chip process.

[0011] In summary, this application includes at least one of the following beneficial technical effects: 1. The PSUB substrate fabricated in this solution uses RDL multilayer wiring technology in conjunction with EMC dielectric material to flexibly control the copper layer thickness, taking into account both high density and high current carrying capacity, while reducing thermal resistance links and improving heat dissipation capacity. At the same time, the structure is simplified, reducing the traditional four-layer structure to two layers, thus solving the heat dissipation problem of high-density integration in electronic systems. 2. This solution can effectively reduce the overall design size of electronic systems and the distance between chips and active / passive devices for signal interconnection, significantly reduce signal insertion loss and transmission delay, and improve system response speed. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of the cross-sectional structure of the PSUB substrate of the present invention; Figure 2 This is a schematic diagram of the packaging of the PSUB substrate of the present invention; Figure 3 This is a schematic diagram of the PSUB substrate manufacturing process of the present invention; Figure 4 This is a schematic diagram of the PSUB substrate packaging process of the present invention.

[0013] Explanation of reference numerals in the attached figures: 1. Metal substrate; 2. High thermal conductivity insulating film; 3. Metallization seed layer; 4. Copper circuit; 5. Conductive structure; 6. EMC filling layer; 7. Copper pillar; 8. Bottom chip; 9. Encapsulation EMC layer; 10. Top chip; 11. Epoxy resin; 12. PSUB substrate. Detailed Implementation

[0014] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. As used in the specification and appended claims of this application, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, “at least one” and “one or more” refer to one, two, or more than two. The term “and / or” is used to describe the relationship between related objects, indicating that three relationships may exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character “ / ” generally indicates that the preceding and following related objects are in an “or” relationship.

[0015] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0016] The following is in conjunction with the appendix Figure 1-4 The present invention will be described in further detail below.

[0017] This application discloses a PSUB packaging substrate based on single-sided substrate technology and its manufacturing method, referring to... Figure 1 The package includes a metal substrate 1, the upper surface of which is covered with a high thermal conductivity insulating film 2. The high thermal conductivity insulating film 2 has at least one wiring structure. Each wiring structure includes a metallization seed layer. The metallization seed layer has copper lines, a conductive structure and an epoxy molding compound (EMC) filling layer 6 arranged from bottom to top. This application defines this package substrate structure as a PSUB substrate.

[0018] The PSUB substrate uses a metal substrate 1 as a permanent heat dissipation structure. A novel single-sided packaging substrate process is adopted on one side of the metal substrate 1, and EMC is used as the main dielectric material of the packaging substrate. This achieves a new structure that simultaneously integrates a PCB circuit board, a SUB packaging carrier board, and a metal substrate 1. This structure eliminates the adhesive layer and substrate between the carrier board and the PCB, and between the PCB and the metal board, further compressing the overall thickness and reducing the overall design size of the electronic system. This makes it suitable for the miniaturization requirements of consumer electronics, automotive electronics, etc. The thinner substrate can integrate more chips and passive devices in a unit space, which is in line with the iterative direction of high-density semiconductor integration.

[0019] Reference Figure 2 It also includes a packaging structure, which includes: copper pillars 7, a bottom chip 8, a packaging EMC layer 9, and a top chip 10; the copper pillars 7 are vertically fixed to the surface of the multilayer wiring structure of the PSUB substrate 12, and the height of the copper pillars 7 is greater than the thickness of the bottom chip 8; the bottom chip 8 is embedded between the copper pillars 7 in a positive mounting manner, and the bumps of the bottom chip 8 are electrically connected to the multilayer wiring structure of the PSUB substrate 12; the packaging EMC layer 9 covers the surface of the PSUB substrate 12, wraps the copper pillars 7 and the bottom chip 8, and the top of the packaging EMC layer 9 is polished to expose the top connection port of the bottom chip 8; the top chip 10 is electrically connected to the top connection port of the bottom chip 8 through a flip-chip process.

[0020] The substrate packaging also uses EMC as the dielectric material, which is fully covered on all six sides of the bottom chip 8. The thermal conductivity is more than twice that of the dielectric material in the traditional solution. The bottom chip 8 does not need to make silicon vias to connect to the upper chip 10, which greatly reduces the process flow. The chips are directly interconnected through bumps, which greatly improves the signal interconnection speed and response time between chips.

[0021] Reference Figure 3 The PSUB substrate is manufactured using a single-sided process, enabling multi-layer, high-density, high-current-carrying-capacity, and high aspect ratio versatility on a thermally conductive metal substrate. This effectively addresses the bottom heat dissipation problem of electronic devices in electronic system integration. The specific manufacturing method is as follows: S1. Select a copper T2 with a thickness of 0.1mm-2mm, preferably 0.4mm, as the metal substrate 1. Use a lamination method to press a layer of ceramic-filled PI material high thermal conductivity insulating film 2 onto the upper surface of the metal substrate 1. The thickness of the high thermal conductivity insulating film 2 is 5μm-50μm, preferably 10μm, and the insulation strength is 15kV / mm. S2. A Ti / Cu composite metallization seed layer 3 is formed on the high thermal conductivity insulating film 2 or EMC filling layer 6 by magnetron sputtering or chemical copper method. The thickness of the Ti layer is 10nm-50nm, preferably 20nm, and the thickness of the Cu layer is 50nm-500nm, preferably 100nm. S3. Coating negative photoresist, first exposure / development to define the copper circuit pattern, using a redistribution layer (RDL) electroplating at a current density of 3A / dm² for 25 minutes to form a copper circuit 4 with a thickness of 5μm-50μm, preferably 20μm; second exposure / development to define the conductive structure pattern, continuing RDL electroplating at a current density of 3.5A / dm² for 30 minutes to form a conductive structure 5 with a diameter of 50μm-200μm, preferably 100μm, and a height of 20μm-50μm, preferably 30μm; S4. Using a molding process with a temperature of 160℃, a pressure of 25MPa, and a time of 60min, EMC material is filled into the wiring gap to form an EMC filling layer 6. The EMC material is epoxy resin + 70% silicon powder. S5. The chemical mechanical polishing (CMP) process with a pressure of 2 kPa and a rotation speed of 300 r / min is used to expose the top of the conductive structure 5 by 1 μm-5 μm, preferably 3 μm, thereby realizing the fabrication of the first layer of rewiring. Steps S6 and S2-S5 are repeated three times to form a four-layer wiring structure, resulting in a PSUB substrate with a total thickness of 50μm-300μm, preferably 150μm.

[0022] To achieve higher density wiring in this solution, a method can be adopted to fabricate a heat dissipation PSUB carrier board by laser stripping the temporary carrier after the multi-layer wiring structure is fabricated on a temporary carrier, such as a silicon wafer, and then hot-pressing it onto a metal substrate 1. The hot-pressing temperature is 180-220℃, the pressure is 20-40MPa, and the time is 30-60min.

[0023] Traditional PCB and substrate processes are all double-sided processes, which cannot create multiple wiring layers on a metal structure. This single-sided process can directly realize a multi-layer structure on a heat-dissipating metal substrate.

[0024] The substrate uses EMC as the dielectric material, eliminating the need for a silicon interposer, reducing thermal resistance, and improving thermal conductivity by more than double compared to traditional dielectric materials. Furthermore, EMC fills and covers the wiring gaps, resulting in more uniform heat dissipation. RDL electroplating allows for flexible control of the copper layer thickness, balancing high density and high current carrying capacity. The wiring process is reduced from four stages to two stages, reducing the stacking steps of the substrate-PCB-metal board, thus lowering process costs and yield risks.

[0025] In existing electronic system architectures, the interconnection distance between chips and active / passive components is on average around 10mm due to the four-layer structure. This solution can achieve carrier-level interconnection density, thinner structure, and integrated design to reduce the interconnection distance by half, thereby greatly optimizing the signal insertion loss and delay issues between electronic components in the system.

[0026] Reference Figure 4 One packaging method for a PSUB substrate is as follows: Step 1: On the surface of the top wiring structure of the PSUB substrate 12, copper pillars 7 are fabricated by RDL electroplating process. The diameter of the copper pillars 7 is 50μm-300μm, preferably 150μm, and the height is 50-200μm, preferably 120μm. The spacing between the copper pillars is 100μm-500μm, preferably 300μm, and they are electrically connected to the top copper line 4 of the PSUB substrate. Step 2: Select the bottom chip 8 with tin-silver-copper bumps, the bump diameter is 50μm and the spacing is 100μm, and mount it between the copper pillars 7 in a positive mounting manner so that the bumps of the bottom chip 8 and the copper line 4 on the top layer of the PSUB substrate 12 are electrically connected by reflow soldering. The reflow soldering temperature is 240℃ and the time is 10s. Step 3: Using a molding process, at a temperature of 170℃, a pressure of 30MPa, and a time of 80min, EMC material is applied to the surface of the PSUB substrate 12. The EMC material consists of epoxy resin and 75% alumina powder, with a coefficient of thermal expansion (CTE) of 12 × 10⁻⁶. -6 / ℃, EMC material is completely embedded in the bottom chip 8 and copper pillars 7 to form a 200μm thick encapsulation EMC layer 9; Step 4: Use a grinding wheel to grind the EMC layer 9 until the top connection port of the bottom chip 8 is fully exposed; Step 5: Select the upper chip 10 with microbumps, fill the bottom with epoxy resin 11 through flip-chip process, cure at 150℃ for 40 minutes, and mount it to the top connection port of the lower chip 8 to complete the encapsulation.

[0027] If a multi-layer embedded chip structure needs to be fabricated in step three, steps one through four can be repeated. During the repetition, EMC materials with different CTEs should be used to address the warpage issue. The difference in the coefficient of thermal expansion of the EMC materials with different CTEs should be controlled within 5 × 10⁻⁶. -6 / ℃ or less.

[0028] By utilizing embedded solutions and embedded structures to achieve bottom heat dissipation of the chip, the heat dissipation performance of the 3D packaging structure is improved; the overall packaging process is greatly reduced, eliminating the need for silicon interposer boards and bottom-level chip interconnect vias, halving the overall process time; and the shorter interconnection distance between chips can greatly improve the signal transmission performance of the 3D packaging module.

[0029] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. Any equivalent modifications or variations made by those skilled in the art based on the content disclosed in the present invention should be included within the scope of protection set forth in the claims.

Claims

1. A method for manufacturing a PSUB packaging substrate based on a single-sided substrate process, characterized in that, Includes the following steps: S1. A layer of highly thermally conductive insulating film (2) is pressed onto a metal substrate (1) by coating or lamination. S2. A metallization seed layer (3) is formed on the high thermal conductivity insulating film (2) or EMC filling layer (6) by magnetron sputtering or chemical copper method. S3. A copper circuit (4) and a conductive structure (5) are formed on the metallized seed layer (3) by two consecutive processes of exposure, development and RDL electroplating of photosensitive material, respectively. The thickness of the copper circuit (4) is 5μm-50μm. S4. The wiring structure is filled with EMC material using a plastic sealing film pressing process to form an EMC filling layer (6). S5. The conductive structure (5) is ground out using a grinding process; S6. Repeat steps S2-S5 several times to form a multi-layer wiring structure and realize the fabrication of the PSUB substrate.

2. The method for manufacturing a PSUB packaging substrate based on a single-sided substrate process according to claim 1, characterized in that: The multilayer wiring structure in steps S3-S5 is fabricated on a temporary carrier. The multilayer wiring structure is bonded to the metal substrate (1) covered with a high thermal conductivity insulating film (2) in step S2 by hot pressing. After peeling off the temporary carrier, the PSUB substrate fabrication is completed.

3. A method for manufacturing a PSUB packaging substrate based on a single-sided substrate process according to claim 1 or 2, characterized in that, It also includes the following packaging steps: S7. On the surface of the multilayer wiring structure of the PSUB substrate (12) obtained in step S6, a copper pillar (7) higher than the thickness of the chip to be packaged is formed, and the height of the copper pillar (7) is 50-200μm. S8. The bottom chip (8) with bumps is mounted in a positive mounting manner between the copper pillars (7) on the surface of the PSUB substrate (12), and the bumps of the bottom chip (8) are electrically connected to the multilayer wiring structure of the PSUB substrate. S9. Using a plastic encapsulation film pressing process, EMC material is covered on the surface of the PSUB substrate, and the bottom chip (8) and copper pillar (7) are embedded to form an encapsulated EMC layer (9). S10. The EMC layer (9) is polished using a polishing process to expose the top connection port of the bottom chip (8). S11. The upper layer chip (10) is mounted on the top connection port of the exposed lower layer chip (8) using a flip-chip process to complete the packaging structure fabrication based on the PSUB substrate (12). If a multilayer embedded chip structure needs to be fabricated in step S9, steps S7-S10 can be repeated. During the repetition, EMC materials with different CTEs should be used to address the warpage issue. The difference in the coefficient of thermal expansion of the EMC materials with different CTEs should be controlled within 5 × 10⁻⁶. -6 / ℃ or less.

4. A PSUB packaging substrate based on single-sided substrate technology, characterized in that: It includes a metal substrate (1), the upper surface of which is covered with a high thermal conductivity insulating film (2), and at least one wiring structure is provided on the high thermal conductivity insulating film (2). Each wiring structure includes a metallization seed layer (3), and copper lines (4), a conductive structure (5) and an EMC filling layer (6) are provided on the metallization seed layer (3) from bottom to top.

5. A PSUB packaging substrate based on single-sided substrate technology according to claim 4, characterized in that: The metal substrate (1) is an aluminum plate or a copper plate.

6. A PSUB packaging substrate based on single-sided substrate technology according to claim 4, characterized in that: It also includes a packaging structure, which includes: copper pillars (7), a bottom chip (8), a packaging EMC layer (9), and an upper chip (10); the copper pillars (7) are vertically fixed to the surface of the multilayer wiring structure of the PSUB substrate (12), and the height of the copper pillars (7) is higher than the thickness of the bottom chip (8); the bottom chip (8) is embedded between the copper pillars (7) in a positive mounting manner, and the bumps of the bottom chip (8) are electrically connected to the multilayer wiring structure of the PSUB substrate (12); the packaging EMC layer (9) covers the surface of the PSUB substrate (12), wraps the copper pillars (7) and the bottom chip (8), and the top of the packaging EMC layer (9) is polished to expose the top connection port of the bottom chip (8); the upper chip (10) is electrically connected to the top connection port of the bottom chip (8) through a flip-chip process.

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