Method and system for measuring contact resistance of power tube and calibration method based on contact resistance
By measuring the total resistance and drain-source current under different gate voltages, a set of equations is constructed to calculate the contact resistance, thus solving the measurement error introduced by the probe contact resistance and realizing high-precision power device performance evaluation, which is suitable for large-scale parallel testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNITED NOVA TECH - XIANFENG (SHAOXING) CORP
- Filing Date
- 2026-03-24
- Publication Date
- 2026-05-12
AI Technical Summary
In the manufacturing process of power devices, when the probe contact resistance is close to the conduction resistance, the measurement error of the two-wire DC test method is large, which affects the accuracy of device performance evaluation. In addition, the Kelvin four-wire test method is costly and difficult to apply to large-scale parallel testing.
The total resistance and drain-source current under different gate voltages are obtained by measuring device, a set of equations are constructed, and the contact resistance is directly calculated and the electrical parameters are calibrated by using the relationship between conduction resistance and contact resistance. Existing probe cards and test channels are used, and no additional hardware modifications are required.
It achieves precise measurement of contact resistance, with measurement accuracy reaching the level of the Kelvin four-wire test method, reducing measurement uncertainty, and is suitable for large-scale parallel testing, thus improving the reliability and accuracy of test results.
Smart Images
Figure CN122017352A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power device performance testing technology, and more specifically to a method, system, and calibration method based on contact resistance for measuring the contact resistance of a power transistor. Background Technology
[0002] Currently, in the manufacturing process of some power devices, after the power device is manufactured, it must undergo WAT testing to evaluate its performance. For example, the linear current of a power device is a core parameter for measuring its conduction capability, on-resistance, and stability.
[0003] Typically, the linear current of power devices is measured using a two-wire DC test method. Since the test circuit includes probes that contact the power device, when the contact resistance of the probes is close to the on-resistance of the power device, the contact resistance will introduce measurement errors, distorting the true performance of the power device. Summary of the Invention
[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.
[0005] To address the existing problems, this application provides a method for measuring the contact resistance of a power transistor, which includes: The measuring device carrying a probe is used to obtain at least two sets of operating parameters of the power transistor in the linear operating region. The at least two sets of operating parameters include the total resistance value and the drain-source current under different gate voltages and constant drain voltage, wherein the total resistance value is the sum of the on-resistance value and the contact resistance value. Based on the electrical parameters related to the on-resistance and the relationships between these parameters, a set of equations is constructed using the total resistance and drain-source current under the first gate voltage and the total resistance and drain-source current under the second gate voltage, in order to determine the on-resistance under the first gate voltage and / or the on-resistance under the second gate voltage. The contact resistance is determined based on the total resistance and on-resistance under the first gate voltage or the total resistance and on-resistance under the second gate voltage.
[0006] In one embodiment, based on electrical parameters related to on-resistance and the relationships between these parameters, a set of equations is constructed regarding the on-resistance under the first gate voltage and the drain-source current under the second gate voltage, using the total resistance value under the first gate voltage and the drain-source current under the second gate voltage. Based on the relationship between total resistance, on-resistance and contact resistance, the resistance difference between the on-resistance under the first gate voltage and the on-resistance under the second gate voltage is determined according to the total resistance value under the first gate voltage and the total resistance value under the second gate voltage. Based on the relationship between drain-source current and on-resistance and the formula for drain-source current in the linear operating region, the resistance ratio of the on-resistance under the first gate voltage to the on-resistance under the second gate voltage is determined according to the drain-source current under the first gate voltage and the drain-source current under the second gate voltage. Based on the resistance difference and resistance ratio, construct a system of equations regarding the on-resistance under the first gate voltage and the on-resistance under the second gate voltage.
[0007] In one embodiment, the resistance difference between the on-resistance under the first gate voltage and the on-resistance under the second gate voltage is obtained by calculating the difference between the total resistance value under the first gate voltage and the total resistance value under the second gate voltage.
[0008] In one embodiment, based on the relationship between drain-source current and on-resistance and the drain-source current formula for the linear operating region, determining the resistance ratio of the on-resistance under the first gate voltage to the on-resistance under the second gate voltage according to the drain-source current under the first gate voltage and the drain-source current under the second gate voltage includes: Based on the drain-source current formula in the linear operating region, the voltage ratio of the channel voltage under the first gate voltage to the channel voltage under the second gate voltage is determined by using the drain-source current under the first gate voltage and the drain-source current under the second gate voltage. Based on the relationship between drain-source current, on-resistance, and channel voltage, the voltage ratio is converted to obtain the resistance ratio.
[0009] In one embodiment, the drain-source current formula for the linear operating region is approximated as: Ids=β(Vgs-Vt)Vds Where β is the transconductance parameter, Vgs is the gate voltage, Vt is the threshold voltage, and Vds is the drain-source voltage.
[0010] In one embodiment, the method further includes: Select two sets of working parameters from at least two sets of working parameters; Based on the electrical parameters related to the on-resistance and the relationships between these parameters, a set of equations about the on-resistance is constructed using two sets of operating parameters to determine the on-resistance under the gate voltage corresponding to the two sets of operating parameters. Repeat the first two steps to obtain the on-resistance at multiple different gate voltages; The relationship between gate voltage and on-resistance is obtained by fitting the on-resistance under multiple different gate voltages, so as to redetermine the on-resistance under the first gate voltage and the on-resistance under the second gate voltage.
[0011] In one embodiment, the contact resistance is used to calibrate the measured values of various electrical parameters acquired when the power transistor is in the linear operating region. The electrical parameters that can be calibrated include at least the drain-source current, on-resistance, and threshold voltage of the power transistor when it is in the linear operating region.
[0012] Another aspect of this application provides a measurement system, including a measuring device carrying a probe, a memory, and a processor. The memory stores a computer program that is executed by the processor. When the computer program is executed by the processor, it causes the processor to perform the aforementioned power transistor contact resistance measurement method.
[0013] In one embodiment, the measuring device carrying the probe includes: A first adjustable power supply, connected to the gate of the power transistor, is used to provide a first target voltage; The second adjustable power supply, connected to the drain of the power transistor, is used to provide the second target voltage; The current detection module is connected to the drain of the power transistor and is used to detect the drain-source current of the power transistor.
[0014] This application further provides a calibration method based on contact resistance, the calibration method based on contact resistance includes: The contact resistance value is obtained using the aforementioned power transistor contact resistance measurement method; Obtain the total resistance of the power transistor in the linear operating region at the target gate voltage and target drain voltage; Based on the contact resistance and the total resistance under the target gate voltage and target drain voltage, determine the on-resistance value under the target gate voltage and target drain voltage; The calibrated drain-source current is determined based on the target drain voltage, target gate voltage, and on-resistance at the target drain voltage.
[0015] The power transistor contact resistance measurement method, system, and contact resistance-based calibration method of this application can directly obtain the total resistance and drain-source current of a power transistor operating in the linear operating region under two different gate voltages and a constant drain voltage. Since the on-resistance has a functional relationship with the gate voltage when the drain voltage is constant, and the contact resistance has the characteristic of remaining constant, a system of equations can be constructed using the total resistance and drain-source current under these two different gate voltages to derive the on-resistance under the first gate voltage and the on-resistance under the second gate voltage, thereby determining the magnitude of the contact resistance. When the contact resistance is known, various electrical parameters of the power transistor in the linear operating region can be calibrated. This measurement method can achieve the measurement accuracy of the Kelvin four-wire test method, while avoiding high implementation costs, making it more suitable for large-scale parallel testing scenarios. Attached Figure Description
[0016] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.
[0017] In the attached image: Figure 1 A flowchart illustrating a power transistor contact resistance measurement method according to a specific embodiment of this application is shown. Figure 2 The current-voltage characteristic curve of an NMOS transistor according to a specific embodiment of this application is shown; Figure 3 The current-voltage characteristic curves of an NMOS transistor under different gate voltages according to a specific embodiment of this application are shown. Figure 4 A flowchart illustrating a power transistor contact resistance measurement method according to another specific embodiment of this application is shown; Figure 5 A schematic structural block diagram of a measurement system according to a specific embodiment of this application is shown; Figure 6 A circuit diagram of a measuring device according to a specific embodiment of this application is shown; Figure 7 A flowchart illustrating a specific embodiment of the calibration method based on contact resistance of this application is shown. Figure 8 A table showing the measured values of total resistance, on-resistance, and contact resistance under different gate voltages according to a specific embodiment of this application is provided. Detailed Implementation
[0018] The present application will now be described more fully with reference to the accompanying drawings, in which embodiments of the present application are illustrated. However, the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0019] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0020] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0021] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms as defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the relevant field and / or the context of this specification, and not as in an ideal or overly formal sense, unless expressly defined herein.
[0022] To fully understand this application, a detailed structure will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0023] Currently, in the manufacturing process of some power devices, after the power devices are manufactured, they undergo WAT testing to evaluate their performance. It is understood that WAT testing is a crucial step in evaluating process quality and device performance. For example, for power devices such as power transistors, their linear current is a core parameter for measuring the device's conduction capability, on-resistance, and process stability. Accurate current is essential for device model calibration, circuit design, and reliability assessment.
[0024] The linear current of power devices is typically measured using either a two-wire DC test or a Kelvin four-wire test. Among these methods: The two-wire DC test method involves applying a fixed bias voltage to the device gate to make it operate in the linear region, and applying a small voltage (e.g., VDS = 100mV) to the drain, then directly measuring the drain-source current. While this method is simple and quick, it introduces measurement errors, thus reducing measurement accuracy. This is because the test circuit includes the contact resistance of two probes at the source and drain. Furthermore, the on-resistance (intrinsic channel resistance) of the power transistor in the linear region is typically small, while the probe contact resistance usually fluctuates between 0.5Ω and 5Ω. This means that the measurement error introduced by the contact resistance can be as high as tens of percent or even several times, severely distorting the true device performance and resulting in unreliable test data that cannot be used for accurate process monitoring and model extraction.
[0025] The Kelvin four-wire test method eliminates the influence of contact resistance in principle by using separate FORCE and SENCE terminals. This method is the standard method for measuring low-value resistance. However, it is costly to implement because it requires double probes for each test pad and places extremely high demands on the design and manufacturing complexity of the probe card. Furthermore, it consumes a significant amount of tester channel resources during measurement, increasing testing costs and making it unsuitable for production line environments with limited probe numbers or requiring large-scale parallel testing.
[0026] Therefore, in view of the aforementioned technical problems, this application proposes a method for measuring the contact resistance of a power transistor, the method comprising: At least two sets of operating parameters of the power transistor in the linear operating region are obtained using a measuring device carrying a probe. The at least two sets of operating parameters include the total resistance value and the drain-source current under different gate voltages and constant drain voltage, wherein the total resistance value is the sum of the on-resistance value and the contact resistance value. Based on the electrical parameters related to the on-resistance and the relationship between the electrical parameters, using the total resistance and drain-source current under the first gate voltage and the total resistance and drain-source current under the second gate voltage, a set of equations is constructed regarding the on-resistance under the first gate voltage and the on-resistance under the second gate voltage to determine the on-resistance under the first gate voltage and / or the on-resistance under the second gate voltage. The contact resistance value is determined based on the total resistance value and on-resistance value under the first gate voltage or the total resistance value and on-resistance value under the second gate voltage.
[0027] The power transistor contact resistance measurement method of this application embodiment can directly obtain the total resistance and drain-source current of a power transistor operating in the linear operating region under two different gate voltages and a constant drain voltage. Since the on-resistance has a functional relationship with the gate voltage when the drain voltage is constant, and the contact resistance has the characteristic of remaining constant, a system of equations can be constructed using the total resistance and drain-source current under these two different gate voltages to derive the on-resistance under the first gate voltage and the on-resistance under the second gate voltage, thereby determining the magnitude of the contact resistance. When the contact resistance is known, various electrical parameters of the power transistor in the linear operating region can be calibrated. This measurement method can achieve the measurement accuracy of the Kelvin four-wire test method, while avoiding high implementation costs, making it more suitable for large-scale parallel testing scenarios.
[0028] Below, for reference Figures 1 to 8 The method for measuring the contact resistance of power transistors in this application is described in detail, wherein, Figure 1 A flowchart illustrating a power transistor contact resistance measurement method according to a specific embodiment of this application is shown. Figure 2 The current-voltage characteristic curve of an NMOS transistor according to a specific embodiment of this application is shown; Figure 3 The current-voltage characteristic curves of an NMOS transistor under different gate voltages according to a specific embodiment of this application are shown. Figure 4 A flowchart illustrating a power transistor contact resistance measurement method according to another specific embodiment of this application is shown; Figure 5 A schematic structural block diagram of a measurement system according to a specific embodiment of this application is shown; Figure 6 A circuit diagram of a measuring device according to a specific embodiment of this application is shown; Figure 7 A flowchart illustrating a specific embodiment of the calibration method based on contact resistance of this application is shown. Figure 8 A table showing the measured values of total resistance, on-resistance, and contact resistance under different gate voltages according to a specific embodiment of this application is provided.
[0029] like Figure 1 As shown, the power transistor contact resistance measurement method of this application includes: S110: Use a measuring device carrying probes to obtain at least two sets of operating parameters of the power transistor in the linear operating region, wherein the at least two sets of operating parameters include the total resistance value and drain-source current under different gate voltages and constant drain voltage, and the total resistance value is the sum of the on-resistance value and the contact resistance value.
[0030] S120: Based on the electrical parameters related to the on-resistance and the relationship between the electrical parameters, using the total resistance and drain-source current under the first gate voltage and the total resistance and drain-source current under the second gate voltage, a set of equations is constructed regarding the on-resistance under the first gate voltage and the on-resistance under the second gate voltage to determine the on-resistance under the first gate voltage and / or the on-resistance under the second gate voltage.
[0031] S130: Determine the contact resistance value based on the total resistance value and on-resistance value under the first gate voltage or the total resistance value and on-resistance value under the second gate voltage.
[0032] To facilitate understanding of the overall solution of this application, before introducing the power transistor contact resistance measurement method of this application, we will first give a brief introduction to the principle it applies.
[0033] like Figure 2 As shown in the figure, a current-voltage characteristic curve consisting of the drain-source current and drain-source voltage of an NMOS device is displayed.
[0034] It should be understood that when measuring the drain-source current in the linear operating region using the two-wire DC test method, voltages are applied to the gate and drain of the NMOS device to make it operate in the linear operating region. Then, the drain-source current is read using a current sensing device such as a current sensor, and the apparent resistance is calculated, or the resistance value is read using a resistance measuring device such as a multimeter. Because the test circuit includes the contact resistance of the probes, the read resistance value is actually the total resistance of the conduction resistance and the contact resistance. Accordingly, the read drain-source current is actually the drain-source current after introducing the contact resistance, rather than the true drain-source current.
[0035] from Figure 2 As can be seen, as the voltage applied to the drain increases, the measured drain-source current also increases, meaning the drain-source current is directly proportional to the drain-source voltage and exhibits a linear relationship. Therefore, since the on-resistance and contact resistance are connected in series, simply measuring the volt-ampere characteristic curve composed of the drain-source current and drain-source voltage cannot distinguish the proportion of on-resistance to contact resistance.
[0036] When different voltages are applied to the gate and drain of an NMOS device, and the NMOS device operates in the linear operating region, the drain-source current can be measured multiple times to obtain the following: Figure 3The figure shows the current-voltage characteristic curves composed of drain-source current and drain-source voltage under different gate voltages.
[0037] from Figure 3 As can be seen, when the voltage applied to the drain remains constant, the drain-source current increases as the voltage applied to the gate increases. Therefore, this pattern can be used to calculate the change in on-resistance by applying different gate voltages. Then, by utilizing the characteristic that the contact resistance remains constant, the contact resistance value can be calculated, thereby eliminating the influence of the contact resistance on the drain-source current test.
[0038] This solution is based on the fundamental physical characteristics of MOS devices. Therefore, the power transistor contact resistance measurement method provided in this application is applicable to various gate-controlled power devices such as ordinary MOSFETs, NLDMOS, LDMOS, and LGBT, and has excellent technical universality.
[0039] Having understood the implementation principle of the power transistor contact resistance measurement method of this application, the measurement method will be described in detail below.
[0040] In step S110, before acquiring at least two sets of operating parameters, it is necessary to ensure that the power transistor operates in the linear operating region. This can be achieved, for example, by applying a voltage to the gate of the power transistor simultaneously with a measuring device. It is important to note that the voltage applied to the drain of the power transistor should not be too large; it must be lower than the difference between the gate voltage and the threshold voltage to ensure that the power transistor is in the ohmic conduction region, satisfying the requirement that the on-resistance is proportional to the reciprocal of the drain-source current.
[0041] Before acquiring at least two sets of operating parameters, an arbitrary voltage can be applied to the gate of the power transistor, followed by a small voltage applied to its drain. By adjusting the voltage applied to the drain, the power transistor can be made to operate in the linear operating region, and the drain-source current in this state can be acquired. In some embodiments, the drain-source current can be read using a current sensing device such as a current sensor.
[0042] It is understandable that the drain-source current measured here is actually the current flowing through the on-resistance and contact resistance. Therefore, the total apparent resistance under this gate voltage, i.e., the total resistance value, can be obtained by calculating the ratio of the drain-source voltage to the drain-source current.
[0043] In some embodiments, the total resistance value can be read using a resistance testing device such as a multimeter.
[0044] At this point, a set of working parameters can be obtained.
[0045] Then, when obtaining the next set of operating parameters, the voltage applied to the gate of the power transistor can be adjusted to another voltage so that the power transistor still operates in the linear operating region. At this time, the total resistance and drain-source current in this state can be obtained in the manner described above to obtain the second set of operating parameters. Among them, the small voltage applied to the drain of the power transistor is a constant voltage.
[0046] Of course, the above operation can be repeated afterward to obtain more sets of working parameters, thus obtaining at least two sets of working parameters.
[0047] After obtaining at least two sets of operating parameters, the contact resistance can be calculated by randomly selecting any two sets of operating parameters from these two sets. For ease of explanation, the gate voltages corresponding to the two sets of operating parameters are referred to as the first gate voltage and the second gate voltage.
[0048] In step S120, the electrical parameters related to the on-resistance can be, for example, the total resistance, contact resistance, drain-source current, channel voltage, etc. Accordingly, the relationship between the various electrical parameters can be, for example, the sum of the on-resistance and the contact resistance as the total resistance, i.e., the following equation (1); the ratio of the channel voltage to the drain-source current as the on-resistance, i.e., the following equation (2); or the drain-source current formula in the linear operating region, i.e., the following equation (3).
[0049] (1) (2) (3) Where R_total is the total resistance, Rch is the on-resistance, Rc is the contact resistance, Vds is the channel voltage, Ids is the drain-source current, μ is the carrier mobility, Cox is the gate oxide capacitance per unit area, W / L is the channel width-to-length ratio, Vgs is the gate voltage, and Vt is the threshold voltage.
[0050] In some embodiments, there are two probes, which are used to contact the source and drain of the power transistor respectively during measurement. Therefore, the aforementioned Rc representing the contact resistance can also be expressed as 2Rc.
[0051] It is worth noting that in some embodiments, equation (3) can be approximated as equation (4), that is: (4) Where β is the transconductance parameter, which is the product of carrier mobility, gate oxide capacitance per unit area, and channel width-to-length ratio.
[0052] This approximation stems from the fact that in the scenario described in this application, the power transistor is in the linear operating region, and the drain-source voltage is much smaller than the difference between the gate voltage and the threshold voltage, at which point 1 / 2V 2ds is a higher-order term of Vds, so it can be ignored.
[0053] By deriving and reasonably combining the aforementioned electrical parameters related to conduction resistance and the relationships between these parameters, a system of equations concerning conduction resistance can be constructed, thereby solving for the resistance value.
[0054] In some embodiments, step S120 can be implemented by the following steps: Step S121: Based on the relationship between total resistance, on-resistance and contact resistance, determine the resistance difference between the on-resistance under the first gate voltage and the on-resistance under the second gate voltage according to the total resistance value under the first gate voltage and the total resistance value under the second gate voltage.
[0055] Step S122: Based on the relationship between drain-source current and on-resistance and the drain-source current formula in the linear operating region, determine the resistance ratio between the on-resistance under the first gate voltage and the on-resistance under the second gate voltage according to the drain-source current under the first gate voltage and the drain-source current under the second gate voltage.
[0056] Step S123: Construct a set of equations about the on-resistance under the first gate voltage and the on-resistance under the second gate voltage based on the resistance difference and resistance ratio.
[0057] The steps described above and their derivation process will be explained one by one below.
[0058] In some embodiments, in step S121, the resistance difference between the on-resistance under the first gate voltage and the on-resistance under the second gate voltage can be obtained by calculating the difference between the total resistance under the first gate voltage and the total resistance under the second gate voltage. The principle is as follows: Based on the aforementioned equation (1), equations (5) and (6) can be obtained.
[0059] (5) (6) Where Rch1 is the on-resistance under the first gate voltage, R_total1 is the total resistance under the first gate voltage, Rch2 is the on-resistance under the second gate voltage, and R_total2 is the total resistance under the second gate voltage.
[0060] Since both equations (5) and (6) contain a term for contact resistance Rc, the difference between equations (5) and (6) can be obtained by subtracting the on-resistance under the first gate voltage and the on-resistance under the second gate voltage. This difference is the difference between the total resistance under the first gate voltage and the total resistance under the second gate voltage, i.e.: In some embodiments, step S122 can be implemented through the following process: First, based on the drain-source current formula in the linear operating region, the voltage ratio of the channel voltage under the first gate voltage to the channel voltage under the second gate voltage is determined by using the drain-source current under the first gate voltage and the drain-source current under the second gate voltage.
[0061] Then, based on the relationship between drain-source current, on-resistance, and channel voltage, the voltage ratio is converted to obtain the resistance ratio.
[0062] The principle used in the aforementioned steps is as follows: Based on the aforementioned equation (4), equations (7) and (8) can be obtained.
[0063] (7) (8) Wherein, Vgs1 is the first gate voltage, Vds1 is the channel voltage under the first gate voltage, Ids1 is the drain-source current under the first gate voltage, Vgs2 is the second gate voltage, Vds2 is the channel voltage under the second gate voltage, and Ids2 is the drain-source current under the second gate voltage.
[0064] Since both equations (7) and (8) contain the transconductance parameter β, the ratio of the channel voltage under the first gate voltage to the channel voltage under the second gate voltage can be obtained by calculating the ratio of equations (7) and (8), thus obtaining the relationship between the channel voltages under different gate voltage conditions, as shown in equation (9) below: (9) Furthermore, since the channel voltage under the first gate voltage and the channel voltage under the second gate voltage are unknown, equation (2) can be substituted into equation (4) to convert the relationship between the drain-source power supply and the channel voltage into a function of the on-resistance, i.e.: (10) Based on the aforementioned equation (10), equations (11) and (12) can be obtained.
[0065] (11) (12) Thus, the relationship between the on-resistance under different gate voltage conditions can be obtained, as shown in the following equation (13): (13) Of course, in some other embodiments, the resistance ratio of the on-resistance under the first gate voltage to the on-resistance under the second gate voltage can also be obtained in other ways.
[0066] When the on-resistance under the first gate voltage and the on-resistance under the second gate voltage are treated as two unknowns, and the resistance difference and resistance ratio between the two gate voltages are known, a system of equations can be constructed regarding the on-resistance under the first and second gate voltages. By analyzing this system of equations, the on-resistance under the first gate voltage and / or the on-resistance under the second gate voltage can be obtained, thus facilitating the further determination of the contact resistance.
[0067] Specifically, taking the on-resistance Rch1 under the first gate voltage as an example: Right now: In this equation, R_total1, R_total2, Vgs1, Vgs2 and Vt are all known quantities, so the on-resistance under the first gate voltage can be calculated.
[0068] Furthermore, once the on-resistance under the first gate voltage or the on-resistance under the second gate voltage is determined, the contact resistance can be calculated using the following formula (14).
[0069] (14) Thus, this application utilizes the physical characteristic that the on-resistance of power devices changes regularly under different gate voltages, while the contact resistance of probes remains constant. By measuring the total resistance under at least two different gate voltages, a system of equations is established to directly solve for and eliminate the influence of contact resistance.
[0070] It should be understood that although the aforementioned steps can calculate the contact resistance, the calculation is based on the total resistance and drain-source current at a single measurement point. Since single-point current values are prone to measurement errors, the accuracy of the calculated on-resistance and contact resistance is limited. To mitigate the errors introduced by a single measurement point, after analytically obtaining the on-resistance under the first gate voltage and / or the on-resistance under the second gate voltage using a system of equations, the on-resistance under the first gate voltage and / or the on-resistance under the second gate voltage can be calibrated.
[0071] like Figure 4 As shown, in some embodiments, the power transistor contact resistance measurement method of this application further includes: Step S410: Select two sets of operating parameters from at least two sets of operating parameters; Step S420: Based on the electrical parameters related to the on-resistance and the relationship between the electrical parameters, a set of equations about the on-resistance is constructed using two sets of operating parameters to determine the on-resistance under the gate voltage corresponding to the two sets of operating parameters.
[0072] Step S430: Repeat the first two steps to obtain the on-resistance under multiple different gate voltages.
[0073] Step S440: The relationship between gate voltage and on-resistance is obtained by fitting the on-resistance under multiple different gate voltages, so as to redetermine the on-resistance under the first gate voltage and the on-resistance under the second gate voltage.
[0074] The implementation process of steps S410 and S420 is the same as that of steps S110 and S120, so it will not be described again here.
[0075] In some embodiments, after obtaining the on-resistance at multiple different gate voltages with the same drain voltage applied, linear or polynomial fitting can be performed on these measurement points to obtain the relationship between the gate voltage and the on-resistance at a constant drain voltage. The on-resistance at the first gate voltage and the second gate voltage can be calibrated using this relationship. A more accurate contact resistance can then be obtained by calculating the contact resistance using the calibrated on-resistance at either the first or second gate voltage.
[0076] This concludes the description of the power transistor contact resistance measurement method of this application. The contact resistance obtained by the power transistor contact resistance measurement method of this application can be used to calibrate the measured values of various electrical parameters obtained when the power transistor is in the linear operating region. Among them, the electrical parameters that can be calibrated can be, for example, the drain-source current, on-resistance, and threshold voltage of the power transistor when it is in the linear operating region.
[0077] In summary, the power transistor contact resistance measurement method of this application can directly obtain the total resistance and drain-source current of a power transistor operating in the linear operating region under two different gate voltages and a constant drain voltage. Since the on-resistance has a functional relationship with the gate voltage when the drain voltage is constant, and the contact resistance has the characteristic of remaining constant, a system of equations can be constructed using the total resistance and drain-source current under these two different gate voltages to derive the on-resistance under the first gate voltage and the on-resistance under the second gate voltage, thereby determining the magnitude of the contact resistance. When the contact resistance is known, various electrical parameters of the power transistor in the linear operating region can be calibrated.
[0078] This application proposes a method for extracting contact resistance by embedding the device's own resistance under different driving intensities, without requiring a dedicated short-circuit test structure. The problem is transformed from measuring an unknown variable and an unknown function into measuring an unknown variable and a measurable proportionality coefficient. The accuracy of the proportionality coefficient directly determines the accuracy of the contact resistance extraction. Specifically, by measuring the electrical response of the same device under different gate voltages, a system of equations is constructed using the device's own physical characteristics, allowing direct calculation of the probe contact resistance without relying on any external reference structure. This fundamentally eliminates the systematic error introduced by contact resistance in the traditional two-wire method, improving the measurement accuracy of drain-source current by 1-2 orders of magnitude, and reducing the measurement uncertainty from >50% to <5%, achieving a measurement confidence level comparable to the four-wire method. This completely solves the industry problem of insufficient accuracy in two-wire testing of low-resistance devices. Furthermore, this application can be based on existing standard two-wire test hardware, i.e., probe cards and test channels, without requiring additional hardware resources as with the four-wire method, thus resulting in zero hardware modification costs. Furthermore, the measurement process can avoid misclassifying good products as defective products or vice versa due to fluctuations in contact resistance, thereby improving the authenticity and reliability of the test results.
[0079] The following is combined Figure 5 A measurement system 500 according to another aspect of this application is described. For example... Figure 5 As shown, the measurement system 500 may include a measurement device 510 carrying a probe, a memory 520, and a processor 530.
[0080] like Figure 6 As shown, the measuring device 510 carrying the probe includes a first adjustable power supply 511, a second adjustable power supply 512, and a current detection module 513.
[0081] Specifically, the first adjustable power supply 511 is connected to the gate of the power transistor to provide a first target voltage. The first target voltage is the voltage applied to the gate of the power transistor. As an example, the first adjustable power supply 511 can be a voltage source, with its positive terminal connected to the gate of the power transistor and its negative terminal connected to the source of the power transistor and grounded.
[0082] The second adjustable power supply 512 is connected to the drain of the power transistor and is used to provide a second target voltage. The second target voltage is the voltage applied to the drain of the power transistor. The second adjustable power supply 512 can be, for example, a voltage source.
[0083] The current detection module 513 is connected to the drain of the power transistor and is used to detect the drain-source current of the power transistor. As an example, the current detection module 513 can be an ammeter. The ammeter can be located on the line connecting the drain of the power transistor to the second adjustable power supply 512, or it can be connected to the source of the power transistor.
[0084] The memory 520 stores a computer program executed by the processor 530. When the computer program is run, it causes the processor 530 to perform the aforementioned power transistor contact resistance measurement method according to the embodiments of this application. The power transistor contact resistance measurement method has been described in detail above. Those skilled in the art can understand the structure and operation of the measurement system 500 in conjunction with the above description. For the sake of brevity, it will not be described again here.
[0085] The following is combined Figure 7 This describes a calibration method based on contact resistance according to another aspect of this application. For example... Figure 7 As shown, the calibration method based on contact resistance includes: Step S710: Obtain the contact resistance value using the power transistor contact resistance measurement method described in the previous embodiment.
[0086] Step S720: Obtain the total resistance of the power transistor in the linear operating region at the target gate voltage and target drain voltage.
[0087] Step S730: Determine the on-resistance value under the target gate voltage and target drain voltage based on the contact resistance and the total resistance value under the target gate voltage and target drain voltage.
[0088] Step S740: Determine the calibrated drain current based on the target drain voltage, the target gate voltage, and the on-resistance at the target drain voltage.
[0089] Understandably, since the contact resistance remains constant, the corresponding on-resistance can be calibrated by obtaining the total resistance value at any gate voltage and any drain voltage. Here, any gate voltage mentioned above is the target gate voltage, and any drain voltage is the target drain voltage.
[0090] This calibration method is primarily applicable when multiple sets of operating parameters are available before calculating the contact resistance. A specific example is provided below to illustrate this application scenario.
[0091] In a specific example, after the measurement system is connected to the power transistor, the test system can automatically perform a multi-gate voltage scan to obtain the drain-source current and total resistance values at different gate voltages under the target drain voltage. Then, the contact resistance value is determined using the power transistor contact resistance measurement method described in the previous embodiment. Since the total resistance value at any gate voltage under the target drain voltage has been obtained, the corresponding on-resistance can be determined based on this total resistance value and the contact resistance. That is, the on-resistance value is the difference between the total resistance value and the contact resistance value.
[0092] The target drain voltage is a constant drain voltage. The target drain voltage can be any small voltage that keeps the power transistor in its linear operating region. Based on this, this application can achieve calibration of the on-resistance under arbitrary gate voltage and arbitrary drain voltage. For example, as... Figure 8 The table shows the total resistance, on-resistance, and contact resistance under different gate voltages.
[0093] Furthermore, after redetermining the resistance values of the on-resistance under the target gate voltage and target drain voltage, the drain-source current can be calibrated based on the relationship between the on-resistance, drain-source voltage, and drain-source current.
[0094] like Figure 6 The circuit diagram of the measuring device 510 shown illustrates this. Since the source of the power transistor is grounded, the aforementioned drain-source voltage is the voltage applied to the drain of the power transistor, and the aforementioned drain-source current is the drain current of the power transistor. Specifically, the drain-source current under the target gate voltage and target drain voltage can be obtained by calculating the ratio of the drain voltage to the on-resistance, thereby calibrating the drain-source current.
[0095] In some embodiments, a large number of identical power transistors can also be arranged in an array and connected in parallel to form a power array. For this power array, the drain-source current is the sum of the drain-source currents of each power transistor. This application enables large-scale parallel testing, which can be applied to such power arrays to calibrate the drain-source current of each power transistor individually, thereby obtaining the true device performance.
[0096] Furthermore, according to embodiments of this application, a storage medium is also provided, on which program instructions are stored. When the program instructions are executed by a computer or processor, they are used to perform corresponding steps of the power transistor contact resistance measurement method of this application. The storage medium may, for example, include a memory card of a smartphone, a storage component of a tablet computer, a hard disk of a personal computer, a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a portable compact disc read-only memory (CD-ROM), a USB memory, or any combination of the above storage media. A computer-readable storage medium may be any combination of one or more computer-readable storage media.
[0097] Furthermore, according to embodiments of this application, a computer program is also provided, which can be stored on a cloud or local storage medium. When this computer program is run by a computer or processor, it is used to perform the corresponding steps of the power transistor contact resistance measurement method of embodiments of this application.
[0098] Based on the above description, the power transistor contact resistance measurement method and system according to the embodiments of this application can directly obtain the total resistance and drain-source current of a power transistor operating in the linear operating region under two different gate voltages and constant drain voltages. Since the on-resistance has a functional relationship with the gate voltage when the drain voltage is constant, and the contact resistance has the characteristic of remaining constant, a system of equations can be constructed using the total resistance and drain-source current under these two different gate voltages to derive the on-resistance under the first gate voltage and the on-resistance under the second gate voltage, thereby determining the magnitude of the contact resistance. When the contact resistance is known, various electrical parameters of the power transistor in the linear operating region can be calibrated. This measurement method can achieve the measurement accuracy of the Kelvin four-wire test method, while avoiding high implementation costs, making it more suitable for large-scale parallel testing scenarios.
[0099] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of the invention. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of the invention. All such changes and modifications are intended to be included within the scope of the invention as claimed in the appended claims.
[0100] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0101] In the several embodiments provided by this invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed.
[0102] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.
[0103] Similarly, it should be understood that, in order to streamline the invention and aid in understanding one or more of the various aspects of the invention, features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of the invention. However, the method of the invention should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with fewer features than all of those in a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.
[0104] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or elements of any method or apparatus so disclosed may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.
[0105] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims, any of the claimed embodiments can be used in any combination.
[0106] The various component embodiments of the present invention can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some modules in the article analysis device according to embodiments of the present invention. The present invention can also be implemented as an apparatus program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such programs implementing the present invention can be stored on a computer-readable medium or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.
[0107] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.
[0108] The above are merely specific embodiments or descriptions of the present invention, and the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. The scope of protection of the present invention should be determined by the scope of the claims.
[0109] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will arise in the mind of those skilled in the art, all of which will fall within the spirit and scope of the concept disclosed herein. More specifically, various modifications and changes may be made in terms of the arrangement and / or components of the subject matter within the scope of this disclosure, the drawings, and the appended claims. In addition to modifications and changes in the components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.
Claims
1. A method for measuring the contact resistance of a power transistor, characterized in that, The method for measuring the contact resistance of the power transistor includes: At least two sets of operating parameters of the power transistor in the linear operating region are obtained using a measuring device carrying a probe. The at least two sets of operating parameters include the total resistance value and the drain-source current under different gate voltages and constant drain voltage, wherein the total resistance value is the sum of the on-resistance value and the contact resistance value. Based on the electrical parameters related to the on-resistance and the relationship between the electrical parameters, using the total resistance and drain-source current under the first gate voltage and the total resistance and drain-source current under the second gate voltage, a set of equations is constructed regarding the on-resistance under the first gate voltage and the on-resistance under the second gate voltage to determine the on-resistance under the first gate voltage and / or the on-resistance under the second gate voltage. The contact resistance value is determined based on the total resistance value and on-resistance value under the first gate voltage or the total resistance value and on-resistance value under the second gate voltage.
2. The method for measuring the contact resistance of a power transistor as described in claim 1, characterized in that, The method of constructing a set of equations regarding the on-resistance under the first gate voltage and the on-resistance under the second gate voltage, based on the electrical parameters related to the on-resistance and the relationships between these parameters, using the total resistance and drain-source current under the first gate voltage and the total resistance and drain-source current under the second gate voltage, includes: Based on the relationship between total resistance, on-resistance and contact resistance, the resistance difference between the on-resistance under the first gate voltage and the on-resistance under the second gate voltage is determined according to the total resistance value under the first gate voltage and the total resistance value under the second gate voltage. Based on the relationship between the drain-source current and the on-resistance and the drain-source current formula of the linear operating region, the resistance ratio of the on-resistance under the first gate voltage to the on-resistance under the second gate voltage is determined according to the drain-source current under the first gate voltage and the drain-source current under the second gate voltage. Based on the resistance difference and the resistance ratio, construct a set of equations regarding the on-resistance under the first gate voltage and the on-resistance under the second gate voltage.
3. The method for measuring the contact resistance of a power transistor as described in claim 2, characterized in that, The difference between the on-resistance under the first gate voltage and the on-resistance under the second gate voltage is obtained by calculating the difference between the total resistance under the first gate voltage and the total resistance under the second gate voltage.
4. The method for measuring the contact resistance of a power transistor as described in claim 2, characterized in that, The determination of the resistance ratio between the on-resistance under the first gate voltage and the on-resistance under the second gate voltage, based on the relationship between the drain-source current and the on-resistance and the drain-source current formula in the linear operating region, and according to the drain-source current under the first gate voltage and the drain-source current under the second gate voltage, includes: Based on the drain-source current formula of the linear operating region, the voltage ratio of the channel voltage under the first gate voltage to the channel voltage under the second gate voltage is determined by using the drain-source current under the first gate voltage and the drain-source current under the second gate voltage. Based on the relationship between the drain-source current, the on-resistance, and the channel voltage, the voltage ratio is converted to obtain the resistance ratio.
5. The method for measuring the contact resistance of a power transistor as described in claim 4, characterized in that, The drain-source current formula for the linear operating region is approximated as: Ids=β(Vgs-Vt)Vds Where β is the transconductance parameter, Vgs is the gate voltage, Vt is the threshold voltage, and Vds is the channel voltage.
6. The method for measuring the contact resistance of a power transistor as described in claim 1, characterized in that, The method further includes: Select two sets of operating parameters from the at least two sets of operating parameters; Based on the electrical parameters related to the on-resistance and the relationships between these electrical parameters, a set of equations about the on-resistance is constructed using the two sets of operating parameters to determine the on-resistance under the gate voltage corresponding to the two sets of operating parameters. Repeat the first two steps to obtain the on-resistance at multiple different gate voltages; The relationship between gate voltage and on-resistance is obtained by fitting the on-resistance under the multiple different gate voltages, so as to redetermine the on-resistance under the first gate voltage and the on-resistance under the second gate voltage.
7. The method for measuring the contact resistance of a power transistor as described in claim 1, characterized in that, The contact resistance is used to calibrate the measured values of the electrical parameters obtained when the power transistor is in the linear operating region. The calibrable electrical parameters include at least the drain-source current, on-resistance, and threshold voltage of the power transistor when it is in the linear operating region.
8. A measurement system, characterized in that, The device includes a measuring apparatus carrying a probe, a memory, and a processor. The memory stores a computer program that is executed by the processor, which, when executed by the processor, causes the processor to perform the power transistor contact resistance measurement method according to any one of claims 1-7.
9. The measurement system as described in claim 8, characterized in that, The measuring device carrying the probe includes: A first adjustable power supply is connected to the gate of the power transistor to provide a first target voltage; A second adjustable power supply is connected to the drain of the power transistor to provide a second target voltage; A current detection module is connected to the drain of the power transistor and is used to detect the drain-source current of the power transistor.
10. A calibration method based on contact resistance, characterized in that, The calibration method based on contact resistance includes: The resistance value of the contact resistance is obtained using the power transistor contact resistance measurement method as described in any one of claims 1-7; Obtain the total resistance of the power transistor in the linear operating region under the target gate voltage and the target drain voltage; Based on the contact resistance and the total resistance value under the target gate voltage and the target drain voltage, determine the on-resistance value under the target gate voltage and the target drain voltage; The calibrated drain-source current is determined based on the target drain voltage, the target gate voltage, and the on-resistance at the target drain voltage.