Crimping power device failure point positioning method and system
By employing methods such as electrical parameter testing, ultrasonic scanning, hotspot localization, and scanning electron microscopy-energy dispersive spectroscopy analysis, the lack of specificity in locating failure points of press-fit power devices has been addressed, enabling rapid and accurate localization that is adapted to the unique packaging structure and failure modes of press-fit power devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- STATE GRID ELECTRIC POWER RES INST
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-12
AI Technical Summary
Existing methods for locating failure points in welded power devices cannot be directly applied to crimped power devices. Furthermore, crimped power devices suffer from high failure costs and limited experience in accumulating failure data, making traditional methods less targeted.
By employing methods such as electrical parameter testing, ultrasonic scanning detection, hotspot localization, and scanning electron microscopy-energy dispersive spectroscopy analysis, combined with extended resistance measurement, the failure points of the press-fit power devices are gradually located, including failure sub-units, chips, regions, and nanoscale structural defects.
It enables rapid and accurate location of failure points in press-fit power devices, solving the problem of lack of specificity in traditional methods. It is highly feasible and operable, and can analyze different failure modes and requirements.
Smart Images
Figure CN122017509A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device testing technology, and specifically to a method and system for locating failure points in press-fit power devices. Background Technology
[0002] Currently, power electronics technology is developing towards higher voltage, higher power, and higher reliability. Driven by application demands in smart grids, new energy power generation, rail transit, and industrial drives, traditional welded power devices are gradually becoming inadequate. Welded power devices suffer from issues such as the lifespan of bonded wire connections and uneven current distribution among parallel chips. In contrast, press-fit power devices utilize a structure where the emitter side of the chip is primarily connected by pads, disc springs, and molybdenum sheets (without bonded wires). Multiple chips are connected in parallel to form sub-units, which in turn form module units. This approach offers advantages such as low thermomechanical stress, good current sharing capability, low parasitic parameters, and ease of modular production, making it a promising candidate for applications in new energy grid connection, flexible DC transmission, and rail transit.
[0003] Due to changes in packaging structure and chip design, the failure modes of press-fit power devices have also changed accordingly, including changes in interface contact mechanisms, enhanced multiphysics coupling, and differences in material processing systems. Existing failure point location methods for soldered power devices cannot be directly applied to the failure mechanism research of press-fit power devices. Furthermore, based on specific application scenarios, press-fit power devices suffer from high failure costs and limited failure experience accumulation, while improving device reliability necessitates analysis and improvement through failure point location. Summary of the Invention
[0004] Purpose of the invention: The first purpose of this invention is to provide a method for locating the failure point of a crimped power device that is highly feasible for multiple failure modes. The second purpose is to provide a system for locating the failure point of a crimped power device.
[0005] Technical Solution: Firstly, this invention provides a method for locating the failure point of a crimped power device, comprising the following steps:
[0006] Electrical parameters of the crimped power device are tested, and the obtained electrical parameter test values are compared with the corresponding electrical parameter standard values to determine the failed sub-units in the crimped power device.
[0007] The leakage current value of each chip in the failed sub-unit is measured one by one, and the chip with the leakage current value greater than the set threshold is identified as the failed chip;
[0008] The failure area on the failed chip can be determined by ultrasonic scanning detection or hotspot location.
[0009] The failure area was profiled by scanning electron microscopy-energy dispersive spectroscopy to locate the failure point at the micro-nano scale.
[0010] The surface structure at the failure point is etched to identify the cellular defects at the failure point and locate the structural initiation position of the failure point at the nanoscale.
[0011] Specifically, the electrical parameter testing of the crimped power device includes: setting test conditions according to the model of the crimped power device, performing high and low temperature dynamic and static retests on each sub-unit of the crimped power device through a dynamic and static testing machine, obtaining the electrical parameter test values, comparing them with the corresponding electrical parameter standard values, and determining the location of the failed sub-unit in the crimped power device.
[0012] Preferably, the electrical parameter testing of the crimped power device also includes: for the crimped power device that has broken down and burned out, testing the CE terminal of the crimped power device with a multimeter to directly locate the failed sub-unit.
[0013] Specifically, ultrasonic scanning detection and localization includes: using interface ultrasonic wave reflection technology to observe whether there are defects at each interface of the chip, and marking the locations where defects exist as failure areas.
[0014] Specifically, hotspot localization includes: using a thermal emission microscope, shorting the GE terminal of the failed chip, continuously applying pressure to the CE terminal, monitoring the temperature distribution and changes on the surface of the failed chip in real time, recording the hotspot locations on the surface of the failed chip and marking them as failure areas.
[0015] Specifically, the cross-sectional analysis of the failure area using scanning electron microscopy-energy dispersive spectroscopy includes: cutting, grinding, and polishing the failure area to obtain a test sample; using scanning electron microscopy-energy dispersive spectroscopy to detect the test sample; observing the physical structure of the failure area by combining the secondary electron mode and backscatter mode of the scanning electron microscope; characterizing the material composition of the failure area by energy dispersive spectroscopy; and thus locating the failure point at the micro-nano scale.
[0016] Preferably, the above method further includes the following steps:
[0017] After identifying the failure area on the chip, the structure in the failure area is removed layer by layer from the outside to the inside, and the structural changes in the failure area are recorded layer by layer until the initial position of the failure point is located. Then, the failure area is analyzed in profile by scanning electron microscopy-energy dispersive spectroscopy to locate the failure point at the micro-nano scale.
[0018] Preferably, the above method further includes the following steps:
[0019] After determining the location of the failed chip in the failed subunit, the extended resistance of the failed chip is measured. After confirming the crystal orientation of the substrate material of the failed chip, the extended resistance of the failed chip is measured layer by layer. The measured value of the extended resistance is compared with the standard value to obtain the doping distribution of the failed chip, and then the process defect location of the failed chip is identified and marked as the failure point.
[0020] Secondly, the present invention provides a failure point location system for crimped power devices, comprising:
[0021] Failure Sub-unit Locating Module: Used to perform electrical parameter tests on crimped power devices, compare the obtained electrical parameter test values with the corresponding electrical parameter standard values, and determine the failure sub-units in the crimped power devices;
[0022] Failed chip location module: used to measure the leakage current value of each chip in the failed sub-unit one by one, and identify the chip with the leakage current value greater than the set threshold as the failed chip;
[0023] Failure Area Location Module: Used to determine the failure area on the chip by ultrasonic scanning detection or hotspot location;
[0024] Micro-nanoscale failure point localization module: used to perform cross-sectional analysis of the failure area using scanning electron microscopy-energy dispersive spectroscopy to locate failure points at the micro-nano scale;
[0025] Nanoscale failure point location module: used to etch the surface structure at the failure point, identify the cellular defects at the failure point, and locate the structural starting position of the failure point at the nanoscale.
[0026] Preferably, the above system further includes the following modules:
[0027] Failure point de-layering and localization module: After determining the failure area on the failure chip, it removes the structure in the failure area layer by layer in the order from the outside to the inside, and records the structural changes in the failure area layer by layer until the initial position of the failure point is located.
[0028] Process defect location module: Used to measure the extended resistance of the failed chip. After confirming the crystal orientation of the substrate material of the failed chip, the extended resistance of the failed chip is measured layer by layer. The measured value of the extended resistance is compared with the standard value to obtain the doping distribution of the failed chip, and then the process defect location of the failed chip is identified and marked as the failure point.
[0029] Beneficial Effects: Compared with existing technologies, the significant advantages of this invention are: First, it locates the failed sub-unit within the press-fit power device using a dynamic and static testing machine or multimeter. Then, it locates the failed chip within the failed sub-unit using IV testing, achieving rapid localization from the device to the internal chip. Next, it achieves planar localization of the internal failure point of the chip through three methods: diffusion resistance measurement, hotspot localization, and ultrasonic localization. The appropriate method can be selected based on the actual failure situation and equipment capabilities. Further, it combines planar delamination localization, SEM&EDS, FIB, and other microscopic localization methods to achieve precise localization of the failure point. Furthermore, this invention provides a scheme for identifying the location of process defects in the failed chip through diffusion resistance measurement, which can explain some special failure scenarios. Based on traditional analysis methods for welded power devices, this invention proposes a specific and flexible failure point location method and device selection scheme, taking into account the unique packaging structure and failure modes of crimped power devices. It solves the problem that traditional failure point location methods lack specificity for crimped power devices, and has the advantages of strong operability and high feasibility. It can solve the problem of unclear focus and correlation of analysis results of different failure point location devices, and can sort out targeted analysis processes for different failure modes and analysis needs. Attached Figure Description
[0030] Figure 1 This is a flowchart of the method in Embodiment 1 of the present invention;
[0031] Figure 2 This is a diagram showing the IV test location results of the failed chip in Embodiment 1 of the present invention;
[0032] Figure 3 This is an interface state diagram of the chip / substrate welding for ultrasonic scanning detection and positioning of the failed chip in Embodiment 1 of the present invention;
[0033] Figure 4 This is an interface state diagram of the chip surface / molybdenum sheet welding layer for ultrasonic scanning detection and positioning of the failed chip in Embodiment 1 of the present invention;
[0034] Figure 5 This is a schematic diagram of the hotspot location results of the failed chip in Embodiment 1 of the present invention;
[0035] Figure 6 This is a scanning electron microscope-energy dispersive spectroscopy (SEM-EDS) characterization diagram of the layered structure in Embodiment 1 of the present invention;
[0036] Figure 7 This is a scanning electron microscope-energy dispersive spectroscopy (SEM-EDS) elemental characterization diagram of the layered structure in Embodiment 1 of the present invention;
[0037] Figure 8 This is a schematic diagram of the location results of the focused ion beam failure point in Embodiment 1 of the present invention;
[0038] Figure 9This is a schematic diagram of the diffusion resistance characterization results in Embodiment 1 of the present invention. Detailed Implementation
[0039] A preferred embodiment of the present invention will be further described below with reference to the accompanying drawings.
[0040] Example 1
[0041] Please see Figure 1 As shown, this embodiment provides a method for locating the failure point of a crimped power device, including the following steps:
[0042] S1. Perform electrical parameter tests on the crimped power device, compare the obtained electrical parameter test values with the corresponding electrical parameter standard values, and determine the failed sub-units in the crimped power device.
[0043] During implementation, based on the model of the crimped power device, such as the labeled voltage and current ratings, corresponding test conditions are set. High and low temperature dynamic and static retests are performed on suspected abnormal crimped power devices and each sub-unit of the crimped power device using dynamic and static testing equipment. Special attention is paid to static parameters such as ICES, IGES, Vcesat, and VF. The datasheets of the crimped power devices are compared to preliminarily determine the failure mode, such as short-circuit breakdown, parameter drift, or open circuit. Sub-units are tested one by one to determine the location of the failed sub-unit within the failed crimped power device. Furthermore, as high-voltage, high-current devices, crimped power devices generate significant energy upon failure, easily leading to short-circuit breakdown. For crimped power devices that can be directly identified as broken down, the failed sub-unit can be quickly located by testing its CE terminal with a multimeter. If all sub-units are intact, the total CE resistance is normal; if a sub-unit is completely short-circuited, the total CE resistance decreases significantly; if a sub-unit is completely open-circuited, after the branch is disconnected, if other branches are intact, the total CE resistance does not change significantly until most branches fail. In addition, due to the impact of failure, devices near the burned-out module / sub-unit are also prone to secondary damage, such as abnormal resistance. When identifying the failed sub-unit, it is necessary to distinguish them and focus on the location of the original failed sub-unit.
[0044] S2. Measure the leakage current of each chip in the failed sub-unit one by one, and identify the chip with a leakage current value greater than the set threshold as the failed chip.
[0045] During implementation, before performing IV testing on each chip in the failed subunit using a probe station and semiconductor analyzer, certain anti-sparking measures must be applied. During testing, apply fluorinated oil to the surface of the sample to be tested or place the sample in a nitrogen environment, and perform the following test steps on each chip: short-circuit the GE terminal and gradually and slowly increase the CE terminal voltage, while simultaneously recording the leakage current value. When the leakage current at the CE terminal is greater than 100μA, the chip is considered to be abnormal.
[0046] Please refer to Figure 2 As shown, Figure 2 The 12 voltage / current curves of different colors represent the leakage current changes at the CE terminal of the 12 chips in the failed subunit at different voltages. Among them, chips No. 3 (orange) and No. 9 (green) show a significant upward trend in leakage current at a voltage of approximately 2100V, while the leakage current curves of the other 10 chips are relatively stable, indicating that the leakage current abnormality is mainly found in chips No. 3 and No. 9 in this subunit.
[0047] S3. Determine the failure area on the failed chip by ultrasonic scanning detection or hotspot location.
[0048] Specifically, interface ultrasonic reflection technology can be used to determine the location of failure areas on a faulty chip and detect the state of the solder interface. The sample is placed in deionized water, with the ultrasonic probe held approximately 2-3 cm above the sample surface. The control software adjusts the detection range and selects an appropriate threshold, focusing on the interface between the chip's front side and the solder layer. Defects such as cracks, voids, and delamination are observed, and the locations of these abnormal points are recorded as failure areas. The relationship between the failure areas on the chip surface and the locations of voids / delamination in the solder is then considered. If the failure area is located directly above a solder void, it indicates that the chip's heat dissipation capacity is affected, and this is recorded. Further analysis using failure information obtained from other steps can then confirm a thermal failure.
[0049] Please refer to Figure 3 and Figure 4 The image shows the ultrasonic scanning results of two different interfaces of the same sample. Figure 2 It characterizes the interface state of the chip / substrate bonding. Figure 3 The interface state of the chip surface / molybdenum sheet bonding layer was characterized. Figure 2 Within the red box, a breakdown point (a black hole with crack propagation) is visible on the surface of the active area of the chip, beneath the molybdenum sheet. Figure 3 No voids or delamination were found in the chip soldering layer at the location indicated by the red box (no large white spots or abrupt grayscale changes were found).
[0050] In specific scenarios, hotspot localization refers to the real-time detection of areas of a chip with abnormal temperature rise due to abnormal current or structural defects under a certain power-on state. This embodiment uses a Thermal / EMMI hotspot localization device (thermal emission microscope). The GE terminal of the failed chip is shorted, and the CE terminal is continuously pressurized to detect the temperature distribution and changes on the chip surface in real time. Typically, limiting the leakage current to within 1mA is sufficient to observe a clear leakage point. The leakage point locations include active regions, transition regions, and termination structures. If the leakage point locations are relatively dispersed, the following options are available: combine with other failure information for judgment; perform delayer localization, repeating the hotspot localization test after removing part of the metal layer to observe whether the hotspot locations tend to concentrate, and then mark them as failure areas.
[0051] To further observe and record the changes in the failure area obtained from ultrasonic scanning or hotspot localization across different layers of the failed chip, chip delamination can be used for localization. First, using chemical reagents or ion etching equipment, the PI layer, passivation layer, and metal layer at the failure area are removed layer by layer from the outside in. This embodiment uses a combination of alkaline solution and ion etching. During delamination, the reaction time and dosage must be carefully controlled to avoid introducing secondary damage. After each layer is removed, plasma cleaning is performed, and the morphology of the PI layer, passivation layer, and metal layer is recorded layer by layer. By comparing the layer-by-layer changes in the failure area, the starting location of the failure point can be determined. If there is a need to observe the PI layer or passivation layer, chip delamination can be skipped, and subsequent steps can be performed directly.
[0052] Please refer to Figure 5 The image shown is a hotspot location result obtained after layer removal and localization. Figure 5 The area marked in red is a significant hotspot in the record, and the location of this hotspot is marked as an invalid area.
[0053] S4. The failure area is profiled by SEM & EDS (scanning electron microscope-energy dispersive spectroscopy) to locate the failure point at the micro-nano scale.
[0054] In the specific implementation process, cold sealing and fixed-point sample preparation techniques are used to perform micro-nano-level profile analysis on the failure area. First, it is necessary to ensure the smoothness and cleanliness of the sample surface, i.e., repeatedly improving surface quality through a cutting-grinding-polishing process to avoid scratches or contamination that could affect observation. Secondary electron and backscattered electron modes are two main imaging modes in SEM (Scanning Electron Microscopy), with significantly different principles and imaging characteristics. The former involves the interaction of incident electrons with surface atoms to excite low-energy electrons, while the latter involves the elastic interaction of incident electrons with deep atomic nuclei to reflect high-energy electrons back. When observing physical structures using SEM in combination with secondary electron and backscattered modes, the electron voltage is set to 1~3kV at high resolution. A reasonable working distance is adjusted, and the area to be observed is centered in the field of view. After adjustment, the secondary electron mode can be directly switched to backscattered mode to resolve layered material structures, but the electron voltage needs to be increased to above 10kV to ensure high image resolution. Before using EDS (energy dispersive spectroscopy) to characterize the local material composition, set the electron voltage to 15-20kV and adjust the working distance to about 10mm. Generally, EDS is used for qualitative analysis of common metallic materials in the semiconductor field (aluminum, copper, tin, and lead, etc.). It combines the analysis results of point, line, and surface modes to collaboratively locate failure points.
[0055] Please refer to Figure 6 and Figure 7 As shown, in this embodiment, the integrity of the chip and the layered structures on its upper and lower surfaces is observed using a scanning electron microscope-energy dispersive spectroscopy (SEM). Figure 6 The image shows a layered structure including a surface welding layer, a front metal layer, a back metal layer, and a substrate. Figure 7 This characterizes the element distribution in different regions, serving as a qualitative analysis method. Figure 7 The main element in the blue area is aluminum, the main element in the purple area is lead, the main element in the cyan area is nickel, the main element in the orange area is tin, and the main element in the red area is silicon.
[0056] S5. The surface structure at the failure point is etched by FIB (Focused Ion Beam) to identify the cellular defects at the failure point and locate the structural starting position of the failure point at the nanoscale.
[0057] Unlike SEM electron beams, FIB uses ion beams (Ga+) to achieve precise etching of the surface layers at failure points. At the nanoscale, based on the failure points located at the micro-nano scale in step S4, a designated analysis area is selected, and the etching depth and rate are set. Changes in the microstructures of the gate oxide layer, dielectric layer, metal layer, and polysilicon are observed in real time. During the ion beam etching process, the image can be dynamically observed at magnifications of 20,000 to 100,000 times. Local structural changes in individual cells are recorded periodically, with a focus on observing the integrity of easily failed structures such as gate oxide and dielectric layers, thus locating the structural initiation position of the failure point at the nanoscale.
[0058] Please refer to Figure 8 As shown, Figure 8 The cellular defect structure obtained after FIB etching clearly shows the difference between it and the standard structures on both sides.
[0059] Furthermore, this embodiment also provides a method for locating failure points generated under certain specific conditions through SRP characterization. After identifying the failed chip in step S2, the crystal phase of the substrate material of the failed chip is first confirmed, such as silicon. <100> The sample to be tested is fixed on the sample stage, ensuring stable probe contact. A small current in the μA range is applied, the voltage drop V is measured, and the spreading resistance Rsp is calculated. The above steps are repeated layer by layer for testing. The test data is calibrated using a standard resistor sample (with known resistivity) to obtain the doping distribution. SRP characterizes minimal damage to the sample to be tested. Through SRP testing, information such as the longitudinal carrier distribution and PN junction depth at the chip failure point can be obtained, identifying the specific location of defects introduced by processes such as ion implantation and marking them as failure points. By comparing with standard values, the degradation mechanism of abnormal carrier distribution can be further analyzed, thereby explaining some specific failure cases.
[0060] Please refer to Figure 9 As shown, Figure 9 The horizontal axis represents the depth from the surface. Figure 9 In the vertical axis, the green curve CD represents the carrier concentration (cm⁻³), the red curve Rho represents the bulk resistivity (Ω·cm), and the yellow curve RM represents the measured original spread resistance (Ω or Ω·cm²). The changes in carrier concentration and resistivity can be directly observed through SRP test results, allowing for the calculation of the PN junction depth.
[0061] Example 2
[0062] This embodiment provides a fault location system for crimped power devices, corresponding to the fault location method for crimped power devices described in Embodiment 1, including:
[0063] Failure Sub-unit Locating Module: Used to perform electrical parameter tests on crimped power devices, compare the obtained electrical parameter test values with the corresponding electrical parameter standard values, and determine the failure sub-units in the crimped power devices;
[0064] Failed chip location module: used to measure the leakage current value of each chip in the failed sub-unit one by one, and identify the chip with the leakage current value greater than the set threshold as the failed chip;
[0065] Failure Area Location Module: Used to determine the failure area on the chip by ultrasonic scanning detection or hotspot location;
[0066] Failure point de-layering and localization module: After determining the failure area on the failure chip, it removes the structure in the failure area layer by layer in the order from the outside to the inside, and records the structural changes in the failure area layer by layer until the initial position of the failure point is located.
[0067] Micro-nanoscale failure point localization module: used to perform cross-sectional analysis of the failure area using scanning electron microscopy-energy dispersive spectroscopy to locate failure points at the micro-nano scale;
[0068] Nanoscale failure point location module: used to etch the surface structure at the failure point, identify the cellular defects at the failure point, and locate the structural starting position of the failure point at the nanoscale.
[0069] Process defect location module: Used to measure the extended resistance of the failed chip. After confirming the crystal orientation of the substrate material of the failed chip, the extended resistance of the failed chip is measured layer by layer. The measured value of the extended resistance is compared with the standard value to obtain the doping distribution of the failed chip, and then the process defect location of the failed chip is identified and marked as the failure point.
Claims
1. A method for locating the failure point of a crimped power device, characterized in that, Includes the following steps: Electrical parameters of the crimped power device are tested, and the obtained electrical parameter test values are compared with the corresponding electrical parameter standard values to determine the failed sub-units in the crimped power device. The leakage current value of each chip in the failed sub-unit is measured one by one, and the chip with the leakage current value greater than the set threshold is identified as the failed chip; The failure area on the failed chip is determined by ultrasonic scanning detection or hotspot localization. The failure area was analyzed by scanning electron microscopy-energy dispersive spectroscopy to locate the failure point at the micro-nano scale. The surface structure at the failure point is etched to identify the cellular defects at the failure point and locate the structural starting position of the failure point at the nanoscale.
2. The method for locating the failure point of a crimped power device according to claim 1, characterized in that, The electrical parameter testing of the crimped power device includes: setting test conditions according to the model of the crimped power device, performing high and low temperature dynamic and static retests on each sub-unit of the crimped power device through a dynamic and static testing machine, obtaining electrical parameter test values, comparing them with the corresponding electrical parameter standard values, and determining the location of the failed sub-unit in the crimped power device.
3. The method for locating the failure point of a crimped power device according to claim 1, characterized in that, The electrical parameter testing of the crimped power device also includes: for the crimped power device that has broken down and burned out, the CE terminal of the crimped power device is tested with a multimeter to directly locate the failed sub-unit.
4. The method for locating the failure point of a crimped power device according to claim 1, characterized in that, The ultrasonic scanning detection and localization includes: using interface ultrasonic wave reflection technology to observe whether there are defects at each interface of the chip, and marking the locations where defects exist as failure areas.
5. The method for locating the failure point of a crimped power device according to claim 1, characterized in that, The hotspot location method includes: using a thermal emission microscope, shorting the GE terminal of the failed chip, continuously applying pressure to the CE terminal, monitoring the temperature distribution and changes on the surface of the failed chip in real time, recording the hotspot locations on the surface of the failed chip and marking them as failure areas.
6. The method for locating the failure point of a crimped power device according to claim 1, characterized in that, The cross-sectional analysis of the failure area using scanning electron microscopy-energy dispersive spectroscopy includes: cutting, grinding, and polishing the failure area to obtain a test sample; using scanning electron microscopy-energy dispersive spectroscopy to detect the test sample; observing the physical structure of the failure area by combining the secondary electron mode and backscatter mode of the scanning electron microscope; characterizing the material composition of the failure area by energy dispersive spectroscopy; and thus locating the failure point at the micro-nano scale.
7. The method for locating the failure point of a crimped power device according to claim 1, characterized in that, It also includes the following steps: After determining the failure area on the failed chip, the structure in the failure area is removed layer by layer in the order from the outside to the inside, and the structural changes in the failure area are recorded layer by layer until the initial position of the failure point is located. Then, the failure area is analyzed in profile by scanning electron microscopy-energy dispersive spectroscopy to locate the failure point at the micro-nano scale.
8. The method for locating the failure point of a crimped power device according to claim 1, characterized in that, It also includes the following steps: After determining the location of the failed chip in the failed subunit, the extended resistance of the failed chip is measured. After confirming the crystal orientation of the substrate material of the failed chip, the extended resistance of the failed chip is measured layer by layer. The measured value of the extended resistance is compared with the standard value to obtain the doping distribution of the failed chip, and then the process defect location of the failed chip is identified and marked as the failure point.
9. A failure point location system for crimped power devices, characterized in that, include: Failure Sub-unit Locating Module: Used to perform electrical parameter tests on crimped power devices, compare the obtained electrical parameter test values with the corresponding electrical parameter standard values, and determine the failure sub-units in the crimped power devices; Failed chip location module: used to measure the leakage current value of each chip in the failed sub-unit one by one, and identify the chip with the leakage current value greater than the set threshold as the failed chip; Failure Area Location Module: Used to determine the failure area on the failed chip by ultrasonic scanning detection or hotspot location; Micro-nanoscale failure point localization module: used to perform cross-sectional analysis of the failure area using scanning electron microscopy-energy dispersive spectroscopy to locate failure points at the micro-nano scale; Nanoscale failure point location module: used to etch the surface structure at the failure point, identify the cellular defects at the failure point, and locate the structural starting position of the failure point at the nanoscale.
10. The failure point location system for crimped power devices according to claim 9, characterized in that, It also includes the following modules: Failure point de-layering and localization module: After determining the failure area on the failure chip, it removes the structure at the failure area layer by layer in the order from the outside to the inside, and records the structural changes in the failure area layer by layer until the initial position of the failure point is located. Process defect location module: used to perform extended resistance measurement on the failed chip, after confirming the crystal orientation of the substrate material of the failed chip, measure the extended resistance of the failed chip layer by layer, compare the extended resistance measurement value with the standard value, obtain the doping distribution of the failed chip, and then identify the process defect location of the failed chip and mark it as the failure point.