Integrated chip and method for autonomously testing and repairing redundancy of interconnection path between core particles

Abstract

The present disclosure provides an integrated chip for autonomous testing and redundancy repair of interconnection paths between core particles, comprising: at least one core particle, each core particle having a set of interconnection ports for interconnection between core particles and a port selection module, the interconnection ports including a switching interface, an interconnection port and a standby interconnection port; the port selection module is used for connecting the interconnection port with an internal logic circuit signal port according to a selection signal; the at least one self-testing and self-repairing module is used for autonomously completing testing of interconnection paths among the core particles under the action of the switching signal and generating a selection signal according to a test result; the self-test and self-repair module comprises a control circuit, a port selection signal generation module, a test vector generation module, a test vector comparison module, a core particle exchange module and a storage module.

Description

Technical Field

[0001] This disclosure relates to the fields of integrated circuit and testing technology, and in particular to an integrated chip and method for autonomous testing and redundancy repair of inter-chip interconnect paths. Background Technology

[0002] As semiconductor process technology evolves closer to its physical limits, the pace of Moore's Law's advancement has slowed significantly. The traditional approach of continuously shrinking transistor size (process technology upgrades) or simply increasing the area of ​​a single chip to improve performance faces the severe challenges of rapidly rising development costs and diminishing marginal returns on performance gains, resulting in a decreasing cost-effectiveness ratio. To overcome these bottlenecks, chiplet heterogeneous integration technology has emerged and become a crucial technological development direction in the post-Moore's Law era. This technology decomposes the complex system-on-a-chip (SoC) into multiple independently fabricated chiplets ("chiplets") with specific functions. These chipslets can be manufactured separately using the process node best suited to their function and cost, and then integrated into a single package using advanced packaging technologies such as silicon interposers and redistribution layers (e.g., 2.5D / 3D packaging), thereby achieving higher system performance, more flexible design, and better overall cost. However, while this advanced integration method brings significant advantages, it also introduces new technological challenges, such as increased testing complexity: package stacking and high-density integration make the internal interconnect signal networks between chips extremely complex and difficult to access directly from the outside. Traditional chip testing methods struggle to efficiently and comprehensively test and diagnose the electrical connectivity of the thousands of interconnect paths between chips after packaging. Yield loss risk: High integration density means a significant increase in the number of interconnects between chips. During manufacturing and packaging, any open circuit, short circuit, or high-resistance fault in any interconnect path can cause the entire integrated chip to malfunction. Due to the sheer number of interconnects, this risk of yield loss caused by interconnect defects is significantly amplified, becoming a key bottleneck restricting the mass production and yield improvement of multi-chip chips. However, current chip-to-chip connectivity testing methods cannot efficiently, accurately, and cost-effectively meet testing requirements. Summary of the Invention

[0003] In view of this, in order to at least partially solve at least one of the aforementioned technical problems, this disclosure provides an integrated chip and method for autonomous testing and redundancy repair of inter-chip interconnect paths. The technical solution is as follows:

[0004] According to one embodiment of this disclosure, an integrated chip for autonomous testing and redundancy repair of inter-chip interconnect paths is provided, comprising: at least one chip, each chip having a set of interconnect ports for inter-chip interconnection and a port selection module, wherein the interconnect ports include a switching interface, an interconnect interface, and a spare interconnect interface; the port selection module is used to connect the interconnect interface to an internal logic circuit signal port according to a selection signal; at least one self-test and self-repair module is used to autonomously complete the testing of the inter-chip interconnect paths under the action of a switching signal, and generate a selection signal according to the test result; the self-test and self-repair module includes a control circuit, a port selection signal generation module, a test vector generation module, a test vector comparison module, a chip switching module, and a storage module.

[0005] According to an embodiment of this disclosure, the control circuit includes a finite state machine for transitioning between seven states: an empty state, a test vector shift state, a test preparation state, a test state, a test completion state, a test result transmission state, and a select signal generation and storage state. A test vector generation module stores test vectors and, under the control of the control circuit, serially shifts the test vectors into a scan chain. A test vector comparison module stores expected test results and compares the actual test results with the expected test results. A chip exchange module transmits and receives state transition signals with other chips through an exchange interface, enabling test collaboration among multiple chips. A port selection signal generation module generates a selection signal based on the test results and a preset redundant interface replacement order. A storage module stores the selection signal and provides a selection signal to the port selection module when the switch signal is off.

[0006] According to an embodiment of this disclosure, the switching interface includes an output interface and an input interface for synchronous transmission of state transition signals with the self-test and self-repair modules of other cores; the interconnect interface is used to transmit signals under normal operating conditions; and the backup interconnect interface is used to replace the faulty interconnect interface according to a selection signal when the interconnect interface fails.

[0007] According to embodiments of this disclosure, interconnect interfaces of the same type are placed among spare interconnect interfaces, so that if an interconnect interface fails, the entire interconnect interface can be shifted upward or downward.

[0008] According to an embodiment of this disclosure, after the switch signal is turned on, the finite state machine jumps from an empty state to a test vector shift state. After the test vector shift is completed, the control circuit controls the chip exchange module to send a preparation completion signal to the corresponding connected chip and waits to receive a preparation completion signal from the connected chip. After both parties receive the preparation completion signal, they jump to the test state. After the test is completed, the control circuit sends a test completion signal to the connected chip and waits to receive a test completion signal from the connected chip. After both parties receive the test completion signal, the test result is shifted to the test vector comparison module.

[0009] According to the embodiments of this disclosure, if there are multiple sets of test vectors, the test vector shift state is returned to repeat the test; if all test vectors have been tested, the test result transmission state is entered.

[0010] According to the embodiments of this disclosure, in the test result transmission state, the output port channel test result of the connected core is sent to the connected core through the core switching module, and the output port channel test result of the core is received. After completion, the state of generating selection signal and storing is entered. In the state of generating selection signal and storing, the port selection signal generation module generates selection signal and stores it in the storage module. After completion, a completion signal is sent to the outside and the finite state machine is set to an empty state.

[0011] According to embodiments of this disclosure, test vectors and expected test results are pre-stored in the test vector generation module and the test vector comparison module during the design phase, and the order of redundant interface replacement is a preset default order.

[0012] In another embodiment of this disclosure, a method for autonomous testing and redundancy repair of inter-chip interconnect paths is also provided. Using the above-mentioned integrated chip, the method includes: activating a self-test and self-repair module in response to an external switching signal; controlling a finite state machine in the control circuit to transition from an empty state to a test vector shifting state; controlling a test vector generation module to serially shift test vectors into the chip interconnect interface scan chain for test vector shifting, and sending a preparation completion signal to the connected chip via a switching interface; upon receiving the preparation completion signal from the connected chip, controlling the output port to output the scan unit signal connected to it, and the input port to change the scan unit signal value connected to it according to the received signal, thus completing the interconnect path test; after the test is completed, sending a test completion signal to the connected chip via the switching interface, and upon receiving... After the test completion signal of the connection core is received, the value of the scanning unit is serially shifted to the test vector comparison module to obtain the input port test result. If there are still multiple test vectors in the test vector generation module, the test vector shifting step is repeated. If all test vectors have been tested, the output port channel test result of the connection core is sent to the connection core through the switching interface, and the output port channel test result of this core is received. Based on the input port test result and the received output port channel test result, the selection signal required by the port selection module is generated and stored according to the preset redundant interface replacement order. Finally, a completion signal is sent to the outside, the finite state machine is set to an empty state, and the port selection module completes the correct connection between the external interconnection interface and the internal logic circuit signal port according to the stored selection signal.

[0013] According to the embodiments of this disclosure, during the test vector shifting process, if the preparation completion signal of the connection chip is not received, the preparation completion signal is resent after waiting for a preset number of clock cycles; during the test result acquisition process, if the test completion signal of the connection chip is not received, the test completion signal is resent after waiting for a preset number of clock cycles. Attached Figure Description

[0014] The objects, features, and advantages of this disclosure will become clearer from the following description of embodiments of the disclosure with reference to the accompanying drawings, in which:

[0015] Figure 1 This is a schematic diagram of an integrated chip for autonomous testing and redundancy repair of inter-chip interconnect paths according to an embodiment of this disclosure.

[0016] Figure 2 This is a schematic diagram of a self-testing and self-repairing module in a chip according to an embodiment of this disclosure.

[0017] Figure 3 This is a schematic diagram illustrating the self-testing and self-repairing principle in the core of this disclosure embodiment.

[0018] Figure 4This is a schematic diagram of the arrangement of the spare interconnect structure in the chip according to an embodiment of the present disclosure.

[0019] Figure 5 This is a schematic diagram of the method for autonomous testing and redundancy repair of inter-chip interconnect paths according to an embodiment of this disclosure. Detailed Implementation

[0020] This disclosure provides an integrated chip and method for autonomous testing and redundancy repair of interconnect paths between chips, enabling a chip to automatically test its interconnect paths with other chips and select the corresponding redundant paths for connection repair based on the test results, thereby ensuring the normal transmission of interconnect signals and improving the production yield of multi-chip chips.

[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0022] In this embodiment of the disclosure, an integrated chip is provided for autonomous testing and redundancy repair of inter-chip interconnect paths, combined with Figures 1 to 4 As shown, the integrated chip includes:

[0023] At least one core, each core having a set of interconnect ports for interconnection between cores and a port selection module, wherein the interconnect ports include a switching interface, an interconnect interface and a spare interconnect interface; the port selection module is used to connect the interconnect interface to an internal logic circuit signal port according to a selection signal;

[0024] At least one self-test and self-repair module is used to autonomously complete the test of the interconnect path between the cores under the action of a switch signal, and generate a selection signal based on the test results;

[0025] The self-test and self-repair module includes a control circuit, a port selection signal generation module, a test vector generation module, a test vector comparison module, a chip exchange module, and a storage module.

[0026] According to embodiments of this disclosure, the switching interface of a core chip includes an output interface and an input interface for synchronous transmission of state transition signals with the self-test and self-repair modules of other core chips; the interconnect interface of the core chip is used for signal transmission under normal operating conditions; the spare interconnect interface of the core chip is used to replace the faulty interconnect interface according to a selection signal when the interconnect interface fails. The port selection module mainly includes a multiplexer (MUX) and a multiplexer (DMUX). (The last two sentences appear to be unrelated and likely represent separate data points.) Figure 1As shown, an integrated chip can include n chips, namely chips C1 to Cn, where n is a positive integer representing the ordinal number of the chip. The switching interface of chip C1 includes one output interface C1_ex_out and one input interface C1_ex_in, and so on. The switching interface of chip Cn includes one output interface Cn_ex_out and one input interface Cn_ex_in. Interconnect interfaces are used to transmit signals under normal operating conditions. The interconnect interface of chip Cn includes two input interfaces (Cn_in1, Cn_in2) and two output interfaces (Cn_out1, Cn_out2). The spare interconnect interface of chip Cn includes one input interface Cn_R_in1 and one output interface Cn_R_out1. Each chip has a port selection module, such as... Figure 1 The numbers shown are C1, C2, C3, C4...Cn-1, Cn.

[0027] According to embodiments of this disclosure, such as Figure 2 As shown, the self-test and self-repair module includes a control circuit, a port selection signal generation module, a test vector generation module, a test vector comparison module, a chip exchange module, and a storage module. Among them:

[0028] The control circuit includes a finite state machine for transitioning between seven states: empty state, test vector shift state, test ready state, test state, test completed state, test result transmission state, and generate and store selection signal state.

[0029] The test vector generation module is used to store test vectors and, under the control of the control circuit, serially shifts the test vectors into the scan chain;

[0030] The test vector comparison module is used to store the expected test results and compare the actual test results with the expected test results;

[0031] The chip exchange module is used to send and receive state transition signals with other chips through the exchange interface, enabling test collaboration among multiple chips;

[0032] The port selection signal generation module is used to generate selection signals based on test results and a preset redundant interface replacement order;

[0033] The storage module is used to store the selection signal and provides a selection signal to the port selection module when the switch signal is off.

[0034] like Figure 2 As shown, the self-test and self-repair module is controlled by an external switch signal. When the switch signal is off (set to 0), only the storage circuit inside the module provides a selection signal to the module that selects different chip ports.

[0035] The control circuit internally contains a finite state machine that cycles through seven states: empty state, test vector shift, test preparation complete, test, test complete, test result transmission, and generating and storing a selection signal. When the switch signal is turned on (set to 1), the control circuit controls the test vector generation module to serially shift the test vector into the chip interconnect interface scan chain. After completion, the control circuit controls the chip exchange module to send a preparation complete signal to the corresponding connected chip. Upon receiving the preparation complete signal from the connected chip, the control circuit controls the output port to output the scan unit signal connected to it, and the input port changes the scan unit signal value connected to it according to the received signal. After the test is completed, the control circuit state machine enters the test complete state and sends a test complete signal to the connected chip through the chip exchange module. Upon receiving the test complete signal, the result is shifted to the test vector comparison module to obtain the input port test result. If there are multiple test vectors, the circuit returns to the test vector shift state and repeats the above steps. After the comprehensive test results are filtered, the control circuit enters the next state, namely test result transmission. The chip exchange module sends the corresponding chip output port channel test result to the corresponding connected chip and receives the channel test result of its own chip output port. Upon receiving the signal, the port selection signal generation module generates the correct selection signal required by the port selection module according to the default replacement order and stores it in the storage module. After storage is completed, the control circuit sends a completion signal to the outside world and sets the internal finite state machine to an empty state.

[0036] According to an embodiment of this disclosure, after the switch signal is turned on, the finite state machine jumps from an empty state to a test vector shift state;

[0037] After the test vector shift is completed, the control circuit controls the core switching module to send a ready-to-complete signal to the corresponding connected core and waits to receive a ready-to-complete signal from the connected core. After both sides receive the ready-to-complete signal, they jump to the test state.

[0038] After the test is completed, the control circuit sends a test completion signal to the connector chip and waits to receive a test completion signal from the connector chip. After both sides receive the test completion signal, the test result is shifted to the test vector comparison module.

[0039] According to the embodiments of this disclosure, if there are multiple sets of test vectors, the test vector shift state is returned to repeat the test; if all test vectors have been tested, the test result transmission state is entered.

[0040] In the test result transmission state, the output port channel test result of the connected core is sent to the connected core through the core switching module, and the output port channel test result of the core is received. After completion, the state of generating selection signal and storing is entered.

[0041] In the state of generating and storing selection signals, the port selection signal generation module generates selection signals and stores them in the storage module. After completion, it sends out a completion signal and sets the finite state machine to an empty state.

[0042] According to embodiments of this disclosure, test vectors and expected test results are pre-stored in the test vector generation module and the test vector comparison module during the design phase, and the order of redundant interface replacement is a preset default order.

[0043] According to embodiments of this disclosure, such as Figure 3 As shown, the implementation process of this scheme is described using two cores (core 1 and core 2) as an example. When designing the core circuit, the interconnect interface test vector needs to be stored in the storage element of the test vector generation module within the interconnect interface self-test and self-repair module, and the expected test results need to be stored in the storage element of the test vector comparison module. For single-core testing, the switch signal can be turned off. The specific testing process can include: First, turning on the switch signals of core 1 and core 2 to enable their respective self-test and self-repair modules. The control circuit state machine in the self-test and self-repair modules of core 1 and 2 transitions from an empty state to a test vector shifting state; Second, the control test vector generation module in the self-test and self-repair modules of core 1 and 2 serially shifts the test vector into the core interconnect interface scan chain. After completion, the control circuit controls the core switching module to send a ready-to-complete signal to the corresponding connected core, i.e., core 1 and 2 send the test ready-to-complete signal to each other through their respective switching interfaces; Third, if one party does not receive the test ready-to-complete signal, it waits until it does. After both sides receive the signal, their respective control circuits control the output port to output the scanning unit signal connected to it, and the input port changes the value of the scanning unit signal connected to it according to the received signal. After the test is completed, the control circuit state machine enters the test completion state and sends a test completion signal to the connected core through the core switching module; in the fourth step, if one side does not receive the test completion signal, it waits until it receives the signal. After both sides receive the signal, the result is shifted to the test vector comparison module to obtain the input port test result. At this time, if there are still multiple test vectors in the test vector generation module, steps two to four are repeated; otherwise, step five is entered; in the fifth step, after the comprehensive test results are filtered, the control circuits of each test self-repair module enter the next state, namely test result transmission. Each core sends the corresponding core output port channel test result to the other core through the core switching module and receives the channel test result of its own core output port; in the sixth step, after receiving the test results, the port selection signal generation module generates the correct selection signal required by the port selection module according to the default replacement order and stores it in the storage module. After storage is completed, the control circuit sends a completion signal to the outside world and sets the internal finite state machine to an empty state.

[0044] The above steps constitute the complete process. The entire testing and repair process, excluding the need to store test vectors and expected results in the self-testing and self-repairing module during the design phase and set the default interface replacement order, can be autonomously completed by the module's internal state machine. The state transition signals of the module's internal state machine are generated by the internal state machines of other connected cores. Furthermore, before entering the next state, the module's internal state machine generates and sends signals to the corresponding core so that its internal state machine can transition to the next state. When the number of spare interconnect interfaces for a core is limited, it can be done as follows: Figure 4 As shown, interconnect interfaces of the same input or output type are placed among spare interconnect interfaces. In this way, if an interconnect interface fails, the entire interconnect interface can be shifted up or down to simplify the generation of the chip port selection module and its selection signal. That is, interconnect interfaces of the same type are placed among spare interconnect interfaces, so that if an interconnect interface fails, the entire interconnect interface can be shifted up or down.

[0045] Another embodiment of this disclosure also provides a method for autonomous testing and redundancy repair of inter-chip interconnect paths, applicable to the integrated chips described above, such as... Figure 5 As shown, the method includes:

[0046] S1: In response to an external switching signal, the self-test and self-repair module is activated, and the finite state machine in the control circuit jumps from the empty state to the test vector shift state;

[0047] S2: The control test vector generation module serially shifts the test vector into the chip interconnect interface scan chain for test vector shifting, and sends a ready-to-complete signal to the connected chip through the exchange interface;

[0048] S3: After receiving the preparation completion signal of the connecting core, the control output port outputs the scanning unit signal connected to it, and the input port changes the scanning unit signal value connected to it according to the received signal to complete the interconnection path test.

[0049] S4: After the test is completed, a test completion signal is sent to the connection core through the switching interface. After receiving the test completion signal from the connection core, the value of the scanning unit is serially shifted to the test vector comparison module to obtain the input port test result.

[0050] S5: If there are still multiple test vectors in the test vector generation module, return to the test vector shifting step and repeat the execution;

[0051] S6: If all test vectors have completed the test, the output port channel test results of the connection core are sent to the connection core through the switching interface, and the output port channel test results of this core are received.

[0052] S7: Based on the input port test results and the received output port channel test results, generate and store the selection signals required by the port selection module according to the preset redundant interface replacement order; and

[0053] S8: Sends a completion signal to the outside world, sets the finite state machine to an empty state, and the port selection module completes the correct connection between the external interconnection interface and the internal logic circuit signal port according to the stored selection signal.

[0054] According to the embodiments of this disclosure, during the test vector shifting process, if the preparation completion signal of the connection chip is not received, the preparation completion signal is resent after waiting for a preset number of clock cycles; during the test result acquisition process, if the test completion signal of the connection chip is not received, the test completion signal is resent after waiting for a preset number of clock cycles.

[0055] This disclosed integrated chip and method for autonomous testing and redundancy repair of inter-chip interconnect paths utilizes an internal state machine to autonomously complete the entire testing and repair process without external intervention. Each chip's state machine triggers the next operation by sending and receiving state transition signals, forming a chain-like collaboration to ensure process synchronization. This addresses technical issues such as low chip yield in multi-chip integrated circuits due to numerous interconnect signal lines and the susceptibility to interconnect path breaks during manufacturing. It automatically tests interconnect paths with other chips and automatically switches to preset redundant paths based on test results, achieving fault repair. Through built-in automated online repair capabilities, it can directly compensate for manufacturing defects, significantly improving the production yield of multi-chip integrated circuits.

[0056] The integrated chip and method for autonomous testing and redundancy repair of inter-chip interconnect paths disclosed herein offer the following advantages: By automatically detecting and utilizing redundant paths to repair interconnect open / short circuit faults, chips that have failed due to interconnect problems can be repaired into qualified chips, directly improving the final factory yield. Simultaneously, the built-in testing mechanism enhances long-term reliability assurance after product delivery. It significantly reduces testing complexity and cost: the testing process requires no external precision control, simplifying the testing procedure and reducing overall testing costs. It possesses online monitoring potential: this mechanism can not only be used for production testing, but its architecture also supports periodic interconnect health checks during system operation, enabling fault warnings or dynamic repairs, enhancing the availability and robustness of critical systems. This "self-testing and self-repairing" circuit can be integrated into each chip as a standardized IP module. This design allows the solution to be flexibly applied to systems with different chip numbers and interconnect topologies, offering excellent scalability and facilitating technology promotion and ecosystem building.

[0057] The embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and have not been described in detail. It should be understood that the above are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. An integrated chip with autonomous testing and redundancy repair of inter-chip interconnect paths, characterized in that, include: At least one core, each core having a set of interconnect ports for inter-core interconnection and a port selection module, wherein the interconnect ports include a switching interface, an interconnect interface, and a spare interconnect interface; the port selection module is used to connect the interconnect interface to an internal logic circuit signal port according to a selection signal; At least one self-test and self-repair module is used to autonomously complete the test of the interconnection path between the cores under the action of a switch signal, and generate the selection signal based on the test results; The self-test and self-repair module includes a control circuit, a port selection signal generation module, a test vector generation module, a test vector comparison module, a chip exchange module, and a storage module.

2. The integrated chip according to claim 1, characterized in that, The control circuit includes a finite state machine for transitioning between seven states: empty state, test vector shift state, test ready state, test state, test completed state, test result transmission state, and generate selection signal and store state. The test vector generation module is used to store test vectors and, under the control of the control circuit, serially shifts the test vectors into the scan chain. The test vector comparison module is used to store the expected test results and compare the actual test results with the expected test results; The chip exchange module is used to send and receive state transition signals with other chips through the exchange interface, so as to realize test collaboration among multiple chips. The port selection signal generation module is used to generate the selection signal according to the test results and the preset redundant interface replacement order; The storage module is used to store the selection signal and to provide the selection signal to the port selection module when the switch signal is off.

3. The integrated chip according to claim 2, characterized in that, The switching interface includes an output interface and an input interface, which are used for synchronous transmission of state transition signals with the self-test and self-repair modules of other cores. The interconnect interface is used to transmit signals under normal operating conditions; The backup interconnect interface is used to replace the faulty interconnect interface according to the selection signal when the interconnect interface fails.

4. The integrated chip according to claim 3, characterized in that, Interconnects of the same type are placed among spare interconnects, so that if an interconnect fails, the entire interconnect can be moved up or down.

5. The integrated chip according to claim 2, characterized in that, After the switch signal is turned on, the finite state machine transitions from an empty state to a test vector shift state; After the test vector shift is completed, the control circuit controls the core switching module to send a preparation completion signal to the corresponding connected core and waits to receive a preparation completion signal from the connected core. After both parties receive the preparation completion signal, they jump to the test state. After the test is completed, the control circuit sends a test completion signal to the connector chip and waits to receive a test completion signal from the connector chip. After both parties receive the test completion signal, the test result is shifted to the test vector comparison module.

6. The integrated chip according to claim 5, characterized in that, If multiple test vectors exist, return the test vector shift state and repeat the test; If all test vectors have been tested, the test result transmission state will begin.

7. The integrated chip according to claim 6, characterized in that, In the test result transmission state, the output port channel test result of the connected core is sent to the connected core through the core switching module, and the output port channel test result of the core is received. After completion, the state of generating selection signal and storing is entered. In the state of generating and storing selection signals, the port selection signal generation module generates a selection signal and stores it in the storage module. After completion, it sends a completion signal to the outside and sets the finite state machine to an empty state.

8. The integrated chip according to claim 1, characterized in that, The test vectors and expected test results are pre-stored in the test vector generation module and the test vector comparison module during the design phase, and the order of replacing redundant interfaces is a preset default order.

9. A method for autonomous testing and redundancy repair of inter-chip interconnect paths, applied to the integrated chip according to any one of claims 1-8, characterized in that, include: In response to an external switching signal, the self-test and self-repair module is activated, and the finite state machine in the control circuit transitions from an empty state to a test vector shift state. The control test vector generation module serially shifts the test vectors into the chip interconnect interface scan chain for test vector shifting, and sends a ready-to-complete signal to the connected chip through the exchange interface. After receiving the connection chip preparation completion signal, the control output port outputs the scanning unit signal connected to it, and the input port changes the scanning unit signal value connected to it according to the received signal to complete the interconnection path test. After the test is completed, a test completion signal is sent to the connection core through the switching interface. After receiving the test completion signal from the connection core, the value of the scanning unit is serially shifted to the test vector comparison module to obtain the input port test result. If there are still multiple test vectors in the test vector generation module, return to the test vector shifting step and repeat the execution; If all test vectors have completed the test, the output port channel test results of the connection core are sent to the connection core through the switching interface, and the output port channel test results of this core are received. Based on the input port test results and the received output port channel test results, generate and store the selection signals required by the port selection module according to the preset redundant interface replacement order; as well as The system sends a completion signal to the outside world, sets the finite state machine to an empty state, and the port selection module completes the correct connection between the external interconnection interface and the internal logic circuit signal port according to the stored selection signal.

10. The method according to claim 9, characterized in that, If the ready-to-complete signal of the connection chip is not received during the test vector shifting process, the ready-to-complete signal will be resent after waiting for a preset number of clock cycles. If the test completion signal of the connected chip is not received during the test result acquisition process, the test completion signal will be resent after waiting for a preset number of clock cycles.

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