Optical co-packaging interlayer interconnection device and method based on 3D printing

Abstract

The invention relates to an optical co-packaging interlayer interconnection device and method based on 3D printing. The device comprises an optical fiber array used for transmitting optical signals; the optical chip module at least comprises two optical chips which realize interlayer interconnection through a plurality of 3D printing waveguides, and the optical chip module and the optical fiber array realize optical signal interconnection through a 3D printing photon lead; and the photoelectric conversion chip is in optical signal interconnection with the optical chip module and is used for carrying out photoelectric conversion on the optical signal. According to the integrated 3D printing reflecting mirror, the angle error is smaller than or equal to 0.05 degrees, the turning loss is smaller than or equal to 0.3 dB / time, and compared with an existing 3D printing scheme (larger than 1 dB / time), the turning loss is reduced by 70%; and through a gradient refractive index interface, the docking loss is less than or equal to 0.5 dB, which is reduced by 83% compared with the traditional lead bonding scheme (greater than 3dB), and the total interlayer loss is less than or equal to 1.1 dB, so that the low-loss requirement of the high-speed CPO is met.

Description

Technical Field

[0001] This application relates to the fields of photonic integration and optoelectronic packaging technology, and in particular to an optical co-packaging interlayer interconnection device and method based on 3D printing. Background Technology

[0002] Currently, the CPO chip interlayer optical interconnect technology related to this invention mainly includes the following aspects: 1. Traditional wire bonding + vertical optical coupler technology The upper and lower layer chips in the CPO architecture are connected by metal leads or single-mode optical fibers. Vertical optical couplers (such as microlenses or grating couplers) are installed at both ends of the leads / fibers to convert horizontally transmitted light waves into vertically transmitted ones, thereby realizing interlayer interconnection. A typical application is Broadcom's CPO 800G module.

[0003] The design and fabrication methods of this technology are relatively mature, compatible with existing CPO packaging production lines, and have low costs, and are being commercialized for low- and medium-speed CPO scenarios. However, it relies on high-precision vision equipment to align the leads / fibers with the chip layer. In practical applications, the alignment deviation (>2μm) results in an insertion loss of >3dB, and the lead spacing is >100μm, which cannot be adapted to high-density channels (<50 channels / cm²), making it difficult to meet the needs of next-generation 1.6T and above CPO.

[0004] 2. Through Silicon Via (TSV) + Microlens Array Technology Vertical vias (TSVs) are etched on a silicon substrate, and insulating and conductive layers are deposited inside the vias. At the same time, microlens arrays are integrated at both ends of the TSVs. The refraction of light waves through the microlenses is used to convert the horizontal transmission to vertical transmission, thereby realizing interlayer interconnection. Typical research teams include Intel Labs and TSMC.

[0005] This technology achieves high integration (channel density > 80 channels / cm²) and stable vertical transmission distance, making it suitable for silicon-based CPO chips. However, its process is complex, requiring more than 6 steps, including deep silicon etching (depth > 100μm), insulating layer deposition, and microlens bonding, resulting in a cost 40% higher than traditional solutions. Furthermore, the thermal expansion coefficients of TSV (silicon material) and microlenses (glass material) differ significantly (Δα > 5 × 10^-6 / ℃), making them prone to lens shift in operating environments of -40 to 85℃, leading to a long-term decrease in reliability (loss change > 0.5dB / 1000h). Additionally, it is only compatible with silicon-based waveguides and cannot be used with other types such as silicon nitride-based waveguides.

[0006] 3. Existing 3D printing optical interconnect technology Desktop 3D printing equipment (such as Formlabs Form 3) is used to print polymer waveguides. External metal mirrors are attached to the bends of the waveguides to achieve vertical deflection of light waves. Alternatively, curved waveguides with large curvature radii (>500μm) can be printed directly for CPO interlayer interconnection. Typical research teams include MIT and Huawei HiSilicon Research Institute.

[0007] This technology offers flexibility and a short rapid prototyping cycle (<3h), allowing for quick adjustment of the waveguide structure. However, it is not optimized for the narrow interlayer spacing (50-200μm) of CPO, and the desktop-grade equipment used has a resolution >25μm and a waveguide cross-section error >10μm, making dense integration impossible. External reflectors require separate assembly, with an angle error >0.5°, resulting in a bending loss >1dB / cycle. Furthermore, it lacks a dedicated docking structure with the on-chip waveguide, leading to a docking loss >1dB due to refractive index mismatch (waveguide 1.5 vs on-chip waveguide 3.45). Additionally, the reflectors lack anti-oxidation treatment, making them prone to oxidation and failure after long-term use.

[0008] The closest implementation to this invention is the "3D printed polymer waveguide + external mirror" CPO interconnect scheme proposed by MIT (published in the journal Optics Express in 2023).

[0009] The similarity between this solution and the present invention is that both use 3D printing technology to fabricate waveguides for inter-layer optical wave transmission in the CPO architecture, with the core idea being "waveguide transmission + reflection redirection".

[0010] However, this solution has obvious shortcomings: First, the reflector is an externally attached type with an angle error >0.5° and no anti-oxidation coating, resulting in a bending loss >1dB / cycle; second, the use of Formlabs Form 3 equipment (25μm resolution) cannot match the waveguide accuracy of the narrow interlayer spacing of CPO; and third, there is no dedicated docking interface, resulting in a docking loss >1dB with the on-chip waveguide. Summary of the Invention

[0011] Therefore, it is necessary to address the shortcomings of existing CPO interlayer interconnection technologies, such as high loss, low density, complex processes and high costs, which cannot meet the technical requirements of next-generation CPO modules of 1.6T and above in high-speed optical communication scenarios, and to provide an optical co-packaging interlayer interconnection device and method based on 3D printing.

[0012] To solve the above-mentioned technical problems, the technical solution provided by the present invention is as follows: A first aspect of the present invention provides a 3D-printed optical co-packaged interlayer interconnect device, comprising: An optical fiber array, used for transmitting optical signals; An optical chip module, comprising at least two optical chips interconnected by multiple 3D-printed waveguides, wherein the optical chip module and the fiber array are interconnected by 3D-printed photonic leads for optical signal interconnection. A photoelectric conversion chip is provided, which is interconnected with the optical chip module to perform photoelectric conversion on the optical signal.

[0013] Furthermore, the optical chip module includes an optical I / O chip and an optical on-chip signal processing chip. The optical I / O chip and the optical fiber array are interconnected by optical signals through 3D-printed photonic leads. The optical I / O chip and the optical on-chip signal processing chip are interconnected by multiple 3D-printed waveguides. The optical on-chip signal processing chip and the photoelectric conversion chip are interconnected by optical signals.

[0014] Furthermore, each of the 3D-printed waveguides includes a first graded-index tapered interface, a first horizontal waveguide segment, a first reflector, a vertical waveguide segment, a second reflector, a second horizontal waveguide segment, and a second graded-index tapered interface, wherein: The optical signal of any of the optical chips enters the 3D printed waveguide through the first graded refractive index Taper interface, passes through the first horizontal waveguide section and the first reflector in sequence, then makes a vertical turn into the vertical waveguide section, then makes a vertical turn through the second reflector into the second horizontal waveguide section, and finally enters another optical chip through the second graded refractive index Taper interface.

[0015] Furthermore, the outer surfaces of the first and second reflectors are coated with a reflective film, and the outer surface of the reflective film is also coated with an anti-oxidation layer.

[0016] Furthermore, the port where the optical chip connects to the 3D-printed waveguide is provided with a silanization layer.

[0017] Furthermore, it also includes a base, on which the fiber array, optical chip module and photoelectric conversion chip are all disposed.

[0018] A second aspect of the present invention provides an interconnection method for an optical co-packaged interlayer interconnection device based on 3D printing according to the first aspect of the present invention, comprising the following steps: At least two optical chips of the optical chip module are stacked and packaged, and fixed to the base; The fiber array is fixed to the base, and the fiber array and the uppermost optical chip of the optical chip module are at the same height; The photoelectric conversion chip is fixed on the base; The fiber array is connected to the optical chip module by 3D-printed photonic leads; At least two optical chip layers of an optical chip module are interconnected by 3D-printed waveguides.

[0019] Furthermore, before stacking and packaging at least two optical chips of the optical chip module, the process further includes silanizing the at least two optical chips to generate a silanized layer.

[0020] Furthermore, the at least two optical chips are subjected to silanization treatment to generate a silanized layer, including: Pretreatment: Clean the optical chip, then activate the optical chip with plasma to make the surface of the optical chip hydrophilic; Solution preparation: Mix ethanol and 3-trimethoxysilylpropyl methacrylate in a petri dish, and add diluted acetic acid before immersing the optical chip; Device immersion treatment: Immerse the optical chip in the prepared solution for a preset time, rinse the device with isopropanol solution, and dry it with nitrogen gas to complete the silanization treatment, generating a silanized layer at the port connected to the 3D printed waveguide.

[0021] Furthermore, the stacking and packaging of at least two optical chips in the optical chip module includes fixing the upper optical chip to the lower optical chip using a four-corner flip-chip method.

[0022] Compared with the prior art, the present invention has the following beneficial effects: This invention utilizes an "integrated 3D printed reflector" (angle error ≤ 0.05°) with a bending loss of ≤ 0.3dB / cycle, which is 70% lower than existing 3D printing solutions (> 1dB / cycle). Through a gradient refractive index interface, the docking loss is ≤ 0.5dB, which is 83% lower than traditional wire bonding solutions (> 3dB), and the total interlayer loss is ≤ 1.1dB, meeting the low-loss requirements of high-speed CPO. Attached Figure Description

[0023] Figure 1 A schematic diagram of an optical co-packaged interlayer interconnect device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the 3D-printed waveguide provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the interconnection method of an optical co-packaged interlayer interconnection device provided in an embodiment of the present invention; In the diagram, 1 is the fiber optic array, 2 is the optical I / O chip, 3 is the optical on-chip signal processing chip, 4 is the 3D printed waveguide, 41 is the graded refractive index Taper interface, 42 is the reflector, 5 is the photoelectric conversion chip, 6 is the base, and 7 is the electrical signal connection line. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0025] Traditional wire bonding + vertical optical coupler technology has the following drawbacks: It has high insertion loss (>3dB), low channel density (<50 channels / cm²), and is difficult to align.

[0026] The reason is: Alignment deviation between the lead / fiber and the chip layer (>2μm) increases scattering loss during optical wave coupling; the physical spacing of the lead itself is >100μm, making dense arrangement impossible; assembly needs to be completed in two steps (first bonding the lead, then attaching the coupler), and the accumulated alignment error further amplifies the loss.

[0027] The through-silicon via (TSV) + microlens array technology has the following drawbacks: High manufacturing costs, poor long-term reliability, and limited adaptability.

[0028] The reason is: TSV fabrication requires complex processes such as deep silicon etching and multi-step coating, resulting in significantly higher equipment and material costs compared to traditional solutions. The thermal expansion coefficients of TSV (silicon) and microlenses (glass) are mismatched, and under temperature cycling conditions, interfacial stress causes microlenses to shift, affecting transmission stability. The refractive parameters of the microlenses are only compatible with waveguides on silicon substrates and cannot meet the refractive index requirements of waveguides made of other materials such as silicon nitride.

[0029] Existing 3D printing optical interconnect technology (MIT, etc.) has the following drawbacks: High turning loss (>1dB / time), insufficient waveguide precision, poor compatibility with on-chip waveguides, and easy oxidation of mirrors.

[0030] The reason is: The external reflector had an angular deviation of >0.5° during assembly and lacked a high-reflectivity coating, leading to increased reflection loss. The desktop 3D printing equipment used had a resolution >25μm, which could not meet the high precision requirements of the CPO interlayer waveguide. The lack of a refractive index transition structure caused abrupt changes in the refractive index between the waveguide and the on-chip waveguide, resulting in interface reflection loss. The reflector lacked an anti-oxidation coating and was easily oxidized by long-term exposure to the packaging environment, leading to a decrease in reflectivity.

[0031] To overcome the shortcomings of traditional wire bonding, TSV + microlens array, and existing 3D printing technologies in CPO interlayer interconnection, this invention proposes a 3D printed integrated interconnection structure that simultaneously possesses low loss, high density, high compatibility, and non-volatile stability characteristics. The specific objectives are as follows: 1. Reduce transmission loss: By using "waveguide-reflector integrated 3D printing" (angle error ≤0.05°) and gold coating and anti-oxidation layer, the bending loss is controlled to ≤0.3dB / time. By using a gradient refractive index interface (linear refractive index transition), the docking loss between the waveguide and the on-chip waveguide is controlled to ≤0.5dB, and the total interlayer transmission loss is ≤1.1dB.

[0032] 2. Improved integration density: Based on the high precision of the Sonata1000 device (XY resolution ≤20nm), the waveguide spacing is designed to be ≤20μm, achieving a channel density of ≥100 channels / cm², which is suitable for the high density requirements of 1.6T and above CPO modules.

[0033] 3. Expanded compatibility: The gradient refractive index interface can customize the refractive index gradient according to the on-chip waveguide material (silicon-based / silicon nitride-based). The integrated structure has no external components and can automatically identify the positions of optical fibers and waveguides.

[0034] The first embodiment of the present invention provides an optical co-packaged interlayer interconnect device based on 3D printing, such as... Figure 1 As shown, it includes: Fiber optic array 1, wherein the fiber optic array 1 is used to transmit optical signals; An optical chip module, comprising at least two optical chips interconnected by multiple 3D-printed waveguides 4, wherein the optical chip module and the fiber array 1 are interconnected by 3D-printed photonic leads; The optical chip is an on-chip integrated photonic chip within a CPO package, serving as the carrier substrate for the 3D printed structure. Photonic chips are typically used for light input / output and processing steps such as optical signal modulation.

[0035] The photoelectric conversion chip 5 is interconnected with the optical chip module to perform photoelectric conversion on the optical signal.

[0036] In a further embodiment, the optical chip module includes an optical I / O chip 2 and an optical on-chip signal processing chip 3, wherein the optical I / O chip 2 and the optical fiber array 1 are interconnected by optical signals through 3D-printed photonic leads, the optical I / O chip 2 and the optical on-chip signal processing chip 3 are interconnected by multiple 3D-printed waveguides 4, and the optical on-chip signal processing chip 3 is interconnected by optical signals with the photoelectric conversion chip 5.

[0037] In a further embodiment, such as Figure 2 As shown, each of the 3D-printed waveguides 4 includes a first graded-index tapered interface 41, a first horizontal waveguide segment, a first reflector 42, a vertical waveguide segment, a second reflector 42, a second horizontal waveguide segment, and a second graded-index tapered interface 41, wherein: The optical signal of any of the optical chips enters the 3D printed waveguide 4 through the first graded refractive index Taper interface 41, passes through the first horizontal waveguide section and the first reflector 42 in sequence, then makes a vertical turn into the vertical waveguide section, then makes a vertical turn through the second reflector 42 into the second horizontal waveguide section, and finally enters another optical chip through the second graded refractive index Taper interface 41.

[0038] In this embodiment, the gradient refractive index Taper interface 41 can customize the refractive index gradient according to the on-chip waveguide material (silicon-based / silicon nitride-based) to adapt to dual-band (1310 / 1550nm), which is twice as wide as the TSV solution (silicon-based only). The integrated structure has no external components, and the loss change is ≤0.2dB in an environment of -40~85℃ for 1000h. Compared with the existing 3D printing solution (>0.6dB), the reliability is improved by 67%, which meets the requirements of industrial use.

[0039] In this embodiment, the 3D-printed waveguide 4 is processed using a Sonata 1000 device and a Reprise 1000 developing and coating device from Vanguard Automation. The 3D-printed waveguide 4 is made of photoresist. The Sonata 1000 is used for 3D printing. The device is based on the two-photon polymerization (TPP) principle. It uses a femtosecond laser (wavelength 780nm) to precisely focus on a point inside the photoresist, causing the photosensitive resin in the focused area to absorb two near-infrared photons simultaneously, initiating curing. By controlling the laser path, a specific waveguide shape can be printed.

[0040] The optical waveguide includes two graded-index edge coupling interfaces, two gold-plated films, and a 45° total internal reflection structure with an anti-oxidation layer. The graded-index interface serves as a transition tape structure between the optical waveguide and the on-chip waveguide, directly contacting the waveguide end face to match the optical modes of the on-chip and optical waveguides and reduce docking losses. The total internal reflection section is a 45° bevel, used to achieve a 90° vertical bend in the light wave. The light wave transmission path includes: upper-layer on-chip waveguide → graded-index interface → horizontal waveguide section → first 45° reflector 42 (vertical bend in the light wave) → vertical waveguide section → second 45° reflector 42 (horizontal turn in the light wave) → horizontal waveguide section → graded-index interface → lower-layer on-chip waveguide. The reverse transmission path is similar.

[0041] The specific printing process is as follows: Start the printing equipment, fix the assembled device on the vacuum adsorption stage, apply photoresist evenly to the area to be printed, locate the chip under the objective lens, and center the printing area in the view. If necessary, level the chip using a rotary stage. Determine the waveguide position by identifying the waveguide end face, and begin printing the lead waveguide between fiber array 1 and the on-chip waveguide.

[0042] Print the interlayer interconnect waveguides. Adjust the structure's position, determining the location of the interlayer waveguides by identifying the waveguide end faces. Based on the waveguide positions, adjust the 3D optical interconnect model (including a Taper transition structure and two 45° reflectors) drawn in Solidworks software. Save the model as a printable STL file and print the interlayer interconnect waveguides.

[0043] Developing the waveguide structure. Two development methods are available: ① Use a Reprise1000 developing and coating equipment to develop the printed structure. This method is convenient and quick. ② Alternatively, you can soak the printed structure in propylene glycol monomethyl ether (PGME) solution for 10-20 minutes (the exact time depends on the amount of photoresist), then soak it in isopropanol (IPA) solution for 5 minutes to wash away the developer, and finally dry it with a nitrogen gun to stabilize the printed structure.

[0044] By simulating and designing specific waveguide cross-sectional dimensions, optimal mode field matching between the on-chip waveguide and the polymer waveguide is ensured. Specifically, the polymer waveguide dimensions are determined by simulating the mode fields of the on-chip waveguide and the polymer waveguide to guarantee optimal mode field matching. (1) Overlapping integrals can be calculated:

[0045] In the formula, For the overlap integral, The electric field of the polymer waveguide cross section, To determine the electric field of the on-chip waveguide, the dimensions of the polymer waveguide are scanned using simulation. maximum; (2) Their respective modulus areas can also be calculated. Make them similar:

[0046] By adjusting the laser power and layer thickness parameters during printing, the low-loss transmission characteristics of the waveguide and the accuracy of the reflector 42 are ensured. By designing the length and refractive index gradient of the gradient refractive index interface, the docking loss between the waveguide and different types of on-chip waveguides is customized to meet the needs of different CPO scenarios.

[0047] This embodiment is based on the 1μm resolution of the Sonata1000 device, with a waveguide spacing of ≤20μm and a channel density of ≥100 channels / cm², which is 100% higher than the traditional wire bonding scheme (<50 channels / cm²). It can adapt to the high-density channel requirements of 1.6T and above CPO modules, and the waveguide cross-section error is ≤5μm, which can stably adapt to the narrow spacing of 50-200μm between CPO layers.

[0048] In a further embodiment, the outer surfaces of the first reflector 42 and the second reflector 42 are coated with a reflective film, and the outer surface of the reflective film is also coated with an anti-oxidation layer.

[0049] In this embodiment, the reflective film can be a gold film, and the anti-oxidation layer can be an aluminum oxide layer. In this embodiment, a gold film is first deposited on the surface of the structure to reduce the bending loss of light waves, and then an aluminum oxide layer is deposited to form an anti-oxidation protective barrier, thereby improving the long-term stability of the structure.

[0050] This embodiment integrates the reflector 42 with the waveguide using 3D printing, achieving an angle error of ≤0.05°. It is also coated with a "gold film + aluminum oxide anti-oxidation layer," which solves the assembly error problem of the external reflector 42 and avoids oxidation failure of the reflective surface. The bending loss is ≤0.3dB / cycle, breaking through the high bending loss bottleneck of existing solutions.

[0051] In a further embodiment, the port where the optical chip connects to the 3D-printed waveguide 4 is provided with a silanization layer.

[0052] The silanization layer serves as the interface layer between the chip's end face and the 3D-printed waveguide 4. The principle is that the inorganic alkoxy group in the silane coupling agent molecule can undergo hydrolysis in an ethanol system to generate active silanol groups (-Si-OH). These silanol groups further undergo dehydration condensation with the hydroxyl groups on the device surface to form stable Si-O-device covalent bonds. Simultaneously, the organic functional group (methacryloyloxy) at the other end of the silane molecule can chemically interact with the polymer chains in the negative photoresist (such as Vancore B, IP-Dip, IP-S, etc.) used subsequently to prepare the polymer microstructure. Ultimately, a chemically bonded transition interface is constructed between the substrate and the polymer microstructure, significantly improving the adhesion between them.

[0053] In a further embodiment, a base 6 is also included, on which the fiber array 1, the optical chip module and the photoelectric conversion chip 5 are all disposed.

[0054] Alternatively, different chips can be assembled together via a base 6.

[0055] A second embodiment of the present invention provides an interconnection method for an optical co-packaged interlayer interconnection device based on 3D printing, as described in the first embodiment of the present invention. Figure 3 As shown, it includes the following steps: At least two optical chips of the optical chip module are stacked and packaged, and fixed on the base 6; The fiber array 1 is fixed to the base 6, and the fiber array 1 and the uppermost optical chip of the optical chip module are at the same height. The photoelectric conversion chip 5 is fixed on the base 6; The fiber array 1 is connected to the optical chip module by 3D printing photonic leads; At least two optical chip layers of the optical chip module are interconnected by 3D printing waveguide 4.

[0056] In a further embodiment, before stacking and packaging at least two optical chips of the optical chip module, the at least two optical chips are further subjected to silanization treatment to generate a silanization treatment layer.

[0057] In a further embodiment, the at least two optical chips are subjected to silanization to generate a silanized layer, including: Pretreatment: Clean the optical chip, then activate the optical chip with plasma to make the surface of the optical chip hydrophilic; Solution preparation: Mix ethanol and 3-trimethoxysilylpropyl methacrylate in a petri dish, and add diluted acetic acid before immersing the optical chip; Device immersion treatment: Immerse the optical chip in the prepared solution for a preset time, rinse the device with isopropanol solution, and dry it with nitrogen gas to complete the silanization treatment. A silanized layer is generated at the port connected to the 3D printed waveguide 4.

[0058] In a further embodiment, the stacking and packaging of at least two optical chips of the optical chip module includes fixing the upper optical chip to the lower optical chip using a four-corner flip-chip method.

[0059] The third embodiment of the present invention describes the processing steps of the 3D-printed optical co-packaged interlayer interconnect device provided in the first embodiment of the present invention. The specific steps include: 1. Silanization of the chip. This mainly includes four steps: ① Chip pretreatment: Clean the optical chip, then activate the substrate with oxygen or air plasma to make its surface hydrophilic, improving the silanization effect. ② Solution preparation: Mix 50 mL of ethanol and 250 μL of 3-(trimethoxysilyl)propyl methacrylate (CAS 2530-85-0) in a petri dish. Before immersing the optical chip, add 1.5 mL of diluted acetic acid (glacial acetic acid:water = 1:10). ③ Optical chip immersion treatment: Immerse the optical chip in the prepared ethanol / 3-(trimethoxysilyl)propyl methacrylate solution for at least 5 minutes. After immersion, rinse the device with isopropanol solution and dry it with nitrogen. This completes the silanization process.

[0060] 2. Assemble the chip and optical fiber. After obtaining the silanized chip, assemble the chip with optical I / O and optical on-chip processing structure together, adjust the position of the optical fiber and chip under an optical microscope, and fix them with UV adhesive.

[0061] 3. Print the waveguide lead. Start the printing equipment, fix the assembled device on the vacuum adsorption stage, apply photoresist evenly to the area to be printed, locate the chip under the objective lens, and center the printing area in the view. If necessary, level the chip using a rotary stage. Determine the waveguide position by identifying the waveguide end face, and begin printing the 3D-printed photonic lead between fiber array 1 and the on-chip waveguide.

[0062] 3. Print the waveguides for interlayer interconnection. Adjust the position of the structure and determine the position of the interlayer waveguides by identifying the waveguide end faces. Based on the position of the waveguides, adjust the 3D optical interconnect model drawn in Solidworks software (the model includes a taper transition structure and two 45° reflectors 42), save the model as a printable STL file, and print the 3D waveguide 4.

[0063] 4. Development of the waveguide structure. Two development methods can be selected. ① Use the Reprise1000 developing and coating equipment to develop the printed structure. This method is convenient and quick. ② Alternatively, the printed structure can be soaked in propylene glycol monomethyl ether (PGME) solution for 10-20 minutes (the specific time depends on the amount of photoresist), then soaked in isopropanol (IPA) solution for 5 minutes to wash away the developer, and finally dried with a nitrogen gun to stabilize the printed structure.

[0064] 5. Encapsulated interconnect structure. First, a gold film is deposited on the surface of the structure to reduce the bending loss of light waves. Then, an aluminum oxide layer is deposited on top to form an anti-oxidation protective barrier and improve the long-term stability of the structure.

Claims

1. A 3D-printed optical co-packaged interlayer interconnect device, characterized in that, include: An optical fiber array, used for transmitting optical signals; An optical chip module, comprising at least two optical chips interconnected by multiple 3D-printed waveguides, wherein the optical chip module and the fiber array are interconnected by 3D-printed photonic leads for optical signal interconnection. A photoelectric conversion chip is provided, which is interconnected with the optical chip module to perform photoelectric conversion on the optical signal.

2. The 3D-printed optical co-packaged interlayer interconnect device according to claim 1, characterized in that, The optical chip module includes an optical I / O chip and an optical on-chip signal processing chip. The optical I / O chip and the optical fiber array are interconnected by optical signals through 3D-printed photonic leads. The optical I / O chip and the optical on-chip signal processing chip are interconnected by multiple 3D-printed waveguides. The optical on-chip signal processing chip and the photoelectric conversion chip are interconnected by optical signals.

3. The 3D-printed optical co-packaged interlayer interconnect device according to claim 1, characterized in that, Each of the 3D-printed waveguides includes a first graded-index tapered interface, a first horizontal waveguide segment, a first reflector, a vertical waveguide segment, a second reflector, a second horizontal waveguide segment, and a second graded-index tapered interface, wherein: The optical signal of any of the optical chips enters the 3D printed waveguide through the first graded refractive index Taper interface, passes through the first horizontal waveguide section and the first reflector in sequence, then makes a vertical turn into the vertical waveguide section, then makes a vertical turn through the second reflector into the second horizontal waveguide section, and finally enters another optical chip through the second graded refractive index Taper interface.

4. The 3D-printed optical co-packaged interlayer interconnect device according to claim 3, characterized in that, The outer surfaces of the first and second reflectors are coated with a reflective film, and the outer surface of the reflective film is also coated with an anti-oxidation layer.

5. The 3D-printed optical co-packaged interlayer interconnect device according to claim 1, characterized in that, The port where the optical chip connects to the 3D printed waveguide is provided with a silanization layer.

6. The 3D-printed optical co-packaged interlayer interconnect device according to any one of claims 1 to 5, characterized in that, It also includes a base, on which the fiber array, optical chip module and photoelectric conversion chip are all mounted.

7. An interconnection method for an optical co-packaged interlayer interconnection device based on 3D printing according to claim 6, characterized in that, Includes the following steps: At least two optical chips of the optical chip module are stacked and packaged, and fixed to the base; The fiber array is fixed to the base, and the fiber array and the uppermost optical chip of the optical chip module are at the same height; The photoelectric conversion chip is fixed on the base; The fiber array is connected to the optical chip module by 3D-printed photonic leads; At least two optical chip layers of an optical chip module are interconnected by 3D-printed waveguides.

8. The interconnection method for the 3D-printed optical co-packaged interlayer interconnection device according to claim 7, characterized in that, Before stacking and packaging at least two optical chips of the optical chip module, the process further includes silanizing the at least two optical chips to generate a silanized layer.

9. The interconnection method for an optical co-packaged interlayer interconnection device based on 3D printing according to claim 8, characterized in that, The at least two optical chips are subjected to silanization treatment to generate a silanized layer, including: Pretreatment: Clean the optical chip, then activate the optical chip with plasma to make the surface of the optical chip hydrophilic; Solution preparation: Mix ethanol and 3-trimethoxysilylpropyl methacrylate in a petri dish, and add diluted acetic acid before immersing the optical chip; Device immersion treatment: Immerse the optical chip in the prepared solution for a preset time, rinse the device with isopropanol solution, and dry it with nitrogen gas to complete the silanization treatment, generating a silanized layer at the port connected to the 3D printed waveguide.

10. The interconnection method for the 3D-printed optical co-packaged interlayer interconnection device according to claim 7, characterized in that, The process of stacking and packaging at least two optical chips of an optical chip module includes fixing the upper optical chip to the lower optical chip using a four-corner flip-chip method.

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