LDO circuit

Abstract

The invention provides an LDO circuit. The LDO circuit comprises a first loop and a second loop, the first loop enables the sampling voltage of the circuit output voltage to be determined by the reference voltage, and the first end voltage of the power tube is used as the circuit output voltage. The second loop can couple the first end voltage of the power tube to the gate end of the power tube through a first capacitor and a first transistor, so that a rapid feedback path is formed, the gate end of the power tube can be flexibly changed, and when the output voltage is changed due to transient rapid jump of a load, through the second loop, the first end voltage of the power tube is output. When the LDO circuit is used, the voltage at the grid end of the power tube can be correspondingly and rapidly increased or decreased to adjust the output current, the response speed of the LDO circuit can be increased, and the working speed of a chip applying the LDO circuit can be increased.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and more particularly to an LDO circuit. Background Technology

[0002] With the rapid development of electronic technology, power management chips are playing an increasingly crucial role in various portable electronic devices such as smartphones, tablets, or other electronic products. LDOs (Low Dropout Regulators) are widely used in power management chips due to their simple structure and excellent performance to achieve voltage regulation.

[0003] One existing LDO circuit uses a flip-flop voltage follower (FVF) to form an FVF-LDO. In this circuit, the gate voltage of the power transistor is usually lower than the circuit input voltage. When the load current changes, the gate voltage of the power transistor cannot change flexibly, making it difficult to achieve a fast response. Summary of the Invention

[0004] To improve the response capability of LDO when the load current changes, the present invention provides an LDO circuit.

[0005] The LDO circuit provided by this invention includes:

[0006] In the first loop, the sampling circuit outputs a voltage and inputs the obtained sampled voltage and reference voltage into an operational amplifier. The output voltage of the operational amplifier is coupled to the gate of a control transistor. The first terminal voltage of the control transistor is amplified through multiple stages and then coupled to the gate of a power transistor. The first terminal voltage of the power transistor is used as the output voltage of the circuit.

[0007] The second loop couples the first terminal voltage of the power transistor to the gate terminal of the power transistor via a first capacitor and a first transistor.

[0008] Optionally, the first and second terminals of the power transistor are respectively coupled to the second terminal of the control transistor and the circuit input voltage.

[0009] Optionally, the power transistor and the control transistor are PMOS transistors, the first terminal voltage of the control transistor is the drain terminal voltage of the control transistor, and the first terminal voltage of the power transistor is the drain terminal voltage of the power transistor.

[0010] Optionally, the LDO circuit includes:

[0011] A voltage sampling module is used to sample the output voltage of the circuit to obtain the sampled voltage. The voltage sampling module includes a first voltage divider resistor and a second voltage divider resistor connected in series between the output voltage of the circuit and ground. The voltage at the series node of the first voltage divider resistor and the second voltage divider resistor is the sampled voltage. One input terminal of the operational amplifier is coupled to the sampled voltage and the other input terminal is coupled to the reference voltage.

[0012] Optionally, the LDO circuit further includes:

[0013] The second capacitor is coupled between the output voltage of the circuit and the input terminal of the operational amplifier coupled to the sampling voltage.

[0014] Optionally, the LDO circuit includes a multi-stage amplification structure for multi-stage amplification of the drain voltage of the control transistor; the multi-stage amplification structure includes:

[0015] A first current mirror unit is used to mirror the current flowing through the control transistor into a bias current; and

[0016] The second current mirror unit is used to mirror the bias current as the pull-up current at the gate of the power transistor, wherein the pull-down current at the gate of the power transistor is constant.

[0017] Optionally, the first current mirror unit includes a second transistor and a third transistor, the gate terminals of the second transistor and the third transistor and the drain terminal of the second transistor are coupled to a first terminal of the control transistor, and the source terminals of the second transistor and the third transistor are grounded; the multi-stage amplification structure further includes a fourth transistor, the source terminal of the fourth transistor is coupled to the drain terminal of the third transistor, and the gate terminal of the fourth transistor is coupled to an input bias voltage, the input bias voltage causing the fourth transistor to operate in the saturation region.

[0018] Optionally, the second current mirror unit includes a fifth transistor and a sixth transistor, the gate terminals of the fifth transistor and the drain terminal of the sixth transistor are coupled to the drain terminal of the fourth transistor, the source terminals of the fifth transistor and the sixth transistor are coupled to the circuit input voltage, and the drain terminal of the sixth transistor is coupled to the gate terminal of the power transistor.

[0019] Optionally, the gate of the first transistor is coupled to an input bias voltage.

[0020] Optionally, the source terminal of the first transistor is coupled to one end of the first capacitor, the drain terminal is coupled to the control terminal of the power transistor, and the other end of the first capacitor is coupled to the first terminal of the power transistor.

[0021] Optionally, the LDO circuit further includes a constant current source coupled between the source terminal of the first transistor and ground, the constant current source being used to provide a constant pull-down current to the first transistor.

[0022] Optionally, the LDO circuit further includes an RC series structure coupled between the circuit input voltage and the control terminal of the power transistor.

[0023] The LDO circuit provided by this invention includes a first loop and a second loop. The first loop determines the sampling voltage of the circuit output voltage based on the reference voltage, using the first terminal voltage of the power transistor as the circuit output voltage. The second loop couples the first terminal voltage of the power transistor to the gate terminal of the power transistor via a first capacitor and a first transistor, thereby forming a fast feedback path. This allows the gate terminal of the power transistor to change flexibly. When the load transiently changes rapidly, causing the output voltage to change, the gate terminal voltage of the power transistor will increase or decrease rapidly accordingly through the second loop to adjust the output current and stabilize the output voltage. This improves the response speed of the LDO circuit and is beneficial for increasing the operating speed of chips using the LDO circuit. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of an LDO circuit according to an embodiment of the present invention. Detailed Implementation

[0025] The LDO circuit of the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0026] This invention relates to an LDO circuit, which includes a first loop (denoted as LP1) and a second loop (denoted as LP2). The first loop LP1 samples the output voltage and inputs the obtained sampled voltage and a reference voltage into an operational amplifier. The output voltage of the operational amplifier is coupled to the gate of a control transistor. The first terminal voltage of the control transistor is amplified by multiple stages and then coupled to the gate of a power transistor. The first terminal voltage of the power transistor is used as the output voltage of the circuit. The second loop LP2 couples the first terminal voltage of the power transistor to the gate of the power transistor through a first capacitor and a first transistor.

[0027] Figure 1 This is a schematic diagram of an LDO circuit according to an embodiment of the present invention. (Refer to...) Figure 1In order to form the first loop, an LDO circuit in one embodiment includes a power transistor MP, a voltage sampling module 10, an operational amplifier EA, a control transistor MC, and a multi-stage amplification structure 20.

[0028] Reference Figure 1 The LDO circuit has an input voltage VIN and an output voltage VOUT. The input range of the input voltage VIN can be set to a wide range, for example, 4.5V to 40V.

[0029] The first terminal of the power transistor MP is the output terminal of the LDO circuit, meaning the voltage at the first terminal of MP is the circuit output voltage VOUT. The second terminal of MP is coupled to the circuit input voltage VIN. By controlling the gate terminal of MP, the output current can be adjusted to stabilize the circuit output voltage VOUT. MP can be, for example, a PMOS transistor, with its source terminal coupled to the circuit input voltage and its drain terminal voltage being the circuit output voltage VOUT. In other embodiments, MP can also be an NMOS transistor or other switching devices.

[0030] The voltage sampling module 10 is used to sample the circuit output voltage VOUT to obtain the sampled voltage VFB. As an example, the voltage sampling module 10 includes a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series between the circuit output voltage VOUT and ground (GND), and the voltage at the series node of the first voltage divider resistor R1 and the second voltage divider resistor R2 is the sampled voltage VFB.

[0031] Operational amplifier EA has a non-inverting input, an inverting input, and an output. The non-inverting input is, for example, coupled to a reference voltage VREF, and the inverting input is, for example, coupled to the series node of a first voltage divider resistor R1 and a second voltage divider resistor R2, i.e., coupled to the sampling voltage VFB. By inputting the reference voltage VREF and the sampling voltage VFB into operational amplifier EA, through the first loop LP1, the sampling voltage VFB can gradually approach or equal the reference voltage VREF. Optionally, the LDO circuit also includes a second capacitor C2, which is coupled between the circuit output voltage VOUT and the input terminal (e.g., the inverting input terminal) of the operational amplifier EA where the coupled sampling voltage VFB is located.

[0032] The control terminal of the control transistor MC is coupled to the output terminal of the operational amplifier EA, so that the output voltage of the operational amplifier EA controls the control transistor MC. In this embodiment, the first terminal of the control transistor MC is coupled to the multi-stage amplification structure 20, and the second terminal is coupled to the first terminal of the power transistor MP (i.e., coupled to the power supply output voltage VOUT). The control transistor MC is, for example, a PMOS transistor, whose gate terminal is coupled to the output terminal of the operational amplifier EA, and whose source terminal is coupled to the drain terminal of the power transistor MP, and whose drain terminal is coupled to the multi-stage amplification structure 20. In other embodiments, the control transistor MC may also be an NMOS transistor or other switching devices.

[0033] A multi-stage amplification structure 20 (i.e., a cascode structure) is positioned between the first terminal of the control transistor MC and the gate terminal of the power transistor MP to amplify the voltage at the first terminal of the control transistor MC through multiple stages before inputting it to the gate terminal of the power transistor MP. The multi-stage amplification structure 20 can employ a common-source, common-gate architecture. For example, refer to... Figure 1 The multi-stage amplification structure 20 includes a first current mirror unit 21 and a second current mirror unit 22. The first current mirror unit 21 mirrors the current flowing through the control transistor MC into a bias current, and the second current mirror unit 22 mirrors the bias current into a pull-up current at the gate of the power transistor MP. Thus, when the load current increases, causing the circuit output voltage VOUT to decrease, the current flowing through the control transistor MC decreases, the bias current decreases, and the pull-up current at the gate of the power transistor MP decreases. Alternatively, the circuit can be configured to keep the pull-down current at the gate of the power transistor MP constant. Therefore, when the pull-up current at the gate of the power transistor MP decreases, the gate voltage of the power transistor MP decreases, VGS increases, thereby increasing the drive current and achieving the effect of adjusting the output current.

[0034] Reference Figure 1As an example, the first current mirror unit 21 includes a second transistor M2 and a third transistor M3. The gate terminals of the second transistor M2 and the drain terminal of the third transistor M3 are coupled to the first terminal of the control transistor MC, and the source terminals of the second transistor M2 and the third transistor M3 are grounded. The multi-stage amplification structure 20 also includes a fourth transistor M4. The source terminal of the fourth transistor M4 is coupled to the drain terminal of the third transistor M3, and its gate terminal is coupled to an input bias voltage VBIAS. The input bias voltage VBIAS causes the fourth transistor M4 to operate in the saturation region to facilitate current mirroring. The second current mirror unit 22 includes a fifth transistor M5 and a sixth transistor M6. The gate terminals of the fifth transistor M5 and the sixth transistor M6 are coupled to the drain terminal of the fourth transistor M4. The source terminals of the fifth transistor M5 and the sixth transistor M6 are coupled to the circuit input voltage VIN, and the drain terminal of the sixth transistor M6 is coupled to the gate terminal of the power transistor MP. In this embodiment, the multi-stage amplification structure 20 adopts an N-type cascode structure, which allows the circuit to accurately mirror the current under low-voltage power supply and also provides a high output impedance, pushing the secondary pole inside the circuit to higher frequencies. The second transistor M2, the third transistor M3, and the fourth transistor M4 are, for example, NMOS transistors, and the fifth transistor M5 and the sixth transistor M6 are, for example, PMOS transistors.

[0035] In this embodiment, the gate of the first transistor M1 is coupled to an input bias voltage. The gate of the fourth transistor M4 can be coupled to the gate of the first transistor M1 located in the second loop LP2. The input bias voltage VBIAS is the gate voltage of the fourth transistor M4 and the first transistor M1. According to the LDO circuit configuration of this embodiment, the value of the input bias voltage VBIAS causes the fourth transistor M4 and the first transistor M1 to operate in the saturation region to facilitate current mirroring. In another embodiment, the gates of the fourth transistor M4 and the first transistor M1 can also be uncoupled and connected to their respective bias voltages.

[0036] To achieve the aforementioned second loop LP2, refer to... Figure 1 The LDO circuit includes a first capacitor C1 and a first transistor M1. The first capacitor C1 is a feedforward capacitor, with one end coupled to the first terminal of the power transistor MP (i.e., the circuit output voltage VOUT), and the other end coupled to the first transistor M1. The first transistor M1 is, for example, an NMOS transistor. The source terminal of the first transistor M1 is coupled to the first capacitor C1, and the drain terminal is coupled to the gate terminal of the power transistor MP. According to Miller's theorem, the first capacitor C1 can effectively change the zero-pole distribution of the circuit. Using the first capacitor C1 and the first transistor M1, a fast feedback path, i.e., a second loop LP2, can be formed between the first terminal and the gate terminal of the power transistor MP. In this embodiment, the gate terminal of the first transistor M1 is coupled to the input bias voltage VBIAS. By setting the value of the input bias voltage VBIAS, the first transistor M1 can be made to operate in the saturation region.

[0037] Optionally, the LDO circuit further includes a constant current source IBIAS, which is coupled between the source terminal of the first transistor M1 and ground, and is used to provide a constant pull-down current to the first transistor M1.

[0038] The LDO circuit may further include an RC series structure coupled between the circuit input voltage VIN and the gate terminal of the power transistor MP. The RC series structure may include, for example: Figure 1 The diagram shows a third capacitor C3 and a resistor R3. One end of the third capacitor C3 is coupled to the circuit input voltage VIN, and the other end is coupled to the resistor R3. One end of the resistor R3 is coupled to the third capacitor C3, and the other end is coupled to the gate of the power transistor MP and the drain of the sixth transistor M6. This RC series structure, through RC low-pass filtering, can compensate for the ripple of the circuit input voltage VIN and improve the power supply rejection ratio.

[0039] When the load current jumps upward, the LDO circuit in the above embodiment operates as follows: The increase in load current causes a decrease in the circuit output voltage VOUT, simultaneously reducing the branch current of the control transistor MC and the second transistor M2. In the first loop LP1, through the mirror image of the second transistor M2 and the third transistor M3, the current in the branches containing the third transistor M3, the fourth transistor M4, and the fifth transistor M5 on the left decreases. Subsequently, through the mirror image of the fifth transistor M5 and the sixth transistor M6, the pull-up current of the sixth transistor M6 decreases. For the second loop LP2, since there is a constant current source IBIAS below the first transistor M1, the pull-down current of the first transistor M1 remains unchanged, causing a decrease in the gate voltage of the power transistor MP. This increases the gate-source voltage VGS of the power transistor MP, increasing the drive current and raising the circuit output voltage VOUT. The operation when the load current jumps downward is the opposite of the adjustment direction when the load current jumps upward.

[0040] The LDO circuit described in the above embodiment includes a first loop LP1 and a second loop LP2. The first loop LP1 determines the sampling voltage VFB of the circuit output voltage VOUT based on the reference voltage VREF, and uses the first terminal voltage of the power transistor MP as the circuit output voltage VOUT. The second loop LP2 can couple the first terminal voltage of the power transistor MP to the control terminal of the power transistor MP through the first capacitor C1 and the first transistor M1, thereby forming a fast feedback path. This allows the control terminal of the power transistor MP to change flexibly. For example, when the output voltage changes due to a rapid transient change in the load, the control terminal voltage of the power transistor MP will increase or decrease rapidly accordingly through the second loop LP2 to adjust the output current and stabilize the output voltage. This can improve the response speed of the LDO circuit and is beneficial to improving the operating speed of the chip using the LDO circuit.

[0041] Furthermore, the LDO circuit described in the above embodiments has a wide input range (e.g., 4.5V to 40V) and a very fast transient response. Moreover, by utilizing the fast response path containing the feedforward capacitor (i.e., the first capacitor C1), the secondary dominant pole inside the circuit can be pushed to a higher frequency, presenting a single pole within the unity-gain bandwidth. The feedforward capacitor and the first voltage divider resistor R1 form a zero point, which can compensate for the secondary pole in the loop, thus resulting in a large loop bandwidth and strong suppression of power supply noise.

[0042] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. An LDO circuit, characterized in that, include: In the first loop, the sampling circuit outputs a voltage and inputs the obtained sampling voltage and reference voltage into an operational amplifier. The output voltage of the operational amplifier is coupled to the gate terminal of a control transistor. The first terminal voltage of the control transistor is amplified by multiple stages and then coupled to the gate terminal of a power transistor. The first terminal voltage of the power transistor is used as the output voltage of the circuit. as well as The second loop couples the first terminal voltage of the power transistor to the gate terminal of the power transistor via a first capacitor and a first transistor.

2. The LDO circuit as described in claim 1, characterized in that, The first and second terminals of the power transistor are respectively coupled to the second terminal of the control transistor and the circuit input voltage.

3. The LDO circuit as described in claim 1, characterized in that, The power transistor and the control transistor are PMOS transistors. The first terminal voltage of the control transistor is the drain terminal voltage of the control transistor, and the first terminal voltage of the power transistor is the drain terminal voltage of the power transistor.

4. The LDO circuit as described in claim 1, characterized in that, include: A voltage sampling module is used to sample the output voltage of the circuit to obtain the sampled voltage. The voltage sampling module includes a first voltage divider resistor and a second voltage divider resistor connected in series between the output voltage of the circuit and ground. The voltage at the series node of the first voltage divider resistor and the second voltage divider resistor is the sampled voltage. One input terminal of the operational amplifier is coupled to the sampled voltage and the other input terminal is coupled to the reference voltage.

5. The LDO circuit as described in claim 1, characterized in that, Also includes: The second capacitor is coupled between the output voltage of the circuit and the input terminal of the operational amplifier coupled to the sampling voltage.

6. The LDO circuit as described in claim 1, characterized in that, This includes a multi-stage amplification structure for amplifying the drain voltage of the control transistor in multiple stages; the multi-stage amplification structure includes: A first current mirror unit is used to mirror the current flowing through the control transistor into a bias current; and The second current mirror unit is used to mirror the bias current as the pull-up current at the gate of the power transistor, wherein the pull-down current at the gate of the power transistor is constant.

7. The LDO circuit as described in claim 6, characterized in that, The first current mirror unit includes a second transistor and a third transistor. The gate terminals of the second transistor and the third transistor, as well as the drain terminal of the second transistor, are coupled to the first terminal of the control transistor. The source terminals of the second transistor and the third transistor are grounded. The multi-stage amplification structure also includes a fourth transistor. The source terminal of the fourth transistor is coupled to the drain terminal of the third transistor, and the gate terminal of the fourth transistor is coupled to an input bias voltage, which causes the fourth transistor to operate in the saturation region.

8. The LDO circuit as described in claim 7, characterized in that, The second current mirror unit includes a fifth transistor and a sixth transistor. The gate terminals of the fifth transistor and the sixth transistor and the drain terminal of the fifth transistor are coupled to the drain terminal of the fourth transistor. The source terminals of the fifth transistor and the sixth transistor are coupled to the circuit input voltage. The drain terminal of the sixth transistor is coupled to the gate terminal of the power transistor.

9. The LDO circuit as described in any one of claims 1 to 8, characterized in that, The gate of the first transistor is coupled to an input bias voltage.

10. The LDO circuit according to any one of claims 1 to 8, characterized in that, The source terminal of the first transistor is coupled to one end of the first capacitor, the drain terminal is coupled to the control terminal of the power transistor, and the other end of the first capacitor is coupled to the first terminal of the power transistor.

11. The LDO circuit according to any one of claims 1 to 8, characterized in that, It also includes a constant current source coupled between the source terminal of the first transistor and ground, the constant current source being used to provide a constant pull-down current to the first transistor.

12. The LDO circuit as described in any one of claims 1 to 8, characterized in that, It also includes an RC series structure coupled between the circuit input voltage and the control terminal of the power transistor.

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