Linear voltage regulator

Abstract

The invention discloses a linear voltage regulator, which relates to the technical field of electronic circuits, and is characterized in that an overshoot suppression circuit is arranged at the voltage output end of the linear voltage regulator, and the grid voltage of a first transistor is regulated by a first regulating circuit based on the grid voltage of a second transistor when the overshoot does not occur; during overshoot, the gate-source voltage of the first transistor is triggered to be rapidly increased along with the voltage change of the voltage output end, so that a current discharge path to the ground is formed; a grid electrode of a power tube of the linear voltage regulator is provided with an undershoot suppression circuit, a second regulation circuit maintains a static working state of a third transistor when undershoot is not carried out, and the grid electrode voltage of the third transistor is triggered to change along with a voltage output end when undershoot is carried out, so that the third transistor triggers the power tube to rapidly supplement current to a load capacitor. On the basis of suppressing the undershoot state of the voltage output end and suppressing the overshoot and undershoot problems of the voltage output end of the linear voltage regulator, the overshoot and undershoot circuit has good robustness on the influence of environment changes such as process and temperature on the overshoot and undershoot circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and more particularly to a linear voltage regulator. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in power management integrated circuits due to their low noise, high accuracy, and simple structure. Traditional LDOs typically require a large external load capacitor to maintain loop stability and suppress output voltage fluctuations. This external capacitor occupies a significant portion of the printed circuit board (PCB), increasing system cost and size, and hindering the high integration and miniaturization of electronic devices. To overcome this drawback, capless LDO designs emerged. These LDOs eliminate the bulky external capacitor, integrating a relatively small load capacitor internally. However, this leads to a situation where, when the load current undergoes rapid and significant step changes, the LDO cannot promptly adjust its power transistor to respond to the load's current demand. This results in large overshoot or undershoot voltages at the LDO's output, with a long recovery time, impacting the stable operation and performance of the load.

[0003] Therefore, how to suppress overshoot or undershoot voltage generated by linear regulators without external capacitors when the load current changes suddenly is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] The present invention provides a linear regulator to at least solve the problem of overshoot or undershoot voltage generated by linear regulators without external capacitors in the related art when the load current changes abruptly.

[0005] To solve the above-mentioned technical problems, the present invention provides a linear regulator, comprising: an error amplifier, a power transistor, a feedback circuit, an overshoot suppression circuit, and an undershoot suppression circuit; The overshoot suppression circuit includes a first transistor, a second transistor, a first current source, and a first adjustment circuit. The first transistor is located between the voltage output terminal of the linear regulator and ground. The second transistor is connected in series with the first current source and connected between the DC power supply and ground. The gate and drain of the second transistor are connected. The first adjustment circuit is located between the gate of the first transistor and the gate of the second transistor. The first adjustment circuit is used to adjust the gate voltage of the first transistor based on the gate voltage of the second transistor when the voltage output terminal is not in an overshoot state. When the voltage output terminal is in an overshoot state, the first adjustment circuit triggers the gate voltage of the first transistor to change with the voltage output terminal to form a current discharge path from the voltage output terminal to the ground terminal. The undershoot suppression circuit includes a third transistor and a second adjustment circuit. The third transistor is disposed between the gate of the power transistor and ground. A first terminal of the second adjustment circuit is connected to the voltage output terminal, and a second terminal of the second adjustment circuit is connected to the gate of the third transistor. The third transistor is used to maintain the static operating state of the third transistor when the voltage output terminal is not in an undershoot state, and when the voltage output terminal is in an undershoot state, to trigger the gate voltage of the third transistor to change with the voltage output terminal so that the third transistor triggers the power transistor to suppress the undershoot state of the voltage output terminal.

[0006] Optionally, the first adjustment circuit includes a common-source amplifier and an operational amplifier; The signal input terminal of the common-source amplifier is connected to the voltage output terminal, the signal output terminal of the common-source amplifier is connected to the gate of the first transistor, the gate of the amplifying transistor in the common-source amplifier is connected to the output terminal of the operational amplifier, and the two input terminals of the operational amplifier are respectively connected to the gate of the first transistor and the gate of the second transistor.

[0007] Optionally, both the first transistor and the second transistor are NMOS transistors.

[0008] Optionally, the common-source amplifier includes a fourth transistor and a fifth transistor; The source of the fourth transistor is the signal input terminal of the common-source amplifier, the drain of the fourth transistor is connected to the drain of the fifth transistor, the gate of the fourth transistor is connected to the output terminal of the operational amplifier, the source of the fifth transistor is grounded, and the gate of the fifth transistor is connected to the gate of the second transistor.

[0009] Optionally, the first adjustment circuit may further include a first capacitor disposed at the DC power supply and the output terminal of the operational amplifier.

[0010] Optionally, the second regulation circuit includes a second capacitor and a first voltage clamping circuit; The second capacitor is located between the gate of the third transistor and ground; the output terminal of the first voltage clamping circuit is connected to the gate of the third transistor, and the first voltage clamping circuit is used to maintain the static operating state of the third transistor when the voltage output terminal is not in an undercharge state.

[0011] Optionally, the first voltage clamping circuit includes a second current source, a sixth transistor, a seventh transistor, and an eighth transistor;

[0012] The third transistor and the eighth transistor are both PMOS transistors; the sixth transistor and the seventh transistor are both NMOS transistors. The first terminal of the second current source is connected to a DC power supply. The second terminal of the second current source is connected to the drain, gate, and gate of the sixth transistor and the seventh transistor. The sources of the sixth and seventh transistors are grounded. The drains of the seventh and eighth transistors, the gate of the eighth transistor, and the gate of the third transistor are connected to the first terminal of the second capacitor. The sources of the eighth and third transistors are connected to the gate of the power transistor. The drain of the third transistor is grounded. The second terminal of the second capacitor is connected to the voltage output terminal.

[0013] Optionally, a source follower may also be provided between the output of the error amplifier and the gate of the power transistor.

[0014] Optionally, the feedback circuit includes a first resistor and a second resistor, the first resistor and the second resistor are connected in series and connected between the voltage output terminal and ground, and the connection point of the first resistor and the second resistor is connected to the positive input terminal of the error amplifier.

[0015] Optionally, the source follower of the error amplifier, the undershoot suppression circuit, and the power transistor are configured as N parallel-connected driving units, and each driving unit includes one source follower, one undershoot suppression circuit, and one power transistor.

[0016] This invention provides an overshoot suppression circuit at the voltage output terminal of a linear regulator and an undershoot suppression circuit at the gate of the power transistor of the linear regulator. The overshoot suppression circuit includes a first transistor, a second transistor, a first current source, and a first adjustment circuit. The second transistor and the first current source are connected in series between the DC power supply and ground. The gate and drain of the second transistor are connected. When there is no overshoot at the voltage output terminal of the linear regulator, the first adjustment circuit adjusts the gate voltage of the first transistor based on the gate voltage of the second transistor. When there is an overshoot at the voltage output terminal, the gate voltage of the first transistor changes with the voltage output terminal to form a current discharge path to ground. The undershoot suppression circuit includes a third transistor and a second adjustment circuit. When there is no undershoot at the voltage output terminal of the linear regulator, the second adjustment circuit maintains the static operating state of the third transistor. When there is an undershoot at the voltage output terminal, the gate voltage of the third transistor changes with the voltage output terminal to trigger the power transistor of the linear regulator to suppress the undershoot state at the voltage output terminal. Through the first and second adjustment circuits, the overshoot and undershoot problems at the voltage output of the linear regulator can be suppressed. The transistors are also well adapted to the effects of environmental changes such as process and temperature. This allows the linear regulator to avoid interference with the main circuit when it is working normally and to maintain good transient response capability during overshoot or undershoot. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a linear voltage regulator provided in an embodiment of the present invention; Figure 2 A circuit diagram of an overshoot suppression circuit provided in an embodiment of the present invention; Figure 3 This is a circuit diagram of an undershoot suppression circuit provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0020] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0021] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] Figure 1 This is a schematic diagram of a linear voltage regulator provided in an embodiment of the present invention.

[0023] like Figure 1 As shown, the linear regulator provided in this embodiment of the invention may include: an error amplifier EA, a power transistor MP, a feedback circuit, an overshoot suppression circuit, and an undershoot suppression circuit;

[0024] The overshoot suppression circuit includes a first transistor M3, a second transistor M1, a first current source Idc1, and a first adjustment circuit. The first transistor M3 is located between the voltage output terminal VOUT of the linear regulator and ground. The second transistor M1 is connected in series with the first current source Idc1 and connected between VDD and ground. The gate and drain of the second transistor M1 are connected. The first adjustment circuit is located between the gate of the first transistor M3 and the gate of the second transistor M1. When the voltage output terminal VOUT is not in an overshoot state, the first adjustment circuit adjusts the gate voltage of the first transistor M3 based on the gate voltage of the second transistor M1. When the voltage output terminal VOUT is in an overshoot state, the first adjustment circuit triggers the gate voltage of the first transistor M3 to change with the voltage output terminal VOUT to form a current discharge path from the voltage output terminal VOUT to the ground terminal.

[0025] The undershoot suppression circuit includes a third transistor M8 and a second adjustment circuit. The third transistor M8 is located between the gate of the power transistor MP and ground. The first terminal of the second adjustment circuit is connected to the voltage output terminal VOUT, and the second terminal of the second adjustment circuit is connected to the gate of the third transistor M8. The third transistor M8 is used to maintain the static operating state of the third transistor M8 when the voltage output terminal VOUT is not in an undershoot state. When the voltage output terminal VOUT is in an undershoot state, the gate voltage of the third transistor M8 is triggered to change with the voltage output terminal VOUT so that the third transistor M8 triggers the power transistor MP to suppress the undershoot state of the voltage output terminal VOUT.

[0026] In this embodiment of the invention, the first transistor M3, the second transistor M1, and the third transistor M8 can be MOS transistors.

[0027] In practical implementation, the first input terminal of the error amplifier EA (which can be either an inverting or non-inverting input terminal) is connected to the voltage feedback terminal of the feedback circuit, and the second input terminal of the error amplifier EA (which can be either a non-inverting or non-inverting input terminal) is connected to the reference voltage terminal. The first terminal of the power transistor MP is connected to the input power supply, and the second terminal of the power transistor MP, the input terminal of the feedback circuit, is connected to the voltage output terminal VOUT of the linear regulator.

[0028] The first terminal (source) of the power transistor MP is connected to the power supply voltage VDD, and its second terminal (drain) is connected to the voltage output terminal VOUT of the LDO circuit. The power transistor MP can be a PMOS transistor. The gate VP of the power transistor MP is connected to the output terminal of the error amplifier EA.

[0029] like Figure 1As shown, in the linear regulator provided in this embodiment of the invention, the feedback circuit may include a first resistor and a second resistor. The first resistor and the second resistor are connected in series and connected between the voltage output terminal VOUT and ground. The connection point of the first resistor and the second resistor is connected to the positive input terminal of the error amplifier EA. That is, the connection point of the first resistor and the second resistor serves as the voltage feedback terminal of the error amplifier EA.

[0030] like Figure 1 As shown, the linear regulator provided in this embodiment of the invention may further include a source follower MS disposed between the output terminal of the error amplifier EA and the gate of the power transistor MP. Specifically, the first path terminal of the source follower MS is connected to the power supply voltage VDD, its second path terminal is connected to the second terminal of the current source Idc, and its control terminal receives the output signal of the error amplifier EA. The first terminal of the current source Idc is connected to the voltage input terminal of the linear regulator (which can be the DC power supply VDD). The second path terminal of the source follower MS is also connected to the control terminal (gate) of the power transistor MP.

[0031] In this embodiment of the invention, the power transistor MP can be a PMOS transistor, and the source follower MS can be a PMOS transistor.

[0032] The linear regulator provided in this embodiment of the invention stabilizes the voltage at the voltage output terminal VOUT at a preset value in steady state by forming a negative feedback loop through the error amplifier EA, the source follower MS, the power transistor MP, and the feedback circuit.

[0033] The linear regulators provided in this invention mainly refer to capless linear regulators (LDOs), such as... Figure 1 As shown, CL is the load capacitor inside the linear regulator chip.

[0034] When the current demand of the load changes, the negative feedback loop of the linear regulator cannot respond to the load change due to bandwidth limitations. It can only respond to the load change by the charge storage capacity of the load capacitor CL. Therefore, the charge change on the load capacitor CL causes the voltage output VOUT to deviate from the ideal value, resulting in overshoot or undershoot effects. As the load change continues, the linear regulator loop begins to respond to the load. First, it detects the difference between the voltage output VOUT and the reference voltage VREF, amplifies it through the error amplifier EA, and then controls the gate voltage VP of the power transistor MP to adjust the output current. Finally, the voltage output VOUT is restored to the ideal value. However, due to the limited bandwidth of the linear regulator LDO, for rapidly changing loads, the voltage output VOUT usually generates a large overshoot or undershoot voltage and recovery time, which affects the stable operation and performance of the load.

[0035] For overshoot or undershoot issues in linear regulators without external capacitors, the load capacitance CL is typically around 100pF. Therefore, to meet the stability requirements of the LDO loop, the dominant pole is located at the output node of the error amplifier EA, and the secondary pole is located at the VOUT node. Due to the low frequency of the dominant pole, this significantly limits the bandwidth and response speed of the LDO. Consequently, the error amplifier EA loop cannot respond quickly to changes in load current, leading to large overshoot or undershoot voltages at the VOUT node and a long recovery time during the error amplifier EA's response. A traditional method to improve response speed is to increase the bandwidth of the error amplifier EA, but this comes at the cost of excessive power consumption.

[0036] As can be seen, there is a bandwidth limit for the design of the error amplifier EA to maintain system stability. The range of bandwidth improvement is limited, and even if the bandwidth of the error amplifier EA is increased, more power consumption will be consumed.

[0037] Therefore, the linear regulator provided in this embodiment of the invention includes an overshoot suppression circuit and an undershoot suppression circuit. The overshoot suppression circuit is located between the voltage output terminal VOUT of the linear regulator and ground, and the undershoot suppression circuit is located between the gate of the power transistor MP and ground.

[0038] Overshoot essentially occurs when the load current suddenly decreases, and the power transistor MP fails to turn off in time, causing excess energy to surge to the output node, resulting in a momentary increase in the voltage at the output terminal VOUT. To address this charge transfer at the output terminal VOUT, the overshoot suppression circuit provided in this embodiment is located at VOUT. By directly opening a current discharge path at VOUT, excess charge can be instantly removed. This is the most direct and least delayed method, and this current discharge path is independent of the control loop, thus not affecting the normal operation of the error amplifier EA and the power transistor MP.

[0039] Undershoot essentially occurs when a sudden increase in load current occurs, and the power transistor MP fails to turn on in time, causing the output node charge to be instantly drained, resulting in a sharp drop in VOUT. Therefore, the essence of undershoot is insufficient supply. Thus, the undershoot suppression circuit provided in this embodiment is located at the gate of the power transistor MP. The power transistor MP is typically the largest transistor in a linear regulator, with extremely high transconductance. Applying a small voltage change to the gate of the power transistor MP can generate a large current change at the voltage output terminal VOUT. Therefore, when undershoot occurs at the voltage output terminal VOUT, by rapidly acting on the gate of the power transistor MP, it controls the power transistor MP to increase the current to the voltage output terminal VOUT before the error amplifier EA. Compared to placing the undershoot suppression circuit at the voltage output terminal VOUT, placing it at the gate of the power transistor MP is more efficient, less wasteful, and beneficial to the stability of the linear regulator.

[0040] Based on the overshoot suppression circuit and undershoot suppression circuit to suppress the overshoot and undershoot problems of the linear regulator, the embodiments of the present invention further improve the robustness of the overshoot suppression circuit and undershoot suppression circuit by the specific structure of the overshoot suppression circuit and undershoot suppression circuit, so that the overshoot suppression circuit and undershoot suppression circuit have high robustness with changes in process, voltage, and temperature (PVT).

[0041] Specifically, the overshoot suppression circuit includes a first transistor M3, a second transistor M1, a first current source Idc1, and a first adjustment circuit. The second transistor M1 and the first current source Idc1 are connected in series between VDD and ground. The gate and drain of the second transistor M1 are connected, forming a diode-connected transistor. When the voltage output terminal VOUT of the linear regulator is not overshooting, the first adjustment circuit adjusts the gate voltage of the first transistor M3 based on the gate voltage of the second transistor. When the voltage output terminal VOUT is overshooting, the gate voltage of the first transistor M3 is triggered to change with the voltage of the voltage output terminal VOUT to form a current discharge path to ground.

[0042] The overshoot state of the voltage output terminal VOUT can refer to either the voltage at VOUT reaching a first voltage threshold or the voltage increase rate at VOUT reaching a first voltage increase rate threshold. Therefore, the component parameters of the overshoot suppression circuit are determined based on the threshold value of the overshoot state of the required voltage output terminal VOUT.

[0043] The undershoot suppression circuit includes a third transistor M8 and a second regulation circuit. When the voltage output terminal VOUT of the linear regulator is not undershooted, the second regulation circuit maintains the static operating state of the third transistor M8. When the voltage output terminal VOUT is undershooted, the gate voltage of the third transistor M8 is triggered to change with the voltage output terminal VOUT so that the third transistor M8 triggers the power transistor MP of the linear regulator to suppress the undershoot state of the voltage output terminal VOUT.

[0044] The undershoot state of the voltage output terminal VOUT can be defined as either the voltage at VOUT being less than a second voltage threshold, or the voltage drop rate at VOUT reaching a second voltage increase rate threshold. Therefore, the component parameters of the undershoot suppression circuit are determined based on the threshold value of the undershoot state of the required voltage output terminal VOUT.

[0045] Through the first and second adjustment circuits, the overshoot and undershoot problems of the voltage output terminal VOUT of the linear regulator can be suppressed. The transistors are also well adapted to the effects of environmental changes such as process and temperature. This allows the linear regulator to avoid interference with the main circuit when it is working normally and maintain good transient response capability during overshoot or undershoot.

[0046] Based on the above embodiments, the present invention further describes the structure of the overshoot suppression circuit.

[0047] Figure 2 The circuit diagram is provided for an overshoot suppression circuit according to an embodiment of the present invention.

[0048] In this embodiment of the invention, the first adjustment circuit may include a common-source amplifier and an operational amplifier (OPA); wherein, the signal input terminal of the common-source amplifier is connected to the voltage output terminal VOUT, the signal output terminal of the common-source amplifier is connected to the gate of the first transistor M3, the gate of the amplifying transistor in the common-source amplifier is connected to the output terminal of the operational amplifier (OPA), and the two input terminals of the operational amplifier (OPA) are respectively connected to the gate of the first transistor M3 and the gate of the second transistor M1.

[0049] In this embodiment of the invention, an operational amplifier (OPA) and a common-source amplifier are used to implement the function of the first adjustment circuit described in the above embodiment. A negative feedback loop is formed using the OPA and the amplifying transistors in the common-source amplifier. Utilizing the virtual short characteristic of the OPA, the gate voltage of the first transistor M3 is clamped to the gate voltage of the second transistor M1.

[0050] Since the second transistor M1 is connected in a diode configuration, and a stable current is provided to it through the first current source Idc1, the gate voltage of the second transistor M1 tends to be stable. Therefore, under the normal operation of the linear regulator, the gate voltage of the first transistor M3 is also stable, and the first transistor M3 is in a static operating state at this time.

[0051] Due to the bandwidth limitation of the operational amplifier (OPA), when an overshoot occurs at the voltage output terminal VOUT of the linear regulator, the source of the common-source amplifier transistor is rapidly raised, and this change is quickly transmitted to the gate of the first transistor M3. At this time, the gate voltage of the first transistor M3 will change with the voltage output terminal VOUT of the linear regulator.

[0052] It should be noted that if only a potential is provided to the gate of the first transistor M3, causing it to operate in a static state when the voltage output VOUT of the linear regulator is not overshooted, and then forming a current discharge path when the voltage output VOUT overshoots, the robustness of such an overshoot suppression circuit is poor because the conduction parameters of the first transistor M3 will drift with changes in PVT. However, the overshoot suppression circuit provided in this embodiment uses a diode-connected second transistor M1 and a first current source Idc1. The changes in the conduction parameters of the first transistor M3 and the second transistor M1 are synchronized, thus ensuring that the first transistor M3 can stably operate in a static state when the voltage output VOUT of the linear regulator is not overshooted, and also has good transient response capability when the voltage output VOUT of the linear regulator overshoots. Therefore, in this embodiment, the operational amplifier OPA is preferably a high-gain, low-bandwidth operational amplifier OPA.

[0053] In this embodiment of the invention, the first transistor M3 and the second transistor M1 can both be NMOS transistors.

[0054] In this embodiment of the invention, the common-source amplifier may include a fourth transistor M4 and a fifth transistor M2; the source of the fourth transistor M4 is the signal input terminal of the common-source amplifier, the drain of the fourth transistor M4 is connected to the drain of the fifth transistor M2, the gate of the fourth transistor M4 is connected to the output terminal of the operational amplifier OPA, the source of the fifth transistor M2 is grounded, and the gate of the fifth transistor M2 is connected to the gate of the second transistor M1.

[0055] In this embodiment of the invention, the fourth transistor M4 and the fifth transistor M2 can be MOS transistors.

[0056] In this embodiment of the invention, the first adjustment circuit may further include a first capacitor C1 disposed at the output terminal of VDD and operational amplifier OPA.

[0057] The overshoot suppression circuit provided in this embodiment of the invention forms a closed-loop negative feedback loop with the operational amplifier OPA and the fourth transistor M4 to perform voltage clamping, so that the gate voltage vb2 of the first transistor M3 is equal to the gate voltage vb1 of the second transistor M1. Thus, the first transistor M3 is equivalent to a voltage-controlled current source controlled by vb2.

[0058] Since the OPA is a high-gain, low-bandwidth operational amplifier, it only clamps the voltage of vb2. However, the closed-loop negative feedback loop formed by OPA-M4 has low bandwidth, and the negative feedback loop cannot respond quickly to high-frequency disturbances at the vb2 node.

[0059] Therefore, high-frequency voltage fluctuations at the output VOUT of the linear regulator will inevitably cause corresponding positive fluctuations at the vb2 voltage node. For example, when a sudden change in the load's current demand causes VOUT to overshoot, due to the slow response of the negative feedback loop of OPA-M4, the voltage of vb2 is also rapidly increased, meaning the gate-source voltage VGS of M3 increases rapidly. The current at the VOUT node is released through the channel of M3, and VOUT quickly recovers. In other words, a fast negative feedback loop is formed between the fourth transistor M4, the fifth transistor M2, and the first transistor M3, which quickly suppresses the overshoot at the output VOUT of the linear regulator.

[0060] In the linear regulator provided by this embodiment, the first transistor M3 adjusts the overshoot of the voltage output terminal VOUT of the linear regulator by releasing current. Compared with the traditional architecture, its static operating point is controlled by vb1 through the negative feedback mechanism of the operational amplifier OPA. That is, the static operating point of the first transistor M3 is a function of the first current source Idc1, so its operating state has high robustness to changes in PVT. Thus, the overshoot suppression circuit provided by this embodiment constructs a high-pass signal path from the voltage output terminal VOUT of the linear regulator to the vb2 node through the operational amplifier OPA, enabling vb2 to respond to the high-frequency overshoot signal of the voltage output terminal VOUT of the linear regulator and quickly adjust the overshoot state of the voltage output terminal VOUT of the linear regulator.

[0061] Based on the above embodiments, the present invention further describes the structure of the undershoot suppression circuit.

[0062] Figure 3 This is a circuit diagram of an undershoot suppression circuit provided in an embodiment of the present invention.

[0063] In this embodiment of the invention, the second adjustment circuit may include a second capacitor CU and a first voltage clamping circuit; wherein, the second capacitor CU is disposed between the gate of the third transistor M8 and ground; the output terminal of the first voltage clamping circuit is connected to the gate of the third transistor M8, and the first voltage clamping circuit is used to maintain the static operating state of the third transistor M8 when the voltage output terminal VOUT is not in an undercharge state.

[0064] In this embodiment of the invention, the second capacitor CU and the first voltage clamping circuit implement the function of the second regulation circuit described in the above embodiment. Utilizing the characteristics of a capacitor, the voltage at one end changes abruptly with the voltage change at the other end. Therefore, when the voltage output terminal VOUT of the linear regulator is not in an undershoot state, the first voltage clamping circuit controls the stability of the gate voltage of the third transistor M8, keeping the third transistor M8 in a static operating state. However, when the voltage output terminal VOUT of the linear regulator is in an undershoot state, the gate voltage of the third transistor M8 is rapidly pulled down by the second capacitor CU, thereby triggering the third transistor M8 to send a signal to the power transistor MP, triggering the power transistor MP to output current to the voltage output terminal VOUT of the linear regulator.

[0065] In this embodiment of the invention, the first voltage clamping circuit includes a first current source Idc2, a sixth transistor M5, a seventh transistor M6, and an eighth transistor M7; the third transistor M8 and the eighth transistor M7 are both PMOS transistors; the sixth transistor M5 and the seventh transistor M6 are both NMOS transistors; the first terminal of the first current source Idc2 is connected to VDD, the second terminal of the first current source Idc2 is connected to the drain of the sixth transistor M5, the gate of the sixth transistor M5, and the gate of the seventh transistor M6, the source of the sixth transistor M5 and the source of the seventh transistor M6 are both grounded, the drain of the seventh transistor M6, the drain of the eighth transistor M7, the gate of the eighth transistor M7, and the gate of the third transistor M8 are connected to the first terminal of the second capacitor CU, the source of the eighth transistor M7 and the source of the third transistor M8 are connected to the gate of the power transistor MP, the drain of the third transistor M8 is grounded, and the second terminal of the second capacitor CU is connected to the voltage output terminal VOUT.

[0066] When the load current demand increases, the error amplifier EA cannot keep up with the response, and the current can only be supplemented by the charge on the load capacitor CL. This causes a significant undershoot at the voltage output VOUT of the linear regulator. The undershoot suppression circuit provided in this embodiment detects the undershoot at the voltage output VOUT of the linear regulator. This signal does not pass through the error amplifier EA, thus achieving a fast response. The undershoot voltage increases the absolute value of the gate-source voltage |VGS| of the third transistor M8, rapidly releasing the charge on the gate of the power transistor MP. This reduces the gate voltage VP of the power transistor MP, allowing it to supplement the current of the load capacitor CL, and the voltage output VOUT of the linear regulator quickly returns to its ideal value.

[0067] In this embodiment of the invention, the source follower MS, undershoot suppression circuit and power transistor MP of the error amplifier EA can be configured as N parallel-connected driving units, and each driving unit includes a source follower, an undershoot suppression circuit and a power transistor MP.

[0068] Because the power transistor MP in a linear regulator is relatively large, its gate parasitic capacitance is also large, limiting the speed of gate charge release. To address this, this embodiment of the invention, based on the undershoot suppression circuit, can divide the module into five separate components. For example, the source follower MS, the undershoot suppression circuit, and the power transistor MP can be arranged as a whole in five parallel sections, while maintaining the overall size of the power transistor MP. Thus, the size of each section of the power transistor MP is reduced to 1 / 5 of its original size, significantly reducing the parasitic capacitance required to drive the undershoot suppression circuit and greatly improving the undershoot suppression response speed.

[0069] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0070] The linear voltage regulator provided by this invention has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A linear voltage regulator, characterized in that, include: Error amplifier, power transistor, feedback circuit, overshoot suppression circuit, and undershoot suppression circuit; The overshoot suppression circuit includes a first transistor, a second transistor, a first current source, and a first adjustment circuit. The first transistor is located between the voltage output terminal of the linear regulator and ground. The second transistor is connected in series with the first current source and connected between the DC power supply and ground. The gate and drain of the second transistor are connected. The first adjustment circuit is located between the gate of the first transistor and the gate of the second transistor. The first adjustment circuit is used to adjust the gate voltage of the first transistor based on the gate voltage of the second transistor when the voltage output terminal is not in an overshoot state. When the voltage output terminal is in an overshoot state, the first adjustment circuit triggers the gate voltage of the first transistor to change with the voltage output terminal to form a current discharge path from the voltage output terminal to the ground terminal. The undershoot suppression circuit includes a third transistor and a second adjustment circuit. The third transistor is disposed between the gate of the power transistor and ground. A first terminal of the second adjustment circuit is connected to the voltage output terminal, and a second terminal of the second adjustment circuit is connected to the gate of the third transistor. The third transistor is used to maintain the static operating state of the third transistor when the voltage output terminal is not in an undershoot state, and when the voltage output terminal is in an undershoot state, to trigger the gate voltage of the third transistor to change with the voltage output terminal so that the third transistor triggers the power transistor to suppress the undershoot state of the voltage output terminal.

2. The linear voltage regulator according to claim 1, characterized in that, The first adjustment circuit includes a common-source amplifier and an operational amplifier; The signal input terminal of the common-source amplifier is connected to the voltage output terminal, the signal output terminal of the common-source amplifier is connected to the gate of the first transistor, the gate of the amplifying transistor in the common-source amplifier is connected to the output terminal of the operational amplifier, and the two input terminals of the operational amplifier are respectively connected to the gate of the first transistor and the gate of the second transistor.

3. The linear voltage regulator according to claim 2, characterized in that, Both the first transistor and the second transistor are NMOS transistors.

4. The linear voltage regulator according to claim 2, characterized in that, The common-source amplifier includes a fourth transistor and a fifth transistor; The source of the fourth transistor is the signal input terminal of the common-source amplifier, the drain of the fourth transistor is connected to the drain of the fifth transistor, the gate of the fourth transistor is connected to the output terminal of the operational amplifier, the source of the fifth transistor is grounded, and the gate of the fifth transistor is connected to the gate of the second transistor.

5. The linear voltage regulator according to claim 2, characterized in that, The first adjustment circuit also includes a first capacitor located at the DC power supply and the output terminal of the operational amplifier.

6. The linear voltage regulator according to claim 1, characterized in that, The second regulation circuit includes a second capacitor and a first voltage clamping circuit; The second capacitor is located between the gate of the third transistor and ground; the output terminal of the first voltage clamping circuit is connected to the gate of the third transistor, and the first voltage clamping circuit is used to maintain the static operating state of the third transistor when the voltage output terminal is not in an undercharge state.

7. The linear voltage regulator according to claim 2, characterized in that, The first voltage clamping circuit includes a second current source, a sixth transistor, a seventh transistor, and an eighth transistor; The third transistor and the eighth transistor are both PMOS transistors; the sixth transistor and the seventh transistor are both NMOS transistors. The first terminal of the second current source is connected to a DC power supply. The second terminal of the second current source is connected to the drain, gate, and gate of the sixth transistor and the seventh transistor. The sources of the sixth and seventh transistors are grounded. The drains of the seventh and eighth transistors, the gate of the eighth transistor, and the gate of the third transistor are connected to the first terminal of the second capacitor. The sources of the eighth and third transistors are connected to the gate of the power transistor. The drain of the third transistor is grounded. The second terminal of the second capacitor is connected to the voltage output terminal.

8. The linear regulator according to claim 1, characterized in that, It also includes a source follower located between the output of the error amplifier and the gate of the power transistor.

9. The linear voltage regulator according to claim 1, characterized in that, The feedback circuit includes a first resistor and a second resistor, which are connected in series between the voltage output terminal and ground. The connection point of the first resistor and the second resistor is connected to the positive input terminal of the error amplifier.

10. The linear regulator according to any one of claims 1 to 9, characterized in that, The source follower of the error amplifier, the undershoot suppression circuit, and the power transistor are configured as N parallel-connected driving units, and each driving unit includes one source follower, one undershoot suppression circuit, and one power transistor.

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