Working frequency adjusting method, processor and electronic equipment

Abstract

The invention provides a working frequency adjusting method, a processor and electronic equipment, and relates to the field of integrated circuits, the working frequency adjusting method is applied to a frequency modulation and voltage regulation module, the frequency modulation and voltage regulation module is connected with the processor, the processor comprises a phase-locked loop, and the working frequency adjusting method comprises the following steps: receiving an adjusting instruction for working frequency; the adjustment instruction is used for indicating a target working frequency required by the processor; under the condition that the phase-locked loop operates, adjusting the frequency of a clock signal output by the phase-locked loop to a target frequency; the target frequency is a clock frequency enabling the processor to work at the target working frequency. The method can effectively reduce abnormal problems possibly occurring in the frequency modulation and voltage regulation process of the processor.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more specifically, provides a method for adjusting operating frequency, a processor, and an electronic device. Background Technology

[0002] DVFS (Dynamic Voltage and Frequency Scaling) technology can dynamically adjust the processor's operating frequency and power supply voltage according to the processor's real-time load, thereby reducing power consumption and improving processor performance.

[0003] Some processors use a phase-locked loop (PLL) to control their operating frequency. Therefore, adjusting the processor's operating frequency requires adjusting the PLL to change the clock signal output by the PLL.

[0004] When adjusting the phase-locked loop (PLL), you need to first switch the current clock source from the PLL to the reference clock, then disable the PLL to adjust the PLL in the disabled state, and finally switch the clock source back from the reference clock to the PLL after the PLL adjustment is completed.

[0005] The reference clock is typically a low-frequency clock; for example, some reference clocks have a frequency of 25MHz. Furthermore, there is a zero-clock issue when the clock source switches between the phase-locked loop and the reference clock, meaning the clock signal may be zero for a short period.

[0006] If, during the process of adjusting the operating frequency, the upper-layer application sends a large number of tasks to the processor, and the processor's various modules may also be performing calculations, data transmissions, writes, and other operations, the processor's frequency may suddenly drop to a very low level or even to 0, which may cause abnormal problems such as system freeze, data backpressure, and data loss. Summary of the Invention

[0007] In view of this, this application aims to provide a method for adjusting the operating frequency, a processor, and an electronic device to reduce possible abnormal problems during processor frequency and voltage adjustment.

[0008] The first invention, according to an embodiment of this application, provides a method for adjusting the operating frequency, applied to a frequency modulation and voltage regulation module. The frequency modulation and voltage regulation module is connected to a processor, and the processor includes a phase-locked loop (PLL). The method for adjusting the operating frequency includes: receiving an adjustment instruction for the operating frequency; the adjustment instruction indicating a target operating frequency required by the processor; and, while the PLL is running, adjusting the frequency of the clock signal output by the PLL to the target frequency; the target frequency being a clock frequency that enables the processor to operate at the target operating frequency.

[0009] In this embodiment, during frequency adjustment, the phase-locked loop (PLL) is not disabled, nor is the clock source switched to the reference clock. Instead, the PLL is used as the processor's clock source. Thus, during frequency adjustment, the processor can operate with the high-frequency clock provided by the PLL, effectively reducing the possibility of the processor's clock frequency being too low or even zero due to switching the clock source during the adjustment of the operating frequency. This effectively reduces the abnormal situation caused by the processor's low operating frequency due to the clock frequency being too low or zero, which cannot meet the task execution requirements.

[0010] In one embodiment, the adjustment instruction includes a frequency modulation type and a target frequency modulation amplitude; the frequency modulation type is either frequency increase or frequency decrease, and the target frequency modulation amplitude is the change in the processor frequency from the initial operating frequency to the target operating frequency; adjusting the frequency of the phase-locked loop output clock signal to the target frequency includes: determining the number of frequency modulations and the amplitude of the last frequency modulation based on a preset step size and the target frequency modulation amplitude; the preset step size is a preset frequency amplitude for a single adjustment of the operating frequency; wherein, the relationship between the preset step size, the target frequency modulation amplitude, the number of frequency modulations, and the amplitude of the last frequency modulation satisfies: X = M × a + Y, where X is the target frequency modulation amplitude, Y is the amplitude of the last frequency modulation, a is the preset step size, Y is less than a, and the number of frequency modulations is M + N times, where N is 0 when Y is 0, and N is 1 when Y is not 0, and M is equal to 0 or is an integer greater than 0; perform the first process M times or less: adjust the working voltage and the phase-locked loop based on the frequency modulation type and the preset step size; after performing the first process M times, perform the second process N times or less: adjust the working voltage and the phase-locked loop based on the frequency modulation type and the last frequency modulation amplitude, so that the frequency of the clock signal output by the phase-locked loop is the target frequency.

[0011] If the frequency of the phase-locked loop (PLL) output clock signal is adjusted too much when the PLL is not disabled, the PLL may lose lock and fail to output a stable frequency clock signal. Therefore, in the embodiments of this application, the frequency is adjusted multiple times based on a preset step size during the adjustment process. This effectively reduces the possibility of the PLL losing lock due to excessively large single adjustment amplitude, and reduces the possibility of processor malfunction due to the PLL's inability to output a stable frequency clock signal. Furthermore, the processor requires sufficient operating voltage to operate at a certain frequency. Therefore, when adjusting the PLL output clock signal frequency, the processor's operating voltage is adjusted to meet the processor's operating requirements, reducing or avoiding malfunctions caused by insufficient operating voltage. Thus, adjustments made to the PLL during operation will not affect the normal operation of the processor.

[0012] In one embodiment, adjusting the phase-locked loop (PLL) based on the frequency modulation type and the preset step size includes: adjusting the feedback division ratio of the PLL based on the frequency modulation type so that the frequency change amplitude of the clock signal output by the PLL corresponds to the preset step size; adjusting the PLL based on the frequency modulation type and the last frequency modulation amplitude includes: adjusting the feedback division ratio of the PLL based on the frequency modulation type so that the frequency change amplitude of the clock signal output by the PLL corresponds to the last frequency modulation amplitude; wherein, if the frequency modulation type is up-modulation, the feedback division ratio of the PLL is increased to increase the frequency of the clock signal output by the PLL; if the frequency modulation type is down-modulation, the feedback division ratio of the PLL is decreased to decrease the frequency of the clock signal output by the PLL.

[0013] In this embodiment, the frequency of the phase-locked loop (PLL) output clock signal is affected by the feedback division ratio. Therefore, the feedback division ratio can be adjusted to increase or decrease the frequency of the PLL output clock signal. When adjusting the feedback ratio, adjusting it based on a preset step size helps reduce or avoid the occurrence of PLL lockout due to excessive frequency adjustment, ensuring that adjustments to the PLL during operation do not affect the normal operation of the processor.

[0014] In one embodiment, the frequency modulation type in the adjustment instruction is frequency up; then the first process further includes: after adjusting the operating voltage based on the frequency modulation type and the preset step size, and before adjusting the phase-locked loop based on the frequency modulation type and the preset step size, waiting for a first preset delay; the first preset delay is a preset time required for the operating voltage to stabilize after adjusting the operating voltage; and the second process further includes: after adjusting the operating voltage based on the frequency modulation type and the last frequency modulation amplitude, and before adjusting the phase-locked loop based on the frequency modulation type and the last frequency modulation amplitude, waiting for the first preset delay.

[0015] In this embodiment, after the operating voltage is adjusted, it needs a period of time to stabilize. During this period, the operating voltage will fluctuate. If the frequency increase operation is performed without waiting for the operating voltage to stabilize, the operating voltage may fluctuate to a smaller value and then become mismatched with the operating voltage required for the adjusted operating frequency, causing abnormal operation of the processor. Therefore, in this embodiment, in both the first and second processes, a first preset delay is waited before the frequency increase operation to reduce or even avoid abnormal situations caused by the mismatch between the operating voltage and operating frequency during frequency and voltage adjustment.

[0016] In one embodiment, the frequency modulation type in the adjustment instruction is frequency reduction; the first process includes: after adjusting the phase-locked loop based on the frequency modulation type and the preset step size, adjusting the operating voltage based on the frequency modulation type and the preset step size; wherein, it is permissible to perform the next first process or the second process when the operating voltage is unstable.

[0017] In this embodiment of the application, during the frequency reduction process, it is necessary to reduce the operating frequency first and then reduce the operating voltage. Since it is a frequency reduction, even if the operating voltage is not stable at this time, the operating voltage will still be greater than the voltage required by the operating voltage after the frequency reduction. Therefore, it is not necessary to consider whether the operating voltage meets the required voltage corresponding to the operating frequency after the frequency adjustment. In this case, the first process or the second process can be performed directly when the operating voltage is not stable, thereby reducing the waiting time for frequency and voltage adjustment and improving the efficiency of frequency and voltage adjustment.

[0018] In one embodiment, before adjusting the operating voltage and the phase-locked loop based on the frequency modulation type, the preset step size, and the phase-locked loop, the method further includes: obtaining a protection voltage band, wherein the protection voltage band is a preset voltage value corresponding to the frequency fluctuation of the clock signal output by the phase-locked loop after adjustment; adjusting the operating voltage based on the frequency modulation type and the preset step size, including: adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the preset step size; and adjusting the operating voltage based on the frequency modulation type and the last frequency modulation amplitude, including: adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the last frequency modulation amplitude; the second process and the Mth first process when N is 0 further include: canceling the protection voltage band on the operating voltage.

[0019] After the frequency of the phase-locked loop (PLL) output clock signal is adjusted, the clock signal frequency will fluctuate for a period of time until it stabilizes at the adjusted frequency. If the fluctuation range is too large, causing the maximum value of the clock signal frequency during the fluctuation process to exceed the current operating voltage, it may cause the processor to malfunction. Therefore, in this embodiment, a protection voltage band can be set based on the required adjusted operating voltage. The protection voltage band is a preset voltage value corresponding to the frequency fluctuation of the PLL's output clock signal after adjustment. Thus, when the frequency of the PLL's output clock signal is used by the processor, the operating voltage required by the processor will not exceed the range of the protection voltage band, reducing or even avoiding abnormal situations during frequency and voltage adjustment. This ensures that adjustments made by the PLL during operation will not affect the normal operation of the processor. Finally, after the frequency adjustment is completed, the protection voltage band is removed from the operating voltage, ensuring that the processor's operating voltage corresponds to the operating frequency, without generating additional power consumption or performance waste.

[0020] In one embodiment, before canceling the protection voltage band on the operating voltage, the method further includes: waiting for a second preset time, the second preset time being the waiting time required for the phase-locked loop to output a stable frequency clock signal after adjusting the frequency.

[0021] After the frequency of the phase-locked loop output clock signal is adjusted, it needs a period of time to stabilize. In this embodiment, waiting for a second preset delay before canceling the protection voltage band can avoid abnormal situations caused by the mismatch between the processor's operating frequency and operating voltage when the frequency is not stable. In one embodiment, the frequency modulation type in the adjustment command is frequency upsampling; adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the preset step size includes: adjusting the operating voltage to be the sum of the current operating voltage, the voltage corresponding to the preset step size, and the protection voltage band; correspondingly, adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the last frequency modulation amplitude includes: adjusting the operating voltage to be the sum of the current operating voltage, the voltage corresponding to the last frequency modulation amplitude, and the protection voltage band; canceling the protection voltage band on the operating voltage includes: subtracting the voltage value corresponding to the protection voltage band from the adjusted operating voltage.

[0022] In this embodiment of the application, during the frequency upsampling process, the operating voltage is increased by an additional voltage value corresponding to the protection voltage band on the basis of the required adjustment voltage, which effectively reduces or avoids processor abnormalities caused by frequency fluctuations after frequency adjustment, resulting in the operating frequency being too high and the current operating voltage being unable to meet the operating voltage corresponding to the operating frequency.

[0023] In one embodiment, the frequency modulation type in the adjustment command is frequency reduction; adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the preset step size includes: adjusting the operating voltage to be the sum of the operating voltage corresponding to the intermediate operating frequency and the protection voltage band; the intermediate operating frequency is the frequency after adjusting the preset step size; if N is 1, canceling the protection voltage band on the operating voltage includes: when adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the last frequency modulation amplitude, adjusting the operating voltage to be the voltage corresponding to the target operating frequency; if N is 0, canceling the protection voltage band on the operating voltage includes: when adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the preset step size for the Mth time, adjusting the operating voltage to be the voltage corresponding to the target operating frequency.

[0024] In this embodiment, frequency reduction occurs first, followed by voltage reduction. Therefore, during frequency reduction, a protection voltage band can be added to the current operating voltage to increase the operating voltage, effectively preventing processor malfunctions caused by operating frequency fluctuations and voltage mismatch during frequency reduction. Furthermore, in both the first and second processes, the voltage is directly adjusted to the target operating frequency during the final frequency adjustment. That is, the protection voltage band is subtracted simultaneously when reducing the voltage by the preset step size or the final frequency adjustment amplitude, thus avoiding dividing the voltage adjustment into two steps and improving the efficiency of voltage adjustment.

[0025] In one embodiment, the protection voltage band is greater than the voltage value corresponding to the difference between the peak frequency fluctuation of the clock signal output by the phase-locked loop and the adjusted operating frequency after the phase-locked loop adjusts the preset step voltage.

[0026] In this embodiment of the application, by setting the protection voltage band in this way, the operating voltage required by the phase-locked loop during frequency modulation will not exceed the operating voltage of the protection voltage band, thereby reducing processor abnormalities caused by mismatch between operating voltage and operating frequency. Thus, the phase-locked loop in operation can be adjusted without affecting the normal operation of the processor.

[0027] In one embodiment, the preset step size is less than the minimum frequency change amplitude at which the phase-locked loop loses its lock.

[0028] In this embodiment, the preset step size is smaller than the minimum frequency change amplitude at which the phase-locked loop (PLL) loses lock. Adjusting the frequency of the PLL output clock signal with the preset step size can effectively prevent the PLL from losing lock, so that the PLL can provide a clock signal for the processor to work normally even when it is adjusted during operation.

[0029] Secondly, embodiments of this application provide a processor, including: a working module; a phase-locked loop connected to the working module, used to provide a clock signal corresponding to the working frequency for the working module; and a frequency and voltage modulation module connected to the phase-locked loop, used to execute the working frequency adjustment method as described in any of the first claims.

[0030] Thirdly, embodiments of this application provide an electronic device including the processor described in the second aspect. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 A flowchart illustrating a method for adjusting operating frequency according to an embodiment of this application; Figure 2 This is a schematic diagram of the frequency upsampling process provided in an embodiment of this application; Figure 3 This is a schematic diagram of a frequency reduction process provided in an embodiment of this application; Figure 4 This is a schematic diagram of an electronic device provided according to an embodiment of this application.

[0033] Icons: Processor 400; Working module 410; Phase-locked loop 420; Frequency and voltage regulation module 430. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0035] First, this application provides a method for adjusting the operating frequency, which can be used to adjust the operating frequency of a processor.

[0036] In this embodiment, the processor controls its operating frequency via a clock signal, which is provided by a phase-locked loop (PLL). In the embodiments of this application, the processor type includes, but is not limited to, various processors that use a PLL as their clock source, such as GPGPU (General-Purpose computing on Graphics Processing Units), GPU (Graphics Processing Unit), CPU (central processing unit), and NPU (Neural Processing Unit). The specific type is not limited herein.

[0037] In the embodiments of this application, the operating frequency adjustment method can be applied to a frequency modulation and voltage regulation module, which can be a control module independent of the processor. For example, the frequency modulation and voltage regulation module can be an MCU (Microcontroller Unit). The frequency modulation and voltage regulation module can communicate with the processor to obtain the processor's status and adjust the operating voltage and operating frequency.

[0038] In some embodiments of this application, the frequency and voltage regulation module may also be part of the processor. For example, the power management module of the processor may be used to implement the function of the frequency and voltage regulation module provided in this application, so as to implement the operating frequency adjustment method using the power management module.

[0039] Next, the operating frequency adjustment method provided in this application will be described. This operating frequency adjustment method can be applied to the aforementioned frequency modulation and voltage regulation module. Please refer to... Figure 1 , Figure 1 This is a flowchart of an embodiment of the operating frequency adjustment method provided in this application. The operating frequency adjustment method includes: S110 receives instructions to adjust the operating frequency.

[0040] In this embodiment of the application, the adjustment instruction is used to indicate the target operating frequency required by the processor.

[0041] In one embodiment, the adjustment instruction may include: a frequency modulation type and a target frequency modulation amplitude. The frequency modulation type is either up-frequency or down-frequency, and the target frequency modulation amplitude is the amount by which the processor adjusts from its initial operating frequency to a target operating frequency.

[0042] The initial operating frequency is the processor's current operating frequency at the moment the adjustment and governance are received.

[0043] For example, when the adjustment instruction is received, the processor's current operating frequency is 1000MHz. During the frequency adjustment process, the processor's operating frequency is increased sequentially from 1000 MHz to 1200 MHz, and then to 1400 MHz. In this example, the frequency adjustment type is upsampling, 1000 MHz is the initial operating frequency, 1400 MHz is the target operating frequency, and (1400-1000) MHz is the target frequency adjustment range.

[0044] For example, when the adjustment command is received, the processor's current operating frequency is 1400MHz. During the frequency adjustment process, the processor's operating frequency decreases sequentially from 1400 MHz to 1200 MHz, and then to 1000 MHz. In this example, the frequency adjustment type is down-regulation, 1400 MHz is the initial operating frequency, 1000 MHz is the target operating frequency, and (1400-1000) MHz is the target frequency adjustment range.

[0045] In one embodiment, the adjustment instruction may directly include the target operating frequency required by the processor, and the frequency modulation and voltage regulation module can calculate the frequency modulation type and the target frequency modulation amplitude. For example, if the received target frequency modulation amplitude is 1400 MHz and the current operating frequency of the processor is 1000 MHz, then the frequency modulation type can be determined to be up-modulation, and the target frequency modulation amplitude is 400 MHz.

[0046] S120, while the phase-locked loop is running, adjusts the frequency of the phase-locked loop output clock signal to the target frequency.

[0047] In this embodiment of the application, the target frequency is the clock frequency that enables the processor to operate at the target operating frequency.

[0048] The processor operates according to the frequency of the clock signal. Generally, the processor's operating frequency is equal to the frequency of the clock signal, i.e., a 1:1 relationship. In some processors, it may be other ratios, which are not limited here.

[0049] Therefore, the frequency of the clock signal can be used to characterize the processor's operating frequency. When the frequency of the phase-locked loop (PLL) output clock signal is adjusted to the target frequency, the processor will operate at the target frequency. When the target frequency is the clock frequency that makes the processor operate at the target frequency, the processor will operate at the target frequency. Therefore, the processor's operating voltage and the frequency of the PLL output clock signal are, to a certain extent, the same.

[0050] The existing frequency modulation process typically includes: switching the processor's clock source from the phase-locked loop (PLL) to the reference clock, disabling the PLL, adjusting the disabled PLL, enabling the PLL until the clock signal output by the PLL is stable, and then switching the processor's clock source back from the reference clock to the PLL to complete the frequency modulation.

[0051] In the embodiments of this application, it is not necessary to switch the processor's clock source from the phase-locked loop (PLL) to a reference clock, nor is it necessary to disable the PLL. Instead, the frequency is adjusted directly during PLL operation. Compared to existing methods, this approach avoids using a reference clock during frequency adjustment. Reference clocks are typically low-frequency clocks, such as 25MHz, while the clock signal provided by the PLL used by the processor is a high-frequency clock, allowing the operating frequency to be stabilized at a higher value, such as 500MHz or 1000MHz. If a reference clock is used as the clock source, the processor's operating frequency will be significantly reduced, thus failing to meet operational requirements.

[0052] Meanwhile, during the process of switching the clock source from the reference clock to the phase-locked loop (PLL) and back to the reference clock, there may be a short period of zero clock. If tasks are assigned or instructions are executed during this period, it may cause the processor to malfunction.

[0053] In the embodiments of this application, when frequency modulation is performed, the phase-locked loop in the running state is directly adjusted. As a result, the phase-locked loop will output a clock signal at least at the frequency before adjustment, and the processor can maintain a high operating frequency. This can effectively reduce or even avoid processor abnormalities caused by the decrease in operating frequency during frequency modulation.

[0054] One reason why the phase-locked loop (PLL) is disabled in current frequency modulation processes is that if the PLL's single frequency adjustment amplitude is too large during the adjustment of the PLL's output clock signal frequency, the PLL may not be able to quickly find the correct control voltage to stabilize the new frequency, resulting in PLL lockout. The specific reasons can be found in the principles of PLLs, which will not be elaborated here. Therefore, current frequency modulation processes adjust the PLL even when it is disabled to avoid abnormal or unstable clock signals output by the PLL.

[0055] Based on this, in the embodiments of the application, adjusting the frequency of the phase-locked loop output clock signal to the target frequency may include: The number of frequency modulations and the amplitude of the last frequency modulation are determined based on the preset step size and the target frequency modulation amplitude. Perform the first process M times or less: adjust the operating voltage and the phase-locked loop based on the frequency modulation type and preset step size; After performing the first process M times, the following second process is performed: based on the frequency modulation type, the amplitude of the last frequency modulation, the operating voltage and the phase-locked loop are adjusted so that the frequency of the phase-locked loop output clock signal is the target frequency.

[0056] The preset step size is the preset frequency amplitude for adjusting the working frequency in a single operation.

[0057] In the embodiments of this application, the adjustment of the phase-locked loop output clock signal is performed in multiple steps. This effectively avoids excessive adjustment in a single step and reduces the likelihood of the phase-locked loop losing lock.

[0058] In the embodiments of this application, the preset step size is smaller than the minimum frequency change amplitude at which the phase-locked loop (PLL) loses lock. For example, if the PLL loses lock when the frequency modulation amplitude exceeds 300MHz in a single operation, the minimum frequency change amplitude is 300MHz, and the preset step size must be less than 300MHz. For example, it can be 100MHz, 150MHz, 200MHz, etc.

[0059] In the embodiments of this application, the minimum frequency change amplitude at which the phase-locked loop (PLL) loses lock can be obtained through testing during the design phase. For example, the frequency of the PLL output clock signal is adjusted multiple times, with each adjustment using a different frequency and the frequency used increasing progressively. After each frequency adjustment, the PLL output is allowed to stabilize until the PLL output clock signal becomes unstable. Then, the frequency used in this adjustment is determined to be the minimum frequency change amplitude at which the PLL loses lock.

[0060] In the embodiments of this application, the relationship between the preset step size, the target frequency modulation amplitude, the number of frequency modulations and the amplitude of the last frequency modulation satisfies: X = M × a + Y, where X is the target frequency modulation amplitude, Y is the amplitude of the last frequency modulation, a is the preset step size, Y is less than a, the number of frequency modulations is M + N times, M is equal to 0 or is an integer greater than 0; when Y is 0, N is 0, and when Y is not 0, N is 1.

[0061] In the embodiments of this application, both M and N can be equal to 0. That is, if the single frequency modulation amplitude is small, less than the preset step size, then M is 0, Y is greater than 0, and N is equal to 1. In this case, the first process can be skipped, and only the second process is performed once. Also, if the target frequency modulation amplitude can be divided evenly by the preset step size, then Y=0 and N is equal to 0. In this case, the second process can be skipped.

[0062] For example, if the preset step size is 200, the relationship can be expressed as X = M × 200 + Y. If the target frequency modulation amplitude X is 500, then the value of M is equal to 2, Y is equal to 100, and N is equal to 1. Accordingly, in this example, when performing frequency and voltage modulation, the frequency amplitude is first adjusted twice by 200, then adjusted once by 100, adjusting the clock signal frequency output by the phase-locked loop three times, thereby adjusting the processor's operating frequency from the initial operating frequency to the target operating frequency in three separate adjustments.

[0063] For example, if the target frequency modulation amplitude X is 400, then the value of M is 2, Y is 0, and N is 0. Accordingly, in this example, only the first process needs to be performed twice, that is, two adjustments of frequency amplitude of 200 are required.

[0064] For example, if the target frequency modulation amplitude X is 100, then the value of M is 0, Y is 100, and N is 1. Accordingly, in this example, only one second process is needed, that is, one adjustment of the frequency amplitude to 100.

[0065] In some embodiments of this application, adjusting the phase-locked loop (PLL) based on the frequency modulation type and the preset step size includes: adjusting the feedback division ratio of the PLL based on the frequency modulation type so that the frequency change amplitude of the clock signal output by the PLL corresponds to the preset step size; Adjusting the phase-locked loop (PLL) based on the frequency modulation type and the amplitude of the last frequency modulation includes: adjusting the feedback division ratio of the PLL based on the frequency modulation type so that the frequency change amplitude of the clock signal output by the PLL corresponds to the amplitude of the last frequency modulation.

[0066] In a phase-locked loop (PLL), the feedback division ratio is positively correlated with the frequency of the output clock signal. That is, as the feedback division ratio increases, the frequency of the output clock signal also increases; conversely, as the feedback division ratio decreases, the frequency of the output clock signal decreases. Therefore, in the embodiments of this application, the frequency of the output clock signal can be adjusted by adjusting the feedback division ratio of the PLL.

[0067] Accordingly, in the embodiments of this application, the frequency modulation type is used to determine the adjustment method of the feedback division ratio. If the frequency modulation type is frequency up, the feedback division ratio of the phase-locked loop is increased so that the frequency of the phase-locked loop output clock signal increases; if the frequency modulation type is frequency down, the feedback division ratio of the phase-locked loop is decreased so that the frequency of the phase-locked loop output clock signal decreases.

[0068] In this embodiment of the application, the frequency of the clock signal output by the phase-locked loop is adjusted to the target frequency in multiple steps. Therefore, the adjustment range of the feedback allocation ratio should correspond to the frequency change range required for this adjustment each time.

[0069] In other words, during the first process (M iterations), the adjustment value of the feedback division ratio must ensure that the frequency change amplitude of the clock signal output by the phase-locked loop corresponds to the preset step size. During the final adjustment, i.e., during the second process, the adjustment value of the feedback division ratio must ensure that the frequency change amplitude of the clock signal output by the phase-locked loop corresponds to the final frequency modulation amplitude.

[0070] The relationship between the feedback division ratio and the output clock signal frequency may differ in phase-locked loops (PLLs) with different structures; therefore, no specific numerical value is provided here. In addition, the PLL output clock signal frequency can be adjusted by modifying the input division and post-division, and these adjustments are not limited here.

[0071] In this context, the processor requires an operating voltage corresponding to its operating frequency to function properly. Therefore, during frequency modulation, the operating voltage also needs to be adjusted. Voltage regulation can refer to sending a voltage regulation command to the processor's power supply module, which then controls the voltage adjustment. For details, please refer to existing technologies; further explanation is omitted here.

[0072] The timing sequence of adjusting voltage and adjusting operating frequency varies depending on the type of frequency modulation.

[0073] For frequency upscaling, the current operating voltage cannot meet the voltage requirements of the upscaled operating frequency because the frequency increases. Therefore, for frequency upscaling, the operating voltage needs to be increased first, and then the operating frequency needs to be increased.

[0074] Accordingly, for the frequency upscaling operation, the first process includes: first adjusting the operating voltage based on the frequency modulation type and a preset step size, and then adjusting the phase-locked loop (PLL) based on the frequency modulation type and a preset step size. The second process includes: first adjusting the operating voltage based on the frequency modulation type and the amplitude of the last frequency modulation, and then adjusting the PLL based on the frequency modulation type and the amplitude of the last frequency modulation.

[0075] For frequency reduction, the current operating voltage will be higher than the voltage requirement of the operating frequency after frequency reduction. Therefore, for frequency reduction, the operating frequency can be reduced first, and then the operating voltage can be reduced.

[0076] Accordingly, for frequency reduction operation, the first process includes: first adjusting the phase-locked loop (PLL) based on the frequency modulation type and a preset step size, and then adjusting the operating voltage based on the frequency modulation type and a preset step size. The second process includes: adjusting the PLL based on the frequency modulation type and the amplitude of the last frequency modulation, and then adjusting the operating voltage based on the frequency modulation type and the amplitude of the last frequency modulation.

[0077] After the operating voltage is adjusted, it will fluctuate for a period of time before stabilizing. During this period, if the frequency of the clock signal output by the phase-locked loop is directly adjusted, the adjusted operating frequency of the processor may not match the operating voltage. For example, if the operating voltage fluctuates to a small value, it may be lower than the voltage required for the adjusted operating frequency of the processor. In this case, the processor will malfunction.

[0078] Therefore, in some embodiments of this application, if the frequency modulation type in the adjustment instruction is frequency up, the first process may further include: after adjusting the operating voltage based on the frequency modulation type and a preset step size, and before adjusting the phase-locked loop based on the frequency modulation type and a preset step size, waiting for a first preset delay. The second process further includes: after adjusting the operating voltage based on the frequency modulation type and the last frequency modulation amplitude, and before adjusting the phase-locked loop based on the frequency modulation type and the last frequency modulation amplitude, waiting for a first preset delay.

[0079] The first preset delay is the preset time required for the operating voltage to stabilize after adjustment. In embodiments of this application, the first preset delay may be greater than or equal to the time required for the operating voltage to stabilize after adjustment.

[0080] In this embodiment, after each adjustment of the operating voltage, the operating frequency is not adjusted immediately, but a first preset delay is waited for the operating voltage to stabilize. This can effectively reduce or avoid the possibility of processor malfunctions due to the operating voltage fluctuation failing to meet the required voltage for the operating frequency during frequency and voltage adjustment.

[0081] The inability of the operating voltage to meet the voltage required for the operating frequency usually occurs during the boost and frequency increase process. However, during the frequency and voltage decrease process, the voltage needs to be reduced again before the frequency is reduced. Therefore, this problem does not exist in the first and second processes in a single operation.

[0082] For two consecutive first processes—that is, after the first first process reduces the voltage, the second first process reduces the frequency—the operating voltage will remain at a relatively high level during this period, and there will be no related problems. For example, after the first first process, the operating frequency is 1400MHz and the operating voltage is 910mV. In the second first process, the operating frequency is first reduced to 1200MHz, and the corresponding operating voltage for 1200MHz is 830mV. Even if the operating voltage fluctuates during the first first process, it will not fall below 830mV. Therefore, during the frequency reduction process, there is no need to wait for the first preset delay.

[0083] That is, if the frequency modulation type in the adjustment instruction is frequency reduction, the first process may include: after adjusting the phase-locked loop based on the frequency modulation type and a preset step size, adjusting the operating voltage based on the frequency modulation type and a preset step size; wherein, it is allowed to perform the next first process or the second process when the operating voltage is not stable.

[0084] Another reason for disabling phase-locked loops (PLLs) in the current frequency modulation process is that after adjusting the frequency, the PLL will experience a fluctuation (or oscillation) process. It cannot immediately lock onto the target frequency and output the clock signal of the target frequency. The PLL will repeatedly try to adjust the frequency of the output clock signal, resulting in oscillation or fluctuation. During the fluctuation, the frequency of the PLL's output clock signal may exceed the target frequency, which will cause the processor's operating frequency to exceed the target operating frequency. At this time, the processor's operating voltage drop cannot meet the requirements, thus causing the processor to malfunction.

[0085] To address this issue, in embodiments of this application, the protection voltage band can be obtained before adjusting the operating voltage and phase-locked loop based on the frequency modulation type and preset step size; Furthermore, adjusting the operating voltage based on the frequency modulation type and preset step size may include: adjusting the operating voltage based on the frequency modulation type, protection voltage band, and preset step size; Furthermore, adjusting the operating voltage based on the frequency modulation type and the amplitude of the last frequency modulation can include: adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the amplitude of the last frequency modulation. Finally, the second process and the Mth first process when N is 0 also include: canceling the protection voltage band on the working voltage.

[0086] In the embodiments of this application, the protection voltage band is the voltage value corresponding to the frequency fluctuation of the clock signal output after the preset phase-locked loop is adjusted. The protection voltage band is greater than the maximum value of the frequency fluctuation.

[0087] The frequency fluctuation range is related to the adjustment range of a single frequency. Taking a preset step size of 200MHz as an example, the peak value of a single fluctuation is usually no more than 100MHz. Correspondingly, if the voltage required for 100MHz is assumed to be 50mV, the protection voltage band can be set to 50mV or greater than 50mV.

[0088] In the embodiments of this application, the maximum amplitude of a single frequency modulation is a preset step size. Therefore, in the embodiments of this application, the protection voltage band can be greater than the voltage value corresponding to the difference between the peak frequency fluctuation of the clock signal output by the phase-locked loop and the adjusted operating frequency after the phase-locked loop adjusts the voltage corresponding to the preset step size.

[0089] For example, if the operating frequency before frequency modulation is 500MHz and the preset step size is 200MHz, the adjusted operating frequency should be 700MHz. The peak frequency fluctuation of the clock signal output by the phase-locked loop is 800MHz. The difference between the peak frequency fluctuation of the clock signal output by the phase-locked loop and the adjusted operating frequency is 100MHz. Therefore, the protection voltage band needs to be greater than the voltage corresponding to 100MHz.

[0090] The methods for adjusting the voltage during frequency upscaling and downscaling differ, and in the embodiments of this application, the methods for setting and canceling the protection voltage band also differ.

[0091] In one embodiment, the frequency modulation type in the adjustment instruction is up-frequency; adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the preset step size may include: adjusting the operating voltage to be the sum of the current operating voltage, the voltage corresponding to the preset step size, and the protection voltage band.

[0092] Accordingly, the operating voltage is adjusted based on the frequency modulation type, protection voltage band, and the amplitude of the last frequency modulation, including adjusting the operating voltage to be the sum of the current operating voltage, the voltage corresponding to the amplitude of the last frequency modulation, and the protection voltage band.

[0093] To remove the protection voltage band from the operating voltage, the following steps are taken: subtract the voltage value corresponding to the protection voltage band from the adjusted operating voltage.

[0094] When increasing the frequency, the voltage is increased first. Therefore, in the embodiments of this application, a protection voltage band can be set at the same time when increasing the voltage, so that the working voltage is adjusted to the sum of the current working voltage, the voltage corresponding to the preset step size / the voltage corresponding to the last frequency modulation amplitude, and the protection voltage band. Thus, the protection voltage band can be set for protection before frequency modulation.

[0095] In the voltage boosting process corresponding to frequency increase, a voltage protection band is added to the voltage during the first step. If N is 1, then in the second to Mth steps of the first and second processes, since the voltage protection band was already added in the first step, no additional voltage protection band is needed in subsequent steps. Instead, the voltage protection band is removed from the operating voltage after the voltage adjustment is completed in the second step. If N is 0, then no voltage protection band is needed in the second to Mth steps of the first process, and the voltage protection band is removed after the voltage adjustment is completed in the Mth step of the first process.

[0096] For example, the initial operating frequency is 1000MHz, corresponding to an operating voltage of 750mV. The target operating frequency is 1400MHz, corresponding to an operating voltage of 910mV. The preset step size is 200MHz, with 200MHz corresponding to a voltage of 80mV. Using this as an example: In the first process, the operating voltage is first increased from 750mV to 880mV, where 880mV = 750mV + 50mV + 80mV. After the voltage stabilizes, the phase-locked loop is adjusted to adjust the operating frequency to 1200MHz, thus completing the first process.

[0097] Next, the second first process is carried out. First, the working voltage is increased from 880mV to 960mV, where 960mV = (750mV + 50mV + 80mV) + 80mV. After the voltage stabilizes, the phase-locked loop is adjusted to adjust the working frequency to 1400MHz, thus completing the second first process.

[0098] Since Y=0, the second process can be omitted.

[0099] Finally, the protection voltage band on the operating voltage can be removed, that is, the operating voltage can be adjusted from 960mV to 910mV to complete the frequency and voltage regulation process.

[0100] Furthermore, it should be noted that in the embodiments of this application, the operating voltage corresponding to the preset step size is not necessarily a fixed value. For example, the operating voltage corresponding to a working frequency of 1000 MHz is 750 mV, the operating voltage corresponding to a working frequency of 1100 MHz is 780 mV, the operating voltage corresponding to a working frequency of 1200 MHz is 830 mV, and the operating voltage corresponding to a working frequency of 1300 MHz is 860 mV. It can be seen that when the operating frequency increases from 1000 MHz to 1100 MHz, the operating voltage increases by 30 mV, while when it increases from 1100 MHz to 1200 MHz, the operating voltage increases by 50 mV. Therefore, the operating voltage corresponding to the preset step size is not necessarily a uniform value.

[0101] In some embodiments of this application, a table or calculation relationship between operating frequency and operating voltage can be preset, and the operating voltage corresponding to the operating frequency to be adjusted can be determined by looking up the table or calculating the relationship.

[0102] Similarly, in some embodiments of this application, before removing the protection voltage band on the operating voltage, a second preset duration can be waited for. The second preset duration is the waiting time required for the phase-locked loop to output a stable frequency clock signal after adjusting the frequency. For example, the second preset duration is 100µs, 200µs, etc. By waiting for the operating frequency to stabilize, the problem of the operating voltage not meeting the requirements when the operating frequency fluctuates is avoided.

[0103] For frequency reduction, i.e., when the frequency modulation type in the adjustment command is frequency reduction, the working voltage is adjusted based on the frequency modulation type, the protection voltage band, and the preset step size. This can include the sum of the working voltage corresponding to the intermediate working frequency and the protection voltage band, wherein the intermediate working frequency is the frequency after adjusting the preset step size.

[0104] If N is 1, meaning the second process needs to be executed, then canceling the protection voltage band on the operating voltage can include: when adjusting the operating voltage based on the frequency modulation type, protection voltage band, and the last frequency modulation amplitude, adjusting the operating voltage to the voltage corresponding to the target operating frequency, where the voltage corresponding to the target operating frequency is the current operating voltage minus the difference between the voltage corresponding to the last frequency modulation amplitude and the protection voltage band. In other words, during the voltage reduction process in the second process, based on the current operating voltage, both the voltage protection band and the voltage corresponding to the last frequency modulation amplitude are simultaneously reduced.

[0105] If N is 0, meaning the second process is not required, then canceling the protection voltage band on the operating voltage can include: during the Mth adjustment of the operating voltage based on the protection voltage band of the frequency modulation type and a preset step size, adjusting the operating voltage to the voltage corresponding to the target operating frequency, where the voltage corresponding to the target operating frequency is the current operating voltage minus the difference between the voltage corresponding to the preset step size and the protection voltage band. That is, during the final (Mth) voltage reduction process of the first process, both the voltage protection band and the voltage corresponding to the preset step size are simultaneously reduced based on the current operating voltage.

[0106] For frequency reduction, since frequency adjustment is performed before voltage adjustment, a protection voltage band needs to be added to the current operating voltage before adjusting the frequency to avoid insufficient operating voltage due to frequency fluctuations. Then, during the final frequency adjustment, the voltage is directly adjusted to the voltage corresponding to the target operating frequency, that is, the voltage corresponding to the protection voltage band is further reduced on top of the original preset step size or the voltage corresponding to the last frequency adjustment amplitude.

[0107] For example, the initial operating frequency is 1400MHz, corresponding to an operating voltage of 910mV. The target operating frequency is 1000MHz, corresponding to an operating voltage of 750mV. The preset step size is 200MHz, with 200MHz corresponding to a voltage of 80mV. Using this as an example: In the first process, the operating voltage is first increased by the protection voltage band, so that the voltage rises from 910mV to 960mV, where 960mV = 910mV + 50mV. After the voltage stabilizes, the phase-locked loop is adjusted to reduce the operating frequency to 1200MHz, thereby reducing the voltage from 960mV to 880mV, i.e., 880mV = 910mV + 50mV - 80mV, thus completing the first process.

[0108] Next, the second first process is performed, adjusting the phase-locked loop to adjust the operating frequency to 1000MHz. Since Y=0, the second process can be skipped. At this point, the operating voltage can be directly adjusted to the voltage corresponding to the target operating frequency of 1000MHz, i.e., reduced from 880mV to 750mV. This is after subtracting the voltage of the protection voltage band: 750mV = 910mV + 50mV - 80mV - 80mV - 50mV. After the voltage stabilizes, the second first process is completed, thus completing the entire frequency and voltage regulation process.

[0109] Similarly, in the actual implementation scenario of this application, the working voltage corresponding to the preset step size is not necessarily a uniform fixed value, and the corresponding voltage can be calculated by looking up a table or by calculating the relationship.

[0110] The above-described solutions can address two potential problems that may arise from frequency modulation during phase-locked loop (PLL) operation: firstly, frequency modulation with a preset step size can resolve the issue of PLL loss of lockout due to excessive frequency modulation; secondly, a protection voltage band can address the problem of operating voltage mismatch caused by frequency fluctuations after frequency modulation.

[0111] For ease of understanding, the process of adjusting the operating frequency is explained here using both up-frequency and down-frequency methods. In this example, after receiving the adjustment command, the target frequency modulation amplitude is determined to be 500MHz. If the preset step size is 200MHz, then M=2, Y=100, N=1, and the number of frequency modulations is M+N=2+1=3 times. This requires two first-process adjustments, one second-process adjustment, and the final frequency modulation amplitude Y is 100MHz. The operating voltage corresponding to each 100MHz is 40mV, the initial operating voltage is V, the initial operating frequency is F, and the protection voltage band is 50mV. In the actual implementation scenario of this application, the operating voltage corresponding to the preset step size is not necessarily a uniform fixed value; the corresponding voltage can be calculated by looking up a table or using a calculation relationship. This example is provided for ease of understanding only and should not be construed as a limitation of this application.

[0112] Please see Figure 2 , Figure 2 This is a schematic diagram of the frequency upsampling process provided in an embodiment of this application.

[0113] After calculating the number of frequency modulations and the amplitude of the last frequency modulation, first determine whether M is greater than 0. If it is greater than 0, then enter the first process and execute the first process M times. Otherwise, if M equals 0, then determine whether N equals 1. If N equals 1, then execute the second process. Otherwise, if N=0, then end directly.

[0114] In this embodiment, M=2 and N=1. Therefore, the first process needs to be performed twice, followed by the second process. Since it is a frequency increase, the voltage needs to be increased first. The preset step size is 200 MHz, so the voltage is increased by 80mV first, while a protection voltage band of 50mV is set. The increased voltage is V + 80mV + 50mV. Then, wait for the first preset delay to allow the operating voltage to stabilize.

[0115] Then, the feedback division ratio of the phase-locked loop is increased so that the frequency of the output clock signal of the phase-locked loop increases from F to F+200MHz.

[0116] After the clock signal output by the phase-locked loop is stabilized, M = M-1 = 2-1 = 1, that is, the new M is 1. Then, it is determined whether M is greater than 0, that is, whether the first process has been executed M times. Since the first process has not been completed twice, the second first process is performed.

[0117] The second first process is similar to the above, except that the voltage corresponding to the preset step size needs to be re-determined through methods such as table lookup. If it is still 80mV, the increased voltage will be V + 80mV + 80mV + 50mV. Then, wait for the first preset delay to allow the operating voltage to stabilize. Next, increase the feedback division ratio of the phase-locked loop (PLL) so that the frequency of the PLL output clock signal increases from F to F + 200MHz + 200MHz. In some embodiments, the voltage corresponding to the preset step size may not be fixed at 80mV; it may be 50mV or other values.

[0118] After the clock signal output by the phase-locked loop is determined to be stable, M = M-1 = 1-1 = 0, and the new M is 0. It is then determined whether M is greater than 0. If it is not greater than 0, it indicates that the first process has been completed.

[0119] At this point, it can be determined whether N equals 1. If N equals 1, the second process is executed, that is, the increased voltage is adjusted to V + 80mV + 80mV + 40mV + 50mV. Then, the first preset delay is waited for the operating voltage to stabilize. Next, the feedback division ratio of the phase-locked loop (PLL) is increased so that the frequency of the PLL output clock signal increases from F to F + 200MHz + 200MHz + 100MHz, and the process waits to confirm that the PLL output clock signal is stable. Similarly, in some embodiments, the voltage corresponding to 100MHz may not be fixed at 40mV, but may be other values.

[0120] When N equals 0, or after the second process is completed, wait for the second preset delay and cancel the protection voltage band, so that the working voltage is: V+80mv+80mv+40mv, and complete the frequency and voltage regulation process.

[0121] Please see Figure 3 , Figure 3 This is a schematic diagram of a frequency reduction process provided in an embodiment of this application.

[0122] During frequency reduction, after calculating the number of frequency adjustments and the amplitude of the last frequency adjustment, it first checks whether M is greater than 0. If it is greater than 0, it enters the first process and executes the first process M times. Otherwise, if M equals 0, it checks whether N equals 1. If N equals 1, it executes the second process. Otherwise, if N=0, it ends directly.

[0123] Similarly, in this embodiment, M=2 and N=1. Therefore, the first process needs to be performed twice, followed by the second process. Entering the first process, since it involves frequency reduction, which involves reducing the frequency first and then the voltage, a protection voltage band needs to be set before starting the frequency reduction. The protection voltage band is set to 50mV, resulting in a voltage increase of V+50mV. Then, without waiting, the frequency of the clock signal output by the phase-locked loop is directly reduced, with a preset step size of 200MHz. The adjusted operating frequency is F-200MHz. Again, without waiting for the frequency to stabilize, the operating voltage is adjusted to the sum of the voltage corresponding to F-200MHz and the voltage protection band, reducing the voltage by 80mV. The reduced voltage is V-80mV +50mV.

[0124] Then, when the first process is completed, M=M-1=2-1=1, the new M is 1, which is greater than 0. Then the second process needs to be performed, which includes: reducing the frequency of the clock signal output by the phase-locked loop. The preset step size is 200MHz, so the adjusted operating frequency is F-200MHz-200MHz. The operating voltage is adjusted to the sum of the voltage corresponding to F-200MHz-200MHz and the voltage protection band, which can reduce the voltage by 80mV. The reduced voltage is V-80 mv-80 mv +50mv.

[0125] After reducing the voltage, since Y=100, N is not equal to 0. Therefore, the voltage protection band is not canceled here, and the subsequent process continues. After the second first process is completed, M=M-1=1-1=0, and Y=100, which makes N equal to 1. Therefore, the second process begins, reducing the frequency of the clock signal output by the phase-locked loop. The final frequency modulation amplitude is 100MHz, so the adjusted operating frequency is F-200MHz-200MHz-100MHz. The operating voltage is adjusted to the voltage corresponding to the target operating frequency, i.e., the voltage corresponding to F-500MHz, where F-500MHz=F-200MHz-200MHz-100MHz. Since the frequency modulation ends after the second process, the protection voltage band can be canceled simultaneously in the second process, so that the voltage drops directly from V-80 mv-80 mv +50mv to V-80 mv-80 mv -40mv.

[0126] Similarly, in this frequency reduction embodiment, the voltage corresponding to the preset step size and the last frequency modulation amplitude is not necessarily a fixed value, but is calculated by looking up a table or calculating a relationship. The configuration method and values ​​may be different for different processors. The above is only an example and should not be construed as a limitation of this application.

[0127] The various embodiments provided in this application can be combined arbitrarily. The above description is merely an example and should not be construed as a limitation of this application.

[0128] Based on the same inventive concept, embodiments of this application also provide a frequency and voltage modulation module, which can implement the operating frequency adjustment method provided in the foregoing embodiments of this application. This frequency and voltage modulation module can be an MCU, a processor's power management module, etc.

[0129] Based on the same inventive concept, this application provides a processor 400, which may be a GPGPU, GPU, CPU, etc., and is not limited thereto.

[0130] Please see Figure 4 , Figure 4 This is a schematic diagram of a processor 400 provided in an embodiment of this application. The processor 400 provided in this embodiment includes: a working module 410, a phase-locked loop 420, and a frequency and voltage modulation module 430.

[0131] The working module 410 is the main working module of the processor, and the working module 410 may include the processing core, video memory and various computing units.

[0132] Phase-locked loop 420 is used to provide a clock signal for the operation of working module 410.

[0133] The frequency and voltage regulation module 430 is used to adjust the frequency of the phase-locked loop output clock signal and the operating voltage of the processor. Specifically, it can be implemented as various power management modules and power chips.

[0134] In the embodiments of this application, the frequency modulation and voltage regulation module 430 is used to execute the operating frequency adjustment method provided in the foregoing embodiments.

[0135] Based on the same inventive concept, this application also provides an electronic device, which may include the processor 400 provided in the foregoing embodiments.

[0136] The electronic device includes, but is not limited to, computers, servers, industrial control computers, and other devices that include processors, and is not restricted in this regard.

[0137] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0138] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for adjusting operating frequency, characterized in that, The method for adjusting the operating frequency is applied to a frequency modulation and voltage regulation module, which is connected to a processor, the processor including a phase-locked loop. Receives an adjustment instruction for the operating frequency; the adjustment instruction is used to indicate the target operating frequency required by the processor; When the phase-locked loop is running, the frequency of the phase-locked loop output clock signal is adjusted to the target frequency; the target frequency is the clock frequency that makes the processor work at the target operating frequency.

2. The operating frequency adjustment method according to claim 1, characterized in that, The adjustment instruction includes a frequency modulation type and a target frequency modulation amplitude; the frequency modulation type is either frequency increase or frequency decrease, and the target frequency modulation amplitude is the change in the processor's frequency from its initial operating frequency to the target operating frequency. Adjusting the frequency of the phase-locked loop output clock signal to the target frequency includes: The number of frequency modulations and the amplitude of the last frequency modulation are determined based on the preset step size and the target frequency modulation amplitude; the preset step size is the preset frequency amplitude for a single adjustment of the working frequency. The relationship between the preset step size, the target frequency modulation amplitude, the number of frequency modulations, and the last frequency modulation amplitude satisfies: X = M × a + Y, where X is the target frequency modulation amplitude, Y is the last frequency modulation amplitude, a is the preset step size, Y is less than a, the number of frequency modulations is M + N times, N is 0 when Y is 0, N is 1 when Y is not 0, and M is equal to 0 or is an integer greater than 0. Execute the first process M times or less: Based on the frequency modulation type, the preset step size adjustment of the operating voltage, and the phase-locked loop; After executing the first process M times, execute the second process N times or less: The operating voltage and the phase-locked loop are adjusted based on the frequency modulation type and the amplitude of the last frequency modulation, so that the frequency of the clock signal output by the phase-locked loop is the target frequency.

3. The operating frequency adjustment method according to claim 2, characterized in that, Adjusting the phase-locked loop based on the frequency modulation type and the preset step size includes: The feedback division ratio of the phase-locked loop is adjusted based on the frequency modulation type so that the frequency change amplitude of the clock signal output by the phase-locked loop corresponds to the preset step size; Adjusting the phase-locked loop based on the frequency modulation type and the amplitude of the last frequency modulation includes: The feedback division ratio of the phase-locked loop is adjusted based on the frequency modulation type so that the frequency change amplitude of the clock signal output by the phase-locked loop corresponds to the amplitude of the last frequency modulation. Wherein, if the frequency modulation type is frequency up, the feedback division ratio of the phase-locked loop is increased to increase the frequency of the phase-locked loop output clock signal; if the frequency modulation type is frequency down, the feedback division ratio of the phase-locked loop is decreased to decrease the frequency of the phase-locked loop output clock signal.

4. The operating frequency adjustment method according to claim 2, characterized in that, The frequency modulation type in the adjustment instruction is up-frequency; The first process further includes: After adjusting the operating voltage based on the frequency modulation type and the preset step size, and before adjusting the phase-locked loop based on the frequency modulation type and the preset step size, a first preset delay is waited for; the first preset delay is a preset time required for the operating voltage to stabilize after the operating voltage is adjusted. Furthermore, the second process also includes: After adjusting the operating voltage based on the frequency modulation type and the last frequency modulation amplitude, and before adjusting the phase-locked loop based on the frequency modulation type and the last frequency modulation amplitude, wait for the first preset delay.

5. The operating frequency adjustment method according to claim 4, characterized in that, The frequency modulation type in the adjustment instruction is frequency reduction; The first process includes: After adjusting the phase-locked loop based on the frequency modulation type and the preset step size, the operating voltage is adjusted based on the frequency modulation type and the preset step size; wherein, it is permissible to perform the first process or the second process again when the operating voltage is unstable.

6. The operating frequency adjustment method according to claim 2, characterized in that, Before adjusting the operating voltage and the phase-locked loop based on the frequency modulation type, the preset step size, and the phase-locked loop, the method further includes: Obtain the protection voltage band, which is a preset voltage value corresponding to the frequency fluctuation of the clock signal output by the phase-locked loop after adjustment; Adjusting the operating voltage based on the frequency modulation type and the preset step size includes: The operating voltage is adjusted based on the frequency modulation type, the protection voltage band, and the preset step size; And, adjusting the operating voltage based on the frequency modulation type and the amplitude of the last frequency modulation includes: The operating voltage is adjusted based on the frequency modulation type, the protection voltage band, and the last frequency modulation amplitude. The second process and the Mth first process when N is 0 further include: The protection voltage band is removed at the operating voltage.

7. The operating frequency adjustment method according to claim 6, characterized in that, Before canceling the protection voltage band at the operating voltage, the method further includes: Wait for a second preset time, which is the preset waiting time required for the phase-locked loop to output a stable frequency clock signal after adjusting the frequency.

8. The operating frequency adjustment method according to claim 6, characterized in that, The frequency modulation type in the adjustment command is up-frequency; The adjustment of the operating voltage based on the frequency modulation type, the protection voltage band, and the preset step size includes: The operating voltage is adjusted to be the sum of the current operating voltage, the voltage corresponding to the preset step size, and the protection voltage band. Accordingly, adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the last frequency modulation amplitude includes: The operating voltage is adjusted to be the sum of the current operating voltage, the voltage corresponding to the last frequency modulation amplitude, and the protection voltage band. The process of canceling the protection voltage band at the operating voltage includes: Based on the adjusted operating voltage, subtract the voltage value corresponding to the protection voltage band.

9. The operating frequency adjustment method according to claim 6, characterized in that, The frequency modulation type in the adjustment command is frequency reduction; the adjustment of the operating voltage based on the frequency modulation type, the protection voltage band, and the preset step size includes: The operating voltage is adjusted to be the sum of the operating voltage corresponding to the intermediate operating frequency and the protection voltage band; the intermediate operating frequency is the frequency after adjusting the preset step size. If N is 1, canceling the protection voltage band on the operating voltage includes: when adjusting the operating voltage based on the frequency modulation type, the protection voltage band, and the last frequency modulation amplitude, adjusting the operating voltage to the voltage corresponding to the target operating frequency; If N is 0, then the protection voltage band is canceled on the operating voltage, including: when the operating voltage is adjusted based on the frequency modulation type, the protection voltage band and the preset step size for the Mth time, the operating voltage is adjusted to the voltage corresponding to the target operating frequency.

10. The operating frequency adjustment method according to claim 6, characterized in that, The protection voltage band is greater than the voltage value corresponding to the difference between the peak frequency fluctuation of the clock signal output by the phase-locked loop and the adjusted operating frequency after the phase-locked loop adjusts the voltage corresponding to the preset step size.

11. The operating frequency adjustment method according to claim 2, characterized in that, The preset step size is less than the minimum frequency change amplitude at which the phase-locked loop loses its lock.

12. A processor, characterized in that, include: Working modules; A phase-locked loop, connected to the working module, is used to provide the working module with a clock signal corresponding to the working frequency; A frequency modulation and voltage regulation module, connected to the phase-locked loop, is used to perform the operating frequency adjustment method as described in any one of claims 1-11.

13. An electronic device, characterized in that, Includes the processor as described in claim 12.

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