Cache-based working frequency adjustment method, processor and electronic equipment

Abstract

The invention provides a cache-based working frequency adjustment method, a processor and electronic equipment, and relates to the field of integrated circuits. The cache-based working frequency adjustment method comprises the following steps: receiving an adjustment instruction for adjusting the working frequency of the processor; the cache is used for receiving an adjustment instruction sent by the processing core, forbidding the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction, and in the process of adjusting the phase-locked loop, the cache receives requests of the processing core and the connection architecture component and limits the requests to be sent to the memory controller so as to limit the processing core to call the memory. According to the method, the abnormity caused by too low working frequency due to clock source switching in the process of adjusting the working frequency of the processor can be reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more specifically, provides a cache-based operating frequency adjustment method, processor, and electronic device. Background Technology

[0002] Currently, DVFS (Dynamic Voltage and Frequency Scaling) technology can dynamically adjust the processor's operating frequency and power supply voltage according to the processor's real-time load, thereby reducing power consumption and improving processor performance.

[0003] The processor's core operates at a frequency controlled by a clock signal provided by a phase-locked loop (PLL). Therefore, adjusting the processor's operating frequency requires adjusting the PLL to change its output clock signal. Adjusting the PLL involves first switching the current clock source from the PLL to a reference clock, then disabling the PLL to adjust it while it's disabled. After adjustment, the clock source is switched back from the reference clock to the PLL. The reference clock is typically a low-frequency clock; for example, some reference clocks have a frequency of 25MHz. It's important to note that switching between the PLL and the reference clock can result in a brief period of zero clock signal.

[0004] If, during the process of adjusting the operating frequency, the upper-layer application sends a large number of tasks to the processor, and the processor's various modules may also be performing calculations, data transmissions, writes, and other operations, the processor's frequency may suddenly drop to a very low level or even to 0, which may cause abnormal problems such as system freeze, data backpressure, and data loss.

[0005] To address the aforementioned issues, some current solutions involve disabling the system clock input during frequency modulation and re-enabling it afterward. However, tasks cannot execute after the system clock input is disabled. Therefore, it is necessary to pre-determine appropriate shutdown procedures and control task pauses, which complicates frequency modulation and hinders timely frequency adjustment.

[0006] Furthermore, when the phase-locked loop (PLL) is disabled, changes in the processing core's frequency cause a drop in the processing core's operating voltage. Combined with application-induced voltage drops, this can lead to the processor's operating voltage falling outside its normal range, causing malfunctions. If the processor's operating voltage needs to be maintained, the voltage value must be increased, which will degrade processor performance. Summary of the Invention

[0007] In view of this, this application aims to provide a cache-based operating frequency adjustment method, processor, and electronic device to reduce the possibility of abnormal problems occurring during the processor's operating frequency adjustment process.

[0008] In a first aspect, embodiments of this application provide a cache-based operating frequency adjustment method for adjusting the operating frequency of a processor; the processor includes a processing core, a connectivity architecture component, a cache, a memory controller, and memory connected in sequence; the processor also includes a phase-locked loop (PLL) connected to the processing core; the PLL provides a clock signal to the processing core so that the processing core operates based on the clock signal; the cache-based operating frequency adjustment method includes: receiving an adjustment instruction to adjust the operating frequency of the processor; disabling the PLL and adjusting the PLL based on the adjustment instruction; during the adjustment of the PLL, the cache receives requests from the processing core and the connectivity architecture component and restricts the requests from being sent to the memory controller, thereby restricting the processing core from accessing the memory.

[0009] In this embodiment, during the process of disabling the processor's phase-locked loop (PLL) and adjusting the frequency, the cache can normally receive requests from the processing core and connectivity components. However, all requests are confined to the cache and cannot be sent to the memory controller. This prevents the processing core from accessing memory and thus from executing requests. Consequently, the processing core will not experience issues such as freezing, data backpressure, or data loss during request execution due to a low or zero operating frequency. Since all requests are temporarily stored in the cache, even if the current task is not completed, the requests in the cache can continue to be output and executed after the frequency adjustment is completed. Compared to the existing method of shutting down the system clock input, this application does not require pre-determining the PLL disabling time or pausing task distribution, effectively improving frequency adjustment efficiency and reducing its complexity. In the existing method of directly disabling the PLL and switching to the reference clock, there will be a brief period of zero frequency, which will cause a drop in the processing core's operating voltage. Combined with the application-induced voltage drop, the two factors may cause the processor's operating voltage to deviate from the normal range. In this application, since the request is temporarily stored in the cache, the processing core cannot call memory to execute. As a result, the processing core cannot perform the application's function, and the application will not cause a drop in the processing core's operating voltage. That is, at this time, there will only be a drop in operating voltage caused by adjusting the frequency, and this drop in operating voltage is less than the drop in operating voltage caused by the application. Therefore, storing the request temporarily in the cache effectively reduces the magnitude of the drop in operating voltage and effectively reduces or avoids anomalies caused by the drop in operating voltage.

[0010] In one embodiment, the cache and the memory controller are configured to control request transmission based on a preset credit mechanism; the credit mechanism includes: the cache allowing request transmission to the memory controller when it has a credit value; before disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction, the method further includes: acquiring and saving the current configuration of the cache for the credit mechanism; controlling the cache to disable the credit mechanism; after the credit mechanism is disabled, the cache is restricted from transmitting requests to the memory controller; and after disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction, the method further includes: restoring the cache's credit mechanism to the current configuration.

[0011] In this embodiment, a credit mechanism is configured between the cache and the memory controller, allowing the cache to send requests to the memory controller only when it has a credit value. This effectively prevents the memory controller from losing data due to overload. Conversely, disabling the credit mechanism restricts the cache from sending requests to the memory controller. Therefore, during frequency adjustment, disabling the credit mechanism can limit the processing core's memory access, preventing anomalies caused by the processing core operating at low or zero frequencies. The credit mechanism configuration can be saved before frequency adjustment and restored afterward. This method is simple to implement and allows for rapid resumption of request transmission between the cache and the memory controller, reducing the time required for frequency adjustment.

[0012] In one embodiment, the processor further includes a credit register connected to the cache, the credit register being used to record the credit value of a request sent by the cache to the memory controller; obtaining and saving the current configuration of the cache for the credit mechanism includes: obtaining and saving the current credit value recorded in the credit register; controlling the cache to disable the credit mechanism includes: adjusting the credit value recorded in the credit register to 0; restoring the cache's credit mechanism to the current configuration includes: adjusting the value recorded in the credit register to the current credit value.

[0013] In this embodiment of the application, during the transmission of requests using the credit mechanism, the credit value is recorded through the credit register. During frequency modulation, only the credit value recorded in the credit register needs to be saved, and the recorded credit value needs to be restored after the frequency modulation is completed. This method realizes the saving and restoration of the credit mechanism in a simple and efficient way, which helps to reduce the time required for frequency modulation and improve the efficiency of frequency modulation.

[0014] In one embodiment, the cache includes a request buffer queue; after controlling the cache to disable the credit mechanism, the method further includes: continuing to receive requests sent by the processing core and the connectivity architecture components through the request buffer queue of the cache.

[0015] In this embodiment, the request buffer queue is a temporary storage area allocated within the cache, essentially a small cache used to store requests that the processing core has issued but not yet completed. By caching a certain number of requests, requests from the processing core and connection architecture components can be sent to the cache normally. After frequency modulation is completed, the cached requests can be output normally, allowing the processing core to continue executing its tasks. This eliminates the need to wait for the processing core to finish its current task before frequency modulation can be performed, reducing the time required for frequency modulation.

[0016] In one embodiment, after the method continues to receive requests sent by the processing core and the connection architecture component through the cached request buffer queue, the method further includes: instructing the processing core to pause request sending until the request buffer queue is full of requests.

[0017] In this embodiment of the application, after the request buffer queue is full of requests, the processing core is instructed to pause request sending, so as to reduce the occurrence of anomalies in the frequency adjustment process in the event that the cache cannot cache new requests and data is lost.

[0018] In one embodiment, the processor further includes a reference clock source connected to the processing core, the reference clock source being used to output a reference clock; the adjustment instruction includes a target operating frequency required by the processor; disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment instruction includes: after controlling the cache to disable the credit mechanism, switching the clock source of the processing core from the phase-locked loop to the reference clock source; disabling the phase-locked loop; waiting until the phase-locked loop is unlocked, adjusting the frequency of the clock signal output by the phase-locked loop to the target frequency; the target frequency is: a clock frequency that enables the processor to operate at the target operating frequency; enabling the phase-locked loop; waiting until the phase-locked loop is locked, switching the clock source of the processing core from the reference clock source back to the phase-locked loop.

[0019] In this embodiment of the application, during frequency modulation, the clock source is switched from the phase-locked loop to the reference clock source, which can avoid shutting down the clock input of the processing core. Therefore, it is not necessary to determine the clock input shutdown time before frequency modulation, and there is no need to control the task to pause and send out, which simplifies the frequency modulation process and reduces the time required for frequency modulation.

[0020] In one embodiment, after controlling the cache to disable the credit mechanism, and before switching the clock source of the processing core from the phase-locked loop to the reference clock source, the method further includes: waiting for the processing core to enter an idle state, wherein the idle state represents the non-busy state of the processing core.

[0021] In this embodiment, when the cache's credit mechanism is disabled, the cache will be unable to send new requests to the memory controller. However, requests from the processing core can still continue to be sent to the cache via the connection architecture components. Once the cache is full of requests, it will instruct the processing core to stop sending requests. At this point, the processing core will enter an idle state, ceasing both request sending and operation. Therefore, controlling the clock source switching in the idle state can prevent frequency adjustment from affecting currently executed tasks, reducing the possibility of data loss. Furthermore, by preventing the processing core from accessing memory for execution, the processing core cannot perform the application's functions. Consequently, the application will not cause a drop in the processing core's operating voltage. The only voltage drop will be due to frequency adjustment, which is less than the voltage drop caused by the application. Therefore, temporarily storing requests in the cache effectively reduces the magnitude of the voltage drop, effectively reducing or avoiding anomalies caused by voltage drops.

[0022] In one embodiment, the adjustment instruction indicates that the type of adjustment to the processor's operating frequency is frequency up: before adjusting the frequency of the phase-locked loop output clock signal to the target frequency, the method further includes: increasing the processor's operating voltage to the voltage corresponding to the target operating frequency.

[0023] In this embodiment of the application, the voltage is increased before frequency upscaling to reduce the possibility of the working voltage not meeting the voltage requirements of the target working frequency, thereby reducing the occurrence of abnormal situations during frequency modulation.

[0024] In one embodiment, the adjustment instruction indicates that the type of adjustment to the processor's operating frequency is frequency reduction; after restoring the cache credit mechanism to the current configuration, the method further includes: reducing the processor's operating voltage to the voltage corresponding to the target operating frequency.

[0025] In this embodiment, during frequency reduction, the current operating voltage is greater than the voltage required for the target operating frequency. Therefore, the voltage can be reduced after frequency modulation is completed. Reducing the voltage after frequency reduction can minimize performance waste.

[0026] In a second aspect, embodiments of this application provide a processor, including: a processing core, a connectivity architecture component, a cache, a memory controller, and memory connected in sequence; the processor further includes a phase-locked loop (PLL) connected to the processing core; the PLL is used to provide a clock signal to the processing core so that the processing core operates based on the clock signal; the cache is configured to: during the process of the PLL being disabled and adjusted, allow receiving requests from the processing core and the connectivity architecture component and restrict the sending of such requests to the memory controller, thereby restricting the processing core from accessing the memory; the PLL is used to connect to a frequency and voltage modulation module, the frequency and voltage modulation module being used to execute the cache-based operating frequency adjustment method as described in any of the first aspects.

[0027] In one embodiment, the processor further includes the frequency and voltage modulation module.

[0028] In one embodiment, the frequency and voltage modulation module is a module independent of the processor.

[0029] In one embodiment, the processor is a GPGPU (General-Purpose computing on Graphics Processing Units).

[0030] Thirdly, embodiments of this application provide an electronic device including the processor described in the second aspect. Attached Figure Description

[0031] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a processor provided in an embodiment of this application; Figure 2 This is a schematic diagram of a clock source connection provided in an embodiment of this application; Figure 3 A flowchart illustrating a cache-based operating frequency adjustment method provided in an embodiment of this application; Figure 4 This is a schematic diagram illustrating the entire process of adjusting the operating voltage and operating frequency according to an embodiment of this application.

[0033] Icons: Processor 100; Phase-Locked Loop 110; Reference Clock Source 111; Multiplexer 112; Processing Core 120; Connectivity Architecture Component 130; Cache 140; Credit Register 141; Memory Controller 150; Memory 160. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0035] First, this application provides a processor whose operating frequency is controlled by a clock signal provided by a phase-locked loop.

[0036] Please see Figure 1 , Figure 1 This is a schematic diagram of a processor according to an embodiment of this application. The processor 100 includes: a phase-locked loop 110, a processing core 120, a connectivity architecture component 130, a cache 140, a memory controller 150, and memory 160. The processing core 120, connectivity architecture component 130, cache 140, memory controller 150, and memory 160 are connected sequentially. The phase-locked loop 110 is connected to the processing core 120 and provides a clock signal to the processing core 120 so that the processing core 120 operates based on the clock signal, and the operating frequency of the processing core 120 matches the frequency of the clock signal.

[0037] Among them, the processing core 120 is the core unit used to perform computing tasks.

[0038] Fabric (connectivity architecture components) is a network architecture responsible for communication between various modules within the processor.

[0039] Caches include various types of cache modules, such as L1 (Level 1 cache), L2 (Level 2 cache), and L3 (Level 3 cache). Among them, the shared cache layer in the processor architecture is LLC (Last Level Cache), also known as L3 cache. It is the last layer of the processor's 100 cores' private cores, used to reduce the number of accesses to external memory locations and improve the performance of the processor 100. For details on LLC, please refer to existing technologies, which will not be elaborated here.

[0040] The memory controller manages data transfer between the processor core and memory. Device memory (or simply memory) stores various data required by the processor.

[0041] The specific structure described above can be referred to in the prior art. The processor 100 may also include other structures, such as a power supply module, a heat dissipation module, etc. The specific structure of the processor 100 or other possible structures can be referred to in the prior art, and will not be elaborated here.

[0042] In the embodiments of this application, cache 140 is configured to: during the process of disabling and adjusting phase-locked loop 110, allow receiving requests from processing core 120 and connection architecture component 130, and restrict the sending of such requests to memory controller 150, thereby limiting processing core 120's access to memory 160. Specific details and implementation methods will be elaborated in the following section on the method for adjusting the operating frequency based on cache 140, and will not be repeated here.

[0043] In the embodiments of this application, the processor type can be any processor 100 that uses the phase-locked loop 110 as its clock source, such as GPGPU (General-Purpose computing on Graphics Processing Units), GPU (Graphics Processing Unit), CPU (central processing unit), NPU (Neural Processing Unit). The specific type is not limited here.

[0044] In embodiments of this application, the processor 100 may further include a frequency modulation and voltage regulation module, i.e., the frequency modulation and voltage regulation module is located within the processor 100. This frequency modulation and voltage regulation module is connected to the phase-locked loop 110, and adjusts the frequency of the clock signal output by the phase-locked loop 110 to adjust the operating frequency of the processor 100's core.

[0045] In the embodiments of this application, the power management module of the processor 100 can implement the function of the frequency modulation and voltage regulation module provided in this application. Correspondingly, the frequency modulation and voltage regulation module can also adjust the operating voltage of the processor 100.

[0046] In some other embodiments of this application, the frequency and voltage modulation module can be a control module independent of the processor 100. For example, the frequency and voltage modulation module can be an MCU (Microcontroller Unit). The frequency and voltage modulation module can be communicatively connected to the phase-locked loop 110 of the processor 100 to obtain the state of the processor 100 and adjust the frequency of the clock signal output by the phase-locked loop 110 to adjust the operating frequency of the processor 100's core. Furthermore, the frequency and voltage modulation module can be connected to the power management module of the processor 100 to control the power management module to adjust the operating voltage of the processor 100.

[0047] In the embodiments of this application, the processor 100 further includes a reference clock source 111, which is configured with a reference clock. The reference clock is a low-frequency clock. For example, the clock signal provided by the phase-locked loop 110 in the processor 100 corresponds to an operating frequency of 750MHz, 1000MHz or higher, and the reference clock corresponds to an operating frequency of 25MHz. In comparison, the frequency of the reference clock is lower.

[0048] Please see Figure 2 , Figure 2 This is a schematic diagram of a clock source connection provided in an embodiment of this application. A phase-locked loop 110 and a reference clock source 111 are connected to a processing core 120 via a multiplexer 112, with one of them providing a clock signal to the processing core 120. The control terminal of the multiplexer 112 can be connected to the aforementioned frequency and voltage modulation module.

[0049] The phase-locked loop 110 is also connected to a reference clock source 111 to adjust the output clock signal using the clock signal provided by the reference clock source 111. For details, please refer to the principle of the phase-locked loop 110, which will not be elaborated here.

[0050] Next, the operating frequency adjustment method based on cache 140 provided in this application will be described in conjunction with the structure of the aforementioned processor 100.

[0051] The cache-based operating frequency adjustment method provided in this application is used to adjust the operating frequency of the processor 100, specifically the operating frequency of the processing core 120.

[0052] In the embodiments of this application, the operating frequency adjustment method based on cache 140 can be applied to the aforementioned frequency and voltage adjustment module. The frequency and voltage adjustment module can be part of the processor 100 or a module independent of the processor 100, and there is no limitation here.

[0053] Please see Figure 3 , Figure 3 A flowchart illustrating a cache-based operating frequency adjustment method according to an embodiment of this application. The cache-based operating frequency adjustment method includes: S310 receives adjustment instructions to adjust the processor's operating frequency.

[0054] In this embodiment of the application, the adjustment instruction may include the target operating frequency required by the processor 100. For example, if the processor 100 is currently operating at 1200MHz and needs to operate at 1000MHz, then the target operating frequency included in the adjustment instruction is 1000MHz.

[0055] The adjustment instruction can characterize the type of adjustment to the processor's operating frequency, including frequency increase and frequency decrease. Frequency increase refers to raising the operating frequency of processor 100, while frequency decrease refers to lowering the operating frequency of processor 100. For example, if the target operating frequency is 1200MHz and the current operating frequency of processor 100 is 1000MHz, then the frequency adjustment type is frequency increase. Conversely, if the target operating frequency is 1000MHz and the current operating frequency of processor 100 is 1200MHz, then the frequency adjustment type is frequency decrease.

[0056] In some embodiments of this application, the adjustment instruction may directly include the adjustment type. For example, different values ​​or parameters may be used to characterize the adjustment type; exemplarily, 1 represents upsampling and 0 represents downsampling.

[0057] In other embodiments, the adjustment type can also be determined by comparing the target operating frequency and the current operating frequency of the processor 100. If the target operating frequency is greater than the current operating frequency of the processor 100, the adjustment type is frequency increase; if the target operating frequency is less than the current operating frequency of the processor 100, the adjustment type is frequency decrease. For example, if the adjustment instruction includes a target operating frequency, the frequency modulation and voltage regulation module can obtain the frequency of the clock signal output by the phase-locked loop 110 to determine the current operating frequency of the processor 100, and then compare the target operating frequency with the current operating frequency to determine the adjustment type.

[0058] S320 disables the phase-locked loop (PLL) and adjusts the PLL based on adjustment instructions. During the PLL adjustment process, it caches the requests from the receiving processing core and connection architecture components and restricts the requests from being sent to the memory controller to limit the processing core's memory access.

[0059] The processing core 120 operates based on the clock signal output by the phase-locked loop 110. The operating frequency of the processing core 120 is related to the frequency of the clock signal output by the phase-locked loop 110. In most cases, the frequency of the clock chip output by the phase-locked loop 110 is equal to the operating frequency of the processing core 120. In some processors 100, the frequency of the clock chip output by the phase-locked loop 110 is an integer multiple of the operating frequency of the processing core 120, which is not limited here. Therefore, in the embodiments of this application, during frequency modulation, the phase-locked loop 110 can be adjusted to change the frequency of the clock signal output by the phase-locked loop 110, so that the phase-locked loop 110 can output a clock signal corresponding to the target operating frequency required by the processing core 120.

[0060] In the embodiments of this application, when adjusting the phase-locked loop 110, the adjustment is performed on the phase-locked loop 110 in a disabled state. However, if the phase-locked loop 110 is not disabled and the clock signal output by the phase-locked loop 110 is used by the processing core 120, the output clock signal may be unstable, leading to abnormal operation of the processing core 120.

[0061] For example, excessive frequency fluctuations can cause the phase-locked loop 110 to lose lock and fail to output a stable clock signal. Alternatively, an unstable clock signal output by the phase-locked loop 110 can cause fluctuations or jitters in the operating frequency of the processor 100, potentially leading to the processor 100's operating frequency exceeding the frequency corresponding to the current operating voltage, thus causing malfunctions. Therefore, in the embodiments of this application, before adjusting the phase-locked loop 110, it can be disabled first, and then the disabled phase-locked loop 110 can be adjusted to reduce malfunctions in the processor 100 caused by unstable clock signals.

[0062] Processing core 120 needs to access memory 160 to execute tasks. Therefore, when executing tasks, processing core 120 sends a request to memory 160 to access memory 160. Connectivity architecture component 130, cache 140, and memory controller 150 serve as components between memory 160 and the processor core 100. The request sent by processing core 120 to memory 160 passes through connectivity architecture component 130, cache 140, and memory controller 150 in sequence, and is then sent to memory 160 by memory controller 150, thus enabling access to memory 160 and allowing processing core 120 to execute tasks normally.

[0063] During the adjustment of the operating frequency of processing core 120, if the operating frequency of processing core 120 is low or zero, such as when the clock source of processing core 120 switches to a lower frequency reference clock or is briefly zero during the switching process, then when processing core 120 calls memory 160 to work, it will work at a low frequency or zero frequency, and the task will not be completed for a long time. Moreover, after the request from processing core 120 is sent to memory 160, subsequent new requests from memory 160 will also be continuously sent to memory 160 and called to memory 160 to execute new requests. This may lead to abnormal situations such as crashes, data backpressure, and data loss.

[0064] In embodiments of this application, the cache 140 can be pre-configured so that during the adjustment of the phase-locked loop 110, the cache 140 can receive requests from the processing core 120 and the connection architecture component 130 and restrict the requests from being sent to the memory controller 150, thereby restricting the processing core 120 from accessing the memory 160.

[0065] When adjusting the frequency, upper-layer applications may be issuing a large number of tasks, and the module itself may be performing calculations, data transmission, and write operations. If the chip core frequency suddenly drops significantly at this time, it can cause system crashes, data backpressure, data loss, and other problems. This is due to a sudden drop in the chip frequency, for example, to an operating frequency of 25MHz or 0MHz, and the module itself may be performing calculations, data transmission, and write operations.

[0066] In the embodiments of this application, cache 140 is restricted from sending requests to memory controller 150, which prevents requests from being sent to memory 160, thereby preventing processing core 120 from accessing memory 160 for work. In this case, even if the operating frequency of processing core 120 is very low, because the request cannot be sent to memory 160 and therefore cannot receive a response, processing core 120 will avoid working during frequency adjustment because it cannot access memory 160. This means that processing core 120 will not perform calculations, data transmission, writes, or other operations during frequency adjustment. Accordingly, the processing core does not perform related work, and the processor has a stable clock input. Therefore, even if the current operating frequency is low or even 0, there will be no abnormal problems such as system freeze, data backpressure, or data loss.

[0067] Meanwhile, when adjusting the phase-locked loop 110, the cache 140 can receive requests from the processing core 120 and the connection architecture component 130. In this case, there is no need to control the task to pause and issue, nor is there a need to wait for the processing core 120 to finish processing the current work. Frequency adjustment can be performed at any time, reducing the preparation work required before frequency adjustment, reducing the time required for frequency adjustment, and improving frequency adjustment efficiency.

[0068] The processor 100 includes various caches, among which the shared cache layer in the processor architecture is an LLC. The LLC is used to store actual data blocks (or cache lines) and their related metadata (such as tags, status, etc.), which accelerates data access, reduces the frequency of accessing main memory, and thus improves overall performance. In the processor 100, the LLC is connected to the memory controller 150. Therefore, in the embodiments of this application, the LLC can be configured as described above.

[0069] In some embodiments of this application, after the phase-locked loop 110 is disabled, the control cache 140 may prevent the sending of requests to the memory controller 150.

[0070] In some embodiments of this application, the cache 140 and the memory controller 150 can be configured to control the transmission of requests based on a preset credit mechanism.

[0071] The credit mechanism includes: cache 140 allows requests to be transmitted to memory controller 150 when a credit value is available. The credit mechanism is a flow control method used to manage the data packet transmission rate between the sender and receiver. The basic principle is that the receiver assigns one or more "credits" to the sender, each credit allowing the sender to transmit a certain amount of data. Once the sender has used a credit to send data, it is only allowed to send data again after the receiver has processed the data and returned an acknowledgment, or the receiver has released the corresponding buffer space. This can be understood as releasing or returning a credit. This method effectively prevents the receiver from losing data due to overload. For details, please refer to existing technologies; further details are omitted here.

[0072] Based on this principle, in the embodiments of this application, a credit mechanism can be configured between cache 140 and memory controller 150, with cache 140 acting as the sender and memory controller 150 as the receiver. Cache 140 can only send data to the receiver when it has a credit value. When the credit mechanism is disabled, cache 140 will be unable to send requests to memory controller 150, thereby achieving the aforementioned function of restricting requests from being sent to memory controller 150.

[0073] Based on this, in some embodiments of this application, the current configuration of the credit mechanism of the cache 140 can be obtained and saved before disabling the phase-locked loop 110 and adjusting the phase-locked loop 110 based on the adjustment instruction; the cache 140 can be controlled to disable the credit mechanism. Thus, after the credit mechanism is disabled, the cache 140 is restricted from transmitting requests to the memory controller 150.

[0074] Furthermore, after disabling phase-locked loop 110 and adjusting phase-locked loop 110 based on adjustment instructions, the method also includes restoring the credit mechanism of cache 140 to its current configuration.

[0075] In this embodiment, since the cache 140 and the memory controller 150 need to transmit requests normally after the frequency is adjusted, the current configuration of the credit mechanism needs to be obtained and saved before adjusting the frequency, and the credit mechanism of the cache 140 needs to be restored to the current configuration after the adjustment.

[0076] In this embodiment, a credit mechanism is configured between the cache 140 and the memory controller 150 so that the cache 140 is only allowed to send requests to the memory controller 150 when it has a credit value. This can effectively prevent the memory controller 150 from losing data due to overload.

[0077] Simultaneously, disabling the credit mechanism restricts the cache 140 from sending requests to the memory controller 150. Therefore, during frequency adjustment, disabling the credit mechanism can limit the processing core 120's access to memory 160, preventing exceptions caused by the processing core 120 operating at lower or zero frequencies. Accordingly, the credit mechanism configuration can be saved before frequency adjustment and restored after adjustment. This method is simple to implement and allows for rapid resumption of request transmission between the cache 140 and the memory controller 150, reducing the time required for frequency adjustment.

[0078] In some embodiments of this application, the processor 100 further includes a credit register 141, which is connected to the cache 140 and is used to record the credit value of the request sent by the cache 140 to the memory controller 150.

[0079] Obtaining and saving the current configuration of the credit mechanism in the cache 140 may include: obtaining and saving the current credit value recorded in the credit register 141.

[0080] Disabling the credit mechanism by controlling cache 140 may include adjusting the credit value recorded in credit register 141 to 0.

[0081] Restoring the credit mechanism of the cache 140 to its current configuration may include adjusting the value recorded in the credit register 141 to the current credit value.

[0082] In this embodiment, the credit value is recorded through the credit register 141. Therefore, during frequency modulation, only the credit value recorded in the credit register 141 needs to be saved, and the recorded credit value needs to be restored after frequency modulation is completed, effectively simplifying the operational complexity of disabling the credit mechanism. This method achieves the saving and restoration of the credit mechanism simply and efficiently, helping to reduce the time required for frequency modulation and improve frequency modulation efficiency.

[0083] In some embodiments of this application, cache 140 includes a request buffer queue. After controlling cache 140 to disable the credit mechanism, the method further includes: continuing to receive requests sent by processing core 120 and connection architecture component 130 through the request buffer queue of cache 140.

[0084] Cache 140 may store various types of data, not limited to requests for processing core 120 and connection architecture component 130. Therefore, in this embodiment, a portion of cache 140 can be allocated specifically for storing requests for processing core 120 and connection architecture component 130, i.e., a request buffer queue can be created. In addition, the request buffer queue can also be a small cache.

[0085] A request buffer queue can be a temporary storage area allocated by an LLC to store requests that have been issued but not yet processed. An LLC is a large caching module that stores data fetched from memory. Between multiple cache levels, the request buffer queue manages the flow of requests from upper-level caches to lower-level caches or memory controllers.

[0086] In the embodiments of this application, the request buffer queue is mainly used to manage asynchronous communication, ensure that requests can be submitted to downstream modules in an orderly manner, and perform flow control when necessary, such as flow control through a credit mechanism.

[0087] In the embodiments of this application, the size of the request buffer queue can be determined based on the performance of the processor 100. A lower-performance processor 100 receives fewer requests during frequency modulation, requiring a smaller request buffer queue; conversely, a lower-performance processor 100 receives more requests during frequency modulation, requiring a larger request buffer queue. Specific configuration can be made according to actual needs and is not limited here. In some embodiments, the size of the request buffer queue can be configured based on the number of requests received by the cache 140 during frequency modulation in different scenarios.

[0088] By using a request buffer queue, upper-layer requests can be prevented from being sent to memory until cache 140 regains its credit and can continue processing requests. Requests from processing core 120 and connection architecture component 130 can be sent to cache 140 normally. After frequency modulation is completed, requests in the request buffer queue can be output normally, allowing processing core 120 to continue executing its task. Thus, frequency modulation can be performed without waiting for processing core 120 to finish its current task, reducing the time required for frequency modulation.

[0089] In some embodiments of this application, after receiving requests sent by processing core 120 and connection architecture component 130 through request buffer queue of cache 140, the method further includes: instructing processing core 120 to pause request sending until request buffer queue is full of requests.

[0090] In the embodiments of this application, a backpressure mechanism can be configured for the processor 100. The backpressure mechanism means that after the request buffer queue of the cache 140 is full, the cache 140 sends an instruction to the processing core 120 to instruct the processing core 120 not to send any more requests. The requests sent by the cache 140 to the processing core 120 are first sent to the processing core 120 through the connection architecture component 130, so that the processing core 120 also stops sending new requests.

[0091] In this embodiment, after the request buffer queue is full of requests, the connection architecture component 130 and the processing core 120 are instructed to pause request sending in order to reduce the occurrence of anomalies during the frequency modulation process in the event that the cache 140 is unable to cache new requests and data is lost.

[0092] The above covers the relevant content regarding cache 140 and the credit mechanism. Next, we will elaborate on the methods for adjusting the operating frequency of processor 100.

[0093] In one embodiment of this application, disabling the phase-locked loop 110 and adjusting the phase-locked loop 110 based on adjustment instructions may include: after the control buffer 140 disables the credit mechanism, switching the clock source of the processing core 120 from the phase-locked loop 110 to the reference clock source 111; disabling the phase-locked loop 110; waiting until the phase-locked loop 110 is unlocked, adjusting the frequency of the clock signal output by the phase-locked loop 110 to the target frequency; enabling the phase-locked loop 110; waiting until the phase-locked loop 110 is locked, switching the clock source of the processing core 120 back from the reference clock source 111 to the phase-locked loop 110.

[0094] In this embodiment, the target frequency is the clock signal frequency that enables the processor 100 to operate at a target operating frequency. This can be achieved by adjusting the feedback division ratio of the phase-locked loop 110 to adjust the frequency of the clock signal output by the phase-locked loop 110. The adjustment method for the phase-locked loop 110 can be found in existing technologies and will not be elaborated upon here.

[0095] In this embodiment, after the control cache 140 disables the credit mechanism, the clock source of the processing core 120 is switched from the phase-locked loop 110 to the reference clock source 111. This allows the processor 100 to operate based on the reference clock signal provided by the reference clock source 111, maintaining a lower operating frequency. This method eliminates the need for the processor 100 to disable the clock input, thus avoiding issues caused by the lack of a clock, such as clock shutdown time and paused task assignment. Consequently, the time required to adjust the clock frequency is reduced.

[0096] In some embodiments of this application, after the control cache 140 disables the credit mechanism and before switching the clock source of the processing core 120 from the phase-locked loop 110 to the reference clock source 111, the method further includes: waiting for the processing core 120 140 to enter an idle state.

[0097] In the embodiments of this application, the state of entering an idle state can be determined by judging the level of the busy signal of the processing core 120. For example, if the busy signal is high, the idle state has not been entered; if the busy signal is low, the idle state has been entered. The hardware busy signal is a general signal, which is formed by ANDing multiple busy states of multiple subsystems and related connection architecture components and subsystems within the processing core 120. The specific details of the idle state can be found in the prior art and will not be elaborated here.

[0098] In the embodiments of this application, when the cache credit mechanism is turned off, the cache will be unable to send new requests to the memory controller. However, the processing core's requests can still continue to be sent to the cache through the connection architecture components. When the cache is full of requests, the cache will instruct the processing core to stop sending requests. At this time, the processing core will enter an idle state, stop sending requests, and stop working.

[0099] In the embodiments of this application, the idle state can indicate that the processing core 120 is in a non-busy state, or in other words, in an idle state. The idle state signifies that the processing core 120 no longer sends requests to the cache. Waiting for the cache 140 to enter the idle state can prevent frequency adjustment from affecting the currently executing work, reducing the possibility of data loss. Furthermore, this prevents the processing core from accessing memory for execution, thus preventing the processing core from implementing the application's functionality. Therefore, the application will not cause a drop in the processing core's operating voltage; only the voltage drop caused by frequency adjustment will occur, and this voltage drop is less than the voltage drop caused by the application. Therefore, temporarily storing requests in the cache effectively reduces the magnitude of the voltage drop, effectively reducing or avoiding anomalies caused by voltage drops.

[0100] The operating frequency of processor core 120 is closely related to its operating voltage. If the operating voltage does not meet the frequency requirements, processor 100 may malfunction or crash. Conversely, if the operating voltage is too high while the operating frequency is too low, processor 100 may experience performance waste. Therefore, before adjusting phase-locked loop 110, it is necessary to determine the frequency adjustment type to determine the timing of operating voltage adjustment based on the adjustment type, and then adjust the operating voltage accordingly. That is, frequency increase is preceded by voltage increase, and frequency decrease is preceded by voltage decrease.

[0101] In one embodiment, if the type of adjustment to the operating frequency of the processor 100 is frequency up, then before adjusting the frequency of the clock signal output by the phase-locked loop 110 to the target frequency, the operating voltage of the processor 100 is increased to the voltage corresponding to the target operating frequency.

[0102] In the embodiments of this application, after increasing the operating voltage of the processor 100 to the voltage corresponding to the target operating frequency, it is necessary to wait for the voltage to stabilize before acquiring and disabling the credit mechanism. The time required to disable the credit mechanism is relatively short, and frequency adjustment and switching will be performed after disabling the credit mechanism to avoid issues arising from voltage instability.

[0103] In other embodiments, the voltage may be stabilized after the credit mechanism is turned off and before the phase-locked loop is disabled and adjusted based on the adjustment command.

[0104] In one embodiment, if the type of adjustment to the operating frequency of the processor 100 is frequency reduction, then after restoring the credit mechanism of the cache 140 to the current configuration, the operating voltage of the processor 100 is reduced to the voltage corresponding to the target operating frequency.

[0105] In this embodiment, the adjustment type can be determined by the target operating frequency and the current operating voltage of the processor 100, or it can be carried in the adjustment instruction; there is no limitation here.

[0106] Increasing the voltage before frequency upscaling reduces the likelihood of the operating voltage not meeting the target operating frequency requirements, thus minimizing abnormal situations during frequency tuning. Conversely, during frequency downscaling, the current operating voltage is higher than the voltage required for the target operating frequency. Therefore, the voltage can be reduced after frequency tuning is complete. Reducing the voltage after frequency downscaling reduces performance waste caused by excessively high operating voltage.

[0107] For ease of understanding, please refer to the following: Figure 4 , Figure 4 This is a schematic diagram illustrating the entire process of adjusting the operating voltage and operating frequency as provided in the embodiments of this application.

[0108] Example 1: Taking frequency upscaling as an example, if the current operating frequency is 1000MHz and the target operating frequency is 1200MHz, the adjustment process includes: After receiving the adjustment command, the frequency and voltage adjustment module will determine the target operating frequency in the adjustment command. If the target operating frequency of 1200MHz is greater than the current operating frequency of processor 100 of 1000MHz, then the adjustment type is determined to be frequency increase. Accordingly, the operating voltage needs to be increased to the operating voltage corresponding to the target operating frequency.

[0109] After the voltage stabilizes, the credit mechanism can be saved and closed, the current credit value n of credit register 141 can be recorded, and the credit value of credit register 141 can be adjusted to 0. Then, wait for the current request in cache 140 to be issued, enter the idle state, and start adjusting the working frequency.

[0110] When adjusting the operating frequency, first switch the clock source from PLL 110 to reference clock source 111. If the switch fails, wait or try switching again. After confirming that the clock source has been switched to reference clock source 111, disable PLL 110. After PLL 110 unlocks, adjust parameters such as the feedback division ratio of PLL 110 to adjust the clock signal corresponding to the target operating frequency of 1200MHz. After adjustment, enable PLL 110 and wait for it to lock. Then switch the clock source from reference clock source 111 to PLL 110. If the switch fails, wait or try switching again.

[0111] After determining that the clock source has switched to PLL 110, the frequency adjustment is complete, and the credit mechanism can be restored, resetting the recorded value of credit register 141 to n. Because it is a frequency upsampling process, the entire frequency modulation process can be terminated directly.

[0112] Example 2: Taking frequency reduction as an example, if the current operating frequency is 1200MHz and the target operating frequency is 1000MHz, the adjustment process includes: After receiving the adjustment command, the frequency and voltage regulation module will determine the target operating frequency in the adjustment command. If the target operating frequency of 1000MHz is less than the current operating frequency of processor 100 of 1200MHz, then the adjustment type will be determined to be frequency reduction.

[0113] Because the voltage is reduced after frequency reduction, the credit mechanism can be directly saved and closed, the current credit value m of credit register 141 is recorded, the credit value of credit register 141 is adjusted to 0, and then the current request in cache 140 is sent, entering the idle state and starting to adjust the working frequency.

[0114] When adjusting the operating frequency, first switch the clock source from PLL 110 to reference clock source 111. If the switch fails, wait or try switching again. After confirming that the clock source has been switched to reference clock source 111, disable PLL 110. After PLL 110 unlocks, adjust parameters such as the feedback division ratio of PLL 110 to adjust the clock signal corresponding to the target operating frequency of 1000MHz. After adjustment, enable PLL 110 and wait for it to lock. Then switch the clock source from reference clock source 111 to PLL 110. If the switch fails, wait or try switching again.

[0115] After determining that the clock source has been switched to the phase-locked loop 110, the part of adjusting the working frequency is completed, and the credit mechanism can be restored, restoring the recorded value of the credit register 141 to m.

[0116] Because it's a frequency reduction, the operating voltage also needs to be lowered to the operating voltage corresponding to 1000MHz, and then the entire frequency modulation process ends.

[0117] The above description is merely an example and should not be construed as limiting this application.

[0118] Based on the same inventive concept, the application also provides a frequency and voltage modulation module independent of the processor whose operating frequency needs to be adjusted. This frequency and voltage modulation module can be an MCU. This module can be connected to the processor to perform the aforementioned cache-based operating frequency adjustment method.

[0119] Based on the same inventive concept, embodiments of this application also provide an electronic device, which may include the processor provided in the foregoing embodiments.

[0120] The electronic device includes, but is not limited to, computers, servers, industrial control computers, and other devices that include processors, and is not restricted in this regard.

[0121] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0122] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for adjusting operating frequency based on caching, characterized in that, Used to adjust the processor's operating frequency; The processor includes a processing core, a connectivity architecture component, a cache, a memory controller, and memory connected in sequence; the processor also includes a phase-locked loop connected to the processing core. The phase-locked loop is used to provide a clock signal to the processing core, so that the processing core operates based on the clock signal; The cache-based operating frequency adjustment method includes: Receive an adjustment command to adjust the operating frequency of the processor; The phase-locked loop (PLL) is disabled and adjusted based on the adjustment instructions. During the adjustment of the PLL, the cache receives requests from the processing core and the connection architecture components and restricts the requests from being sent to the memory controller, thereby restricting the processing core from accessing the memory.

2. The cache-based operating frequency adjustment method according to claim 1, characterized in that, The cache and the memory controller are configured to control the transmission of requests based on a preset credit mechanism; The credit mechanism includes: the cache allows requests to be transmitted to the memory controller if it has a credit value; Before disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment command, the method further includes: Obtain and save the current configuration of the cache for the credit mechanism; The cache is controlled to disable the credit mechanism; after the credit mechanism is disabled, the cache is restricted from sending requests to the memory controller. And, after disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment command, the method further includes: Restore the cached credit mechanism to the current configuration.

3. The cache-based operating frequency adjustment method according to claim 2, characterized in that, The processor also includes a credit register connected to the cache, which is used to record the credit value of a request sent by the cache to the memory controller. The step of obtaining and saving the current configuration of the cache for the credit mechanism includes: obtaining and saving the current credit value recorded in the credit register; The control of the cache to disable the credit mechanism includes: adjusting the credit value recorded in the credit register to 0; Restoring the cached credit mechanism to the current configuration includes: adjusting the value recorded in the credit register to the current credit value.

4. The cache-based operating frequency adjustment method according to claim 2, characterized in that, The cache includes a request buffer queue; After controlling the cache to disable the credit mechanism, the method further includes: The cached request buffer queue continues to receive requests sent by the processing core and the connection architecture components.

5. The cache-based operating frequency adjustment method according to claim 4, characterized in that, After the method continues to receive requests sent by the processing core and the connection architecture components through the cached request buffer queue, the method further includes: The process continues until the request buffer queue is full, at which point the processing core is instructed to pause request sending.

6. The cache-based operating frequency adjustment method according to any one of claims 2-5, characterized in that, The processor also includes a reference clock source, which is connected to the processing core and is used to output a reference clock. The adjustment instructions include the target operating frequency required by the processor; Disabling the phase-locked loop and adjusting the phase-locked loop based on the adjustment command includes: After controlling the cache to disable the credit mechanism, the clock source of the processing core is switched from the phase-locked loop to the reference clock source; Disable the phase-locked loop; Wait until the phase-locked loop loses lock, then adjust the frequency of the phase-locked loop output clock signal to the target frequency; the target frequency is the clock frequency that makes the processor operate at the target operating frequency. Enable the phase-locked loop; Once the phase-locked loop (PLL) is locked, the clock source of the processing core is switched back from the reference clock source to the PLL.

7. The cache-based operating frequency adjustment method according to claim 6, characterized in that, After controlling the cache to disable the credit mechanism, and before switching the clock source of the processing core from the phase-locked loop to the reference clock source, the method further includes: Wait for the processing core to enter the idle state, which indicates that the processing core is in a non-busy state.

8. The cache-based operating frequency adjustment method according to claim 6, characterized in that, The adjustment instruction indicates that the type of adjustment to the processor's operating frequency is frequency increase: Before adjusting the frequency of the phase-locked loop output clock signal to the target frequency, the method further includes: Increase the processor's operating voltage to the voltage corresponding to the target operating frequency.

9. The cache-based operating frequency adjustment method according to claim 6, characterized in that, The adjustment instruction indicates that the type of adjustment to the processor's operating frequency is frequency reduction; After restoring the cached credit mechanism to the current configuration, the method further includes: The processor's operating voltage is reduced to the voltage corresponding to the target operating frequency.

10. A processor, characterized in that, include: The processor comprises a processing core, a connection architecture component, a cache, a memory controller, and memory, which are connected in sequence; the processor also includes a phase-locked loop (PLL) connected to the processing core. The phase-locked loop is used to provide a clock signal to the processing core, so that the processing core operates based on the clock signal; The cache is configured to: during the process of the phase-locked loop being disabled and adjusted, allow receiving requests from the processing core and the connection architecture components and restrict the sending of such requests to the memory controller, thereby restricting the processing core from accessing the memory; The phase-locked loop is used to connect to the frequency modulation and voltage regulation module, which is used to execute the buffer-based operating frequency adjustment method as described in any one of claims 1-9.

11. The processor according to claim 10, characterized in that, The processor also includes the frequency and voltage modulation module.

12. The processor according to claim 10, characterized in that, The frequency and voltage regulation module is a module independent of the processor.

13. The processor according to claim 10 or 11, characterized in that, The processor is a general-purpose graphics processing unit (GPGPU).

14. An electronic device, characterized in that, include: The processor as described in any one of claims 10-13.

Images