Simulink code generation method and device based on hardware instruction

Abstract

The invention provides a Simulink code generation method and device based on a hardware instruction, and relates to the technical field of embedded code generation, the method comprises the following steps: obtaining an initial data flow diagram of a model, and reconstructing the initial data flow diagram based on a preset optimization rule to obtain a reconstructed target data flow diagram; analyzing the topological structure of the reconstructed data flow diagram, determining an execution dependency relationship among the components, and deducing a code translation sequence; respectively generating a code snippet corresponding to each component in the code translation sequence, and integrating the generated code snippets according to a code translation sequence indicated by the code translation sequence to obtain a target code. According to the code generation method and device, in the code generation process, the candidate rules capable of maximizing delay reduction can be selected to recognize the optimizable components, the corresponding hardware specific instructions are comprehensively generated for the optimizable components, and therefore efficient embedded codes capable of being directly deployed are generated.

Description

Technical Field

[0001] This application relates to the field of embedded code generation technology, and in particular to a Simulink code generation method and apparatus based on hardware instructions. Background Technology

[0002] Simulinl is a key tool for Model-Driven Development (MDD) and has become a cornerstone in safety-critical systems engineering, such as automotive, aerospace, and medical systems. It improves the productivity, reliability, and maintainability of development by abstracting complex system behaviors into high-level models.

[0003] In model-driven development, code generation plays a crucial role, automatically converting high-level models into embedded code, thereby reducing manual workload and coding errors. Because embedded devices typically feature low power consumption and high real-time performance, applications must meet specific energy consumption and performance targets.

[0004] Therefore, there is an urgent need for a code generation solution that can reduce the execution latency of hardware instructions and improve the overall code performance. Summary of the Invention

[0005] The purpose of this application is to provide a Simulink code generation method and apparatus based on hardware instructions, which can select candidate rules that maximize latency reduction to identify optimizable components during the code generation process, and generate corresponding hardware-specific instructions for the optimizable components, thereby producing efficient embedded code that can be directly deployed.

[0006] This application provides a Simulink code generation method based on hardware instructions, including: An initial data flow graph of the target Simulink model is obtained, and the initial data flow graph is reconstructed based on pre-set optimization rules to obtain the reconstructed target data flow graph. The optimization rules are used to reduce the execution latency of hardware instructions. Topology analysis is performed on the target data flow graph to determine the execution dependencies between components, and a code translation sequence is derived based on the execution dependencies between components. Code snippets corresponding to each component are generated, and the generated code snippets are integrated according to the code translation order indicated by the code translation sequence to obtain the target code. The components in the target data flow graph include: optimizable components and basic components. The code snippets corresponding to optimizable components are hardware instructions, and the code snippets corresponding to basic components are executable functional code.

[0007] Optionally, the step of reconstructing the initial data flow graph based on pre-set optimization rules to obtain the reconstructed target data flow graph includes: acquiring multiple available optimization rules and the evaluation result of each available optimization rule; the evaluation result is used to characterize the reduction in latency of executing hardware instructions; and iteratively updating the initial data flow graph based on the evaluation result of each available optimization rule until the reconstructed target data flow graph is obtained; wherein, the iterative update includes: using a latency-sensitive method to select the optimal rule that can maximize the reduction of execution latency from the multiple available optimization rules, and using the optimal rule to reconstruct the initial data flow graph.

[0008] Optionally, obtaining multiple available optimization rules and the evaluation result of each available optimization rule includes: determining the deployment platform of the target code, and selecting multiple available optimization rules that match the deployment platform of the target code from the optimization rules pre-set in the rule base; evaluating each available optimization rule among the multiple available optimization rules to obtain the evaluation result of each available optimization rule.

[0009] Optionally, the step of iteratively updating the initial data flow graph based on the evaluation results of each available optimization rule until the reconstructed target data flow graph is obtained includes: determining the available optimization rules applicable to each component based on the applicability matching results of the available optimization rules with the initial data flow graph, obtaining multiple candidate rules, and determining the execution latency reduction value of each candidate rule based on the evaluation results of each candidate rule; one component corresponds to at least one candidate rule; using a preset screening method to select the optimal rule for data flow graph reconstruction from the multiple candidate rules, and updating the data flow graph based on the selected optimal rule until the reconstructed target data flow graph is obtained; wherein, the preset screening method includes: if the execution latency reduction value of any target candidate rule among the multiple candidate rules is greater than the current maximum latency reduction value, then updating the current latency reduction value based on the execution latency reduction value of the target candidate rule, and determining the target candidate rule as the optimal rule.

[0010] Optionally, each of the plurality of optimal rules is represented as a subgraph of a data flow graph; the step of updating the data flow graph based on the selected optimal rules until the reconstructed target data flow graph is obtained includes: encapsulating the data flow graph subgraph into a new component based on the input and output ports of the target data flow graph subgraph used to represent the optimal rules; assigning corresponding functional attributes to the new component; and marking the new component as an optimizable component.

[0011] Optionally, generating code snippets corresponding to each component includes: for optimizable components, matching hardware feature instructions corresponding to each optimizable component based on the deployment platform of the target code, the component function and data type of each optimizable component; generating assembly code corresponding to each optimizable component based on the hardware feature instructions corresponding to each optimizable component, and mapping the input and output data of the assembly code corresponding to each optimizable component to the input and output ports of each optimizable component.

[0012] Optionally, generating code snippets for each component includes: generating corresponding functional code for each basic component based on its component functionality.

[0013] Optionally, the step of integrating the generated code snippets according to the code translation order indicated by the code translation sequence to obtain the target code includes: combining the code snippets corresponding to each optimizable component and the code snippets corresponding to each basic component, and integrating the generated code snippets according to the code translation sequence to obtain the target code.

[0014] This application also provides a Simulink code generation device based on hardware instructions, including: A data flow graph reconstruction module is used to obtain the initial data flow graph of the target Simulink model and reconstruct the initial data flow graph based on pre-set optimization rules to obtain the reconstructed target data flow graph; the optimization rules are used to reduce the execution latency of hardware instructions. A code generation module is used to perform topology analysis on the target data flow graph, determine the execution dependencies between components, and derive the code translation sequence based on the execution dependencies between components. The code generation module is also used to generate code snippets corresponding to each component, and integrate the generated code snippets according to the code translation order indicated by the code translation sequence to obtain the target code. The components in the target data flow graph include: optimizable components and basic components; the code snippets corresponding to optimizable components are hardware instructions, and the code snippets corresponding to basic components are executable functional code.

[0015] Optionally, the data flow graph reconstruction module is specifically used to obtain multiple available optimization rules and the evaluation result of each available optimization rule; the evaluation result is used to characterize the reduction in latency of executing hardware instructions; the data flow graph reconstruction module is further used to iteratively update the initial data flow graph based on the evaluation result of each available optimization rule until the reconstructed target data flow graph is obtained; wherein, the iterative update includes: using a latency-sensitive method to select the optimal rule that can maximize the reduction of execution latency from the multiple available optimization rules, and using the optimal rule to reconstruct the initial data flow graph.

[0016] Optionally, the data flow graph reconstruction module is specifically used to determine the deployment platform of the target code and to select multiple available optimization rules that match the deployment platform of the target code from the optimization rules pre-set in the rule base; the data flow graph reconstruction module is also specifically used to evaluate each of the multiple available optimization rules to obtain the evaluation result of each available optimization rule.

[0017] Optionally, the data flow graph reconstruction module is specifically used to determine the applicable optimization rules for each component based on the applicability matching results of the available optimization rules with the initial data flow graph, obtain multiple candidate rules, and determine the execution latency reduction value of each candidate rule based on the evaluation result of each candidate rule; one component corresponds to at least one candidate rule; the data flow graph reconstruction module is further used to use a preset filtering method to filter out the optimal rule for data flow graph reconstruction from the multiple candidate rules, and update the data flow graph based on the filtered optimal rule until the reconstructed target data flow graph is obtained; wherein, the preset filtering method includes: if the execution latency reduction value of any target candidate rule among the multiple candidate rules is greater than the current maximum latency reduction value, then update the current latency reduction value based on the execution latency reduction value of the target candidate rule, and determine the target candidate rule as the optimal rule.

[0018] Optionally, each of the plurality of optimal rules is represented as a data flow graph subgraph; the data flow graph reconstruction module is specifically used to encapsulate the data flow graph subgraph into a new component based on the input port and output port of the target data flow graph subgraph used to represent the optimal rule; the data flow graph reconstruction module is also specifically used to assign corresponding functional attributes to the new component and mark the new component as an optimizable component.

[0019] Optionally, the code generation module is specifically used to match the hardware feature instructions corresponding to each optimizable component based on the deployment platform of the target code, the component function and data type of each optimizable component; the code generation module is also specifically used to generate assembly code corresponding to each optimizable component based on the hardware feature instructions corresponding to each optimizable component, and map the input and output data of the assembly code corresponding to each optimizable component to the input and output ports of each optimizable component.

[0020] Optionally, the code generation module is specifically used to generate corresponding functional code for each basic component based on the component functions of each basic component.

[0021] Optionally, the code generation module is specifically used to synthesize the code snippets corresponding to each optimizable component and the code snippets corresponding to each basic component, and to integrate the generated code snippets according to the code translation sequence to obtain the target code.

[0022] This application also provides a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of the hardware instruction-based Simulink code generation method as described above.

[0023] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of any of the above-described hardware instruction-based Simulink code generation methods.

[0024] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the hardware instruction-based Simulink code generation method as described above.

[0025] The hardware instruction-based Simulink code generation method and apparatus provided in this application first obtain an initial data flow graph of the target Simulink model, and then reconstruct the initial data flow graph based on pre-set optimization rules to obtain a reconstructed target data flow graph; the optimization rules are used to reduce the execution latency of hardware instructions; then, topology analysis is performed on the target data flow graph to determine the execution dependencies between components, and a code translation sequence is derived based on the execution dependencies between components; finally, code fragments corresponding to each component are generated, and the generated code fragments are integrated according to the code translation order indicated by the code translation sequence to obtain target code; wherein, the components in the target data flow graph include: optimizable components and basic components; the code fragments corresponding to optimizable components are hardware instructions, and the code fragments corresponding to basic components are executable functional code. In this way, during the code generation process, candidate rules that maximize latency reduction can be selected to identify optimizable components, and corresponding hardware-specific instructions can be generated for optimizable components, thereby producing efficient embedded code that can be directly deployed. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is one of the flowcharts illustrating the hardware instruction-based Simulink code generation method provided in this application; Figure 2 This is the second flowchart of the hardware instruction-based Simulink code generation method provided in this application; Figure 3 This is a schematic diagram of the rules provided in this application; Figure 4 This is a schematic diagram of the hardware instruction-based Simulink code generation device provided in this application; Figure 5 This is a schematic diagram of the structure of the electronic device provided in this application. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] Several effective methods exist in related technologies to ensure code efficiency. Simulink Embedded Coder, as Simulink's built-in code generator, offers various optimization options. For example, it improves performance by reducing redundant assignments through expression folding and variable reuse, and by minimizing the number of conditional statements through merging loop structures. DFSynth aims to optimize complex branching structures in Simulink models by decomposing the target model into blocks embedded in control statements and generating custom code templates for each block. Other research leverages hardware features to accelerate code execution. For instance, Mercury improves instruction pipeline utilization and overall code performance by adjusting the code translation order to avoid data hazards.

[0031] Despite the significant progress made by the aforementioned code generators, they neglect the importance of hardware-specific instructions, resulting in inefficient generated code. In other words, they fail to identify optimizable code blocks in the target model and cannot synthesize suitable hardware instructions for these blocks. Modern processors include dedicated instructions in their instruction sets to perform complex operations that would otherwise require multiple regular instructions. For example, the Tricore processor, developed by Infineon and widely used in the automotive industry, provides several dedicated instructions to meet stringent real-time requirements, such as the QSEED.F instruction for calculating the reciprocal of the square root. These instructions are implemented in hardware, significantly reducing execution latency compared to software-based implementations.

[0032] Furthermore, relying on the compiler to automatically utilize these hardware-specific instructions is not ideal. Current state-of-the-art compilers (such as GCC and Clang) typically employ pattern matching for instruction selection, but they struggle to fully leverage complex hardware-specific instructions, such as saturation-type instructions. These instructions often have complex control flow and multiple code variations, making it difficult to develop general matching strategies. Moreover, even under high-level compiler optimizations, directly using hardware-specific instructions through inline assembly can still yield significant performance improvements.

[0033] In fact, Simulink models contain rich semantic information, such as parameters and connectivity relationships, which can bring potential advantages when synthesizing hardware-specific instructions. For example, saturation is an inherent parameter of Simulink components and can be used to determine whether saturated instructions should be synthesized. However, to effectively utilize model semantics for hardware-specific instruction synthesis, the following two challenges must be addressed: 1. The first challenge is how to formulate accurate optimization rules and efficiently apply them to instruction synthesis. Given the rich semantics of the model, optimization rules must consider not only the properties of the components themselves but also the connectivity relationships between them. Simultaneously, key features must be extracted from a large number of irrelevant or secondary attributes. Furthermore, optimization rules often involve analyzing the connectivity relationships between multiple components, leading to a huge search space. Moreover, since the same component may be associated with multiple optimization rules simultaneously, choosing the appropriate rule to maximize performance improvement becomes a critical issue. 2. The second challenge is how to design a coarse-grained optimization framework. Different hardware platforms often provide functionally equivalent but semantically different instructions. Writing separate optimization rules for each instruction is not only tedious but also prone to errors. Furthermore, when synthesizing appropriate instructions, their semantic characteristics must be carefully considered. Therefore, developing a unified optimization scheme that can effectively handle instruction variations and model semantic diversity is a challenging task.

[0034] To address the aforementioned technical problems in related technologies, this application proposes an efficient Simulink model code generator based on hardware-specific instruction synthesis. First, the model is parsed to extract the core content required to construct the target model's data flow graph, such as component attributes and connection relationships. Simultaneously, this application designs a series of optimization rules, represented in the form of data flow subgraphs, with constraints related to component parameters, data types, and other key attributes. Through this process, the system can filter out content irrelevant to optimization, laying the foundation for subsequent optimization stages. For functionally equivalent but semantically different instructions, they are merged into a single optimization rule; for platform-specific instructions, separate optimization rules are formulated for each. Next, applicable optimization rules are selected based on the target platform and iteratively matched with the data flow graph to identify potential optimization candidates. This application selects candidates that maximize latency reduction, updates the data flow graph, and marks the updated components as "optimizable." Finally, based on instruction syntax and component attributes, corresponding hardware-specific instructions are synthesized for these optimizable components. The generated code is integrated with the code of other basic components in the order of translation, thereby producing efficient embedded code that can be directly deployed.

[0035] The hardware instruction-based Simulink code generation method provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0036] like Figure 1 As shown in the embodiment of this application, a Simulink code generation method based on hardware instructions is provided. This method may include the following steps 101 to 103: Step 101: Obtain the initial data flow graph of the target Simulink model, and reconstruct the initial data flow graph based on the pre-set optimization rules to obtain the reconstructed target data flow graph.

[0037] The optimization rules are used to reduce the execution latency of hardware instructions.

[0038] For example, such as Figure 2 As shown in the embodiments of this application, the Simulink code generation method based on hardware instructions includes two parts: data flow graph reconstruction and hardware-oriented synthesis. To facilitate subsequent code generation, the data flow graph first needs to be reconstructed. That is, instruction mapping rules are constructed based on component parameters and the data flow graph, and the model data flow graph is reconstructed based on these rules to serve subsequent hardware instruction synthesis.

[0039] Specifically, for the reconstruction of the data flow graph, the first step is to parse the Simulink model and extract key information, including component attributes, connection relationships, input / output ports, etc., and then construct the data flow graph based on this information as a preparatory step before optimization. Simultaneously, a series of optimization rules are designed, represented in the form of data flow subgraphs, with constraints related to component parameters, data types, and other attributes. Functionally equivalent but semantically different instructions are merged into the same optimization rule; while platform-specific instructions are defined with independent optimization rules. Based on the target platform, available rules are selected from the rule base and matched against the data flow graph to obtain potential optimization candidates. Subsequently, the candidate that maximizes latency reduction is selected to update the data flow graph and used in the next optimization iteration. The updated components are marked as optimizable components.

[0040] Specifically, step 101 above may also include the following steps 101a and 101b: Step 101a: Obtain multiple available optimization rules and the evaluation result of each available optimization rule; the evaluation result is used to characterize the reduction in latency of executing hardware instructions.

[0041] For example, to filter out content irrelevant to optimization, embodiments of this application construct all optimization rules based on the data flow graph and its associated component attributes, and encapsulate them into an optimization rule base for subsequent use. Specifically, each optimization rule is essentially a constrained data flow subgraph, with constraints relating to component parameters, data types, and other attributes related to instruction synthesis. Figure 3 The diagram shows some typical optimization rules in the rule base of this application. In these rules, the left side represents the data flow subgraph, and the right side represents the corresponding constraints. Taking the "Saturation Add" rule as an example, its corresponding data flow subgraph is an Add component with the following constraints: the "saturation" parameter of this component is enabled (i.e., saturation is enabled), and the data type is int or unsigned int. Furthermore, for instructions that are functionally equivalent but semantically different on different platforms, they are merged into the same optimization rule. For example, the target platform constraint in the "Saturation Add" rule can take three values: Tricore, ARM, and RISC-V, meaning that the tool can automatically synthesize and generate the corresponding saturated addition instructions based on the target platform. For instructions unique to a specific platform, this application embodiment designs dedicated optimization rules, such as... Figure 3 The “Condition Add” rule shown.

[0042] Specifically, step 101a above may also include the following steps 101a1 and 101a2: Step 101a1: Determine the deployment platform of the target code, and select multiple available optimization rules that match the deployment platform of the target code from the pre-set optimization rules in the rule base.

[0043] Step 101a2: Evaluate each of the multiple available optimization rules to obtain the evaluation result of each available optimization rule.

[0044] For example, before performing specific optimizations, this embodiment of the application also performs adaptive configuration based on the target deployment platform of the generated code. First, based on the platform constraints of each optimization rule in the rule base, an available optimization rule matching the current platform is selected. Then, in conjunction with the corresponding instruction set documentation, the reduction in execution latency that can be achieved by utilizing relevant hardware instructions is evaluated, and the evaluation result is used in the subsequent optimization decision-making process.

[0045] Step 101b: Based on the evaluation results of each available optimization rule, iteratively update the initial data flow graph until the reconstructed target data flow graph is obtained.

[0046] The iterative update includes: using a latency-sensitive method to select the optimal rule from the multiple available optimization rules that can maximize the reduction of execution latency, and using the optimal rule to reconstruct the initial data flow graph.

[0047] For example, before performing specific optimizations, this application embodiment adaptively configures the code based on the target deployment platform. First, based on the platform constraints of each optimization rule in the rule base, an available optimization rule matching the current platform is selected. Then, in conjunction with the corresponding instruction set documentation, the reduction in execution latency that can be achieved by utilizing relevant hardware instructions is evaluated, and the evaluation result is used in the subsequent optimization decision-making process.

[0048] Specifically, step 101b above may also include the following steps 101b1 and 101b2: Step 101b1: Based on the applicability matching results of the available optimization rules with the initial data flow graph, determine the applicable available optimization rules for each component, obtain multiple candidate rules, and determine the execution latency reduction value of each candidate rule based on the evaluation results of each candidate rule.

[0049] Each component corresponds to at least one candidate rule.

[0050] Step 101b2: Use a preset filtering method to select the optimal rule for data flow graph reconstruction from the multiple candidate rules, and update the data flow graph based on the selected optimal rule until the reconstructed target data flow graph is obtained.

[0051] The preset filtering method includes: if the execution latency reduction value of any target candidate rule among the plurality of candidate rules is greater than the current maximum latency reduction value, then the current latency reduction value is updated based on the execution latency reduction value of the target candidate rule, and the target candidate rule is determined as the optimal rule.

[0052] For example, such as Figure 2As shown, for the selected optimization rules, a latency-sensitive matching method is used to filter the optimal rule that maximizes the reduction of execution latency, which is then used to update the data flow graph. First, for each selected rule, this embodiment matches the rule with the data flow graph to determine its applicability. If the matching result is true, the rule is considered an optimization candidate for further use. Since the same component may meet multiple candidate rules simultaneously, this embodiment selects the rule that maximizes the reduction of execution latency for optimization. This strategy not only improves overall performance but also effectively avoids potential rule conflicts. For each candidate rule, the execution latency reduction value calculated during the platform configuration phase is first obtained, and then this value is compared with the current maximum latency reduction value. If the new value is larger, the maximum value is updated, and the current rule is marked as the optimal rule.

[0053] Specifically, each of the above-mentioned optimal rules is represented as a subgraph of a data flow graph. Step 101b2, which updates the data flow graph based on the selected optimal rules until the reconstructed target data flow graph is obtained, may further include steps 101b21 and 101b22: Step 101b21: Based on the input and output ports of the target data flow graph subgraph used to represent the optimal rule, encapsulate the data flow graph subgraph into a new component.

[0054] Step 101b22: Assign corresponding functional attributes to the new component and mark the new component as an optimizable component.

[0055] For example, regarding the updating of the data flow graph, this embodiment uses the obtained optimal rule to update the data flow graph, that is, to encapsulate the matched subgraph into a new component. The input and output ports of this subgraph become the input and output ports of the new component. Furthermore, the component is assigned corresponding functional attributes according to the rule type and marked as an optimizable component. It should be noted that this process is iterative. The tool continuously performs latency-sensitive matching to obtain new optimization candidates, and selects the optimal rule to update the data flow graph in each iteration until no new candidate rules exist.

[0056] It is understood that the data flow reconstruction process in this application embodiment mainly includes: 1. Constructing an initial data flow graph: parsing the input model file, extracting component attributes, inter-component connection relationships, and input / output port information, and constructing an initial data flow graph based on this; 2. Rule base matching and selection: selecting optimization rules that match the platform from a preset optimization rule base according to the configuration of the target hardware platform. Each optimization rule is defined in the form of a data flow subgraph with constraints, including component parameters, data types, and platform support information; 3. Latency-sensitive iterative optimization: with the goal of reducing execution latency, matching the selected optimization rules with the current data flow graph, evaluating and selecting the optimal rule that maximizes the reduction of latency from the successfully matched rules; updating the data flow graph using the optimal rule, and encapsulating the matched subgraph into a new optimizable component; repeating the matching, selection, and update steps until no new candidate rules are generated, resulting in the reconstructed data flow graph (i.e., the target data flow graph mentioned above).

[0057] Then, based on the reconstructed data flow graph and the instruction architecture of the deployment platform, the corresponding hardware instructions can be synthesized using inline assembly to generate deployable, high-performance embedded code.

[0058] Step 102: Perform topology analysis on the target data flow graph to determine the execution dependencies between components, and derive the code translation sequence based on the execution dependencies between components.

[0059] The components in the target data flow graph include: optimizable components and basic components; the code snippets corresponding to the optimizable components are hardware instructions, and the code snippets corresponding to the basic components are executable functional code.

[0060] For example, for the reconstructed data flow graph, a topology-based approach is used to analyze the connections between components, and the translation sequence is derived based on the dependencies. The components in the sequence can be divided into two categories: optimizable components and basic components. For optimizable components, corresponding hardware-specific instructions are generated to improve performance; while for basic components, corresponding code is directly generated based on their inherent functions.

[0061] Step 103: Generate code snippets for each component and integrate them according to the code translation order indicated by the code translation sequence to obtain the target code.

[0062] Exemplary examples, such as in the embodiments of this application, Figure 2 As shown, different code generation methods are used for optimizable components and basic components. For optimizable components, hardware instructions are translated and combined with the functional code directly generated from the basic components to obtain the final embedded code, i.e., the target code mentioned above.

[0063] Specifically, step 103 above, for the code generation of optimizable components, may further include the following steps 103a1 and 103a2: Step 103a1: For optimizable components, based on the deployment platform of the target code, the component function and data type of each optimizable component, match the hardware feature instructions corresponding to each optimizable component.

[0064] Step 103a2: Based on the hardware feature instructions corresponding to each optimizable component, generate assembly code corresponding to each optimizable component, and map the input and output data of the assembly code corresponding to each optimizable component to the input and output ports of each optimizable component.

[0065] For example, for code generation of optimizable components, the first step is to select appropriate hardware-specific instructions based on the target platform, component functionality, and data type. These factors affect the type of instructions generated by synthesis. For instance, for the "SaturationAdd" rule, different instructions need to be selected for synthesis if the data type is int or unsigned int. Subsequently, the tool generates inline assembly code representing the corresponding instructions and maps the input and output data to the input and output ports of the target component, respectively.

[0066] Specifically, in step 103 above, the code generation for the basic components may further include the following step 103b: Step 103b: For the basic components, generate corresponding functional code based on the component functions of each basic component.

[0067] For example, for basic components, the tool supports using custom dynamic link library (DLL) files to automatically generate corresponding code based on the component's functionality. It's important to note that even components of the same type may differ in their attributes (e.g., data types), leading to different generated code. Therefore, these key attributes are configured as parameters in the corresponding DLL file to generate accurate and matching code. Subsequently, the code generated for the basic and optimizable components is synthesized, and the function code for the target model is constructed according to the aforementioned translation sequence. Furthermore, relevant auxiliary information is encapsulated in specific header files for later use. Finally, the tool packages all generated code into a complete codebase ready for deployment.

[0068] The hardware instruction-based Simulink code generation method provided in this application first obtains the initial data flow graph of the target Simulink model and reconstructs it based on pre-set optimization rules to obtain the reconstructed target data flow graph. The optimization rules are used to reduce the execution latency of hardware instructions. Then, topology analysis is performed on the target data flow graph to determine the execution dependencies between components, and a code translation sequence is derived based on these dependencies. Finally, code snippets corresponding to each component are generated, and the generated code snippets are integrated according to the code translation order indicated by the code translation sequence to obtain the target code. The components in the target data flow graph include optimizable components and basic components. The code snippets corresponding to optimizable components are hardware instructions, and the code snippets corresponding to basic components are executable functional code. In this way, during the code generation process, candidate rules that maximize latency reduction can be selected to identify optimizable components, and corresponding hardware-specific instructions can be generated for the optimizable components, thereby producing efficient embedded code that can be directly deployed.

[0069] It should be noted that the hardware instruction-based Simulink code generation method provided in this application can be executed by a hardware instruction-based Simulink code generation device, or a control module within that device for executing the hardware instruction-based Simulink code generation method. This application uses the execution of the hardware instruction-based Simulink code generation method by a hardware instruction-based Simulink code generation device as an example to illustrate the hardware instruction-based Simulink code generation device provided in this application.

[0070] It should be noted that, in the embodiments of this application, the Simulink code generation methods based on hardware instructions shown in the accompanying drawings are all illustrated using one accompanying drawing from an embodiment of this application as an example. In specific implementations, the Simulink code generation methods based on hardware instructions shown in the accompanying drawings of the above methods can also be implemented in conjunction with any other accompanying drawings illustrated in the above embodiments, which will not be elaborated here.

[0071] The hardware instruction-based Simulink code generation apparatus provided in this application is described below. The hardware instruction-based Simulink code generation method described below can be referred to in correspondence with the hardware instruction-based Simulink code generation method described above.

[0072] Figure 4 A schematic diagram of the hardware instruction-based Simulink code generation device provided in the embodiments of this application is shown below. Figure 4 As shown, it specifically includes: The data flow graph reconstruction module 401 is used to obtain the initial data flow graph of the target Simulink model and reconstruct the initial data flow graph based on pre-set optimization rules to obtain the reconstructed target data flow graph; the optimization rules are used to reduce the execution latency of hardware instructions. The code generation module 402 is used to perform topology analysis on the target data flow graph, determine the execution dependencies between components, and derive the code translation sequence based on the execution dependencies between components; the code generation module 402 is also used to generate code fragments corresponding to each component, and integrate the generated code fragments according to the code translation order indicated by the code translation sequence to obtain the target code; wherein, the components in the target data flow graph include: optimizable components and basic components; the code fragments corresponding to optimizable components are hardware instructions, and the code fragments corresponding to basic components are executable functional code.

[0073] Optionally, the data flow graph reconstruction module 401 is specifically used to obtain multiple available optimization rules and the evaluation result of each available optimization rule; the evaluation result is used to characterize the reduction in latency of executing hardware instructions; the data flow graph reconstruction module 401 is further used to iteratively update the initial data flow graph based on the evaluation result of each available optimization rule until the reconstructed target data flow graph is obtained; wherein, the iterative update includes: using a latency-sensitive method to select the optimal rule that can maximize the reduction of execution latency from the multiple available optimization rules, and using the optimal rule to reconstruct the initial data flow graph.

[0074] Optionally, the data flow graph reconstruction module 401 is specifically used to determine the deployment platform of the target code and select multiple available optimization rules that match the deployment platform of the target code from the optimization rules pre-set in the rule base; the data flow graph reconstruction module 401 is also specifically used to evaluate each of the multiple available optimization rules to obtain the evaluation result of each available optimization rule.

[0075] Optionally, the data flow graph reconstruction module 401 is specifically used to determine the applicable optimization rules for each component based on the applicability matching results of the available optimization rules with the initial data flow graph, obtain multiple candidate rules, and determine the execution latency reduction value of each candidate rule based on the evaluation result of each candidate rule; one component corresponds to at least one candidate rule; the data flow graph reconstruction module 401 is further used to use a preset filtering method to filter out the optimal rule for data flow graph reconstruction from the multiple candidate rules, and update the data flow graph based on the filtered optimal rule until the reconstructed target data flow graph is obtained; wherein, the preset filtering method includes: if the execution latency reduction value of any target candidate rule among the multiple candidate rules is greater than the current maximum latency reduction value, then update the current latency reduction value based on the execution latency reduction value of the target candidate rule, and determine the target candidate rule as the optimal rule.

[0076] Optionally, each of the plurality of optimal rules is represented as a data flow graph subgraph; the data flow graph reconstruction module 401 is specifically used to encapsulate the data flow graph subgraph into a new component based on the input port and output port of the target data flow graph subgraph used to represent the optimal rule; the data flow graph reconstruction module 401 is further used to assign corresponding functional attributes to the new component and mark the new component as an optimizable component.

[0077] Optionally, the code generation module 402 is specifically used to match the hardware feature instructions corresponding to each optimizable component based on the deployment platform of the target code, the component function and data type of each optimizable component; the code generation module 402 is also specifically used to generate assembly code corresponding to each optimizable component based on the hardware feature instructions corresponding to each optimizable component, and map the input and output data of the assembly code corresponding to each optimizable component to the input and output ports of each optimizable component.

[0078] Optionally, the code generation module 402 is specifically used to generate corresponding functional code for each basic component based on the component function of each basic component.

[0079] Optionally, the code generation module 402 is specifically used to synthesize the code fragments corresponding to each optimizable component and the code fragments corresponding to each basic component, and to integrate the generated code fragments according to the code translation sequence to obtain the target code.

[0080] The hardware instruction-based Simulink code generation apparatus provided in this application first obtains the initial data flow graph of the target Simulink model and reconstructs the initial data flow graph based on pre-set optimization rules to obtain the reconstructed target data flow graph. The optimization rules are used to reduce the execution latency of hardware instructions. Then, topology analysis is performed on the target data flow graph to determine the execution dependencies between components, and a code translation sequence is derived based on these dependencies. Finally, code snippets corresponding to each component are generated, and the generated code snippets are integrated according to the code translation order indicated by the code translation sequence to obtain the target code. The components in the target data flow graph include optimizable components and basic components. The code snippets corresponding to optimizable components are hardware instructions, and the code snippets corresponding to basic components are executable functional code. In this way, during the code generation process, candidate rules that maximize latency reduction can be selected to identify optimizable components, and corresponding hardware-specific instructions can be generated for the optimizable components, thereby producing efficient embedded code that can be directly deployed.

[0081] Figure 5 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 5 As shown, the electronic device may include: a processor 510, a communications interface 520, a memory 530, and a communications bus 540, wherein the processor 510, the communications interface 520, and the memory 530 communicate with each other through the communications bus 540. The processor 510 can call logical instructions in the memory 530 to execute a hardware instruction-based Simulink code generation method. This method includes: first, obtaining an initial data flow graph of the target Simulink model and reconstructing the initial data flow graph based on pre-set optimization rules to obtain a reconstructed target data flow graph; the optimization rules are used to reduce the execution latency of hardware instructions; then, performing topology analysis on the target data flow graph to determine the execution dependencies between components and deriving a code translation sequence based on these dependencies; finally, generating code snippets corresponding to each component and integrating the generated code snippets according to the code translation order indicated by the code translation sequence to obtain target code; wherein the components in the target data flow graph include: optimizable components and basic components; the code snippets corresponding to optimizable components are hardware instructions, and the code snippets corresponding to basic components are executable functional code. In this way, during the code generation process, candidate rules that maximize latency reduction can be selected to identify optimizable components, and corresponding hardware-specific instructions can be generated for the optimizable components, thereby producing efficient embedded code that can be directly deployed.

[0082] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0083] On the other hand, this application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can execute the hardware instruction-based Simulink code generation method provided by the above methods. The method includes: first, obtaining an initial data flow graph of the target Simulink model, and reconstructing the initial data flow graph based on a pre-set optimization rule to obtain a reconstructed target data flow graph; the optimization rule is used to reduce the execution latency of hardware instructions; then, performing topology analysis on the target data flow graph to determine the execution dependencies between components, and deriving a code translation sequence based on the execution dependencies between components; finally, generating code fragments corresponding to each component, and integrating the generated code fragments according to the code translation order indicated by the code translation sequence to obtain target code; wherein, the components in the target data flow graph include: optimizable components and basic components; the code fragments corresponding to optimizable components are hardware instructions, and the code fragments corresponding to basic components are executable functional code. In this way, during the code generation process, candidate rules that maximize latency reduction can be selected to identify optimizable components, and corresponding hardware-specific instructions can be generated for the optimizable components, thereby producing efficient embedded code that can be directly deployed.

[0084] Furthermore, this application also provides a computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program is implemented to execute the aforementioned hardware instruction-based Simulink code generation methods. This method includes: first, obtaining an initial data flow graph of a target Simulink model, and reconstructing the initial data flow graph based on pre-set optimization rules to obtain a reconstructed target data flow graph; the optimization rules are used to reduce the execution latency of hardware instructions; then, performing topology analysis on the target data flow graph to determine the execution dependencies between components, and deriving a code translation sequence based on the execution dependencies between components; finally, generating code fragments corresponding to each component, and integrating the generated code fragments according to the code translation order indicated by the code translation sequence to obtain target code; wherein the components in the target data flow graph include: optimizable components and basic components; the code fragments corresponding to optimizable components are hardware instructions, and the code fragments corresponding to basic components are executable functional code. Thus, during the code generation process, candidate rules that maximize latency reduction can be selected to identify optimizable components, and corresponding hardware-specific instructions can be generated for the optimizable components, thereby producing efficient embedded code that can be directly deployed.

[0085] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0086] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A Simulink code generation method based on hardware instructions, characterized in that, include: The initial data flow graph of the target Simulink model is obtained, and the initial data flow graph is reconstructed based on pre-set optimization rules to obtain the reconstructed target data flow graph; the optimization rules are used to reduce the execution latency of hardware instructions. Perform topology analysis on the target data flow graph to determine the execution dependencies between components, and derive the code translation sequence based on the execution dependencies between components; Each component's corresponding code snippet is generated separately, and the generated code snippets are integrated according to the code translation order indicated by the code translation sequence to obtain the target code; The components in the target data flow graph include: optimizable components and basic components; the code snippets corresponding to the optimizable components are hardware instructions, and the code snippets corresponding to the basic components are executable functional code.

2. The method according to claim 1, characterized in that, The process of reconstructing the initial data flow graph based on pre-set optimization rules to obtain the reconstructed target data flow graph includes: Obtain multiple available optimization rules and the evaluation result of each available optimization rule; the evaluation result is used to characterize the reduction in latency of executing hardware instructions; Based on the evaluation results of each available optimization rule, the initial data flow graph is iteratively updated until the reconstructed target data flow graph is obtained; The iterative update includes: using a latency-sensitive method to select the optimal rule from the multiple available optimization rules that can maximize the reduction of execution latency, and using the optimal rule to reconstruct the initial data flow graph.

3. The method according to claim 2, characterized in that, The process of obtaining multiple available optimization rules and the evaluation results of each available optimization rule includes: The deployment platform of the target code is determined, and multiple available optimization rules that match the deployment platform of the target code are selected from the pre-set optimization rules in the rule base; Each of the multiple available optimization rules is evaluated to obtain the evaluation result of each available optimization rule.

4. The method according to claim 2, characterized in that, The process of iteratively updating the initial data flow graph based on the evaluation results of each available optimization rule until the reconstructed target data flow graph is obtained includes: Based on the applicability matching results of the available optimization rules with the initial data flow graph, the applicable available optimization rules for each component are determined, resulting in multiple candidate rules. Based on the evaluation results of each candidate rule, the reduction value of execution latency for each candidate rule is determined; each component corresponds to at least one candidate rule. The optimal rule for data flow graph reconstruction is selected from the multiple candidate rules using a preset filtering method, and the data flow graph is updated based on the selected optimal rule until the reconstructed target data flow graph is obtained. The preset filtering method includes: if the execution latency reduction value of any target candidate rule among the plurality of candidate rules is greater than the current maximum latency reduction value, then the current latency reduction value is updated based on the execution latency reduction value of the target candidate rule, and the target candidate rule is determined as the optimal rule.

5. The method according to claim 4, characterized in that, Each of the multiple optimal rules is represented as a subgraph of a data flow graph; The process of updating the data flow graph based on the selected optimal rules until the reconstructed target data flow graph is obtained includes: Based on the input and output ports of the target data flow graph subgraph used to represent the optimal rule, the data flow graph subgraph is encapsulated into a new component; Assign corresponding functional attributes to the new component and mark the new component as an optimizable component.

6. The method according to claim 1, characterized in that, The step of generating code snippets corresponding to each component includes: For optimizable components, based on the deployment platform of the target code, the component function and data type of each optimizable component, the hardware feature instructions corresponding to each optimizable component are matched; Based on the hardware feature instructions corresponding to each optimizable component, the assembly code corresponding to each optimizable component is generated, and the input and output data of the assembly code corresponding to each optimizable component are mapped to the input and output ports of each optimizable component.

7. The method according to claim 1, characterized in that, The step of generating code snippets corresponding to each component includes: For basic components, corresponding functional code is generated based on the component functions of each basic component.

8. The method according to any one of claims 1 to 7, characterized in that, The process of integrating the generated code fragments according to the code translation sequence indicated by the code translation sequence to obtain the target code includes: The code snippets corresponding to each optimizable component and each basic component are combined, and the generated code snippets are integrated according to the code translation sequence to obtain the target code.

9. A Simulink code generation device based on hardware instructions, characterized in that, The device includes: The data flow graph reconstruction module is used to obtain the initial data flow graph of the target Simulink model and reconstruct the initial data flow graph based on pre-set optimization rules to obtain the reconstructed target data flow graph; the optimization rules are used to reduce the execution latency of hardware instructions. The code generation module is used to perform topology analysis on the target data flow graph, determine the execution dependencies between components, and derive the code translation sequence based on the execution dependencies between components; The code generation module is also used to generate code fragments corresponding to each component, and to integrate the generated code fragments according to the code translation order indicated by the code translation sequence to obtain the target code; The components in the target data flow graph include: optimizable components and basic components; the code snippets corresponding to the optimizable components are hardware instructions, and the code snippets corresponding to the basic components are executable functional code.

10. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the hardware instruction-based Simulink code generation method as described in any one of claims 1 to 8.

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