RISC-V vector extension-oriented cross-function vector register cooperative allocation method and device

Abstract

This invention relates to the field of computer technology and provides a method and apparatus for cross-function vector register collaborative allocation for RISC-V vector extensions. The method includes: performing cross-function data flow analysis on the program to identify active vector registers and construct an active information set; establishing LMUL constraint propagation relationships based on this and determining the target LMUL configuration; performing collaborative vector register allocation between the caller and callee based on the active information set and the target LMUL configuration, and establishing a register mapping relationship; performing overflow optimization based on vector characteristics for vector data that cannot be retained; and collaboratively maintaining the vector execution context at function call boundaries. This invention can reduce register reallocation and overflow overhead during cross-function calls, reduce memory access pressure, and improve RISC-V vector register resource utilization and program execution efficiency.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method and apparatus for cross-function vector register collaborative allocation for RISC-V vector extension. Background Technology

[0002] RISC-V Vector Extension (RVV) employs a variable vector length and register set length multiplier (LMUL) mechanism, enabling a single vector instruction to dynamically adjust its computational granularity based on runtime hardware resources. It also significantly improves the flexibility and scalability of vector computation by concatenating multiple physical registers into a logical register set.

[0003] Current compilers often limit vector register allocation to the scope within functions, typically employing a conservative strategy at function call boundaries: overflowing active registers into memory before the call and reloading them upon return. For the RVV architecture, this approach presents several problems: First, there's a lack of coordinated allocation between the calling and called functions, resulting in invalid release or reallocation of active register data across functions, leading to low utilization. Second, when LMUL is greater than 1, logical registers occupy multiple physical registers, and overflowing the entire set significantly increases memory access frequency and overhead. Third, the continuous occupancy of register sets is not maintained before and after the function call, potentially requiring register rearrangement upon return. Fourth, inconsistent LMUL configurations between the calling and calling functions, coupled with a lack of constraint propagation and coordination mechanisms, easily lead to register resource fragmentation.

[0004] Therefore, how to achieve coordinated allocation of vector registers across function scopes and reduce overflow and reload overhead has become a pressing technical problem that needs to be solved. Summary of the Invention

[0005] This invention provides a cross-function vector register collaborative allocation method and apparatus for RISC-V vector extension, which solves the problems of low vector register utilization and large overflow overhead in the prior art when cross-function calls, and realizes cross-function collaborative allocation of vector registers and on-demand overflow optimization.

[0006] This invention provides a cross-function vector register cooperative allocation method for RISC-V vector extension, comprising the following steps: Perform cross-function range data flow analysis on the program, identify vector register data that remain active at function call boundaries, and construct a cross-function vector activity information set; Based on the cross-function vector active information set, a register group length multiplication factor constraint propagation relationship is established between the calling function and the called function, and consistency modeling and constraint convergence are performed to determine the target register group length multiplication factor configuration that satisfies the cross-function register reuse condition. Based on the cross-function vector activity information set and the target register group length multiplication factor configuration, the vector registers of the calling function and the called function are collaboratively allocated; For vector data that cannot be retained in the vector register, overflow optimization processing based on vector characteristics is performed. The overflow optimization processing includes dynamically pruning the range of valid elements in the physical register according to the vector execution context, splitting the logical register group and performing hierarchical overflow according to the active probability, and delaying or merging the overflow operation. The vector execution context is collaboratively maintained at the function call boundary, and the vector execution context includes vector length, element width, and mask state.

[0007] In some implementations, the step of performing cross-function range data flow analysis on the program, identifying vector register data that remains active at function call boundaries, and constructing a cross-function vector activity information set includes: constructing the program's function call graph and the control flow graph of each function; based on the function call graph and the control flow graph, performing activity analysis and cross-function activity information propagation on the vector registers within each function, determining whether each vector register still retains valid data at the function call boundary; identifying vector registers that retain valid data as vector registers that remain active at the function call boundary; and recording the register group occupancy status, register group length multiplication factor configuration, and the physical register starting number and continuous occupancy range at the function call boundary of the identified vector registers to construct the cross-function vector activity information set.

[0008] In some implementations, the step of establishing a register group length multiplication factor constraint propagation relationship between the calling function and the called function based on the cross-function vector activity information set, and performing consistency modeling and constraint convergence to determine the target register group length multiplication factor configuration that satisfies the cross-function register reuse condition includes: based on the cross-function vector activity information set, passing the register group length multiplication factor configuration corresponding to the active vector registers in the calling function as a constraint condition to the called function, establishing a register group length multiplication factor constraint relationship between the calling function and the called function at the function call boundary; performing consistency modeling on the register group length multiplication factor configurations of the calling function and the called function respectively based on the physical register alignment rules and register group continuous occupancy constraints to obtain a cross-function register allocation constraint model; and iteratively adjusting the cross-function register allocation constraint model with the optimization objectives of minimizing the number of register reallocations, avoiding register group splitting, and reducing the overflow trigger probability until the constraint convergence condition is met to obtain the target register group length multiplication factor configuration.

[0009] In some implementations, the step of coordinating the allocation of vector registers for the calling and called functions based on the cross-function vector activity information set and the target register group length multiplication factor configuration includes: performing unified physical register allocation on the cross-function active vector registers in the calling and called functions based on the cross-function vector activity information set and the target register group length multiplication factor configuration; establishing a vector register mapping table at the function call boundary, wherein the mapping table describes the correspondence between the physical register numbers before and after the call, and records the corresponding register group length multiplication factor configuration and activity status identifier; and after the function call returns, quickly restoring or directly reusing the vector register state based on the correspondence in the mapping table.

[0010] In some implementations, for vector data that cannot be retained in the vector register, overflow optimization processing based on vector characteristics is performed, including: dynamically pruning the effective element range in the physical register according to the real-time vector length, element width, and mask state to determine the effective data range to be overflowed, wherein the size of the effective data range is determined by the product of the vector length and the byte width corresponding to the element width, and only the data in the effective data range is written back to memory; for logical register groups with a register group length multiplication factor greater than 1, the logical register group is split into multiple physical register sub-units; priority sorting is performed according to the activity probability of each physical register sub-unit in subsequent basic blocks, and partial overflow or hierarchical saving is performed according to the priority order, wherein the starting physical register number of each physical register sub-unit satisfies the register group alignment constraint; under the premise of satisfying the register group alignment constraint, the overflow operation is delayed to the last non-vector operation position before the function call; for multiple consecutive function calls sharing the same vector execution context, redundant overflow operations and reload operations are merged.

[0011] In some implementations, the vector execution context is collaboratively maintained at the function call boundary, including: at the function call boundary, obtaining the vector execution context established before the call, the vector execution context including vector length, element width, and mask state; passing the vector execution context to the called function, enabling the called function to reuse the vector state configured before the call, and maintaining the consistency of the vector execution context during the function call; and, under the premise of satisfying the program execution semantics, identifying and eliminating redundant vector configuration instruction sequences, the redundant vector configuration instruction sequences including vector length setting instructions, element width setting instructions, or mask state setting instructions that are repeated with the established vector execution context.

[0012] The present invention also provides a cross-function vector register cooperative allocation device for RISC-V vector extension, comprising the following modules: The cross-function analysis module is used to perform cross-function range data flow analysis on the program, identify vector register data that remains active at the function call boundary, and construct a cross-function vector activity information set; The constraint modeling module is used to establish a register group length multiplication factor constraint propagation relationship between the calling function and the called function based on the cross-function vector activity information set, and to perform consistency modeling and constraint convergence to determine the target register group length multiplication factor configuration that satisfies the cross-function register reuse condition. The collaborative allocation module is used to collaboratively allocate the vector registers of the calling function and the called function according to the cross-function vector activity information set and the target register group length multiplication factor configuration; The overflow optimization module is used to perform overflow optimization processing based on vector characteristics for vector data that cannot be retained in the vector register. The overflow optimization processing includes dynamically pruning the range of valid elements in the physical register according to the vector execution context, splitting the logical register group and performing hierarchical overflow according to the active probability, and delaying or merging the overflow operation. The context maintenance module is used to collaboratively maintain the vector execution context at the function call boundary. The vector execution context includes the vector length, element width, and mask state.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the cross-function vector register cooperative allocation method for RISC-V vector extension as described above.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the cross-function vector register cooperative allocation method for RISC-V vector extension as described above.

[0015] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the cross-function vector register cooperative allocation method for RISC-V vector extension as described above.

[0016] This invention provides a method and apparatus for cross-function vector register collaborative allocation for RISC-V vector extensions, which offers the following advantages: By performing cross-function range data flow analysis on the program and constructing a cross-function vector activity information set, the compiler can identify vector data that still needs to be maintained at function call boundaries, avoiding blind release and reallocation caused by the lack of cross-function information in existing technologies, thereby improving the overall utilization rate of vector registers; by establishing a register set length multiplication factor constraint propagation relationship between the calling function and the called function and performing consistency modeling and constraint convergence, both parties adopt compatible register occupancy granularity before and after function calls, avoiding register resource fragmentation caused by inconsistent configurations; and by coordinating the vector registers of the calling function and the called function... The allocation ensures that vector registers active across functions remain continuously occupied or consistently mapped before and after function calls, avoiding the additional instruction overhead of register reordering. For vector data that cannot be retained in registers, overflow optimization based on vector characteristics is performed. This includes dynamically pruning the effective element range according to the vector execution context, splitting the logical register group and overflowing in stages according to active probability, and delaying or merging overflow operations. This ensures that overflow operations only target the effective data range and are selectively saved according to priority, thereby reducing the number of memory accesses and sudden memory access latency. By coordinating the maintenance of vector execution context, such as vector length, element width, and mask state, at function call boundaries, duplicate vector configuration instructions are avoided, maintaining a consistent vector execution context across function scopes. In summary, this invention achieves the reuse and on-demand overflow of vector registers across function scopes while ensuring the semantic correctness of the program, reducing register overflow overhead and execution latency along the function call path. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is one of the flowcharts illustrating the cross-function vector register collaborative allocation method for RISC-V vector extension provided by this invention.

[0019] Figure 2 This is the second flowchart of the cross-function vector register collaborative allocation method for RISC-V vector extension provided by this invention.

[0020] Figure 3This is a diagram illustrating the key mechanism for cross-function vector register collaborative allocation provided by this invention.

[0021] Figure 4 This is one of the structural schematic diagrams of the cross-function vector register collaborative allocation device for RISC-V vector extension provided by the present invention.

[0022] Figure 5 This is the second schematic diagram of the cross-function vector register collaborative allocation device for RISC-V vector extension provided by the present invention.

[0023] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0025] The terminology involved in this invention will be explained below.

[0026] Vector Length (VL) refers to the number of vector elements involved in the calculation in the RVV instruction, and can be dynamically configured at runtime.

[0027] The register set length multiplier (LMUL) is the multiplication factor in RVV that combines multiple physical vector registers into a single logical vector register set.

[0028] The mask (vmask) refers to the state of the mask register in the RVV instruction, which controls whether each vector element participates in the operation.

[0029] Standard Element Width (SEW) refers to the bit width of each vector element in the RVV instruction.

[0030] A call graph is a directed graph used in a compiler to describe the call relationships between functions.

[0031] A control flow graph (CFG) is a graph structure used in a compiler to describe the jump relationships between basic blocks within a function.

[0032] Intermediate Representation (IR) refers to the program representation in the compiler that lies between the source code and the machine code.

[0033] A scalar is a single data element that is used in operations, as opposed to vector operations.

[0034] Single Instruction Multiple Data (SIMD) refers to a parallel computing architecture that processes multiple data points simultaneously with a single instruction.

[0035] Just-In-Time (JIT) compilation refers to a compilation technique that compiles a program at runtime.

[0036] This invention provides a cross-function vector register collaborative allocation method and apparatus for RISC-V vector extension. By performing unified analysis and collaborative optimization of vector register usage status, LMUL configuration and vector execution context across function scopes, it reduces unnecessary register overflow and reload operations, lowers function call overhead and improves vector computation performance while ensuring program semantic correctness.

[0037] The following is combined with Figures 1-6 The embodiments of the present invention are described in detail.

[0038] The cross-function vector register collaborative allocation method for RISC-V vector extension provided in this embodiment of the invention is executed by a cross-function vector register collaborative allocation device for RISC-V vector extension. This device can be configured in a computer, which can be a local computer or a cloud computer. The local computer can be a computer, tablet, etc., and no specific limitation is made here.

[0039] Figure 1 This is a flowchart illustrating the cross-function vector register cooperative allocation method for RISC-V vector extension provided by the present invention, as shown below. Figure 1 As shown, the method includes the following steps: S110. Perform cross-function range data flow analysis on the program, identify vector register data that remain active at the function call boundary, and construct a cross-function vector activity information set.

[0040] According to the present invention, a cross-function vector register collaborative allocation method for RISC-V vector extension is provided. This method performs cross-function range data flow analysis on the program, identifies vector register data that remains active at function call boundaries, and constructs a cross-function vector activity information set. The method includes: constructing the program's function call graph and the control flow graph of each function; based on the function call graph and control flow graph, performing activity analysis and cross-function activity information propagation on the vector registers within each function, determining whether each vector register still holds valid data at the function call boundary; identifying vector registers that retain valid data as vector registers that remain active at the function call boundary; and recording the register group occupancy, LMUL configuration, and the starting physical register number and continuous occupancy range at the function call boundary of the identified vector registers to construct the cross-function vector activity information set.

[0041] Specifically, when performing cross-function scope vector register cooperative allocation in a program, cross-function vector liveness analysis is performed first. The compiler constructs the function call graph of the program to be compiled and the control flow graph within each function. Based on the constructed function call graph and control flow graph, the compiler performs liveness analysis on the vector registers within each function to determine whether each vector register still retains valid data at the function call boundary. Specifically, if a vector register will be used on the program path after the current function call point, and its definition point is located within the current function or passed from the calling function, then the vector register is considered to be active at the function call boundary. The compiler identifies vector registers that retain valid data as vector registers that are active at the function call boundary. The compiler records the register set occupancy of each identified active vector register, the LMUL configuration corresponding to the register set, and the physical register starting number and continuous occupancy range of the active vector register at the function call boundary. Based on the above recorded information, the compiler constructs a cross-function vector liveness information set, which is used for subsequent register set length multiplication factor constraint propagation and cooperative allocation.

[0042] This embodiment constructs function call graphs and control flow graphs, and performs cross-function range activity analysis on vector registers within each function. This allows for the accurate identification of vector registers and their register group occupancy information that still hold valid data at function call boundaries. This provides an accurate cross-function activity information basis for subsequent register collaborative allocation, avoiding blind register release and reallocation caused by the lack of cross-function information in existing technologies, and improving the utilization efficiency of vector registers across function ranges.

[0043] S120. Based on the cross-function vector active information set, establish a register group length multiplication factor constraint propagation relationship between the calling function and the called function, and perform consistency modeling and constraint convergence to determine the target LMUL configuration that satisfies the cross-function register reuse condition.

[0044] According to the present invention, a cross-function vector register collaborative allocation method for RISC-V vector extension is provided. Based on the cross-function vector activity information set, a register set length multiplication factor constraint propagation relationship is established between the calling function and the called function. Consistency modeling and constraint convergence are then performed to determine the target LMUL configuration that satisfies the cross-function register reuse condition. The method includes: based on the cross-function vector activity information set, the LMUL configurations corresponding to the active vector registers in the calling function are passed to the called function as constraints, establishing a register set length multiplication factor constraint relationship between the calling and called functions at the function call boundary; based on physical register alignment rules and register set contiguous occupancy constraints, consistency modeling is performed on the respective register LMUL configurations of the calling and called functions to obtain a cross-function register allocation constraint model; with the optimization objectives of minimizing the number of register reallocations, avoiding register set splitting, and reducing the overflow trigger probability, the cross-function register allocation constraint model is iteratively adjusted until the constraint convergence condition is met, thus obtaining the target LMUL configuration.

[0045] Specifically, during LMUL constraint propagation and consistency modeling, the compiler first uses the cross-function vector activity information set to pass the LMUL configurations corresponding to the active vector registers in the calling function as constraints to the called function. Specifically, if an active vector register in the calling function uses a specific LMUL value (e.g., LMUL=2), this LMUL configuration is passed to the called function as a constraint, requiring the called function to use a compatible LMUL configuration when allocating vector registers, thus establishing an LMUL constraint relationship between the calling and called functions at the function call boundary. The compiler then performs consistency modeling of the LMUL configurations of the calling and called functions based on physical register alignment rules and register set contiguous occupancy constraints. Physical register alignment rules require that the starting position of the logical register set in the physical register file must meet alignment conditions; for example, when LMUL=2, the starting physical register number must be even. Register set contiguous occupancy constraints require that multiple physical registers belonging to the same logical register set be consecutively numbered. Based on these rules and constraints, the compiler constructs a cross-function register allocation constraint model. The compiler iteratively adjusts the cross-function register allocation constraint model with the optimization goals of minimizing the number of register reallocations, avoiding register set splits, and reducing the probability of overflow triggering. During the iteration process, if a conflict is found between the LMUL configurations of the calling and called functions, or if a register set split is caused, the constraint is gradually converged by adjusting the allocation order of inactive registers or appropriately modifying the LMUL configuration value until the constraint convergence condition is met, and finally the target LMUL configuration is obtained.

[0046] This embodiment passes the LMUL configuration of the active vector register in the calling function as a constraint to the called function, and performs consistency modeling and iterative convergence based on the physical register alignment rules and continuous occupancy constraints. This ensures that the calling and called functions use compatible LMUL configurations at the function call boundary, avoiding register resource fragmentation and register group splitting caused by inconsistent configurations, and reducing the number of register reallocations and overflow trigger probability during cross-function calls.

[0047] S130. Based on the cross-function vector activity information set and the target LMUL configuration, coordinate the allocation of vector registers for the calling function and the called function.

[0048] According to the present invention, a cross-function vector register collaborative allocation method for RISC-V vector extension is provided. Based on a cross-function vector activity information set and a target LMUL configuration, the method collaboratively allocates vector registers for the calling and called functions. This includes: performing unified physical register allocation for cross-function active vector registers in the calling and called functions based on the cross-function vector activity information set and the target LMUL configuration; establishing a vector register mapping table at the function call boundary, whereby the mapping table describes the correspondence between physical register numbers before and after the call, and records the corresponding LMUL configuration and activity status identifier; and after the function call returns, quickly restoring or directly reusing the vector register state based on the correspondence in the mapping table.

[0049] Specifically, during vector register cooperative allocation, the compiler performs unified physical register allocation for cross-function active vector registers in both the calling and called functions, based on the cross-function vector activity information set and the target LMUL configuration obtained through constraint convergence. Specifically, during allocation, the compiler ensures that cross-function active vector registers maintain continuous physical register positions or satisfy a consistent mapping relationship before and after the function call. That is, if an active vector register is allocated a specific physical register set in the calling function, the compiler prioritizes maintaining the same physical register starting number and continuous occupied range when allocating registers for the called function, thereby avoiding register set splitting or rearrangement operations caused by register reallocation. Subsequently, the compiler establishes a vector register mapping table at the function call boundary. This mapping table describes the correspondence between physical register numbers before and after the call, and records the corresponding LMUL configuration and active status flag. For example, the mapping table contains the following entries: physical register numbers v8 to v15 before the call (corresponding to LMUL=2), physical register numbers v8 to v15 after the call, and an active status flag indicating validity. After the function call returns, the compiler quickly restores or directly reuses the vector register state according to the corresponding relationship in the mapping table: if the register numbers before and after the call are the same in the mapping table, the existing data in the register is directly reused; if the numbers are different, the register data is restored from the position after the call to the position before the call according to the mapping relationship.

[0050] This embodiment performs unified physical register allocation on the vector registers active across functions in both the calling and called functions, and establishes a mapping table at the function call boundary to record the correspondence between register numbers. This ensures that the vector registers active across functions remain continuously occupied or mapped consistently before and after the function call, avoiding register set splitting or rearranging operations introduced by register reallocation. Furthermore, it enables rapid restoration or direct reuse of register states after the function returns, thereby reducing additional instruction overhead and execution latency.

[0051] S140. For vector data that cannot be retained in the vector register, perform overflow optimization processing based on vector characteristics. Overflow optimization processing includes dynamically pruning the range of valid elements in the physical register according to the vector execution context, splitting the logical register group and performing hierarchical overflow according to the active probability, and delaying or merging the overflow operation.

[0052] According to the present invention, a cross-function vector register collaborative allocation method for RISC-V vector extension is provided. For vector data that cannot be retained in the vector register, overflow optimization processing based on vector characteristics is performed, including: dynamically pruning the effective element range in the physical register according to the real-time VL, SEW, and vmask states to determine the effective data range to be overflowed, wherein the size of the effective data range is determined by the product of the byte widths corresponding to VL and SEW, and only the data within the effective data range is written back to memory; for logical register groups with a register group length multiplication factor greater than 1, the logical register group is split into multiple physical register sub-units; priority sorting is performed according to the activity probability of each physical register sub-unit in subsequent basic blocks, and partial overflow or hierarchical saving is performed according to the priority order, wherein the starting physical register number of each physical register sub-unit satisfies the register group alignment constraint; under the premise of satisfying the register group alignment constraint, the overflow operation is delayed to the last non-vector operation position before the function call; for multiple consecutive function calls sharing the same vector execution context, redundant overflow operations and reload operations are merged.

[0053] Specifically, during overflow optimization based on vector characteristics, for vector data that cannot be retained in the vector register, the compiler first dynamically trims the range of valid elements in the physical register based on the real-time VL, SEW, and vmask states to determine the valid data range to be overflowed. The size of this valid data range is determined by the product of the byte widths of VL and SEW. For example, when VL is 8 bytes and SEW is 4 bytes, the size of the valid data range is 32 bytes. The compiler only writes the data within this valid data range back to memory, and does not write back invalid data in the register that exceeds the valid range. For logical register sets with a register set length multiplication factor greater than 1 (e.g., LMUL=2, occupying two consecutive physical registers), the compiler splits the logical register set into multiple physical register subunits.

[0054] The compiler prioritizes physical register sub-units based on their probability of being active in subsequent basic blocks. Sub-units with higher activity probabilities are retained in registers first, while those with lower activity probabilities undergo overflow saving first, and partial overflow or hierarchical saving is performed according to priority. During this process, the initial physical register number of each physical register sub-unit satisfies register set alignment constraints; for example, when LMUL=2, the initial physical register number is even. Furthermore, while satisfying register set alignment constraints, the compiler uses instruction scheduling techniques to delay overflow operations until the last non-vector operation before the function call, preventing premature overflow that could lead to register data being written back prematurely. For multiple consecutive function calls sharing the same vector execution context, the compiler merges redundant overflow and reload operations. That is, if multiple consecutive function calls share the same vector register active state and LMUL configuration, only one overflow save is performed, and subsequent calls directly reuse the saved register state.

[0055] This embodiment dynamically trims the valid data range based on the real-time VL, SEW, and vmask states, writing only valid data back to memory to avoid memory access operations for invalid data. By splitting the logical register group into physical register sub-units and grading overflow according to active probability, the latency of a single burst memory access is reduced. By delaying the overflow operation to the last non-vector operation position before the function call and merging redundant memory access operations of consecutive calls, the number of overflow operations and memory bandwidth usage are reduced. Thus, while ensuring the correctness of register allocation, the memory access overhead of vector register overflow is significantly reduced.

[0056] S150. Cooperatively maintain the vector execution context at the function call boundary. The vector execution context includes the VL, SEW, and vmask states.

[0057] According to the present invention, a cross-function vector register collaborative allocation method for RISC-V vector extension is provided, which collaboratively maintains the vector execution context at the function call boundary. The method includes: at the function call boundary, obtaining the vector execution context established before the call, the vector execution context including VL, SEW, and vmask states; passing the vector execution context to the called function, enabling the called function to reuse the vector states configured before the call, and maintaining the consistency of the vector execution context during the function call; and, under the premise of satisfying program execution semantics, identifying and eliminating redundant vector configuration instruction sequences, including VL setting instructions, SEW setting instructions, or vmask state setting instructions that are repeated with the established vector execution context.

[0058] Specifically, during the coordinated maintenance of the vector execution context, the compiler first obtains the vector execution context established before the function call boundary. This vector execution context includes the VL, SEW, and vmask states. Specifically, the compiler records the VL value, SEW value, and vmask register state information set by the last vector configuration instruction in the current function. Subsequently, the compiler passes this vector execution context to the called function, allowing the called function to reuse the vector states configured before the call. For example, if the calling function has set VL to 128, SEW to 4 bytes, and vmask to fully enabled, the called function does not need to re-execute the vector configuration instructions at its entry point and can directly reuse this configuration state, thereby maintaining the consistency of the vector execution context during function calls.

[0059] While satisfying the semantics of program execution, the compiler also identifies and eliminates redundant vector configuration instruction sequences. Specifically, the compiler analyzes the vector configuration instructions in the called function. If a VL setting instruction sets a value that is the same as a VL already established before the call, and a SEW setting instruction sets a value that is the same as a SEW already established before the call, then that vector configuration instruction is identified as redundant and deleted. Similarly, for vmask state setting instructions, if the setting result is consistent with the vmask state before the call, it is also identified as redundant and deleted. Through the above redundant instruction elimination operation, the compiler avoids repeatedly inserting vector configuration instructions that overlap with the established context at the function call boundary.

[0060] This embodiment obtains the vector execution context established before the function call at the function call boundary and passes it to the called function, allowing the called function to reuse the vector state configured before the call, thus avoiding the repeated execution of vector configuration instructions. At the same time, by identifying and eliminating VL setting instructions, SEW setting instructions, and vmask state setting instructions that are duplicated with the established context, redundant vector configuration operations are reduced. Thus, while maintaining the consistency of cross-function vector execution context, the overhead of vector configuration instructions is reduced, and program execution efficiency is improved.

[0061] The technical solution of the present invention will be further illustrated below through overall embodiments.

[0062] Example 1: This embodiment provides a cross-function vector register cooperative allocation method for RISC-V vector extension, including the following steps: Step S1: Cross-function vector activity analysis.

[0063] During the compilation phase, cross-function range data flow analysis is performed on the program to identify vector register data that remains active at the function call boundary, construct a cross-function vector activity information set, record the corresponding vector register group occupancy and its LMUL configuration, and identify the starting register number and continuous occupancy range of the vector register at the function call boundary.

[0064] Step S2: LMUL constraint propagation and consistency modeling.

[0065] Based on the cross-function vector activity information set, an LMUL constraint propagation relationship is established between the calling and called functions. According to the physical alignment rules of RVV vector registers and the continuous occupancy constraint of register sets, the consistency model of the LMUL configuration of each function is performed. A constraint convergence strategy is used to determine the target LMUL configuration that satisfies the cross-function register reuse condition, ensuring that the granularity of vector register set occupancy remains compatible before and after function calls. Iterative adjustments are made with the goals of minimizing the number of register reallocations, avoiding register set splitting, and reducing the probability of overflow triggering.

[0066] Step S3: Cooperative allocation of vector registers and maintenance of continuity.

[0067] During the register allocation phase, based on cross-function activity information and LMUL constraints, the vector registers of the calling and called functions are allocated collaboratively. This ensures that the physical register positions of cross-function active vector registers remain continuous or mappable consistent before and after the function call, thereby avoiding register set rearrangement. A vector register mapping table is established at the function call boundary to describe the correspondence between the physical register numbers before and after the call. This mapping table is used to guide the rapid restoration or direct reuse of vector register states after the function call returns.

[0068] Step S4: Overflow optimization based on vector characteristics.

[0069] For vector data that cannot be fully retained in registers, overflow optimization strategies based on RVV characteristics are adopted, including: On-demand overflow based on execution context: The effective element range in the physical register is dynamically pruned according to the real-time VL, SEW, and vmask states; the overflow data block size is determined by VL and SEW, and the number of overflow data bytes is the product of the corresponding byte widths of VL and SEW; based on the effective element range, only the corresponding data interval is written back to memory to reduce invalid memory access bandwidth usage. Physically aligned hierarchical overflow: For logical register groups with LMUL>1, they are split into multiple independent physical register sub-units. The sub-units are prioritized according to their activity probability in subsequent basic blocks, and partial overflow or hierarchical saving is performed to reduce the latency of single burst memory access and ensure that the starting physical register number of the sub-units meets the RVV register group alignment constraint. Delayed Overflow and State Merging: Under the premise of satisfying register pressure constraints, instruction scheduling techniques are used to postpone overflow operations to the last non-vector operation slot before the function call; at the same time, if multiple consecutive function calls share the same vector execution context, redundant overflow and reload instructions are merged.

[0070] Step S5: Cooperative maintenance of vector execution context.

[0071] At the function call boundary, the vector execution context is maintained collaboratively, including the passing of VL, SEW, and vmask states; and the established vector configuration state is reused before and after the call to avoid repeatedly inserting vector configuration instructions, so as to maintain the consistency of cross-function vector execution context, and eliminate redundant vector configuration instruction sequences while satisfying execution semantics.

[0072] Example 2: This embodiment provides a detailed flowchart of a cross-function vector register cooperative allocation method for RISC-V vector extension, which runs in a compiler system and mainly includes the following steps (corresponding to method schemes S1–S5): Figure 2 As shown.

[0073] Step S1: Cross-function vector activity analysis 1. Function call relationship analysis CallGraph for compiler build process; Analyze the call relationships between functions and the basic block control flow graph (CFG).

[0074] 2. Cross-function register liveness identification Perform liveness analysis on the vector registers within each function; Determine which registers still hold valid data at the function call boundary.

[0075] 3. Information Set Construction Construct a cross-function vector activity information set, recording: vector register number, register group occupancy status, LMUL configuration, starting register number, and continuous occupancy range.

[0076] Output: A set of activity information across function vectors, providing input for the constraint modeling module.

[0077] Step S2: LMUL Constraint Propagation and Consistency Modeling 1. LMUL constraint propagation Establish LMUL constraints between the calling function and the called function; By combining physical register alignment rules and contiguous occupancy constraints, cross-function register group granularity compatibility is ensured.

[0078] 2. Constraint Model Construction The LMUL configuration and register group continuity requirements of each function are transformed into a unified constraint model.

[0079] 3. Constrained Convergence Strategy The constraints are converged through iterative adjustments. Optimization goals: Minimize the number of register reallocations, avoid register set splitting, and reduce the probability of overflow triggering.

[0080] Output: LMUL configuration and register occupancy constraint information that satisfy the cross-function register reuse conditions.

[0081] Step S3: Vector Register Co-allocation and Continuity Preservation 1. Collaborative allocation Based on cross-function activity information and LMUL constraints, the vector registers of the calling function and the called function are uniformly allocated; Maintain consistent occupancy or mapping of active registers across functions.

[0082] 2. Establishing mapping relationships Establish a vector register mapping table at function call boundaries; This mapping table describes the correspondence between physical register numbers before and after the call; After the function returns, it is used to guide the rapid restoration or direct reuse of the register state.

[0083] Output: Cross-function scope vector register collaborative allocation is completed, and a mapping table is generated.

[0084] Step S4: Overflow optimization based on vector characteristics 1. Overflow on demand The range of valid elements in the register is dynamically trimmed based on the real-time VL, SEW, and vmask states. Number of bytes of overflowing data block = VL × (SEW / 8); Only write the valid range back to memory to reduce invalid memory accesses.

[0085] 2. Hierarchical overflow When LMUL>1, the logical register is split into physical sub-units; Sort by activity probability and perform partial overflow or hierarchical saving; Ensure that the sub-unit start register number meets the alignment requirements.

[0086] 3. Delayed Overflow and State Merging Delay the overflow operation to the last non-vector operation slot before the function call; For functions that call the shared vector environment consecutively, merge redundant overflow and reload operations.

[0087] Output: The optimized overflow strategy has been executed successfully, reducing memory bandwidth usage and access latency.

[0088] Step S5: Cooperative maintenance of vector execution context 1. Context passing and reuse Pass the VL, SEW, and vmask states at function call boundaries; Reuse the vector configuration state that was established before the call to avoid repeatedly inserting configuration instructions.

[0089] 2. Elimination of redundant instructions Eliminate redundant vector configuration instruction sequences while ensuring program semantics; Maintain a consistent vector execution context across functions, and support register co-allocation and overflow optimization.

[0090] Output: Execution context consistency is maintained across function vectors, and register states can be quickly recovered.

[0091] Example 3: Detailed Implementation of Key Mechanisms This embodiment further illustrates the core mechanism of the cross-function vector register collaborative allocation method for RISC-V vector extension, including the LMUL propagation mechanism, the establishment and management of the vector register mapping table, and the hierarchical overflow strategy, such as... Figure 3 As shown.

[0092] I. LMUL Propagation and Constraint Convergence Mechanism 1. Cross-function LMUL propagation At the function call boundary, establish LMUL constraint relationships for the active vector registers of the calling function and the callee function; The LMUL configuration information of the caller function register group is passed to the callee function to ensure that the physical register occupancy granularity of the logical register group is compatible. For multi-level nested function calls, the LMUL configuration is converged to the optimal consistent state of all call chain nodes through iterative propagation.

[0093] 2. Constrained Convergence Strategy The goal is to minimize the number of register reallocations and avoid register set splits; For register groups that do not meet the constraints, the LMUL configuration and register allocation order are adjusted iteratively to ensure that registers are used continuously and reusably across function ranges; During convergence, if conflicts occur, priority is given to maintaining the continuity of active registers across functions, and the allocation of inactive registers is adjusted in a suboptimal manner.

[0094] 3. Constraint Model Output After convergence, an LMUL configuration table spanning the function range is generated, providing input for the register co-allocation module.

[0095] II. Vector Register Mapping Table Mechanism 1. Establishing the mapping relationship table Establish a vector register mapping table at function call boundaries; The table entries include: physical register number before the call, physical register number after the call, corresponding LMUL configuration, and active status indicator.

[0096] 2. Mapping Relationship Table Management When the function returns, the calling function restores the vector register state according to the mapping table or directly reuses the register. Supports fast register recovery in continuous function call chains, reducing register relocation and additional overflow operations; The mapping table can store mapping information for multiple levels of nested calls, enabling unified management of register states across function scopes.

[0097] 3. Mapping table and register coordination The mapping table, used in conjunction with the register co-allocation module, makes the continuity of registers across functions maintainable; A static mapping table can be generated during the compilation phase, or it can be dynamically maintained by the JIT / backend at runtime.

[0098] III. Tiered Spill Strategy 1. Principle of graded overflow For logical register groups with LMUL>1, they are split into multiple physical register sub-units; Prioritize each subunit based on its probability of being active in subsequent basic blocks or functions; High-priority sub-units are reserved in registers first, while low-priority sub-units overflow into memory during execution.

[0099] 2. Trim overflow as needed Calculate the effective overflow range based on VL and SEW: Only write valid data back to memory to reduce redundant memory accesses.

[0100] 3. Delay and Merge Overflow By using instruction scheduling techniques, overflow operations are delayed until the last non-vector operation slot before the function call; For vector environments shared by multiple consecutive function calls, redundant overflow and reload instructions are merged to reduce memory access overhead; For consecutive hierarchical sub-unit overflows, execution can be performed in physical alignment order to ensure the execution efficiency of burst memory accesses.

[0101] 4. Combining graded overflow with LMUL The combination of hierarchical overflow mechanism and LMUL propagation mechanism can maximize register reuse while ensuring the continuity of registers across functions; Avoid additional overflow overhead caused by inconsistent LMULs or register set splits.

[0102] Compared with existing technologies, the cross-function vector register cooperative allocation method for RISC-V vector extension provided by this invention has the following beneficial effects by performing unified modeling and cooperative optimization of vector register usage status, LMUL configuration, and vector execution context across function scopes: 1. Improve vector register utilization and reduce invalid reallocations. By using cross-function vector liveness analysis (step S1) and vector register collaborative allocation mechanism (step S3), vector register data that remains active at the function call boundary can be identified and maintained, allowing it to reside in the physical register before and after the call. This avoids the register release and reallocation at the function boundary in traditional techniques, thereby significantly improving vector register utilization.

[0103] 2. Reduce register overflow overhead in the function call path By propagating LMUL constraints and modeling consistency (step S2), a unified register occupancy granularity constraint is established between the calling function and the called function to avoid register reallocation and whole-group overflow caused by inconsistent LMUL configurations. At the same time, combined with the overflow optimization strategy based on vector characteristics (step S4), unnecessary register overflow and reload operations are reduced, thereby effectively reducing the memory access overhead on the function call path.

[0104] 3. Maintain the continuity of the vector register set to reduce rearrangement overhead. By maintaining the continuous occupancy of the vector register group during the register allocation phase and establishing a register mapping table at the function call boundary (step S3), the vector registers are kept continuously occupied before and after the function call, avoiding the register reordering operation introduced by register reallocation in the prior art, thereby reducing additional instruction overhead and reducing execution latency.

[0105] 4. Reduce register resource fragmentation and improve resource utilization efficiency. By using the cross-function LMUL constraint propagation mechanism (step S2), the granularity of vector register occupancy in different functions is modeled in a unified manner, so that the register group allocation satisfies the alignment and continuity constraints, avoiding the fragmentation problem of register resources caused by inconsistent LMUL configuration, thereby improving the overall utilization efficiency of physical register resources.

[0106] 5. Enable on-demand, tiered, and delayed overflow to reduce memory bandwidth pressure. Through the hierarchical overflow and on-demand pruning mechanism (step S4), memory write-back can be performed only on the valid data range according to the VL, SEW and vmask states, and the logical register group can be split and priority managed to achieve partial overflow and hierarchical storage; at the same time, through the delayed overflow and state merging strategy, the overflow operation is postponed and redundant memory access is merged, thereby significantly reducing memory bandwidth usage and memory access latency.

[0107] 6. Maintain consistency of execution context across function vectors and reduce configuration overhead. Through the vector execution context collaborative maintenance mechanism (step S5), the VL, SEW and vmask states are passed and reused during function calls to avoid repeatedly inserting vector configuration instructions and eliminate redundant configuration operations while satisfying program semantics, thereby maintaining a stable vector execution context and reducing additional instruction overhead.

[0108] 7. Provides cross-function global optimization capabilities to improve overall execution performance. By jointly designing cross-function liveness analysis, LMUL constraint propagation, register co-allocation, and overflow optimization mechanisms, the compiler can make global optimization decisions across functions. Compared with existing technologies that only perform local optimizations within functions, this can better leverage the performance potential of the RISC-V vector extension architecture and improve the overall execution efficiency of the program.

[0109] The following describes the cross-function vector register collaborative allocation device for RISC-V vector extension provided by the present invention. The cross-function vector register collaborative allocation device for RISC-V vector extension described below can be referred to in correspondence with the cross-function vector register collaborative allocation method for RISC-V vector extension described above.

[0110] like Figure 4 The diagram shows a cross-function vector register cooperative allocation device for RISC-V vector extension provided by the present invention, comprising: The cross-function analysis module 410 is used to perform cross-function range data flow analysis on the program, identify vector register data that remains active at the function call boundary, and construct a cross-function vector activity information set; The constraint modeling module 420 is used to establish LMUL constraint propagation relationship between the calling function and the called function based on the cross-function vector activity information set, and to perform consistency modeling and constraint convergence to determine the target LMUL configuration that satisfies the cross-function register reuse condition. The collaborative allocation module 430 is used to collaboratively allocate the vector registers of the calling function and the called function based on the cross-function vector activity information set and the target LMUL configuration. Overflow optimization module 440 is used to perform overflow optimization processing based on vector characteristics for vector data that cannot be retained in the vector register. Overflow optimization processing includes dynamically pruning the range of valid elements in the physical register according to the vector execution context, splitting the logical register group and performing hierarchical overflow according to the active probability, and delaying or merging overflow operations. The context maintenance module 450 is used to collaboratively maintain the vector execution context at function call boundaries. The vector execution context includes the VL, SEW, and vmask states.

[0111] Specifically, this embodiment provides a cross-function vector register collaborative allocation device for RISC-V vector extension, which can be deployed in a compiler system as part of a back-end register allocation and optimization module, and is used to perform cross-function range vector register collaborative optimization on the program during the compilation stage.

[0112] like Figure 5 As shown, the device mainly includes: a cross-function analysis module, a constraint modeling module, a collaborative allocation module, an overflow optimization module, and a context maintenance module. The modules interact and collaborate with each other through an intermediate data structure.

[0113] I. Cross-function analysis module The cross-function analysis module is used to perform cross-function range data flow analysis on the program during the compilation phase, specifically including: Perform control flow graph (CFG) and call relationship analysis on each function in the program to construct a function call graph. Based on the function call graph, cross-function activity analysis is performed on vector registers to identify vector data that remains active at the function call boundary; Construct a cross-function vector activity information set and record the register group occupancy and LMUL configuration of each vector register; The identifier vector register is the starting physical register number and the range of continuous occupancy at the function call boundary.

[0114] The output of the cross-function analysis module serves as the input for subsequent constraint modeling and register allocation.

[0115] II. Constraint Modeling Module The constraint modeling module is used to establish vector register allocation constraints based on cross-function analysis results, specifically including: Establish LMUL constraint propagation relationships between the calling and called functions to ensure that cross-function active vector registers meet consistent register set occupancy granularity requirements. Based on the physical alignment rules of RISC-V vector registers and the constraint of continuous occupancy of register groups, a consistency model is performed on the LMUL configuration of each function; Construct a cross-function register allocation constraint model and iteratively adjust the model using a constraint convergence strategy; During the iteration process, with the optimization objectives of minimizing the number of register reallocations, avoiding register set splits, and reducing the probability of overflow triggering, the target LMUL configuration that satisfies the cross-function register reuse condition is determined.

[0116] The constraint modeling module outputs unified LMUL configuration constraints and register occupancy constraints.

[0117] III. Collaborative Allocation Module The cooperative allocation module is used to implement cooperative allocation of cross-function vector registers during the register allocation phase, specifically including: Based on cross-function activity information and LMUL constraints, the vector registers of the calling function and the called function are uniformly allocated; Maintain the physical register positions of cross-function active vector registers consecutively or satisfy a consistent mapping relationship before and after the function call; Avoid register set splitting or rearranging operations caused by register reallocation; A vector register mapping table is established at the function call boundary to describe the correspondence between the physical register numbers before and after the call; After the function returns, the state of the vector register is quickly restored or directly reused based on the mapping table.

[0118] The above-mentioned collaborative allocation mechanism enables the reuse and layout preservation of vector registers across function ranges.

[0119] IV. Overflow Optimization Module The overflow optimization module is used to perform overflow optimization processing on the vector register in response to insufficient register resources, specifically targeting the RISC-V vector characteristics. This includes: 1. On-demand overflow submodule The effective element range in the physical register is dynamically pruned based on the real-time VL, SEW, and vmask states. The size of the overflow data block is determined by VL and SEW, and the number of overflow data bytes is the product of the corresponding byte widths of VL and SEW. Memory write-back is performed only on valid data ranges to reduce the bandwidth usage of invalid memory accesses.

[0120] 2. Hierarchical Overflow Submodule For logical vector register groups with LMUL greater than 1, they are split into multiple physical register sub-units; Prioritize each sub-unit based on its probability of being active in subsequent basic blocks; Perform partial overflow or tiered saving to reduce latency for single burst memory accesses; Ensure that the starting physical register number of each subunit satisfies the register group alignment constraint.

[0121] 3. Delayed Overflow Submodule While satisfying register pressure constraints, overflow operations are delayed until the last non-vector operation position before the function call; For scenarios where multiple consecutive function calls share the same vector execution context, redundant overflow and reload operations are merged.

[0122] V. Context Maintenance Module The context maintenance module is used to maintain the consistency of the vector execution context during function calls, specifically including: Manage the vector execution context at function call boundaries, including the passing of VL, SEW, and vmask states; Reuse the vector configuration state that was established before the call to avoid repeatedly inserting vector configuration instructions; Eliminate redundant vector configuration instruction sequences while satisfying program execution semantics; Maintain a stable vector execution context during cross-function execution to support register co-allocation and reuse mechanisms.

[0123] VI. Explanation of Module Collaboration Relationships The modules mentioned above collaborate by sharing an intermediate data structure: The cross-function analysis module outputs activity information, which is then provided to the constraint modeling module. The constraint modeling module outputs LMUL and register constraints, which are then provided to the collaborative allocation module. The collaborative allocation module calls the overflow optimization module for auxiliary processing during the allocation process; The context maintenance module runs through the entire function call process and works in conjunction with the collaborative allocation module and the overflow optimization module.

[0124] Through the collaboration of the above modules, this embodiment can achieve efficient allocation and reuse of vector registers across function ranges, reduce overflow overhead and improve overall execution efficiency.

[0125] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6As shown, the electronic device may include: a processor 610, a communication interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communication interface 620, and the memory 630 communicate with each other through the communication bus 640. The processor 610 can invoke logical instructions in memory 630 to execute a cross-function vector register cooperative allocation method for RISC-V vector extension. This method includes: performing cross-function range data flow analysis on the program, identifying vector register data that remains active at function call boundaries, and constructing a cross-function vector activity information set; establishing an LMUL constraint propagation relationship between the calling and called functions based on the cross-function vector activity information set, performing consistency modeling and constraint convergence, and determining a target LMUL configuration that satisfies the cross-function register reuse condition; and cooperatively allocating vector registers for the calling and called functions based on the cross-function vector activity information set and the target LMUL configuration; wherein, for vector data that cannot be retained in vector registers, overflow optimization processing based on vector characteristics is performed, including dynamically pruning the effective element range within physical registers according to the vector execution context, splitting the logical register group and performing hierarchical overflow according to the activity probability, and delaying or merging overflow operations; and cooperatively maintaining the vector execution context at function call boundaries, the vector execution context including VL, SEW, and vmask states.

[0126] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (RM), random access memory (RAM), magnetic disks, or optical disks.

[0127] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the cross-function vector register cooperative allocation method for RISC-V vector extension provided by the above methods. This method includes: performing cross-function range data flow analysis on the program, identifying vector register data that remain active at function call boundaries, and constructing a cross-function vector active information set; based on the cross-function vector active information set, establishing a register set length multiplication factor constraint propagation relationship between the calling function and the called function, and performing consistency modeling and constraint... The process involves convergence to determine the target LMUL configuration that satisfies the cross-function register reuse condition. Based on the cross-function vector activity information set and the target LMUL configuration, the vector registers of the calling and called functions are collaboratively allocated. For vector data that cannot be retained in the vector registers, overflow optimization based on vector characteristics is performed. This overflow optimization includes dynamically pruning the effective element range within the physical registers according to the vector execution context, splitting the logical register group and performing hierarchical overflow based on activity probability, and delaying or merging overflow operations. The vector execution context is collaboratively maintained at the function call boundary, and the vector execution context includes VL, SEW, and vmask states.

[0128] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon. When executed by a processor, the computer program implements a cross-function vector register cooperative allocation method for RISC-V vector extensions provided by the methods described above. This method includes: performing cross-function range data flow analysis on the program to identify vector register data that remains active at function call boundaries and constructing a cross-function vector activity information set; establishing an LMUL constraint propagation relationship between the calling function and the called function based on the cross-function vector activity information set, and performing consistency modeling and constraint convergence to determine whether cross-function register reuse is satisfied. The target LMUL configuration is determined based on the conditions. The vector registers of the calling and called functions are collaboratively allocated according to the cross-function vector activity information set and the target LMUL configuration. For vector data that cannot be retained in the vector registers, overflow optimization based on vector characteristics is performed. This overflow optimization includes dynamically pruning the effective element range within the physical registers according to the vector execution context, splitting the logical register group and performing hierarchical overflow according to the activity probability, and delaying or merging overflow operations. The vector execution context is collaboratively maintained at the function call boundary, and the vector execution context includes VL, SEW, and vmask states.

[0129] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0130] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as RM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.

[0131] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A cross-function vector register cooperative allocation method for RISC-V vector extension, characterized in that, include: Perform cross-function range data flow analysis on the program, identify vector register data that remain active at function call boundaries, and construct a cross-function vector activity information set; Based on the cross-function vector active information set, a register group length multiplication factor constraint propagation relationship is established between the calling function and the called function, and consistency modeling and constraint convergence are performed to determine the target register group length multiplication factor configuration that satisfies the cross-function register reuse condition. Based on the cross-function vector activity information set and the target register group length multiplication factor configuration, the vector registers of the calling function and the called function are collaboratively allocated; For vector data that cannot be retained in the vector register, overflow optimization processing based on vector characteristics is performed. The overflow optimization processing includes dynamically pruning the range of valid elements in the physical register according to the vector execution context, splitting the logical register group and performing hierarchical overflow according to the active probability, and delaying or merging the overflow operation. The vector execution context is collaboratively maintained at the function call boundary, and the vector execution context includes vector length, element width, and mask state.

2. The cross-function vector register cooperative allocation method for RISC-V vector extension according to claim 1, characterized in that, The process of performing cross-function range data flow analysis on the program, identifying vector register data that remains active at function call boundaries, and constructing a cross-function vector activity information set includes: Construct the function call graph of the program and the control flow graph of each function; Based on the function call graph and the control flow graph, the activity analysis of the vector registers in each function and the propagation of cross-function activity information are performed to determine whether each vector register still retains valid data at the function call boundary. The vector register that holds valid data is identified as the vector register that remains active at the function call boundary; The register group occupancy status, register group length multiplication factor configuration, and physical register starting number and continuous occupancy range at the function call boundary of the identified vector register are recorded to construct the cross-function vector activity information set.

3. The cross-function vector register cooperative allocation method for RISC-V vector extension according to claim 1, characterized in that, The step of establishing a register set length multiplication factor constraint propagation relationship between the calling and called functions based on the cross-function vector activity information set, performing consistency modeling and constraint convergence, and determining the target register set length multiplication factor configuration that satisfies the cross-function register reuse condition includes: Based on the cross-function vector active information set, the register group length multiplication factor corresponding to the active vector register in the calling function is configured and passed to the called function as a constraint condition, thereby establishing a register group length multiplication factor constraint relationship between the calling function and the called function at the function call boundary. Based on the physical register alignment rules and the consecutive occupancy constraints of register groups, a consistency model is performed on the register group length multiplication factor configuration of the calling function and the called function to obtain a cross-function register allocation constraint model. With the optimization objectives of minimizing the number of register reallocations, avoiding register group splits, and reducing the probability of overflow triggering, the cross-function register allocation constraint model is iteratively adjusted until the constraint convergence condition is met, and the target register group length multiplication factor configuration is obtained.

4. The cross-function vector register cooperative allocation method for RISC-V vector extension according to claim 1, characterized in that, The step of coordinating the allocation of vector registers for the calling and called functions based on the cross-function vector activity information set and the target register group length multiplication factor includes: Based on the cross-function vector activity information set and the target register group length multiplication factor configuration, a unified physical register allocation is performed on the cross-function active vector registers in the calling function and the called function; A vector register mapping table is established at the function call boundary. The mapping table is used to describe the correspondence between the physical register number before the call and the physical register number after the call, and to record the corresponding register group length multiplication factor configuration and active status identifier. After the function call returns, the vector register state is quickly restored or directly reused according to the corresponding relationship in the mapping table.

5. The cross-function vector register cooperative allocation method for RISC-V vector extension according to claim 1, characterized in that, For vector data that cannot be retained in the vector register, overflow optimization processing based on vector characteristics is performed, including: Based on the real-time vector length, element width, and mask status, the effective element range in the physical register is dynamically pruned to determine the effective data range to be overflowed. The size of the effective data range is determined by the product of the vector length and the byte width corresponding to the element width. Only the data within the effective data range is written back to memory. For a logical register group whose register group length multiplication factor is greater than 1, the logical register group is split into multiple physical register sub-units; Priority sorting is performed based on the activity probability of each physical register subunit in subsequent basic blocks, and partial overflow or hierarchical saving is performed according to the priority order, wherein the starting physical register number of each physical register subunit satisfies the register group alignment constraint. Provided that register set alignment constraints are met, overflow operations are delayed until the last non-vector operation position before the function call is executed; For multiple consecutive function calls that share the same vector execution context, redundant overflow operations and reload operations are merged.

6. The cross-function vector register cooperative allocation method for RISC-V vector extension according to claim 1, characterized in that, The method of collaboratively maintaining the vector execution context at function call boundaries includes: At the function call boundary, obtain the vector execution context that was established before the call, the vector execution context including vector length, element width and mask state; The vector execution context is passed to the called function, so that the called function can reuse the vector state configured before the call and maintain the consistency of the vector execution context during the function call. Under the premise of satisfying the semantics of program execution, identify and eliminate redundant vector configuration instruction sequences, including vector length setting instructions, element width setting instructions, or mask state setting instructions that are repeated with the established vector execution context.

7. A cross-function vector register cooperative allocation device for RISC-V vector extension, characterized in that, include: The cross-function analysis module is used to perform cross-function range data flow analysis on the program, identify vector register data that remains active at the function call boundary, and construct a cross-function vector activity information set; The constraint modeling module is used to establish a register group length multiplication factor constraint propagation relationship between the calling function and the called function based on the cross-function vector activity information set, and to perform consistency modeling and constraint convergence to determine the target register group length multiplication factor configuration that satisfies the cross-function register reuse condition. The collaborative allocation module is used to collaboratively allocate the vector registers of the calling function and the called function according to the cross-function vector activity information set and the target register group length multiplication factor configuration; The overflow optimization module is used to perform overflow optimization processing based on vector characteristics for vector data that cannot be retained in the vector register. The overflow optimization processing includes dynamically pruning the range of valid elements in the physical register according to the vector execution context, splitting the logical register group and performing hierarchical overflow according to the active probability, and delaying or merging the overflow operation. The context maintenance module is used to collaboratively maintain the vector execution context at the function call boundary. The vector execution context includes the vector length, element width, and mask state.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the cross-function vector register cooperative allocation method for RISC-V vector extension as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the cross-function vector register cooperative allocation method for RISC-V vector extension as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the cross-function vector register cooperative allocation method for RISC-V vector extension as described in any one of claims 1 to 6.

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