Method of generating in-memory processing request for in-memory operations, and electronic device and method for in-memory processing

Abstract

A method of generating an in-memory processing request for an in-memory (PIM) operation, and an electronic device and method for in-memory processing are disclosed. A method of generating a PIM request for an in-memory operation includes receiving configuration information for generating a PIM request from a processor; obtaining information on the PIM request command from the command table, the step of obtaining being based on the configuration information; and generating a PIM request based on the obtained information about the PIM request command.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2024-0160432, filed on November 12, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0002] The following description relates to methods and apparatus for generating in-memory processing requests. Background Technology

[0003] In typical von Neumann architecture computer systems, the functionality of memory devices can be separated from the functionality of the processor that performs operations on the data in the memory devices. Therefore, bottlenecks can occur when large amounts of data are exchanged between memory devices and processors in systems used to perform neural network operations, process big data, or process Internet of Things (IoT) data, requiring operations on such large volumes. To address this issue, research has been actively conducted on in-memory processing (PIM) of memory devices, which combines the functions of memory and the processor for performing arithmetic operations. Summary of the Invention

[0004] The present invention is provided in a simplified form to introduce the choice of concepts further described in the following detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to help determine the scope of the claimed subject matter.

[0005] The aspect provides usable in-memory system technology, in which in-memory operating devices operate or not operate via dedicated memory commands.

[0006] This provides in-memory system technology that can be used without processor hardware modifications.

[0007] The technology provides in-memory system technology that can generate in-memory processing (PIM) requests for in-memory operations in modules separate from the processor, allowing the processor to perform separate operations when generating PIM requests for in-memory operations.

[0008] However, the technical aspects are not limited to those mentioned above, and other technical aspects may exist.

[0009] In one general aspect, a method for generating a PIM request for in-memory operation includes: receiving configuration information from a processor for generating the PIM request; obtaining information about a PIM request command from a command table, the obtaining step being based on the configuration information; and generating the PIM request based on the obtained information about the PIM request command.

[0010] The steps to obtain information about PIM request commands may include: obtaining information about PIM request commands from the command table based on the start address of the command table included in the configuration information.

[0011] The steps of generating a PIM request may include: generating address information corresponding to the PIM request based on information indicating the address range included in the information about the PIM request command and address mapping information included in the configuration information; and generating a PIM request including the generated address information.

[0012] Address mapping information may include: bit mapping information between memory fields and addresses, as well as address incrementing pattern information for memory fields.

[0013] The steps for obtaining information about the PIM request command may include: further obtaining information about the PIM request command from the command table based on the trigger signal received from the processor for generating the PIM request.

[0014] The method may further include: sending a PIM request to a memory controller, the memory controller being configured to control a PIM memory, and the PIM memory being configured to perform in-memory operations.

[0015] The processor can store command tables.

[0016] The command table may include information about one or more PIM request commands.

[0017] Information about PIM request commands may include the type of PIM request command, the address of the PIM request command, and / or the data that will be manipulated through the PIM request command.

[0018] Information about PIM request commands may also include fence information indicating whether a memory fence operation should be performed on the PIM request command.

[0019] The type can indicate the type of in-memory operation or the type of general memory operation.

[0020] In another general aspect, an electronic device for in-memory operations includes: a processor; a memory controller; a PIM memory; and a PIM request generation module. The processor can send configuration information for generating PIM requests to the PIM request generation module, and the PIM request generation module can perform operations to obtain information about PIM request commands from a command table based on the configuration information, and is configured to perform operations to generate PIM requests based on the PIM request commands.

[0021] PIM requests can be sent to the memory controller, which is configured to control the PIM memory.

[0022] The steps to obtain information about PIM request commands may include: obtaining information about PIM request commands from the command table based on the start address of the command table included in the configuration information.

[0023] The steps of generating a PIM request may include: generating address information corresponding to the PIM request based on information indicating the address range included in the information about the PIM request command and address mapping information included in the configuration information; and generating a PIM request including the generated address information.

[0024] Address mapping information may include: bit mapping information between memory fields and addresses, as well as address incrementing pattern information for memory fields.

[0025] The steps for obtaining information about the PIM request command may include: further obtaining information about the PIM request command from the command table based on the trigger signal received from the processor for generating the PIM request.

[0026] The processor can store the command table in the storage space linked to the electronic device.

[0027] The command table may include information about one or more PIM request commands.

[0028] Information about a PIM request command may include at least one of the following: type information, address information, data information, and fence information indicating whether a memory fence operation should be performed on the PIM request command.

[0029] In another general aspect, a method includes: generating a table including entries by a processor, each entry including a corresponding description of a PIM request command; storing the table at a location in memory; storing a configuration indicating the location of the table; generating a trigger signal by the processor; accessing the configuration to obtain the location of the table in response to the trigger signal; accessing entries in the table based on the obtained location of the table to generate PIM requests corresponding to the descriptions of the PIM request commands, each PIM request including an indication and address of its PIM operation type; receiving the PIM requests by a memory controller, and generating PIM commands corresponding to the PIM requests based on the PIM requests by the memory controller; and receiving the PIM commands by a PIM memory device, and executing the PIM commands by the PIM memory device.

[0030] Other features and aspects will become clear from the following detailed description, drawings, and claims. Attached Figure Description

[0031] Figure 1 Examples of configurations for a memory system for in-memory processing (PIM) according to one or more embodiments are shown.

[0032] Figure 2 Examples of methods for generating PIM requests for in-memory operations are shown according to one or more embodiments.

[0033] Figure 3A and Figure 3B Each shows an example of a command table according to one or more embodiments.

[0034] Figure 4A and Figure 4B Each example shows information about a PIM request command according to one or more embodiments.

[0035] Figures 5A to 5C Each example illustrates address mapping information according to one or more embodiments.

[0036] Figures 6A to 6C Each illustrates an example of an address via a memory field according to one or more embodiments.

[0037] Figure 7 An example of the hardware configuration of a PIM request generation module according to one or more embodiments is shown.

[0038] Figure 8 An example of a hardware configuration for an address generation module according to one or more embodiments is shown.

[0039] Figure 9A and Figure 9B Each illustrates an example of a configuration of a memory system for in-memory operation according to one or more embodiments.

[0040] Figures 10A to 10C Examples of configurations of memory systems including command tables for PIM requests, according to one or more embodiments, are shown respectively.

[0041] Throughout the accompanying drawings and detailed embodiments, unless otherwise stated or provided, the same or identical reference numerals will be understood to refer to the same or identical elements, features, and structures. The drawings may not be to scale, and for clarity, illustration, and convenience, the relative dimensions, scale, and depiction of elements in the drawings may be exaggerated. Detailed Implementation

[0042] The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become clear upon understanding the disclosure of this application. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but may be changed as will become clear upon understanding the disclosure of this application, except for operations that must occur in a specific order. Furthermore, for greater clarity and conciseness, descriptions of features known upon understanding the disclosure of this application may be omitted.

[0043] The features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein have been provided only to illustrate some of the many feasible ways in which the methods, apparatus, and / or systems described herein will be clear upon understanding the disclosure of this application.

[0044] The terminology used herein is for the purpose of describing various examples only and is not intended to limit disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. As used herein, the term "and / or" includes any one or any combination of any two or more of the associated listed items. As a non-limiting example, the terms "comprising," "including," and "having" indicate the presence of the features, quantities, operations, components, elements, and / or combinations thereof stated, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0045] Throughout this specification, when a component or element is described as being "connected to," "joined to," or "attached to" another component or element, the component or element may be directly "connected to," "joined to," or "attached to" the other component or element, or there may reasonably be one or more other components or elements present in between. When a component or element is described as being "directly connected to," "directly joined to," or "directly attached to" another component or element, there may not be any other elements present in between. Similarly, expressions such as "between" and "immediately between," "adjacent to," and "closely adjacent to" may be interpreted as described above.

[0046] Although terms such as “first,” “second,” and “third,” or A, B, (a), (b), etc., may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts should not be limited by these terms. For example, each of these terms is not used to define the nature, order, or sequence of the corresponding component, assembly, region, layer, or part, but only to distinguish the corresponding component, assembly, region, layer, or part from other components, assemblies, regions, layers, or parts. Therefore, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part referred to as the first component, first assembly, first region, first layer, or first part may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, based on an understanding of the disclosure of this application. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and in the disclosure of this application, and shall not be interpreted in an idealized or overly formal sense. The use of the term “may” herein with respect to examples or embodiments (e.g., what an example or embodiment may include or implement) indicates the existence of at least one example or embodiment that includes or implements such a feature, but not all examples are limited thereto.

[0048] Figure 1 Examples of configurations for a memory system for in-memory processing (PIM) according to one or more embodiments are shown.

[0049] Reference Figure 1 According to an embodiment, the memory system 100 may include a processor 110, a PIM request generation module (PIM request generator) 120, a memory controller 130, and a PIM memory 140. In short, in the following description, a PIM request may be generated by the PIM request generation module 120 in response to a trigger / signal from a processor (e.g., a processor executing code for an application using the PIM memory 140). The PIM request generation module 120 may respond by generating a PIM request, which may be a descriptive form of a PIM command. The PIM request generation module 120 may send the generated PIM request to the memory controller 130. The memory controller 130 may convert / translate the PIM request into a corresponding memory command that is received by (and can be executed by) the PIM memory 140.

[0050] Processor 110 may be a host or a host processor. Processor 110 (e.g., processor 110 executing code for an application using PIM memory 140) may generate a command list (potentially reusable) that can be used by PIM request generation module 120 to generate PIM requests when needed; processor 110 may store the command list in storage space included in memory system 100 or in any storage space linked to memory system 100. For example, processor 110 may control the storage of the command list. The storage space storing the command list may be any space accessible to PIM request generation module 120. The command list is described in detail below; however, briefly, the entries in the command list provide information (e.g., corresponding descriptions of PIM request commands) about the corresponding PIM commands (and possibly non-PIM commands) that can be used to generate the respective corresponding PIM requests.

[0051] Processor 110 can send and load configuration information into PIM request generation module 120; the configuration information (or simply "configuration") facilitates access to the corresponding command table (e.g., acts as a pointer to the command table). When processor 110 commands / signals / triggers PIM request generation module 120, PIM request generation module 120 can then use the configuration already loaded therein to generate a PIM request (entry-by-entry in each command table). The configuration may point to a command table and may include additional information to facilitate PIM request generation module 120's access to the command table. The configuration may be input by a user or may be generated in processor 110 based on user input. The configuration for generating PIM requests is described in detail below. Incidentally, for example, an application executing on processor 110 may generate and persistently store multiple different command tables (multiple different command tables that can be selectively used as needed), and various different configurations may be loaded into PIM request generation module 120 at different times to control which command table to use when processor 110 signals / triggers PIM request generation module 120 to generate a PIM request.

[0052] The PIM request generation module 120 may include a circuit system and control logic. The PIM request generation module 120 may perform operations for generating PIM requests based on the circuit and control logic. For example, the PIM request generation module 120 may obtain information about PIM request commands from entries in a command table based on configuration information received from (loaded by) the processor 110. The PIM request generation module 120 may generate a PIM request based on the obtained information about the PIM request commands. The operation method of the PIM request generation module 120 for generating PIM requests is described in detail below.

[0053] The PIM request generation module 120 can send a PIM request generated by itself to the memory controller 130. Based on the PIM request, the memory controller 130 can generate memory commands (e.g., PIM commands or non-PIM commands), addresses, and data. The memory commands can be PIM-specific memory commands for in-memory operations. The memory controller 130 can send the memory commands, addresses, and data to the PIM memory 140 based on the PIM request, and the PIM memory 140 can perform the operation corresponding to the PIM request.

[0054] PIM memory 140 may include memory for performing in-memory operations. In other words, PIM memory 140 may be memory that performs in-memory operations in addition to general memory operations such as reading and writing. In-memory operations can be performed on data stored in PIM memory 140 before, during, and after an operation (that is, operations are performed on data in situ within PIM memory 140 without having to specifically move the data for the operation). PIM memory 140 may be dynamic random access memory (DRAM), but is not limited to this example. For example, PIM memory 140 may be one of various types of random access memory (RAM) such as static RAM (SRAM), magnetic RAM (MRAM), phase-change RAM (PRAM), ferroelectric RAM (FRAM), or resistive RAM (RRAM)).

[0055] PIM memory 140 can be divided into one or more layers of memory fields. For example, memory fields can be divided into memory channels, memory banks, rows, and columns. For example, PIM memory 140 may include one or more memory channels. Each memory channel may include one or more memory banks. Each memory bank may include memory cells connected to word lines (WLs). WLs may be connected to memory cells individually. Memory cell arrays may include memory cells (not shown) arranged in row and column directions. Each memory cell may be connected to a corresponding WL and a corresponding BL among multiple bit lines (BLs). Based on the address of the row received from memory controller 130, one or more WLs may be selected as access targets. The one or more WLs selected as access targets may be activated.

[0056] For example, PIM memory 140 can perform an operation of a type included / specified in the generated PIM request. For example, as a non-limiting example, the operation performed in PIM memory 140 according to the type of operation included / indicated in the PIM request could be an operation to write data to an address included in the PIM request, an operation to read data stored at an address included in the PIM request, an operation to perform a mathematical / logical operation by reading data stored at an address included in the PIM request (the data can act as an operand in a mathematical / logical operation), an operation to store data stored at an address included in the PIM request in a register of one or more PIM memories 140, an operation to store data stored in registers of one or more PIM memories 140 in an address included in the PIM request, an operation to write data included in the PIM request to a register of one or more PIM memories 140, or an operation to read data stored in registers of one or more PIM memories 140.

[0057] In some embodiments, the PIM request generation module 120 may replace the direct memory access (DMA) controller of the memory system 100. In other words, the PIM request generation module 120 can provide the functionality of a DMA controller. In this case, in addition to PIM requests for in-memory operations, general memory requests (as opposed to PIM requests) may also be sent to the memory controller 130 by / through the PIM request generation module 120.

[0058] In some embodiments, the memory system 100 may be or include electronic devices for in-memory operations. These electronic devices may include a processor 110, a memory controller 130, a PIM memory 140, and a PIM request generation module 120.

[0059] Figure 2 Examples of methods for generating PIM requests for in-memory operations are shown according to one or more embodiments.

[0060] For example, Figure 2 The method for generating a PIM request shown in the figure can be obtained by Figure 1 The PIM request generation module 120 is executed.

[0061] Reference Figure 2 According to an embodiment, the method for generating a PIM request may include operation 210: receiving configuration (configuration information) to be used in generating the PIM request; the configuration may be obtained from a processor (e.g., Figure 1The processor 110 receives the information. The configuration may include information set to facilitate the generation of a PIM request by enabling the PIM request generation module 120 to obtain data from a command table. For example, the configuration may include address and / or address mapping information of the command table that can be used to generate PIM memory addresses from address information stored in the command table.

[0062] The address information of the command table (in the currently loaded configuration) enables the PIM request generation module to access the command table (which is stored in memory). The address information of the command table may include, for example, the start address of the command table. As previously mentioned, the processor may have previously stored the command table at its address. For example, the processor may correspond to... Figure 1 The processor 110. The memory storing the command table can be any storage space accessible to the PIM request generation module.

[0063] According to some embodiments, a method for generating a PIM request may include operation 220: accessing a command table based on a configuration (wherein the command table's address / location), and obtaining information about a PIM request command from entries in the command table. For example, operation 220 of obtaining information about a PIM request command may include: obtaining information about a PIM request command from the command table based on the start address of the command table included in the currently loaded configuration. The PIM request generation module may access the start address of the command table included in the configuration information and may obtain information stored in the command table.

[0064] The command table may include information about one or more PIM request commands (e.g., one or more table entries or nodes describing the corresponding PIM request commands). For example, there may be n entries in the command table containing corresponding information sets about n corresponding PIM request commands (n is a natural number greater than 0). This set of information about the PIM request commands is used to request operations on the PIM memory and may include, for example, type information, address information, and / or data information corresponding to the PIM request commands. The type information, address information, and data information are described below.

[0065] The type information is the type of operation requested by the PIM memory and may include, for example, information indicating the type of operation within the memory or information indicating the type of general memory operation. General memory operation types may include operation types that are not in-memory operations but are performed in general memory (such as read and write).

[0066] Address information indicates the address of the PIM memory and may include, for example, information indicating the address range of the PIM memory. For example, address information may include a start address and an end address. In this case, address information may indicate a memory region ranging from the start address to the end address. As another example, address information may include a start address and size / range information. In this case, address information may indicate a memory region of a size indicated by the size information from the start address. The address obtained by adding the size information to the start address may be the end address of the memory region indicated by the address information. For example, address information may include information indicating the address range of the source (src) memory from which data is retrieved. For example, address information may include information indicating the address range of the destination (dst) memory from which data is stored. Depending on the type, address information may include (i) information indicating the address range of the source memory or (ii) information indicating the address range of the destination memory.

[0067] Data information may include information indicating data to be stored in memory or data used for operation.

[0068] Reference Figure 3A Example of command table 310 can be a data structure (such as a linked list) (other data structures (such as fixed-format tables) can also be used to represent command tables). In short, the nodes / entries of the linked list contain a corresponding set of information about the corresponding command for a PIM request. Command table 310 may include a first node 311 corresponding to a first PIM request command (PIM req CMD 0), a second node 312 corresponding to a second PIM request command (PIM req CMD 1), and a third node 313 corresponding to a third PIM request command (PIM req CMD 2). When the first PIM request command has a next command, the next command is the second PIM request command, and the first node 311 may include the address of the head of the second node 312 (thus linking the first node 311 to the second node 312). When the second PIM request command has a next command, the next command is the third PIM request command, and the second node 312 may include the address of the head of the third node 313 (thus linking the second node 312 to the third node 313).

[0069] For example, refer to Figure 3BThe first node 320 may include a first set of information regarding the first PIM request command. This first set of information may include the type 321 of the first PIM request command, the destination (DST) start address 322, the destination (DST) end address 323, and data information (data 0, data 1) 324 (e.g., the data information may be used as an operand for the corresponding PIM command). The first set of information may also include the address (next CMD) 325 of the header of the second node 330, where a second set of information regarding the second PIM request command is stored.

[0070] The second set of information stored in the second node 330 may include information about the second PIM request command. This second set of information may include the type 331 of the second PIM request command, the source (SRC) start address 332, the source (SRC) end address 333, the destination start address 334, and the destination end address 335. If the second node 330 is the last node in the command table (that is, if there is no next command to the second PIM request command in the command table), then the second node 330 may include information indicating that it is the last node in the command table (the end or terminator of the command table) 336.

[0071] Reference Figure 4A The example information set regarding the PIM request command may include fence information 410 indicating whether a memory fence (or memory barrier) operation should be performed in response to the PIM request command. If the fence information 410 indicates that a memory fence operation should be performed, then operations for other PIM requests may not be performed until the operation for the corresponding PIM request is completed. For example, the information (or information set) regarding the PIM request command may include at least one of the following: type information of the PIM request command, address information of the PIM request command, data information of the PIM request command, and fence information 410.

[0072] Reference Figure 4B Examples of address information may include source memory size information 421 instead of the source end address, to indicate the address range of the source memory. Address information may include destination memory size information 422 instead of the destination end address, to indicate the address range of the destination memory.

[0073] Refer again Figure 2In some embodiments, the operation 220 of obtaining the information set regarding the PIM request command may further include generating a trigger signal for the PIM request based on a trigger from the processor, and obtaining the information set regarding the PIM request command from a command table. The trigger signal for generating the PIM request is a request for an in-memory operation received from the processor and can be distinguished from a general memory request. The PIM request generation module may obtain the information set regarding the PIM request command from a command table indicated by configuration in response to the trigger signal received from the processor.

[0074] In some embodiments, general memory requests that are not for in-memory operations may not be processed in the PIM request generation module. For example, general memory requests (such as reads and writes) may not be sent to the PIM request generation module, but may instead be sent to be processed in the DMA controller and / or memory controller.

[0075] In some embodiments, general memory requests that are not for in-memory operations can also be processed in the PIM request generation module. For example, if an electronic device including a memory system or PIM memory device includes a PIM request generation module instead of a DMA controller, a general memory request can also be sent to the PIM request generation module.

[0076] In some embodiments, the method for generating a PIM request may include operation 230: generating a PIM request based on information about a PIM request command obtained in operation 220. For example, the PIM request may be generated to include type information of the PIM request command obtained from a command table. For example, the generated PIM request may include data information of the PIM request command obtained from a command table. For example, the generated PIM request may include address information of the PIM request command obtained from a command table. For example, the PIM request may also be generated to include address information generated based on address information obtained from a command table.

[0077] In some embodiments, the operation 230 of generating a PIM request may include: generating address information corresponding to the PIM request based on information indicating the address range (which is included in information about the PIM request command) and address mapping information included in the configuration, and generating a PIM request including the generated address information. For example, the information indicating the address range of the PIM memory obtained from the generated address command table may include information that has been converted / translated into the address of the PIM memory based on the address mapping information.

[0078] Address mapping information may include information for converting / translating address information included in the command table to addresses of the PIM memory. For example, address mapping information may include information for generating addresses of the PIM memory corresponding to the address range obtained from the command table.

[0079] In some embodiments, the address mapping information may include mapping information between memory fields and address bits.

[0080] For example, refer to Figure 5A When the address information stored in the command table is 16-bit data, the address mapping information may include table 501, which represents the bit positions mapped to each memory field as 1. (See reference...) Figure 5A Table 501 specifies that for bit positions 1 through 16, the Chan field can be mapped to bit positions 9 through 12. The Bank field can be mapped to bit positions 5 through 8. The Row field can be mapped to bit positions 1 through 4. The Col field can be mapped to bit positions 13 through 16.

[0081] For example, refer to Figure 5B When the address information stored in the command table is 32-bit data, the address mapping information may include table 502, which represents the memory fields mapped to each bit location. (See reference...) Figure 5B The positions

[28] to

[31] can be mapped to the row field, the position

[27] can be mapped to the memory bank (ba), and the positions [0] to [2] can be mapped to the column (co) field.

[0082] In some embodiments, the address mapping information may include mapping information between address information stored in the command table and address information in the PIM memory. For example, refer to Figure 5C When the address information stored in the command table is 32-bit data, the address mapping information may include Table 503, which indicates the bit position of the PIM memory address mapped to each bit position of the address information stored in the command table. Referring to Table 503, bit position

[31] of the address information stored in the command table is mapped to bit position

[31] of the PIM memory address, bit position

[30] of the address information stored in the command table is mapped to bit position

[28] of the PIM memory address, and bit position

[29] of the address information stored in the command table is mapped to bit position

[27] of the PIM memory address.

[0083] In some embodiments, the address mapping information may include increment pattern information for the address of each memory field. The increment pattern information for the address of each memory field may include information indicating which address of the memory field first increments from the start address to the end address when information indicating an address range is obtained.

[0084] For example, such as Figure 6AAs shown, when the start address 610 is obtained, based on the address mapping information, the start address 610 can be divided into an address 611 mapped to the row field, an address 612 mapped to the bank field, an address 613 mapped to the channel field, and an address 614 mapped to the column field. In other words, as... Figure 6C As shown, starting address 610 can be partitioned into address 631 via a memory field. (See reference...) Figure 6C The address of the memory channel (Chan) field at the start address can be 00, the address of the memory bank (Bank) field at the start address can be 0000, the address of the row (Row) field at the start address can be 1111_0000_0000_0000, and the address of the column (Col) field can be 00_0000.

[0085] For example, such as Figure 6B As shown, when the end address 620 is obtained, based on the address mapping information, the end address 620 can be divided into an address 621 mapped to the row field, an address 622 mapped to the bank field, an address 623 mapped to the channel field, and an address 624 mapped to the column field. In other words, as... Figure 6C As shown, end address 620 can be partitioned into address 632 via a memory field. (See reference...) Figure 6C The address of the memory channel (Chan) field at the end address can be 11, the address of the memory bank (Bank) field at the end address can be 0000, the address of the row (Row) field at the end address can be 1111_0000_0000_0001, and the address of the column (Col) field can be 11_1111.

[0086] The PIM request generation module can generate PIM memory addresses within a range by incrementing the address by one from the start address to the end address. For example, the generation of PIM memory addresses within a range can be performed in an address generation module included within the PIM request generation module. The address generation module is described in detail below.

[0087] Address mapping information may include priority information (e.g., rank information) of memory fields. The PIM request generation module can generate PIM memory addresses within an address range by increasing the address from the address of a memory field with a low priority / rank. For example, if the priority of a memory field is in the order of column, channel, and row, then... Figure 6AThe address of the column field in the starting address 610 can be increased by 1, and the addresses 1111_0000_0000_0000_0000_0000_0001 and 1111_0000_0000_0000_0000_0000_0000_0010 can be generated sequentially. If the column field address is generated as 11_1111, which is the address of the column field ending at address 620, then the memory channel field address increments by one from 00 to 01, resulting in addresses 1111_0000_0000_0000_0000_0100_0000, 1111_0000_0000_0000_0000_0100_0001, and 1111_0000_0000_0000_0000_0100_0010. If the column field address is generated as 11_1111, which is the address of the column field ending at address 620, then the memory channel field address increments by one. If the address of the memory channel field is generated as 11 of the address of the channel field ending at address 620, then the start address of the memory bank field can be the same as the end address of the memory bank field, and the address of the row field with the next priority is increased by 1, and the address 1111_0000_0000_0001_0000_0000_0000_0000 is generated.

[0088] In some embodiments, the generated PIM request may include one or more PIM memory addresses generated based on address mapping information obtained from the address information obtained from the command table.

[0089] In some embodiments, the method of generating a PIM request may include sending the PIM request to a memory controller configured to control a PIM memory, which is configured to perform in-memory operations. For example, the memory controller may correspond to... Figure 1 The memory controller 130, and the PIM memory can correspond to Figure 1 PIM memory 140.

[0090] If the generated PIM request is of the in-memory operation type, the PIM memory that has received the memory command requesting an in-memory operation based on the PIM request through the memory controller will perform the in-memory operation. The PIM memory can perform the in-memory operation based on the address information and data information included in the PIM request.

[0091] If the generated PIM request is of the general memory operation type (i.e., any non-PIM memory operation), the PIM memory that receives the corresponding memory command requesting a general memory operation based on the PIM request through the memory controller can perform the general memory operation. The PIM memory performs the general memory operation based on the address information and data information included in the PIM request.

[0092] Figure 7 An example of the hardware configuration of a PIM request generation module according to one or more embodiments is shown.

[0093] Reference Figure 7 In some embodiments, the PIM request generation module 700 may, for example, obtain the request from a processor (e.g., Figure 1 The processor 110 receives configuration 701. The received configuration 701 can be stored in a configuration register 710 for storing configuration information of the PIM request generation module 700.

[0094] The PIM request generation module 700 can receive a trigger signal 702 that triggers the generation of a PIM request by the PIM request generation module 700. The PIM request generation module 700 can perform the aforementioned operation of generating a PIM request in response to receiving the trigger signal 702, which can be obtained from a processor (e.g., Figure 1 The processor 110 is received.

[0095] In response to trigger signal 702, PIM request generation module 700 can obtain information about PIM request commands from the command table; the information is obtained based on the currently loaded configuration 701. For example, the type information of the PIM request command obtained from the command table can be stored in the type register (Type reg). For example, the address information obtained from the command table can be stored in register 730 (including SRC start address register (reg), SRC end address register, DST start address register, and DST end address register) used for storing address information. For example, the data information obtained from the command table (e.g., data 0 reg, data 1 reg, ..., data 7 reg) can be stored in register 740 (data reg file) used for storing data information.

[0096] As described above, the command table can be in the form of a linked list including one or more nodes corresponding to each PIM request. Type information, address information, and / or data information for each type can be obtained and stored in registers 710, 720, 730, and 740 of the PIM request generation module 700 (e.g., information can be loaded into these registers each time a node is read from the linked list). A node may include information indicating the address of the next node, and this information can also be stored in register (next CMD address reg) 750 of the PIM request generation module 700, thereby allowing the PIM request generation module 700 to generate PIM requests for a sequence of corresponding commands in the linked list (command table). When a PIM request is generated for a specific node (e.g., the node indicated by the address stored in register 750), data from that node can be loaded into the registers (specifically, type information, address information, and / or data information can be loaded into registers 710, 720, 730, 740, and 750 of the PIM request generation module 700). If the node most recently loaded into registers 710, 720, 730, 740, and 750 is the last node stored in the command table, then the information indicating the next node may not be retrieved. For example, if a node is the last node stored in the command table, the information indicating it is the last node can be retrieved, and this information can be stored in register 750 (e.g., a predefined address value). If the information indicating it is the last node is stored in register 750, then the operation of retrieving information from the command table can be terminated.

[0097] The PIM request generation module 700 may include an address generation module (address generator) 760. The address generation module 760 can be configured to generate PIM memory addresses based on configuration 701 and address information included in register 730 for storing addresses. As described above, the address generation module 760 can generate one or more PIM memory addresses within a range corresponding to the start and end addresses of the source (SRC) and / or destination (DST) based on address mapping information included in configuration information 701.

[0098] The PIM request generation module 700 may include a PIM request controller 770 configured to output PIM requests. The PIM request controller 770 may generate a PIM request 703, which includes type information stored in a type register 720, address information generated in an address generation module 760, and / or data information stored in a data register 740.

[0099] Figure 8 An example of a hardware configuration for an address generation module according to one or more embodiments is shown.

[0100] Reference Figure 8 The address generation module 800 can generate PIM memory address information 802, 803, 804 and 805 by converting address information obtained from the command table (e.g., SRC start address 802, SRC end address 803, DST start address 804, DST end address 805 and next CMD address) based on the address mapping information 801 included in the configuration.

[0101] Address generation module 800 may include increment module 810. Increment module 810 can distinguish received address information 802, 803, 804, and 805 through memory fields based on address mapping information 801. The address of each memory field can be assigned to a counter. Increment module 810 can control the counter through each memory field based on address increment pattern information included in address mapping information 801. The counter for each memory field can increment the address of each memory field by one. For example, the counter for each memory field may include a channel counter 821 that increments the address of a memory channel field, a memory bank counter 822 that increments the address of a memory bank field, a row counter 823 that increments the address of a row field, and a column counter 824 that increments the address of a column field. Increment module 810 can control the increment of the address of each memory field based on the priority of the memory fields included in address mapping information 801.

[0102] When at least one counting operation is performed between counters, the outputs of the counters can be combined into an address via the field-to-address translation module 830. The address combined in the field-to-address translation module 830 can be output as a PIM memory address 806. The output PIM memory address 806 can be an address that is incremented by 1 from the previous output address.

[0103] The address generation module 800 can generate and output an address 806 that increases by one from the start address to the end address.

[0104] The address generation module 800 can divide a series of addresses into memory fields according to predetermined address mapping information, and can generate addresses that increase by one according to the priority / level of the memory fields in an incrementing pattern. For example, the address generation module 800 can generate a four-dimensional continuous address by dividing a series of addresses into four memory fields (i.e., memory channel, memory bank, row, and column). In other words, in addition to one-dimensional and two-dimensional continuous addresses, the address generation module 800 can also generate n-dimensional continuous addresses.

[0105] As described above, the PIM request generation module can be used as a DMA controller. The PIM request generation module enables the address generation module 800 to generate one-dimensional or two-dimensional consecutive addresses to perform DMA controller operations. For example, the address generation module 800 can generate a one-dimensional consecutive address from start address to end address by using only one counter per memory field. Alternatively, the address generation module 800 can generate a two-dimensional consecutive address from start address to end address by using two counters per memory field. Both requests for in-memory operations and general memory requests can be sent to the memory controller via the PIM request generation module.

[0106] Figure 9A and Figure 9B Each illustrates an example of a configuration of a memory system for in-memory operation according to one or more embodiments.

[0107] Reference Figure 9A The memory system 901, and Figure 1 Unlike the memory system 100 shown, the PIM request generation module 911 may be included in the processor 920. If the PIM request generation module 911 is included in the processor 920, the communication overhead with the processor 920 can be reduced.

[0108] Reference Figure 9B The memory system 902, and Figure 1 The memory system 100 shown in the figure and Figure 9A Unlike the memory system 901 shown, the PIM request generation module 912 may be included in the memory controller 930. If the PIM request generation module 912 is included in the memory controller 930, general memory requests and requests for in-memory operations can be easily scheduled.

[0109] Figures 10A to 10C Examples of configurations of memory systems including command tables for PIM requests, according to one or more embodiments, are shown respectively.

[0110] Reference Figure 10A The memory system 1001 may include a command table (PIM Request CMD table) 1011 for PIM requests, which may be included in the PIM generation module 1020. In other words, the command table 1011 may be stored in the storage space of the PIM generation module 1020. As described above, the address of the command table 1011 may be included in the configuration. The PIM request generation module 1020 may refer to the address of the command table 1011 included in the configuration to obtain the data stored in the command table 1011.

[0111] Reference Figure 10B The memory system 1002, and Figure 10AUnlike the memory system 1001 shown, the command table 1012 may be included in the PIM memory 1030. In other words, the command table 1012 may be stored in a portion of the space in the PIM memory 1030.

[0112] Reference Figure 10C The memory system 1003, and Figure 10A The memory system 1001 shown in the figure and Figure 10B Unlike the memory system 1002 shown, command table 1013 may be included in general memory 1040. General memory 1040 may be a memory that does not support in-memory operations, unlike PIM memory 1030. For example, memory system 1003 may include memory controller 0 and memory controller 1.

[0113] The units described herein may be implemented using hardware components, software components, and / or combinations thereof. The processing device may be implemented using one or more general-purpose or special-purpose computers, such as, for example, processors, controllers, and arithmetic logic units (ALUs), digital signal processors (DSPs), microcomputers, field-programmable gate arrays (FPGAs), programmable logic units (PLUs), microprocessors, or any other means capable of responding to and executing instructions in a defined manner. The processing device may run an operating system (OS) and one or more software applications running on the OS. The processing unit may also access, store, manipulate, process, and generate data in response to the execution of the software. For simplicity, the description of the processing unit is used as the singular; however, those skilled in the art will understand that the processing unit may include multiple processing elements and various types of processing elements. For example, the processing unit may include multiple processors, or a single processor and a single controller. Furthermore, different processing configurations (such as parallel processors) are feasible.

[0114] Software may include computer programs, code, instructions, or specific combinations thereof for independently or jointly instructing or configuring a processing unit to operate as needed. Software and data may be stored in any type of machine, component, physical or virtual device, or computer storage medium or device capable of providing instructions or data to or being interpreted by the processing unit. Software may also be distributed across networked computer systems, enabling it to be stored and executed in a distributed manner. Software and data may be stored on one or more non-transitory computer-readable recording media.

[0115] The methods described in the examples above can be recorded in a non-transitory computer-readable medium containing program instructions to implement the various operations described above. The medium may also include program instructions, data files, data structures, etc., individually or in combination. The program instructions recorded on the medium may be program instructions specifically designed and constructed for the purposes of the examples, or they may be of types known and available to those skilled in the art of computer software. Examples of non-transitory computer-readable media include magnetic media (such as hard disks, floppy disks, and magnetic tapes); optical media (such as CD-ROMs and DVDs); magneto-optical media (such as optical discs); and hardware devices specifically configured to store and execute program instructions (such as read-only memory (ROM), RAM, flash memory, etc.). Examples of program instructions include machine code (such as machine code generated by a compiler) and files containing higher-level code that can be executed by a computer using an interpreter.

[0116] Regarding Figures 1 to 10CThe described computing devices, electronic devices, processors, memories, information output systems and hardware, storage devices, and other devices, apparatuses, units, modules, and components are implemented by or represent hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components performing the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer may be implemented by one or more processing elements, such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field-programmable gate arrays, programmable logic arrays, microprocessors, or any other means or combination of means configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, the processor or computer includes or is connected to one or more memories storing instructions or software executed by the processor or computer. Hardware components implemented by a processor or computer can execute instructions or software (such as an operating system (OS) and one or more software applications running on the OS) to perform the operations described in this application. The hardware component can also access, manipulate, process, create, and store data in response to the execution of instructions or software. For simplicity, the singular terms "processor" or "computer" are used in the description of the examples described in this application; however, in other examples, multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component, or two or more hardware components, may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, may implement a single hardware component, or two or more hardware components. The hardware components can have any one or more different processing configurations, examples of which include: single processor, discrete processor, parallel processor, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0117] Figures 1 to 10CThe methods for performing the operations described in this application, as shown, are executed by computing hardware (e.g., one or more processors or a computer), which is implemented to execute instructions or software as described above to perform the operations performed by the methods described in this application. For example, a single operation, or two or more operations, may be executed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be executed by one or more processors, or a processor and a controller, and one or more other operations may be executed by one or more other processors, or additional processors and additional controllers. One or more processors, or a processor and a controller, may execute a single operation, or two or more operations.

[0118] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above can be written as computer programs, code segments, instructions, or any combination thereof to individually or collectively instruct or configure one or more processors or computers to operate as a machine or special-purpose computer to perform operations performed by the hardware components and methods described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) that is directly executed by one or more processors or computers. In another example, the instructions or software include high-level code that is executed by one or more processors or computers using an interpreter. The instructions or software can be written in any programming language based on the block diagrams and flowcharts shown in the accompanying drawings and the corresponding description herein, which disclose algorithms for performing operations performed by the hardware components and methods described above.

[0119] Instructions or software used to control computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, as well as any associated data, data files, and data structures, may be recorded, stored, or fixed in, or on, one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage devices, hard disk drives (HDDs), solid-state drives (SSDs), card storage devices (such as multimedia cards or microcards (e.g., Secure Digital (SD) or Extreme Digital (XD))), magnetic tape, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state drives, and any other device configured to store instructions or software and any associated data, data files, and data structures in a non-transitory manner, and to provide instructions or software and any associated data, data files, and data structures to one or more processors or computers, enabling one or more processors or computers to execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed across a networked computer system, such that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner by one or more processors or computers.

[0120] While this disclosure includes specific examples, it will be clear upon understanding this disclosure that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered descriptive only and not for limiting purposes. The description of features or aspects in each example should be considered applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and / or if components in the described system, architecture, apparatus, or circuit are combined in a different manner, and / or replaced or supplemented by other components or their equivalents.

[0121] Therefore, in addition to the above disclosure, the scope of the disclosure may also be defined by the claims and their equivalents, and all variations within the scope of the claims and their equivalents shall be interpreted as included in the disclosure.

Claims

1. A method for generating an in-memory processing request for an in-memory operation, the method comprising: Receive configuration information from the processor to generate in-memory processing requests; Information about in-memory processing request commands is obtained from the command table, and the steps obtained are based on configuration information; as well as An in-memory processing request is generated based on the information obtained about the in-memory processing request command.

2. The method as described in claim 1, wherein, The steps to obtain information about in-memory processing request commands include: Based on the start address of the command table included in the configuration information, information about the in-memory processing request command is obtained from the command table.

3. The method as described in claim 1, wherein, The steps for generating an in-memory processing request include: Based on the information indicating the address range included in the information about the in-memory processing request command and the address mapping information included in the configuration information, address information corresponding to the in-memory processing request is generated; and Generate an in-memory processing request that includes the generated address information.

4. The method of claim 3, wherein, Address mapping information includes: The mapping information between memory fields and addresses, and the incrementing pattern information of the addresses of memory fields.

5. The method of claim 1, wherein, The steps to obtain information about in-memory processing request commands include: Further, based on the trigger signal received from the processor for generating an in-memory processing request, information about the in-memory processing request command is obtained from the command table.

6. The method of claim 1, further comprising: The in-memory processing request is sent to the memory controller, which is configured to control the in-memory processing memory, which is configured to perform in-memory operations.

7. The method of claim 1, wherein, The processor controls the storage of the command table.

8. The method of claim 1, wherein, The command table contains information about one or more in-memory processing request commands.

9. The method of claim 1, wherein, Information about in-memory processing request commands includes the type of the in-memory processing request command, the address of the in-memory processing request command, and / or the data to be manipulated by the in-memory processing request command.

10. The method of claim 9, wherein, Information about in-memory processing request commands also includes fence information indicating whether a memory fence operation should be performed on the in-memory processing request command.

11. The method of claim 9, wherein, The type indicates the type of in-memory operation or the type of general memory operation.

12. A non-transitory computer-readable storage medium for storing instructions, which, when executed by a processor, cause the processor to perform the method according to any one of claims 1 to 11.

13. An electronic device for in-memory processing, the electronic device comprising: processor; Memory controller; In-memory processing memory; as well as In-memory request generation module The processor is configured to send configuration information to the memory-based request generation module, and The in-memory processing request generation module is configured to perform operations that retrieve information about in-memory processing request commands from the command table based on configuration information, and is also configured to perform operations that generate in-memory processing requests based on the in-memory processing request commands.

14. The electronic device of claim 13, wherein, The in-memory processing request is sent to the memory controller, which is configured to control the in-memory processing memory.

15. The electronic device of claim 13, wherein, The steps to obtain information about in-memory processing request commands include: Based on the start address of the command table included in the configuration information, information about the in-memory processing request command is obtained from the command table.

16. The electronic device of claim 13, wherein, The steps for generating an in-memory processing request include: Based on the information indicating the address range included in the information about the in-memory processing request command and the address mapping information included in the configuration information, address information corresponding to the in-memory processing request is generated; and Generate an in-memory processing request that includes the generated address information.

17. The electronic device of claim 16, wherein, Address mapping information includes: The mapping information between memory fields and addresses, and the incrementing pattern information of the addresses of memory fields.

18. The electronic device of claim 13, wherein, The steps to obtain information about in-memory processing request commands include: Further, based on the trigger signal received from the processor for generating an in-memory processing request, information about the in-memory processing request command is obtained from the command table.

19. The electronic device as claimed in any one of claims 13 to 18, wherein, The command table includes information about one or more in-memory processing request commands, and Information about in-memory processing request commands includes at least one of the following: type information, address information, data information, and fence information indicating whether a memory fence operation should be performed on the in-memory processing request command.

20. A method for in-memory processing, comprising: The processor generates a table containing entries, each entry including a description of the corresponding processing request command in memory; The table is stored in the memory location; Storage configuration, the configuration indicating the location of the table; The processor generates a trigger signal; In response to a trigger signal, access the configuration to obtain the location of the table; Based on the obtained position in the table, the entries in the table are accessed to generate in-memory processing requests corresponding to the respective descriptions of the in-memory processing request commands, each in-memory processing request including an indication of the in-memory processing operation type and an address; The memory controller receives in-memory processing requests and generates in-memory processing commands corresponding to the in-memory processing requests based on the in-memory processing requests. as well as The memory processing device receives and executes in-memory processing commands.

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