Instruction processing method, programmable processor, electronic equipment and storage medium

Abstract

The invention discloses an instruction processing method for a programmable processor, the programmable processor, electronic equipment and a storage medium. A virtual machine kernel function runs on the programmable processor, the virtual machine kernel function comprises at least one pre-generated machine instruction sequence suitable for the programmable processor, and each pre-generated machine instruction sequence in the at least one pre-generated machine instruction sequence has a corresponding byte code array. The instruction processing method comprises the steps of compiling a target kernel function corresponding to a source code into a target byte code array, wherein the target byte code array comprises N target byte codes; determining a pre-generated machine instruction sequence corresponding to the kth target byte code from the kernel function of the virtual machine by using the kth target byte code in the N target byte codes; and executing the pre-generated machine instruction sequence corresponding to the kth target byte code. According to the instruction processing method, cross-platform efficient operation of source codes is achieved, and the flexibility and efficiency of processor program deployment are remarkably improved.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of computers, and more specifically to an instruction processing method, a processor, an electronic device, and a storage medium. Background Technology

[0002] With the rapid development of technologies such as Artificial Intelligence (AI), text processing, and image processing, the demands for computing performance and data processing efficiency are increasing daily. In these scenarios, processors such as Graphics Processing Units (GPUs) and General-Purpose Graphics Processing Units (GPGPUs) have become core acceleration devices due to their powerful parallel computing capabilities. To adapt to the efficient execution of parallel computing hardware platforms such as GPUs and GPGPUs in AI and image processing scenarios, programming languages ​​and programming models for these processors have become a crucial bridge connecting algorithm logic and hardware computing power. Current general-purpose programming languages ​​can map tasks such as matrix operations in deep neural networks and pixel-level operations in image processing to processor-executable kernel functions, fully unleashing the computing potential of multi-core parallel architectures. With the diversification of AI, models, and application scenarios, different hardware architectures place differentiated requirements on programming interfaces, memory management, and execution scheduling. General-purpose programming languages ​​struggle to balance execution efficiency and hardware adaptability; therefore, dedicated programming languages ​​for specific processor hardware platforms have become the core support for ensuring the efficient deployment and operation of AI computing tasks. Summary of the Invention

[0003] This disclosure provides at least one embodiment of an instruction processing method for a programmable processor, wherein the programmable processor runs a virtual machine kernel function, the virtual machine kernel function includes at least one pre-generated machine instruction sequence suitable for the programmable processor, each of the at least one pre-generated machine instruction sequence having a corresponding bytecode array, the instruction processing method comprising: compiling a target kernel function corresponding to source code into a target bytecode array, wherein the target bytecode array includes N target bytecodes, where N is a positive integer; using the k-th target bytecode among the N target bytecodes to determine the pre-generated machine instruction sequence corresponding to the k-th target bytecode from the virtual machine kernel function, where k = 0, 1, ..., N-1; and executing the pre-generated machine instruction sequence corresponding to the k-th target bytecode.

[0004] For example, in the instruction processing method provided in at least one embodiment of this disclosure, the kth target bytecode contains a first instruction address of a pre-generated machine instruction sequence corresponding to the kth target bytecode. Determining the pre-generated machine instruction sequence corresponding to the kth target bytecode from the virtual machine kernel function using the kth target bytecode among the N target bytecodes includes: using the first instruction address to determine the position of the pre-generated machine instruction sequence corresponding to the kth target bytecode in the virtual machine kernel function.

[0005] For example, in the instruction processing method provided in at least one embodiment of this disclosure, the virtual machine kernel function maintains a jump table. The jump table includes a mapping relationship between the first instruction address and the second instruction address of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function. Determining the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function using the first instruction address includes: determining the second instruction address using the first instruction address based on the jump table; and jumping to the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function based on the second instruction address.

[0006] For example, in the instruction processing method provided in at least one embodiment of this disclosure, the kth target bytecode includes the first bytecode address of the kth target bytecode in the target bytecode array, and the virtual machine kernel function includes a first jump instruction. The first jump instruction is used to determine the position of the kth target bytecode in the target bytecode array based on the first bytecode address before determining the pre-generated machine instruction sequence corresponding to the kth target bytecode from the virtual machine kernel function.

[0007] For example, in the instruction processing method provided in at least one embodiment of this disclosure, a local variable table is created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, the at least one local variable including a target local variable, the pre-generated machine instruction sequence corresponding to the k-th target bytecode corresponds to a first operation of the target local variable, the k-th target bytecode contains a first variable address corresponding to the target local variable, and executing the pre-generated machine instruction sequence corresponding to the k-th target bytecode includes: using the first variable address to determine the position of the target local variable in the local variable table; and performing the first operation on the target local variable.

[0008] For example, in the instruction processing method provided in at least one embodiment of this disclosure, a local variable table is created in the shared memory space of the programmable processor. The local variable table includes at least one local variable. The instruction processing method further includes: loading at least one kernel function parameter of the target kernel function and the operand of the kernel function parameter into the local variable table, so as to use the at least one kernel function parameter as a local variable in the local variable table.

[0009] For example, in the instruction processing method provided in at least one embodiment of this disclosure, a local variable table and an operand stack are created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, and the at least one local variable includes a first local variable. The operands of the first local variable are stored in the local variable table. In response to a loading operation of the pre-generated machine instruction sequence corresponding to the k-th target bytecode corresponding to the first local variable, the pre-generated machine instruction sequence corresponding to the k-th target bytecode is executed, including: copying the operands of the first local variable from the local variable table to the operand stack.

[0010] For example, in the instruction processing method provided in at least one embodiment of this disclosure, a local variable table and an operand stack are created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, and the at least one local variable includes at least one second local variable. The operands of the at least one second local variable are stored in the operand stack. In response to a first operation corresponding to the at least one second local variable in the pre-generated machine instruction sequence corresponding to the k-th target bytecode, the pre-generated machine instruction sequence corresponding to the k-th target bytecode is executed, including: retrieving the operands of the at least one second local variable from the operand stack; performing the first operation using the operands of the at least one second local variable to obtain a first operation result; and storing the first operation result in the operand stack.

[0011] For example, in the instruction processing method provided in at least one embodiment of this disclosure, a local variable table and an operand stack are created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, and the at least one local variable includes a third local variable. The operand of the third local variable corresponds to a first operation result obtained by performing a first operation in the programmable processor. The first operation result is stored in the operand stack. In response to the storage operation of the third local variable corresponding to the pre-generated machine instruction sequence corresponding to the k-th target bytecode, the pre-generated machine instruction sequence corresponding to the k-th target bytecode is executed, including: copying the first operation result from the operand stack to the position of the operand of the third local variable in the local variable table.

[0012] For example, in the instruction processing method provided in at least one embodiment of this disclosure, in response to the fact that the pre-generated machine instruction sequence corresponding to the k-th target bytecode does not include an exit instruction and k is less than N-1, after executing the pre-generated machine instruction sequence corresponding to the k-th target bytecode, the instruction processing method further includes: jumping to the (k+1)-th target bytecode in the target bytecode array; using the (k+1)-th target bytecode, determining the pre-generated machine instruction sequence corresponding to the (k+1)-th target bytecode from the virtual machine kernel function; and executing the pre-generated machine instruction sequence corresponding to the (k+1)-th target bytecode.

[0013] For example, in the instruction processing method provided in at least one embodiment of this disclosure, the (k+1)th target bytecode contains the address of the second bytecode of the (k+1)th target bytecode in the target bytecode array, and the virtual machine kernel function contains a second jump instruction corresponding to the second bytecode address. After executing the pre-generated machine instruction sequence corresponding to the kth target bytecode, jumping to the (k+1)th target bytecode in the target bytecode array includes: executing the second jump instruction to determine the position of the (k+1)th target bytecode in the target bytecode array based on the second bytecode address.

[0014] For example, at least one embodiment of the instruction processing method provided in this disclosure further includes: compiling the source code into an intermediate form expression; in response to the intermediate form expression including a hotspot kernel function, compiling the hotspot kernel function into a sequence of native machine instructions suitable for the programmable processor in real time; and executing the sequence of native machine instructions.

[0015] For example, in the instruction processing method provided in at least one embodiment of this disclosure, compiling a target kernel function corresponding to the source code into the target bytecode array includes: compiling the target kernel function into the target bytecode array in response to the intermediate form expression including the target kernel function.

[0016] For example, at least one embodiment of the instruction processing method provided in this disclosure further includes: compiling the source code into an intermediate form expression; determining the intermediate form expression as the target kernel function; and simultaneously compiling the target kernel function corresponding to the source code into the target bytecode array, initiating just-in-time compilation of the intermediate form expression to compile the intermediate form expression into a sequence of native machine instructions suitable for the programmable processor in the background of the programmable processor.

[0017] At least one embodiment of this disclosure also provides a programmable processor, wherein a virtual machine kernel function runs on the programmable processor, the virtual machine kernel function includes at least one pre-generated machine instruction sequence suitable for the programmable processor, each of the at least one pre-generated machine instruction sequence having a corresponding bytecode array, the programmable processor comprising: a compilation module configured to compile a target kernel function corresponding to source code into a target bytecode array, wherein the target bytecode array includes N target bytecodes, where N is a positive integer; a determination module configured to use the kth target bytecode among the N target bytecodes to determine the pre-generated machine instruction sequence corresponding to the kth target bytecode from the virtual machine kernel function, where k = 0, 1, ..., N-1; and an execution module configured to execute the pre-generated machine instruction sequence corresponding to the kth target bytecode.

[0018] At least one embodiment of this disclosure also provides an electronic device. The electronic device includes: one or more processors; a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the one or more processors, and the one or more computer program modules are used to implement the instruction processing method provided in any embodiment of this disclosure.

[0019] At least one embodiment of this disclosure also provides a storage medium. The storage medium stores non-transitory computer-readable instructions that, when executed by a computer, implement the instruction processing method provided in any embodiment of this disclosure.

[0020] The instruction processing method, programmable processor, electronic device, and storage medium provided in at least one embodiment of this disclosure, by compiling source code into hardware platform-independent general bytecode, and then translating the bytecode into a sequence of machine instructions for the corresponding platform based on the virtual machine kernel function running on the hardware platform, can achieve one-time compilation of source code into bytecode and multi-platform interpretation and execution, thereby realizing efficient cross-platform operation of source code. In addition, after the source code is modified, it does not need to be recompiled and linked for specific hardware. The results can be immediately executed based on the virtual machine kernel function to view the results, shortening the development feedback cycle, lowering the development threshold, accelerating prototype verification, and significantly improving the flexibility and efficiency of processor program deployment. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0022] Figure 1This is a schematic diagram of the architecture of a general-purpose graphics processing unit (GPGPU).

[0023] Figure 2 An exemplary flowchart of an instruction processing method provided in at least one embodiment of this disclosure;

[0024] Figure 3 A schematic diagram illustrating an example of an instruction processing method provided in at least one embodiment of this disclosure;

[0025] Figure 4 A schematic diagram illustrating another example of the instruction processing method provided in at least one embodiment of this disclosure;

[0026] Figure 5 A schematic diagram illustrating yet another example of the instruction processing method provided in at least one embodiment of this disclosure;

[0027] Figure 6 A schematic block diagram of a programmable processor provided for at least one embodiment of the present disclosure;

[0028] Figure 7 A schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0029] Figure 8 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure;

[0030] Figure 9 This is a schematic diagram of a storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0033] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and components may be omitted. When any component of the embodiments of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0034] Currently, programming languages ​​in the computer field are mainly divided into two categories based on their execution method: compiled languages ​​and interpreted languages. Compiled languages ​​are those where, before program execution, a dedicated compiler translates the user-provided source code into machine instruction code that the target hardware platform can directly recognize and execute. Subsequent program execution does not require further translation; it simply executes the compiled machine instruction code. This results in high execution efficiency and is well-suited to the computational needs of programmable processors. In contrast, interpreted languages ​​do not require complete compilation before execution. Instead, an interpreter program reads the source code line by line or block by block, translates each section immediately after reading it, and executes the translated machine instructions simultaneously. Its core characteristic is that translation and execution occur concurrently, eliminating the need to generate separate machine instruction code files. While this offers some convenience in development and debugging, its execution efficiency is lower, making it difficult to meet the performance requirements of large-scale parallel computing tasks handled by processors such as GPUs and GPGPUs.

[0035] In current applications of programmable processors such as GPUs and GPGPUs, mainstream programming languages ​​(e.g., CUDA, OpenCL) generally adopt a compiled language architecture. However, these compiled programming languages ​​suffer from several insurmountable technical drawbacks in practical applications: Firstly, the compiled machine instruction code is highly bound to specific operating systems and hardware architectures, exhibiting strong platform dependence. To ensure the same source code runs correctly on different hardware and software platforms (e.g., GPUs from different manufacturers, operating system versions), developers need to perform separate compilation operations for each target platform. This significantly increases development workload and reduces cross-platform compatibility, hindering the large-scale promotion and application of related technologies and products. Secondly, most compiled programming languages ​​are proprietary to specific hardware manufacturers, lacking universality. Programming languages ​​for different manufacturers' hardware platforms differ significantly in syntax rules, programming logic, and interface design, further increasing development difficulty and cost, and limiting the application scenarios of programmable processors.

[0036] In addition, the inherent characteristics of compiled languages ​​further limit the development efficiency and debugging convenience of processor-related programs. Specifically, during program development, if developers make any modifications to the source code, regardless of the size of the modification, the entire source code needs to be recompiled and linked. Each recompilation and linking process after modification is time-consuming, severely reducing development efficiency, extending the project development cycle, and increasing project development costs. At the same time, compiled languages ​​have poor debuggability. If errors or exceptions occur during program execution, they cannot be directly debugged in real time through the source code. Problem localization and troubleshooting can only be achieved with the help of symbol tables, dedicated debuggers, and other auxiliary tools. This not only increases the difficulty and cost of debugging but may also cause project delays due to the inability to locate problems in a timely manner, making it difficult to meet the application requirements of artificial intelligence, deep learning, and other fields that demand high stability and reliability of programs.

[0037] This disclosure provides at least one embodiment of an instruction processing method for a programmable processor. The programmable processor runs a virtual machine kernel function, which includes at least one pre-generated machine instruction sequence suitable for the programmable processor. Each pre-generated machine instruction sequence has a corresponding bytecode array. The instruction processing method includes: compiling a target kernel function corresponding to source code into a target bytecode array, wherein the target bytecode array includes N target bytecodes, where N is a positive integer; using the k-th target bytecode among the N target bytecodes, determining the pre-generated machine instruction sequence corresponding to the k-th target bytecode from the virtual machine kernel function, where k = 0, 1, ..., N-1; and executing the pre-generated machine instruction sequence corresponding to the k-th target bytecode.

[0038] At least one embodiment of this disclosure also provides at least one programmable processor, electronic device, and storage medium for implementing the instruction processing method of the above embodiments.

[0039] The instruction processing method, programmable processor, electronic device, and storage medium provided in at least one embodiment of this disclosure, by compiling source code into hardware platform-independent general bytecode, and then translating the bytecode into a sequence of machine instructions for the corresponding platform based on the virtual machine kernel function running on the hardware platform, can achieve one-time compilation of source code into bytecode and multi-platform interpretation and execution, thereby realizing efficient cross-platform operation of source code. In addition, after the source code is modified, it does not need to be recompiled and linked for specific hardware. The results can be immediately executed based on the virtual machine kernel function to view the results, shortening the development feedback cycle, lowering the development threshold, accelerating prototype verification, and significantly improving the flexibility and efficiency of processor program deployment.

[0040] At least one embodiment of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the same reference numerals will be used to refer to the same elements described in different drawings.

[0041] The programmable processor provided in at least one embodiment of this disclosure can be a hardware platform with programmable capabilities, such as a CPU, GPU, GPGPU, Tensor Processing Unit (TPU), etc. The type and specific implementation of the programmable processor can be selected according to actual needs, and the embodiments of this disclosure do not limit this.

[0042] Figure 1 This is a schematic diagram of a general-purpose graphics processing unit (GPGPU).

[0043] For example, with Figure 1 Taking the general-purpose graphics processor shown as an example, a general-purpose graphics processor is actually an array of streaming processor clusters (SPCs), such as including... Figure 1 The diagram shows streaming processor clusters 1, ..., M, where M is a positive integer greater than 1. In a graphics processing unit (GPU), one streaming processor cluster processes one computational task, or multiple streaming processor clusters process one computational task. Multiple streaming processor clusters share data through a global cache or global memory.

[0044] For example, such as Figure 1 As shown, taking streaming processor cluster 1 as an example, a streaming processor cluster includes multiple computing units (CUs, such as streaming processors), for example... Figure 1The computation unit is structured as computation unit 1, computation unit 2, ..., computation unit Y, where Y is a positive integer. Each computation unit performs arithmetic and logical operations other than matrix calculations such as matrix multiplication and convolution, including operations like accumulation, reduction, and regular addition, subtraction, multiplication, and division. A computation unit contains multiple cores (also called computation kernels), each including an arithmetic logic unit (ALU), a floating-point unit, etc., which execute specific computational tasks. Furthermore, the computation unit also includes registers (e.g., ...). Figure 1 The register file and shared memory in a computing unit are used to store source and destination data related to computing tasks in a hierarchical manner. The shared memory in a computing unit is used to share data between the cores of that computing unit.

[0045] For example, in parallel computing, computational tasks are typically executed by multiple threads. These threads are divided into multiple thread blocks before execution in a general-purpose graphics processor (or parallel computing processor), and then dispatched via a thread block dispatch module. Figure 1 (Not shown in the image) Multiple thread blocks are distributed to various computation units. All threads in a thread block must be assigned to the same computation unit for execution. Simultaneously, thread blocks are broken down into minimum execution thread bundles (or simply thread bundles), each containing a fixed number (or less than this fixed number) of threads, for example, 32 threads. Multiple thread blocks can execute in the same computation unit or in different computation units.

[0046] For example, in each computing unit, the thread beam scheduling / distribution module ( Figure 1 (Not shown in the diagram) Thread bundles are scheduled and allocated so that multiple computing cores within the computing unit can run thread bundles. Depending on the number of computing cores in the computing unit, multiple thread bundles within a thread block can be executed concurrently or in a time-sharing manner. Multiple threads within each thread bundle execute the same instructions. Memory execution instructions are issued to shared memory within the computing unit or further issued to intermediate-level caches, global caches, or global memory for read and write operations, etc.

[0047] Figure 2 An exemplary flowchart of an instruction processing method provided in at least one embodiment of this disclosure.

[0048] For example, Figure 2 The instruction processing method shown is for a programmable processor that runs a virtual machine kernel function; the virtual machine kernel function includes one or more pre-generated machine instruction sequences suitable for the programmable processor, each pre-generated machine instruction sequence having a corresponding bytecode array.

[0049] For example, such as Figure 2 As shown, the instruction processing method may include the following steps S110 to S130.

[0050] Step S110: Compile the target kernel function corresponding to the source code into an array of target bytecode.

[0051] For example, in step S110, the source code can be program code written by the user, such as program code written by the developer to implement a specific computing task (such as matrix operation of AI model, pixel operation of image processing, etc.), such as simple operation logic code for GPU parallel computing.

[0052] For example, in step S110, the target kernel function can be a program module corresponding to a specific computational task, generated by compiling source code. For example, in some examples, the target kernel function can be an intermediate representation (IR) generated by compiling source code; in other examples, the target kernel function can be a specific kernel function selected from multiple kernel functions contained in the intermediate representation generated from source code, which needs to be processed separately for accelerated interpretation, that is, the kernel function processed by the instruction processing method provided in at least one embodiment of this disclosure.

[0053] It should be noted that, in at least one embodiment of this disclosure, the source code and its corresponding target kernel function can be selected according to actual needs, and the embodiments of this disclosure do not impose any restrictions on this.

[0054] For example, in step S110, the target bytecode array includes N target bytecodes, where N is a positive integer. For example, in actual runtime, the target bytecode array can be loaded from the programmable processor's global memory into a shared storage space (such as shared memory or intermediate cache) for execution.

[0055] For example, bytecode is intermediate code generated after compiling the target kernel function corresponding to the source code. Unlike machine instructions that are executed directly on the hardware, bytecode can be encoded in binary or other forms and is interpreted and executed on the virtual machine kernel function (or virtual machine program) written on the processor. For example, the bytecode compiled from the same source code is the same on different processor hardware models or different operating system platforms, and it will not change due to different platform architectures or instruction sets. The virtual machine then translates the bytecode into machine instructions that can run on the corresponding platform according to the characteristics of each platform.

[0056] For example, bytecode can be implemented in binary form or in other forms as needed, and the embodiments disclosed herein do not limit this.

[0057] Step S120: Using the kth target bytecode among the N target bytecodes, determine the pre-generated machine instruction sequence corresponding to the kth target bytecode from the virtual machine kernel function, where k = 0, 1, ..., N-1.

[0058] For example, step S120 involves using a virtual machine program in the programmable processor to interpret (or translate) the k-th target bytecode to obtain the corresponding pre-generated machine instruction sequence. For example, in step S120, the pre-generated machine instruction sequence is a pre-written machine instruction sequence suitable for the programmable processor, which can be directly executed on the programmable processor. For example, the programmable processor needs to pre-write pre-generated machine instruction sequences for all bytecode, so that any bytecode can be interpreted and executed by the programmable processor. For example, the specific instruction content of the pre-generated machine instruction sequence is related to the specific hardware platform. Different hardware platforms (e.g., different types or models of programmable processors) have different native machine instructions; therefore, the specific instruction content of the pre-generated machine instruction sequence obtained by translating the same bytecode on different hardware platforms is different. In other words, the same set of bytecode can be interpreted and converted into machine language corresponding to different hardware platforms, thereby achieving cross-platform operation. The specific form of the pre-generated machine instruction sequence can be selected according to actual needs, and the embodiments of this disclosure do not limit this.

[0059] For example, in at least one embodiment of this disclosure, the virtual machine kernel function is a complete program composed of pre-generated machine instruction sequences corresponding to all bytecode. The virtual machine is a runtime environment simulated by software. The virtual machine executes the computational logic in the virtual machine program by scheduling the virtual machine kernel function, such as interpreting and executing the pre-generated machine instruction sequences corresponding to the bytecode. For example, in actual runtime, the virtual machine kernel function can be loaded from the global memory of the programmable processor into the instruction cache for execution. For example, a detailed description of the virtual machine or virtual machine kernel function can be found in relevant descriptions in the art, and will not be repeated here. Its specific form can be selected according to actual needs, and the embodiments of this disclosure do not limit it.

[0060] Step S130: Execute the pre-generated machine instruction sequence corresponding to the k-th target bytecode.

[0061] For example, in step S130, the pre-generated machine instruction sequence corresponding to the k-th target bytecode is a set of instructions that the hardware can directly execute after the k-th target bytecode has been translated by the virtual machine. It is used to complete the actual operation on the data. For example, it may include load instructions, store instructions, operation instructions or jump instructions, etc. The specific instructions can be selected according to actual needs. The embodiments of this disclosure do not limit this.

[0062] For example, step S130 can be executed by one or more computing units in a programmable processor, or by other execution modules. The specific execution can be selected according to actual needs, and the embodiments of this disclosure do not limit this.

[0063] It should be noted that, in at least one embodiment of this disclosure, the target bytecode array can be composed of any one or more bytecodes forming any set of target bytecode arrays, and each bytecode in the target bytecode array that needs to be interpreted and executed can be configured according to... Figure 2 The steps S120-S130 shown are used to interpret and execute the target bytecode. For example, the k-th target bytecode can be the starting target bytecode in the interpretation and execution flow of the target bytecode array, or it can be any other target bytecode in the interpretation and execution flow of the target bytecode array. The specific choice can be made according to actual needs, and the embodiments of this disclosure do not limit this.

[0064] In some examples, the k-th target bytecode contains the address of the first instruction in the pre-generated machine instruction sequence corresponding to the k-th target bytecode. For example, Figure 2 Step S120 may further include the following step S121.

[0065] Step S121: Use the first instruction address to determine the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function.

[0066] For example, in step S121, the first instruction address corresponds to the specific position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function. For instance, the first instruction address can be directly set to the line number of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function, thereby enabling direct lookup of the specific position of the pre-generated machine instruction sequence in the virtual machine kernel function; the first instruction address can also indirectly correspond to the line number of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function, for example, by looking up the relationship between the first instruction address and the line number of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the jump table, thereby finding the specific position of the pre-generated machine instruction sequence in the virtual machine kernel function; the first instruction address can also be set to other forms, which can be selected according to actual needs, and the embodiments of this disclosure do not limit this.

[0067] For example, in some examples, the virtual machine kernel function maintains a jump table, which includes a mapping relationship between the first instruction address and the second instruction address in the virtual machine kernel function corresponding to the pre-generated machine instruction sequence corresponding to the k-th target bytecode. For example, step S121 may further include the following steps S1211~S1212.

[0068] Step S1211: Based on the jump table, determine the second instruction address using the first instruction address;

[0069] Step S1212: Jump to the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function based on the second instruction address.

[0070] For example, in step S1211, based on the mapping relationship between the first instruction address and the second instruction address included in the jump table, the second instruction address can be found using the first instruction address. For example, the second instruction address can be the line number of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function, or it can be set to other forms. The specific choice can be made according to actual needs, and the embodiments of this disclosure do not limit this.

[0071] For example, in step S1212, the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function can be determined based on the second instruction address, so that a jump can be made to that position to... Figure 2 The pre-generated machine instruction sequence is executed in step S130.

[0072] For example, in some examples, the k-th target bytecode contains the address of the first bytecode of the k-th target bytecode in the target bytecode array. For example, a virtual machine kernel function contains a first jump instruction, which is used to... Figure 2 Before step S120, the position of the kth target bytecode in the target bytecode array is determined based on the address of the first bytecode.

[0073] For example, if the k-th target bytecode is the starting target bytecode in the interpretation and execution flow of the target bytecode array, then at the beginning of the virtual machine program, a first jump instruction can be used to jump to the k-th target bytecode to determine which target bytecode the virtual machine interpretation will start from. If the k-th target bytecode is not the starting target bytecode in the interpretation and execution flow of the target bytecode array, then at the end of the execution of the pre-generated machine instruction corresponding to the previous target bytecode, a first jump instruction can be used to jump to the k-th target bytecode to determine which target bytecode needs to be interpreted by the virtual machine.

[0074] For example, the above process can be implemented by setting a bytecode array pointer. For instance, the first jump instruction corresponds to a bytecode array pointer. At the start of the virtual machine program, the bytecode array pointer points to the starting bytecode in the target bytecode array. Figure 1The steps S120-S130 shown illustrate the interpretation and execution of the starting bytecode; during the execution of the virtual machine program, when the pre-generated machine instruction corresponding to the previous target bytecode finishes execution, the bytecode array pointer points to the next target bytecode to be executed, through... Figure 1 The steps S120~S130 shown are used to interpret and execute the target bytecode.

[0075] For example, in some examples, a local variable table is created in the shared memory space of the programmable processor, which includes one or more local variables, including the target local variable.

[0076] For example, in at least one embodiment of this disclosure, a local variable table can be created in the shared memory space of the programmable processor. The local variable table can be used to store one or more local variables and their corresponding operands. For example, the target local variable can be any local variable in the local variable table. The target local variable can be a kernel function parameter used as an input variable in the target kernel function corresponding to the source code, or it can be an intermediate temporary variable during the operation process. It can also be selected as other types of parameters or variables according to actual needs; the embodiments of this disclosure do not limit this. Similarly, the operands corresponding to the target local variable can be specific values ​​of the kernel function parameters, or they can be intermediate data or the final result obtained during the operation process. They can also be selected as other types of data according to actual needs; the embodiments of this disclosure do not limit this either.

[0077] For example, the pre-generated machine instruction sequence corresponding to the k-th target bytecode corresponds to the first operation on the target local variable, and the k-th target bytecode contains the address of the first variable corresponding to the target local variable. For example, Figure 1 The step S130 shown includes the following steps S131~S132.

[0078] Step S131: Use the address of the first variable to determine the position of the target local variable in the local variable table;

[0079] Step S132: Perform the first operation on the target local variable.

[0080] For example, in step S131, the k-th target bytecode contains the address of a first variable corresponding to a target local variable. This first variable address is used to find the specific location of the target local variable in the local variable table. For example, the first variable address can be directly set to the row number of the target local variable in the local variable table, thereby enabling direct lookup of the specific location of the target local variable in the local variable table. The first variable address can also be implemented using a mapping table or other methods, and the specific choice can be made according to actual needs. The embodiments of this disclosure do not limit this.

[0081] For example, in step S132, the first operation on the target local variable can be an actual operation on the operands of the target local variable. This first operation can be actually executed by one or more machine instructions in the pre-generated machine instruction sequence corresponding to the k-th target bytecode. For example, the first operation can be a load operation, a store operation, an arithmetic operation, or a jump operation, etc., and can be selected according to actual needs. The embodiments of this disclosure do not limit this.

[0082] For example, in some examples, the instruction processing method provided in at least one embodiment of this disclosure may further include the following step S140.

[0083] Step S140: Load at least one kernel function parameter and the operands of the target kernel function into the local variable table, so that at least one kernel function parameter is a local variable in the local variable table.

[0084] For example, in step S140, the kernel function parameters and their operands, which are input variables in the target kernel function, can be loaded into the local variable table as local variables; the target bytecode and its corresponding pre-generated machine instructions can call the kernel function parameters to perform the corresponding actual operations on the operands of the kernel function parameters.

[0085] For example, in some examples, an operand stack is also created in the shared memory space of the programmable processor. The operand stack is a stack structure used to temporarily store data and perform calculations during the execution of virtual machine kernel functions. All kinds of operations are performed through the operand stack, such as retrieving operands from the stack for calculation and then pushing the calculation result back onto the stack, thereby realizing data processing such as loading, calculation, and storage. For a detailed introduction to the operand stack, please refer to the description in this field, which will not be repeated here.

[0086] For example, in some examples, the local variable table includes a first local variable, and the operands of the first local variable are stored in the local variable table. For instance, a load operation on the first local variable corresponds to a pre-generated sequence of machine instructions for the k-th target bytecode. Figure 2 Step S130 may further include the following step S133.

[0087] Step S133: Execute one or more machine instructions from the pre-generated machine instruction sequence corresponding to the k-th target bytecode, and copy the operands of the first local variable from the local variable table to the operand stack.

[0088] For example, in step S133, when the loading operation of the first local variable in the pre-generated machine instruction sequence corresponding to the k-th target bytecode is performed, the pre-generated machine instruction sequence includes one or more machine instructions for loading the first local variable. For example, by executing one or more machine instructions in the pre-generated machine instruction sequence, the operands of the first local variable can be copied from the local variable table to the operand stack, thereby realizing the corresponding loading operation.

[0089] For example, in some examples, the local variable table includes one or more second local variables, the operands of which are stored in the operand stack. For example, the one or more second local variables may include a first local variable whose operands were copied from the local variable table to the operand stack in a previous load operation; the one or more second local variables may also be other types of local variables, which can be selected according to actual needs, and the embodiments of this disclosure do not limit this.

[0090] For example, the first operation corresponding to the pre-generated machine instruction sequence corresponding to the k-th target bytecode is the operation performed on the one or more second local variables. Figure 2 Step S130 may further include the following steps S134 to S136.

[0091] Step S134: Remove at least one operand of the second local variable from the operand stack;

[0092] Step S135: Perform the first operation using at least one operand of the second local variable to obtain the first operation result;

[0093] Step S136: Store the first operation result onto the operand stack.

[0094] For example, when the pre-generated machine instruction sequence corresponding to the k-th target bytecode corresponds to the first operation on one or more second local variables, the pre-generated machine instruction sequence includes one or more machine instructions for performing the first operation on one or more second local variables. For example, in step S134, the operands of one or more second local variables used for the first operation are taken out of the operand stack; in step S135, the first operation is performed on the taken operands of one or more second local variables to obtain the first operation result; in step S136, the first operation result is stored back into the operand stack for use in subsequent operations.

[0095] For example, in some examples, the local variable table includes a third local variable whose operands correspond to the first operation result obtained by performing the first operation in the programmable processor, and the first operation result is stored in the operand stack.

[0096] For example, in response to the pre-generated machine instruction sequence corresponding to the k-th target bytecode, a storage operation on the third local variable is performed. Figure 2 Step S130 may further include the following step S137.

[0097] Step S137: Copy the result of the first operation from the operand stack to the operand position of the third local variable in the local variable table.

[0098] For example, in step S137, when the storage operation of the third local variable in the pre-generated machine instruction sequence corresponding to the k-th target bytecode is performed, the pre-generated machine instruction sequence includes one or more machine instructions for storing the third local variable. For example, by executing one or more machine instructions in the pre-generated machine instruction sequence, the operand of the third local variable (i.e., the first operation result) can be copied from the operand stack to the local variable table.

[0099] For example, before executing step S137, the operand position of the third local variable in the local variable table can be empty (i.e., without data); after executing step S137, the result of the first operation is copied to the operand position of the third local variable in the local variable table. As another example, before executing step S137, the operand position of the third local variable in the local variable table can be other data; after executing step S137, the result of the first operation is copied to the operand position of the third local variable in the local variable table to overwrite the previous data.

[0100] It should be noted that, in at least one embodiment of this disclosure, the shared storage space of the programmable processor can be shared memory in the programmable processor computing unit, or it can be an intermediate-level cache shared by multiple computing units, or it can be selected as other types of storage space in the programmable processor according to actual needs. The specific selection can be made according to actual needs, and the embodiments of this disclosure do not limit this.

[0101] The instruction processing method provided in at least one embodiment of this disclosure creates a local variable table and operand stack in the shared memory space of the programmable processor. This eliminates the need for data transfer across modules or chips during the execution of bytecode and machine instructions, reducing memory access latency and improving instruction execution efficiency. Furthermore, the storage management method of the local variable table and operand stack facilitates unified monitoring and scheduling of the kernel function's running status by the hardware, enhancing the system's controllability and flexibility.

[0102] For example, in some cases, the pre-generated machine instruction sequence corresponding to the k-th target bytecode does not include an exit instruction and k is less than N-1. Figure 1After step S130 shown, the instruction processing method provided in at least one embodiment of this disclosure may further include the following steps S150 to S170.

[0103] Step S150: Jump to the (k+1)th target bytecode in the target bytecode array;

[0104] Step S160: Using the (k+1)th target bytecode, determine the pre-generated machine instruction sequence corresponding to the (k+1)th target bytecode from the virtual machine kernel function;

[0105] Step S170: Execute the pre-generated machine instruction sequence corresponding to the (k+1)th target bytecode.

[0106] For example, if the pre-generated machine instruction sequence corresponding to the k-th target bytecode does not include an exit instruction, and the k-th target bytecode is not the last target bytecode in the target bytecode array, then in step S150, the execution jumps to the (k+1)-th target bytecode in the target bytecode array, which is the next target bytecode to be executed. For example, the k-th and (k+1)-th target bytecodes can be two adjacent bytecodes in the bytecode array, or they can be two non-adjacent bytecodes. The specific settings can be configured according to actual needs, and the embodiments of this disclosure do not impose any limitations on this.

[0107] For example, in steps S160~S170, the (k+1)th target bytecode is subjected to AND... Figure 2 The same operations are performed in steps S120 to S130 to determine and execute the pre-generated machine instruction sequence corresponding to the (k+1)th target bytecode.

[0108] For example, the (k+1)th target bytecode contains the address of its second bytecode within the target bytecode array, and the virtual machine kernel function contains a second jump instruction corresponding to that second bytecode address. For example, in Figure 1 After step S130, step S150 may further include the following step S151.

[0109] Step S151: Execute the second jump instruction to determine the position of the (k+1)th target bytecode in the target bytecode array based on the address of the second bytecode.

[0110] For example, in step S151, when the execution of the pre-generated machine instruction corresponding to the k-th target bytecode ends, a second jump instruction can be used to jump to the (k+1)-th target bytecode to perform subsequent virtual machine interpretation and execution steps on the (k+1)-th target bytecode.

[0111] It should be noted that, in at least one embodiment of this disclosure, the operation method for interpreting and executing the (k+1)th target bytecode is the same as that for the kth target bytecode, as described above, and will not be repeated here.

[0112] Figure 3 This is a schematic diagram illustrating an example of an instruction processing method provided in at least one embodiment of this disclosure. For example, Figure 3 It can be Figure 1 This is a specific example of the instruction processing method shown.

[0113] For example, such as Figure 3 As shown, programmable processor ( Figure 3 (Not shown in the image) A virtual machine kernel function runs in the programmable processor, and a local variable table and operand stack are created in the programmable processor's shared memory space. For example, during actual runtime, the virtual machine kernel function can be loaded from the programmable processor's global memory into the instruction cache for execution. For example, as... Figure 3 As shown, Figure 2 In step S110, the array of target bytecode compiled from the target kernel function corresponding to the source code can be loaded from the global memory of the programmable processor into the shared memory space.

[0114] For example, such as Figure 3 As shown, taking the `func(a, b)` operation in the source code as an example, `func(a, b)` is used to implement `c = a + b`, where `a` and `b` are the two kernel function parameters corresponding to the target kernel function in the source code, and `c` is an intermediate temporary variable during the operation. For example, before the program runs, in step S140, the kernel function parameters `a` and `b` and their operands are loaded into the local variable table as two local variables.

[0115] For example, the contents of the local variable table can be simplified as follows: Figure 3 The local variable table takes the form shown. For example, the first column of the local variable table represents the row number of the local variable, the second column represents the local variables a, b, and c, and the third column represents the operands of the local variables. For example, the operand of local variable a in this local variable table is 1.0 (i.e., a = 1.0), and the operand of local variable b is 1.0 (i.e., b = 2.5); the operand position of c is empty before the actual addition operation is performed.

[0116] For example, the target bytecode array compiled from the source code can be simplified to the following expression: Figure 3 As shown in the form. For example, as Figure 3As shown, the first column of the target bytecode array represents the bytecode address 0, 1, 2, 3 of the target bytecode. That is, the bytecode array includes 4 rows of bytecode (the 0th target bytecode, the 1st target bytecode, the 2nd target bytecode, and the 3rd target bytecode).

[0117] For example, such as Figure 3 As shown, taking the 0th target bytecode as an example, in order from left to right, "load a" indicates that the 0th target bytecode is used to load 'a', "1" indicates the first instruction address of the pre-generated machine instruction sequence corresponding to the 0th target bytecode, and "000" indicates the first variable address of the local variable in the local variable table corresponding to the target bytecode. For example, Figure 3 The representation of the first, second, and third target bytecodes is similar to that of the 0th target bytecode, and will not be repeated here.

[0118] For example, the pre-generated machine instruction sequence corresponding to the target bytecode array above can be simply represented as follows: Figure 3 The form shown in the dashed box within the virtual machine kernel function. For example, as... Figure 3 As shown, in the pre-generated machine instruction sequence, the first line `jump code[pc++]` represents the first jump instruction. The initial value of `pc` corresponds to the address 0 of the first bytecode of the 0th target bytecode, and `code` represents the target bytecode array (that is, this first jump instruction is used to jump between multiple target bytecodes in the target bytecode array). For example, in... Figure 2 Before step S120, by executing the first jump instruction, the position of the 0th target bytecode in the target bytecode array can be determined based on the address of the first bytecode.

[0119] For example, in Figure 3 In the pre-generated machine instruction sequences shown, 1, 10, and 20 represent the second instruction addresses, respectively. The machine instruction sequence corresponding to second instruction address 1 is used to perform a load operation, the machine instruction sequence corresponding to second instruction address 10 is used to perform an add operation, and the machine instruction sequence corresponding to second instruction address 1 is used to perform a store operation. It should be noted that the specific instruction content is omitted in the simplified representation of the pre-generated machine instruction sequences above. The instruction content of different machine instruction sequences can be set according to actual needs. For details, please refer to the description in this art. The embodiments disclosed herein do not limit this.

[0120] For example, further, such as Figure 3As shown, in step S121, the first instruction address 1 in the 0th target bytecode directly corresponds to the second instruction address 1 in the machine instruction sequence, thereby determining the position of the pre-generated machine instruction sequence (i.e. the sequence corresponding to load) corresponding to the 0th target bytecode in the virtual machine kernel function.

[0121] For example, such as Figure 3 As shown, in order to execute the pre-generated machine instruction sequence corresponding to the 0th target bytecode, in step S131, the address 000 of the first variable in the 0th target bytecode is used to determine the row number 000 of the corresponding local variable a in the local variable table, so that the corresponding loading operation can be performed on the local variable a in step S132.

[0122] For example, specifically, such as Figure 3 As shown, in step S133, one or more machine instructions in the pre-generated machine instruction sequence corresponding to the 0th target bytecode are executed to copy the operand 2.5 of the local variable a from the local variable table to the top of the operand stack, thereby completing the corresponding loading operation on the local variable a.

[0123] For example, further, such as Figure 3 As shown, when the pre-generated machine instruction corresponding to the 0th target bytecode finishes execution, in step S151, the second jump instruction jump code[pc++] is executed. Since the value of pc increases from 0 to 1 after the execution of the first jump instruction jump code[pc++] in the initial first line, the value of pc corresponds to the address 1 of the first target bytecode when the second jump instruction jump code[pc++] is executed. Thus, the position of the first target bytecode in the target bytecode array can be determined through this second bytecode address 1, and the jump can be made to the first target bytecode.

[0124] For example, for subsequent target bytecode, the corresponding operations are performed in a similar manner as described above. For example, as... Figure 3 As shown, for the first target bytecode, in step S121, the first instruction address 1 in the first target bytecode directly corresponds to the second instruction address 1 in the machine instruction sequence, thereby determining the position of the pre-generated machine instruction sequence (i.e., the sequence corresponding to load) corresponding to the first target bytecode in the virtual machine kernel function; in step S131, the first variable address 001 in the first target bytecode is used to determine the row number 001 of its corresponding local variable b in the local variable table; in step S133, one or more machine instructions in the pre-generated machine instruction sequence corresponding to the first target bytecode are executed to copy the operand 2.5 of the local variable b from the local variable table to the top of the operand stack, thereby completing the corresponding loading operation on the local variable b.

[0125] For example, further, such as Figure 3 As shown, when the pre-generated machine instruction corresponding to the first target bytecode finishes execution, in step S151, the second jump instruction jump code[pc++] is executed, so that the position of the second target bytecode in the target bytecode array can be determined through the address 2 of the second bytecode, and the jump can be made to the second target bytecode.

[0126] For example, such as Figure 3 As shown, for the second target bytecode, in step S121, the first instruction address 10 in the second target bytecode directly corresponds to the second instruction address 10 in the machine instruction sequence, thereby determining the pre-generated machine instruction sequence corresponding to the second target bytecode (i.e., Figure 3 The position of the sequence corresponding to add in the virtual machine kernel function; in step S134, the operands 2.5 and 1.0 of local variables b and a are sequentially retrieved from the top of the operand stack; in step S135, the pre-generated machine instruction sequence corresponding to the second target bytecode is executed, and the operands 1.0 and 2.5 of local variables a and b are used to perform an addition operation to obtain the first operation result 3.5; in step S136, the first operation result 3.5 is stored at the top of the operand stack.

[0127] For example, further, such as Figure 3 As shown, when the pre-generated machine instruction corresponding to the second target bytecode finishes execution, in step S151, the second jump instruction jump code[pc++] is executed, so that the position of the third target bytecode in the target bytecode array can be determined through the address 3 of the second bytecode, and the jump can be made to the third target bytecode.

[0128] For example, such as Figure 3 As shown, for the third target bytecode, in step S121, the first instruction address 20 in the third target bytecode directly corresponds to the second instruction address 20 in the machine instruction sequence, thereby determining the position of the pre-generated machine instruction sequence (i.e., the sequence corresponding to store) in the virtual machine kernel function corresponding to the third target bytecode; in step S131, the first variable address 010 in the third target bytecode is used to determine the row number 003 of its corresponding local variable c in the local variable table; in step S137, the first operation result 3.5 is copied from the top of the operand stack to the position of the operand of the third local variable c in the local variable table.

[0129] For example, further, such as Figure 3As shown, when the pre-generated machine instructions corresponding to the third target bytecode finish execution, the jump instruction `jump code[pc++]` is executed, jumping to subsequent instructions. Figure 3 Bytecode not shown (e.g., bytecode corresponding to the termination program) is used for subsequent operations.

[0130] For example, by operating on the 0th, 1st, 2nd, and 3rd target bytecodes as described above, the func(a, b) operation in the source code can be implemented to obtain the corresponding calculation result.

[0131] It should be noted that, Figure 3 The bytecode, pre-generated instruction sequence, local variable table, operand stack, etc. shown are all simple examples. Other implementation methods can also be selected according to actual needs. The embodiments disclosed herein do not limit this.

[0132] Figure 4 This is a schematic diagram of another example of the instruction processing method provided in at least one embodiment of this disclosure. For example, Figure 4 It can be Figure 1 Another specific example of the instruction processing method shown.

[0133] For example, such as Figure 4 As shown, when the program starts executing, the target bytecode array compiled from the target kernel function corresponding to the source code in step S110 is loaded into the shared memory space of the programmable processor; a local variable table and operand stack are created in the shared memory space, and then the kernel function parameters and operands of the target kernel function are loaded into the local variable table; the bytecode array pointer is set to point to the starting bytecode in the target bytecode array; if the current bytecode is determined to be a valid bytecode, the current bytecode is interpreted and executed, otherwise the processor program is terminated.

[0134] For example, such as Figure 4 As shown, further, the jump table is queried using the current bytecode, and in step S1211, the first instruction address of the pre-generated machine instruction sequence corresponding to the current bytecode is used to determine the second instruction address of the pre-generated machine instruction sequence in the virtual machine kernel function; in step S1212, the jump is made to the position of the pre-generated machine instruction sequence corresponding to the current target bytecode in the virtual machine kernel function based on the second instruction address, so that the pre-generated machine instruction sequence is executed in step S130.

[0135] For example, such as Figure 4 As shown, further, when the pre-generated machine instruction corresponding to the current bytecode finishes execution, it is determined whether the next machine instruction is an exit instruction; if it is not an exit instruction, the bytecode array pointer is moved to point to the next bytecode to be executed, and the above operation is repeated.

[0136] It should be noted that, Figure 4 The operation flow shown is only an example. The instruction processing method provided in at least one embodiment of this disclosure can also be implemented in other ways according to actual needs. The embodiments of this disclosure do not limit this.

[0137] The instruction processing method provided in at least one embodiment of this disclosure compiles the source code into hardware platform-independent general bytecode, and then translates the bytecode into a sequence of machine instructions for the corresponding platform based on the virtual machine kernel function running on the hardware platform. This enables one-time compilation of source code into bytecode and multi-platform interpretation and execution, thereby achieving efficient cross-platform operation of the source code. In addition, after the source code is modified, it does not need to be recompiled and linked for specific hardware. The results can be immediately executed based on the virtual machine kernel function to view the results, shortening the development feedback cycle, lowering the development threshold, accelerating prototype verification, and significantly improving the flexibility and efficiency of processor program deployment.

[0138] For example, in some examples, the instruction processing method provided in at least one embodiment of this disclosure may further include the following steps S101 to S103.

[0139] Step S101: Compile the source code into an intermediate form;

[0140] Step S102: In response to the intermediate form expression including hotspot kernel functions, the hotspot kernel functions are compiled in just-in-time into a sequence of native machine instructions suitable for the programmable processor;

[0141] Step S103: Execute the native machine instruction sequence.

[0142] For example, the intermediate form expression compiled from the source code in step S101 may include one or more kernel functions, which may include hotspot kernel functions. For example, hotspot kernel functions may be frequently called kernel functions, or they may be selected as other types of kernel functions. The specific selection can be made according to actual needs, and the embodiments of this disclosure do not limit this.

[0143] For example, in step S102, if the intermediate form expression includes a hotspot kernel function, the hotspot kernel function can be compiled into a native machine instruction sequence suitable for the programmable processor by a Just-In-Time Compiler (JIT), and then run directly in step S103.

[0144] For example, Figure 1 Step S110 may also include the following step S111.

[0145] Step S111: In response to the intermediate form expression including the target kernel function, compile the target kernel function into a target bytecode array.

[0146] For example, the target kernel function can be a specific kernel function selected from among multiple kernel functions included in the intermediate form expression that requires separate accelerated interpretation processing; for example, it can be a kernel function that is called only once or a small number of times. For example, in step S111, if the intermediate form expression includes a target kernel function, the target kernel function can be compiled into a target bytecode array for use. Figure 1 The steps S120~S130 shown are for subsequent processing.

[0147] For example, because hot kernel functions are called frequently, by compiling them once and completely into a sequence of native machine instructions that the target hardware platform can directly recognize and execute, subsequent program execution does not require further translation; it can simply execute the compiled machine instruction code, thereby improving runtime efficiency and processor performance. Conversely, if the target kernel function is called only once or a few times, through... Figure 1 The steps S110~S130 shown are interpreted and executed, which can quickly obtain compilation and execution results, and does not require recompiling and linking when the source code needs to be modified, thus better adapting to the computing needs of programmable processors.

[0148] For example, in other examples, the instruction processing method provided in at least one embodiment of this disclosure may further include the following steps S101, S104 to S105.

[0149] Step S101: Compile the source code into an intermediate form;

[0150] Step S104: Determine the intermediate form as the target kernel function;

[0151] Step S105: While compiling the target kernel function corresponding to the source code into an array of target bytecode, start just-in-time compilation of the intermediate form expression to compile the intermediate form expression into a sequence of native machine instructions suitable for the programmable processor in the background of the programmable processor.

[0152] For example, the intermediate form expression compiled from the source code in step S101 may include one or more kernel functions, and these one or more kernel functions can be identified as the target kernel function in step S104; in step S105, during execution... Figure 1 Simultaneously with step S110, just-in-time compilation is initiated on the intermediate form expression in the background of the programmable processor to obtain a sequence of native machine instructions suitable for the programmable processor.

[0153] For example, through steps S104~S105 above, on the one hand, it can be achieved by... Figure 1The steps S110~S130 shown demonstrate that the interpretation and execution can quickly obtain the compilation and execution results. On the other hand, the native machine instruction sequence can be compiled in the background in real time. Therefore, when the source code is called a second time, the already compiled native machine instruction sequence can be directly called for execution without repeated interpretation and compilation, which effectively reduces the execution time and significantly improves the overall running performance.

[0154] Figure 5 This is a schematic diagram of another example of the instruction processing method provided in at least one embodiment of this disclosure. For example, Figure 5 It can be Figure 1 The steps S110~S130 shown are a specific example of steps S101~S103 above.

[0155] For example, such as Figure 5 As shown, when the program starts executing, in step S101, the source code is compiled into an intermediate form expression; further, it is determined whether the kernel function to be compiled in the intermediate form expression is a hot kernel function.

[0156] For example, if the kernel function to be compiled in the intermediate form is a hot kernel function, the hot kernel function is optimized, and then in step S102, the hot kernel function is compiled in real time into a sequence of native machine instructions suitable for the programmable processor. For example, further, the kernel function parameters of the hot kernel function are prepared, and by determining that it does not need to use bytecode, the sequence of native machine instructions can be directly started. Then, in step S103, the sequence of native machine instructions is executed to obtain the corresponding execution result.

[0157] For example, if the kernel function to be compiled in the intermediate form is not a hotspot kernel function, then the kernel function to be compiled is determined as the target kernel function, and in step S110, the target kernel function is compiled into a target bytecode array. For example, further, the kernel function parameters of the hotspot kernel function are prepared; by determining that it needs to use bytecode, the virtual machine kernel function can be started. In steps S120~S130, the bytecode in the target bytecode array is interpreted and its corresponding pre-generated machine instruction sequence is executed to obtain the corresponding execution result.

[0158] It should be noted that, Figure 5 The operation flow shown is only an example. The instruction processing method provided in at least one embodiment of this disclosure can also be implemented in other ways according to actual needs. The embodiments of this disclosure do not limit this.

[0159] Figure 6 A schematic block diagram of a programmable processor provided for at least one embodiment of the present disclosure.

[0160] For example, such as Figure 6As shown, the programmable processor 200 includes a compilation module 210, a determination module 220, and an execution module 230.

[0161] For example, compiler module 210 is configured to compile the target kernel functions corresponding to the source code into an array of target bytecode. For example, the target bytecode array includes N target bytecodes, where N is a positive integer. That is, compiler module 210 can be configured to execute, for example... Figure 2 The step S110 is shown.

[0162] For example, the determination module 220 is configured to use the k-th target bytecode from N target bytecodes to determine the pre-generated machine instruction sequence corresponding to the k-th target bytecode from the virtual machine kernel function, where k = 0, 1, ..., N-1. That is, the determination module 220 can be configured to execute, for example... Figure 2 The step S120 shown.

[0163] For example, execution module 230 is configured to execute the pre-generated machine instruction sequence corresponding to the k-th target bytecode. That is, execution module 230 can be configured to execute, for example... Figure 2 The step S130 shown.

[0164] For example, in some examples, the k-th target bytecode contains the first instruction address of the pre-generated machine instruction sequence corresponding to the k-th target bytecode. For example, the determining module 220 is also configured to use the first instruction address to determine the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function.

[0165] For example, the virtual machine kernel function maintains a jump table, which includes a mapping relationship between the first instruction address and the second instruction address in the virtual machine kernel function corresponding to the pre-generated machine instruction sequence corresponding to the k-th target bytecode. For example, the determining module 220 is also configured to: determine the second instruction address using the first instruction address based on the jump table; and jump to the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function based on the second instruction address.

[0166] For example, in some examples, the k-th target bytecode contains the address of the first bytecode of the k-th target bytecode in the target bytecode array. For example, the virtual machine kernel function contains a first jump instruction, which is used to determine the position of the k-th target bytecode in the target bytecode array based on the first bytecode address before determining the pre-generated machine instruction sequence corresponding to the k-th target bytecode from the virtual machine kernel function.

[0167] For example, in some examples, a local variable table is created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, which includes a target local variable. The pre-generated machine instruction sequence corresponding to the k-th target bytecode corresponds to a first operation on the target local variable. For example, the k-th target bytecode contains the address of a first variable corresponding to the target local variable. For example, the execution module 230 is further configured to: determine the position of the target local variable in the local variable table using the first variable address; and perform a first operation on the target local variable.

[0168] For example, in some examples, a local variable table is created in the shared memory space of the programmable processor, and the local variable table includes at least one local variable. For example, the programmable processor 200 also includes a loading module 240 configured to load at least one kernel function parameter of the target kernel function and the operands of the kernel function parameter into the local variable table, so as to make at least one kernel function parameter a local variable in the local variable table.

[0169] For example, in some examples, a local variable table and an operand stack are created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, and the at least one local variable includes a first local variable whose operands are stored in the local variable table. For example, in response to a pre-generated machine instruction sequence corresponding to the k-th target bytecode corresponding to a load operation of the first local variable, the execution module 230 is further configured to copy the operands of the first local variable from the local variable table to the operand stack.

[0170] For example, in some examples, a local variable table and an operand stack are created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, and the at least one local variable includes at least one second local variable. The operands of the at least one second local variable are stored in the operand stack. For example, in response to a first operation corresponding to at least one second local variable in a pre-generated machine instruction sequence corresponding to the k-th target bytecode, the execution module 230 is further configured to: retrieve the operands of at least one second local variable from the operand stack; perform the first operation using the operands of at least one second local variable to obtain a first operation result; and store the first operation result in the operand stack.

[0171] For example, a local variable table and an operand stack are created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, and the at least one local variable includes a third local variable. The operand of the third local variable corresponds to the first operation result obtained by performing a first operation in the programmable processor, and the first operation result is stored in the operand stack. For example, in response to the storage operation of the third local variable corresponding to the pre-generated machine instruction sequence corresponding to the k-th target bytecode, the pre-generated machine instruction sequence corresponding to the k-th target bytecode is executed. The execution module 230 is also configured to copy the first operation result from the operand stack to the position of the operand of the third local variable in the local variable table.

[0172] For example, in some examples, in response to the fact that the pre-generated machine instruction sequence corresponding to the k-th target bytecode does not include an exit instruction and k is less than N-1, after executing the pre-generated machine instruction sequence corresponding to the k-th target bytecode, the execution module 230 is further configured to jump to the (k+1)-th target bytecode in the target bytecode array; the determination module 220 is further configured to use the (k+1)-th target bytecode to determine the pre-generated machine instruction sequence corresponding to the (k+1)-th target bytecode from the virtual machine kernel function; and the execution module 230 is further configured to execute the pre-generated machine instruction sequence corresponding to the (k+1)-th target bytecode.

[0173] For example, the (k+1)th target bytecode contains the address of the second bytecode of the (k+1)th target bytecode in the target bytecode array, and the virtual machine kernel function contains a second jump instruction corresponding to the second bytecode address. For example, after executing the pre-generated machine instruction sequence corresponding to the kth target bytecode, the execution module 230 is further configured to execute the second jump instruction to determine the position of the (k+1)th target bytecode in the target bytecode array based on the second bytecode address.

[0174] For example, in some examples, compilation module 210 may also be configured to: compile source code into an intermediate form expression; and, in response to the intermediate form expression including hotspot kernel functions, compile the hotspot kernel functions into a native machine instruction sequence suitable for the programmable processor. For example, execution module 230 may also be configured to execute a native machine instruction sequence.

[0175] For example, compiler module 210 can also be configured to: compile the target kernel function into an array of target bytecode in response to an intermediate form expression including the target kernel function.

[0176] For example, in some examples, compiler module 210 may also be configured to: compile source code into an intermediate form expression; determine the intermediate form expression as a target kernel function; and, while compiling the target kernel function corresponding to the source code into an array of target bytecode, initiate just-in-time compilation of the intermediate form expression to compile the intermediate form expression into a sequence of native machine instructions suitable for the programmable processor in the background of the programmable processor.

[0177] Due to the above description, for example Figure 2 The instruction processing method shown has already described in detail the operations of the programmable processor 200, so for the sake of brevity, it will not be repeated here. For relevant details, please refer to the above description. Figures 2-5 The description.

[0178] It should be noted that, Figure 6 The various modules described above in the programmable processor 200 shown can be configured individually as software, hardware, firmware, or any combination thereof to perform specific functions. For example, these modules may correspond to dedicated integrated circuits, pure software code, or modules combining software and hardware. As an example, see [reference needed]. Figure 6 The device described may be a PC computer, tablet device, personal digital assistant, smartphone, web application or other device capable of executing program instructions, but is not limited thereto.

[0179] Furthermore, although the programmable processor 200 has been divided into modules for executing corresponding processes in the above description, it will be clear to those skilled in the art that the processes executed by each module can also be executed without any specific module division in the device or without clear boundaries between the modules. In addition, the above references... Figure 6 The programmable processor 200 described is not limited to the modules described above, but may also include other modules (e.g., reading modules, control modules, etc.) as needed, or the above modules may be combined.

[0180] At least one embodiment of this disclosure also provides an electronic device including one or more processors and a memory; the memory includes one or more computer program modules; the one or more computer program modules are stored in the memory and configured to be executed by one or more processors, and the one or more computer program modules include computer-executable instructions for implementing the instruction processing methods provided in the embodiments of this disclosure described above. For example, the one or more processors may include the programmable processor provided in at least one embodiment of this disclosure.

[0181] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0182] For example, such as Figure 7 As shown, the electronic device 300 includes a processor 310 and a memory 320. For example, the memory 320 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 310 is used to execute the non-transitory computer-readable instructions, which, when executed by the processor 310, can perform one or more steps according to the instruction processing method described above. The memory 320 and the processor 310 can be interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0183] For example, processor 310 can be a central processing unit (CPU), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), digital signal processor (DSP), or other processing unit with memory access and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) can be an x86, RISC-V, or ARM architecture. Processor 310 can be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 300 to perform desired functions.

[0184] For example, memory 320 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable optical disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 310 may run one or more computer program modules to implement various functions of electronic device 300. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0185] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 300 can be referred to the description of the instruction processing method provided in at least one embodiment of this disclosure above, and will not be repeated here.

[0186] Figure 8 A schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0187] For example, such as Figure 8As shown, the electronic device 400 is, for example, suitable for implementing the instruction processing method provided in the embodiments of this disclosure. It should be noted that... Figure 8 The illustrated electronic device 400 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0188] For example, such as Figure 8 As shown, electronic device 400 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 41, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 42 or a program loaded from storage device 48 into random access memory (RAM) 43. RAM 43 also stores various programs and data required for the operation of electronic device 400. Processing device 41, ROM 42, and RAM 43 are interconnected via bus 44. Input / output (I / O) interface 45 is also connected to bus 44. Typically, the following devices can be connected to I / O interface 45: input devices 46 including, for example, touch screens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 47 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 48 including, for example, magnetic tapes, hard disks, etc.; and communication devices 49. Communication device 49 allows electronic device 400 to communicate wirelessly or wiredly with other electronic devices to exchange data.

[0189] Although Figure 8 An electronic device 400 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 400 may alternatively implement or have more or fewer devices.

[0190] For detailed descriptions and technical effects of the electronic device 400, please refer to the above description of the instruction processing method; it will not be repeated here.

[0191] Figure 9 This is a schematic diagram of a storage medium provided for at least one embodiment of the present disclosure.

[0192] For example, such as Figure 9 As shown, storage medium 500 stores non-transitory computer-readable instructions 510. For example, when the non-transitory computer-readable instructions 510 are executed by a computer, one or more steps in the instruction processing method described above are performed.

[0193] For example, this storage medium 500 can be applied to Figure 7 In the illustrated electronic device 300, for example, the storage medium 500 can be the memory 320 within the electronic device 300. For example, a description of the storage medium 500 can be found here. Figure 7The corresponding description of the memory 320 in the illustrated electronic device 300 will not be repeated here.

[0194] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0195] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0196] The following points need to be clarified regarding this disclosure:

[0197] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0198] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0199] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for instruction processing in a programmable processor, characterized in that, The programmable processor runs a virtual machine kernel function, which includes at least one pre-generated machine instruction sequence suitable for the programmable processor. Each of the at least one pre-generated machine instruction sequence has a corresponding bytecode array. The instruction processing method includes: The target kernel function corresponding to the source code is compiled into an array of target bytecode, wherein the array of target bytecode includes N target bytecodes, where N is a positive integer; Using the kth target bytecode among the N target bytecodes, determine the pre-generated machine instruction sequence corresponding to the kth target bytecode from the virtual machine kernel function, where k = 0, 1, ..., N-1; Execute the pre-generated machine instruction sequence corresponding to the k-th target bytecode.

2. The instruction processing method according to claim 1, characterized in that, The k-th target bytecode contains the first instruction address of the pre-generated machine instruction sequence corresponding to the k-th target bytecode. Using the kth target bytecode among the N target bytecodes, determine the pre-generated machine instruction sequence corresponding to the kth target bytecode from the virtual machine kernel function, including: The first instruction address is used to determine the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function.

3. The instruction processing method according to claim 2, characterized in that, The virtual machine kernel function maintains a jump table, which includes a mapping relationship between the first instruction address and the second instruction address of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function. Determining the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function using the first instruction address includes: Based on the jump table, the second instruction address is determined using the first instruction address; Based on the second instruction address, jump to the position of the pre-generated machine instruction sequence corresponding to the k-th target bytecode in the virtual machine kernel function.

4. The instruction processing method according to claim 1, characterized in that, The k-th target bytecode contains the address of the first bytecode of the k-th target bytecode in the target bytecode array. The virtual machine kernel function contains a first jump instruction, which is used to determine the position of the kth target bytecode in the target bytecode array based on the first bytecode address before determining the pre-generated machine instruction sequence corresponding to the kth target bytecode from the virtual machine kernel function.

5. The instruction processing method according to claim 1, characterized in that, A local variable table is created in the shared memory space of the programmable processor. The local variable table includes at least one local variable, which includes a target local variable. The pre-generated machine instruction sequence corresponding to the k-th target bytecode corresponds to the first operation of the target local variable. The k-th target bytecode contains the address of the first variable corresponding to the target local variable. Execute the pre-generated machine instruction sequence corresponding to the k-th target bytecode, including: The location of the target local variable in the local variable table is determined using the address of the first variable. Perform the first operation on the target local variable.

6. The instruction processing method according to claim 1, characterized in that, A local variable table is created in the shared memory space of the programmable processor, and the local variable table includes at least one local variable. The instruction processing method further includes: At least one kernel function parameter of the target kernel function and the operands of the kernel function parameter are loaded into the local variable table, so that the at least one kernel function parameter is used as a local variable in the local variable table.

7. The instruction processing method according to claim 1, characterized in that, The programmable processor has a local variable table and an operand stack created in its shared memory space. The local variable table includes at least one local variable, and the at least one local variable includes a first local variable whose operands are stored in the local variable table. In response to the loading operation of the first local variable corresponding to the pre-generated machine instruction sequence corresponding to the k-th target bytecode, the pre-generated machine instruction sequence corresponding to the k-th target bytecode is executed, including: The operands of the first local variable are copied from the local variable table to the operand stack.

8. The instruction processing method according to claim 1, characterized in that, The programmable processor has a local variable table and an operand stack created in its shared memory space. The local variable table includes at least one local variable, and the at least one local variable includes at least one second local variable. The operands of the at least one second local variable are stored in the operand stack. In response to a first operation of the pre-generated machine instruction sequence corresponding to the at least one second local variable corresponding to the k-th target bytecode, the pre-generated machine instruction sequence corresponding to the k-th target bytecode is executed, including: Remove the operand of the at least one second local variable from the operand stack; The first operation is performed using the operands of the at least one second local variable to obtain the first operation result; The result of the first operation is stored in the operand stack.

9. The instruction processing method according to claim 8, characterized in that, The programmable processor has a local variable table and an operand stack created in its shared memory space. The local variable table includes at least one local variable, and the at least one local variable includes a third local variable. The operands of the third local variable correspond to the first operation result obtained by performing a first operation in the programmable processor. The first operation result is stored in the operand stack. In response to the storage operation of the third local variable corresponding to the pre-generated machine instruction sequence corresponding to the k-th target bytecode, the pre-generated machine instruction sequence corresponding to the k-th target bytecode is executed, including: The result of the first operation is copied from the operand stack to the operand position of the third local variable in the local variable table.

10. The instruction processing method according to claim 1, characterized in that, In response to the fact that the pre-generated machine instruction sequence corresponding to the k-th target bytecode does not include an exit instruction and k is less than N-1, after executing the pre-generated machine instruction sequence corresponding to the k-th target bytecode, the instruction processing method further includes: Jump to the (k+1)th target bytecode in the target bytecode array; Using the (k+1)th target bytecode, determine the pre-generated machine instruction sequence corresponding to the (k+1)th target bytecode from the virtual machine kernel function; Execute the pre-generated machine instruction sequence corresponding to the (k+1)th target bytecode.

11. The instruction processing method according to claim 10, characterized in that, The (k+1)th target bytecode contains the address of the second bytecode of the (k+1)th target bytecode in the target bytecode array, and the virtual machine kernel function contains a second jump instruction corresponding to the address of the second bytecode. After executing the pre-generated machine instruction sequence corresponding to the k-th target bytecode, jump to the (k+1)-th target bytecode in the target bytecode array, including: Execute the second jump instruction to determine the position of the (k+1)th target bytecode in the target bytecode array based on the second bytecode address.

12. The instruction processing method according to claim 1, characterized in that, The instruction processing method further includes: The source code is compiled into an intermediate form. In response to the intermediate form expression including hotspot kernel functions, the hotspot kernel functions are compiled in real time into a sequence of native machine instructions suitable for the programmable processor; Execute the native machine instruction sequence.

13. The instruction processing method according to claim 12, characterized in that, Compiling the target kernel function corresponding to the source code into the target bytecode array includes: In response to the intermediate form expression including the target kernel function, the target kernel function is compiled into the target bytecode array.

14. The instruction processing method according to claim 1, characterized in that, The instruction processing method further includes: The source code is compiled into an intermediate form. The intermediate form is defined as the target kernel function; While compiling the target kernel function corresponding to the source code into the target bytecode array, just-in-time compilation is initiated on the intermediate form expression to compile the intermediate form expression into a sequence of native machine instructions suitable for the programmable processor in the background of the programmable processor.

15. A programmable processor, characterized in that, The programmable processor runs a virtual machine kernel function, which includes at least one pre-generated machine instruction sequence suitable for the programmable processor. Each of the at least one pre-generated machine instruction sequence has a corresponding bytecode array. The programmable processor includes: The compilation module is configured to compile the target kernel function corresponding to the source code into an array of target bytecode, wherein the array of target bytecode includes N target bytecodes, where N is a positive integer; The determination module is configured to use the kth target bytecode among the N target bytecodes to determine the pre-generated machine instruction sequence corresponding to the kth target bytecode from the virtual machine kernel function, where k = 0, 1, ..., N-1; The execution module is configured to execute the pre-generated machine instruction sequence corresponding to the k-th target bytecode.

16. An electronic device, characterized in that, The electronic device includes: One or more processors; Memory, including one or more computer program modules; The one or more computer program modules are stored in the memory and configured to be executed by the one or more processors, and the one or more computer program modules are used to implement the instruction processing method according to any one of claims 1-14.

17. A storage medium, characterized in that, The storage medium stores non-transitory computer-readable instructions, which, when executed by a computer, implement the instruction processing method according to any one of claims 1-14.

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