Cache block zero clearing method, processor and chip

Abstract

The embodiment of the invention relates to a cache block zero clearing method, a processor and a chip, and relates to the technical field of computers, and the cache block zero clearing method comprises the steps that a cache block zero clearing micro instruction carrying parameters is acquired, and the parameters comprise physical addresses and do not comprise data; writing the physical address into a storage address buffer; matching a corresponding cache block in a cache according to the physical address in the storage address buffer; and writing the data 0 into the cache block. A cache block zero clearing operation is abstracted into a special microinstruction which only carries a physical address and does not contain a data load, so that a series of operation links of obtaining zero value data from a register file or a data bus, writing a zero value into a storage data buffer, reading the data from the data buffer, transmitting the data to a cache and the like are eliminated. The simplified execution path directly shortens the processing period of the instruction in the assembly line and reduces the operation delay, so that the instruction throughput rate and the overall execution efficiency of the processor are improved.

Description

Technical Field

[0001] The embodiments in this specification relate to the field of computer technology, specifically to a method for clearing cache blocks, a processor, and a chip. Background Technology

[0002] In current CPU designs, due to the significant latency of direct memory access, caches are used to cache data, accelerating data retrieval and improving CPU performance. However, caching also introduces several issues. For applications handling highly sensitive information, such as encryption keys, the operating system needs to use instructions to write cache blocks to zero to ensure this data is completely removed from the cache and enhance security. Additionally, in hardware fault detection and recovery, upon detecting a hardware failure, the operating system may need to perform a series of maintenance operations, including writing cache blocks to zero to restore normal operation. Furthermore, optimizing memory initialization operations, especially in scenarios requiring frequent memory allocation, necessitates frequently writing cache blocks to zero.

[0003] In mainstream CPU architectures such as RSIC-V (RV), the CBO.ZERO instruction is used to clear cache blocks to zero. The CBO.ZERO instruction in RV carries a virtual address (VA), which needs to be converted to a physical address (PA) in the load store unit (LSU). The PA is then compared with the PA of the cache block in the LSU. If they match, 0 needs to be written to that cache block.

[0004] like Figure 1As shown, in existing technical solutions, the CBO.ZERO instruction reuses the microarchitecture of the ordinary STORE instruction. It stores the address-related information of the CBO.ZERO instruction in the address buffer of the STORE Buffer (SB), and stores the data 0 in the data buffer of the SB. The address entries and data entries in the SB are not one-to-one, but linked together. Since some STORE-type instructions do not carry data, and the data volume of STORE instructions is relatively small, the number of data entries in the SB is generally less than the number of address entries. Because CBO.ZERO needs to write data 0 the size of a cache block (currently 64B), while the existing SB data buffer width is 16B, a single CBO.ZERO instruction needs to be sent to the LSU in four separate transactions. In the SB, the CBO.ZERO instruction checks the TAG. If the corresponding PA address hits the cache block and has write permission, it writes 0 to the corresponding cache block. If it misses, it needs to get write permission from the L2 Cache and then write 0 to the cache block.

[0005] The existing CBO.ZERO technology reuses the LSU microarchitecture processing flow of ordinary STORE instructions, resulting in low performance and high power consumption. Summary of the Invention

[0006] The purpose of the embodiments in this specification is to provide a cache block clearing method, processor, and chip to overcome the problems of existing methods, such as reliance on human experience, large overlap of classification results, and low feasibility.

[0007] To solve the above-mentioned technical problems, the specific technical solutions of the embodiments in this specification are as follows:

[0008] On the one hand, the embodiments of this specification provide a method for clearing cache blocks, including:

[0009] Obtain a cache block clearing microinstruction carrying parameters, wherein the parameters include the physical address but do not include the data;

[0010] Write the physical address into the storage address buffer;

[0011] Match the corresponding cache block in the cache based on the physical address in the storage address buffer;

[0012] Write the data 0 into the cache block.

[0013] Furthermore, the parameters also include the instruction type;

[0014] The method further includes:

[0015] Write the instruction type into the storage address buffer.

[0016] Furthermore, the cache includes at least a level 1 cache, a level 2 cache, and a level 3 cache;

[0017] The step of matching the corresponding cache block in the cache according to the physical address in the storage address buffer includes:

[0018] The cache block in the first-level cache that matches the physical address in the storage address buffer and is in a writable state is searched.

[0019] Furthermore, the method also includes:

[0020] If there is no cache block in the L1 cache that matches the physical address in the storage address buffer and is in a writable state, obtain the first count value of the first counter, which is used to count the executed clear instructions;

[0021] Determine whether the first count value is less than the first write threshold, the first write threshold being used to control the maximum number of consecutive zero-clear instructions written to the L1 cache;

[0022] If so, write data 0 to the first-level cache;

[0023] If not, write the data 0 to the second-level cache or the third-level cache.

[0024] Further, writing data 0 into the first-level cache includes:

[0025] Read the instruction type from the memory address buffer;

[0026] According to the instruction type, write data 0 into the first-level cache.

[0027] Furthermore, writing data 0 to the second-level cache or the third-level cache includes:

[0028] Determine whether the first count value is less than the second write threshold; the second write threshold is used to control the maximum number of consecutive zero-clear instructions written to the L1 cache and L2 cache;

[0029] If so, write the data 0 to the second-level cache;

[0030] If not, write the data 0 to the level 3 cache.

[0031] Furthermore, writing data 0 to the three-level cache includes:

[0032] If there is no cache block in the L2 cache that matches the physical address in the storage address buffer, then the instruction type is read from the storage address buffer;

[0033] According to the instruction type, data 0 is written to the corresponding cache block in the level 3 cache.

[0034] Furthermore, writing data 0 to the three-level cache further includes:

[0035] If a cache block exists in the L2 cache that matches the physical address in the storage address buffer, and the cache block is writable, then the instruction type is read from the storage address buffer.

[0036] According to the instruction type, write data 0 into the cache block in the second-level cache.

[0037] Furthermore, the first write threshold is the associativity of the L1 cache;

[0038] The second write threshold is determined by the following formula:

[0039] alloc_l2_threshold=(L2_C / L1_C)*alloc_l1_threshold;

[0040] In the formula, alloc_l2_threshold represents the write threshold of the L2 cache, L2_C represents the cache capacity of the L2 cache, L1_C represents the cache capacity of the L1 cache, and alloc_l1_threshold represents the write threshold of the L1 cache.

[0041] Furthermore, the method also includes:

[0042] Obtain the second count value of the second counter, which is used to count instructions that are neither clear instructions nor write instructions;

[0043] If the first count value is greater than or equal to the first count threshold, the second counter is reset;

[0044] If the second count value is equal to the second count threshold, the first counter is reset.

[0045] Furthermore, the method also includes:

[0046] After writing the data 0 to the first-level cache, second-level cache, or third-level cache, increment the first count value of the first counter by 1.

[0047] Furthermore, the method also includes:

[0048] If a cache block exists in the first-level cache that matches the physical address in the storage address buffer, and the cache block is in a non-writable state, a cache miss instruction is sent to the second-level cache.

[0049] Based on the writable instruction returned by the second-level cache, the data 0 is written to the cache block in the first-level cache.

[0050] Further, writing data 0 into the cache block includes:

[0051] Based on the physical address in the storage address buffer, determine multiple instructions to be executed to access the cache block;

[0052] Arbitrate the instruction that writes data 0 with the plurality of instructions to be executed;

[0053] Once the instruction to write data 0 wins the arbitration, data 0 will be written to the cache block.

[0054] On the other hand, embodiments of this specification provide a cache block clearing device, including:

[0055] The acquisition module is used to acquire a cache block clearing micro-instruction carrying parameters, wherein the parameters include the physical address but do not include data;

[0056] The first write module is used to write the physical address into the storage address buffer;

[0057] The matching module is used to match the corresponding cache block in the cache based on the physical address in the storage address buffer;

[0058] The second write module is used to write data 0 into the cache block.

[0059] Furthermore, the embodiments of this specification provide a method for implementing a read instruction, including:

[0060] The target physical address of the read instruction is matched and checked against the physical address of the zeroing instruction recorded in the memory address buffer that precedes the read instruction.

[0061] If a zeroing instruction with a matching physical address exists, the data 0 is returned to the read instruction according to the instruction type of the zeroing instruction.

[0062] Furthermore, embodiments of this specification provide an apparatus for implementing read instructions, comprising:

[0063] The matching module is used to match and check the target physical address of the read instruction with the physical address of the clear instruction recorded in the memory address buffer that precedes the read instruction.

[0064] The return module is used to return data 0 to the read instruction if a zeroing instruction with a matching physical address exists, based on the instruction type of the zeroing instruction.

[0065] Furthermore, embodiments of this specification provide a processor for performing any of the methods described above.

[0066] In another aspect, embodiments of this specification provide a chip including a processor for performing the methods described in any of the foregoing descriptions.

[0067] As can be seen from the technical solutions provided in the embodiments of this specification above, the embodiments of this specification can obtain a cache block clearing microinstruction carrying parameters, the parameters including a physical address but excluding data; write the physical address into a storage address buffer; match the corresponding cache block in the cache according to the physical address in the storage address buffer; and write the data 0 into the cache block. Regarding power consumption optimization, since the microinstruction itself does not carry data and completely bypasses access to the storage data buffer during execution, it completely eliminates the large-scale circuit switching power consumption associated with all-zero data read / write operations. Simultaneously, this mechanism ensures that the clearing operation does not require driving and transmitting a large number of all-zero bits on the processor's internal bus. This not only significantly reduces the dynamic power consumption of the bus interface but also effectively alleviates bus congestion, freeing up valuable bandwidth for other critical data accesses. Regarding hardware resource utilization, for the valuable and limited resource of the storage data buffer, by making the clearing instruction run completely independently of this resource, the limited buffer entries are reserved for ordinary storage instructions that truly need to temporarily store data. This design directly reduces the risk of pipeline blockage caused by a full data buffer, comprehensively improves resource utilization efficiency, and significantly enhances the overall performance of the CPU when handling mixed workloads.

[0068] As can be seen from the technical solutions provided in the embodiments of this specification above, the embodiments of this specification can also perform a matching check between the target physical address of the read instruction and the physical address of the clear instruction recorded in the memory address buffer that precedes the read instruction; if a clear instruction with a matching physical address exists, data 0 is returned to the read instruction according to the instruction type of the clear instruction. Zero-latency data forwarding is achieved through address matching checks. When the physical address of the read instruction matches the address of an earlier, incomplete clear instruction, the read instruction does not need to wait for the clear instruction to be actually executed and written to the cache, and can immediately obtain data from the memory address buffer. This completely eliminates the inherent latency caused by accessing the cache array and even the lower-level memory, transforming a complete memory read operation into a direct register read, improving instruction throughput and program execution speed. By avoiding such unnecessary cache access, significant dynamic power saving is achieved. Traditional read instruction execution requires activating large-scale circuits such as the word lines and bit lines of the cache, resulting in huge power consumption. After a successful address match, subsequent access to the cache data array is directly blocked, eliminating the need for these high-power units to operate. At the same time, since there is no need to read data from the cache, signal switching activity on the internal data bus is reduced, thus reducing power consumption at the system level. Attached Figure Description

[0069] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the accompanying drawings used in the description of the embodiments or prior art will be briefly introduced below.

[0070] Figure 1 This is a flowchart illustrating the existing cache block clearing method provided in the embodiments of this specification;

[0071] Figure 2 This is a flowchart of a cache block clearing method provided in the embodiments of this specification;

[0072] Figure 3 This is a schematic diagram of the overall process of a cache block clearing method provided in the embodiments of this specification;

[0073] Figure 4 This is a flowchart of a cache block clearing method provided in the embodiments of this specification;

[0074] Figure 5 This is a schematic diagram illustrating the structural composition of a cache block clearing device provided in the embodiments of this specification;

[0075] Figure 6 This is a flowchart illustrating a method for implementing a read instruction as provided in an embodiment of this specification;

[0076] Figure 7 This is a schematic diagram of the structural composition of a read instruction implementation device provided in the embodiments of this specification. Detailed Implementation

[0077] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this specification.

[0078] It should be noted that the terms "first," "second," etc., used in this specification, claims, and the foregoing drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0079] Reference Figure 1 As shown, in existing CBO.ZERO implementations, several performance and energy efficiency bottlenecks exist because instructions need to write data 0 to the storage buffer of the memory buffer. First, a single CBO.ZERO instruction, because it operates on an entire cache block, often needs to be broken down into multiple micro-operations and sent to the read / write unit. This process introduces additional instruction decomposition and reassembly overhead, leading to reduced execution efficiency. Second, writing all-zero data to the storage buffer generates significant dynamic power consumption and occupies valuable buffer entries, reducing the effective utilization of the memory buffer and thus affecting the overall CPU performance.

[0080] Furthermore, when the software performs zeroing operations on a large number of cache blocks, it typically requires multiple consecutive calls to the CBO.ZERO instruction. If the target address is not found in the L1 cache, traditional architectures need to initiate cache miss requests at each level, and only execute the zeroing write after the data block is loaded into the L1 cache. This mechanism has two major problems: First, continuous zeroing operations on large amounts of data will frequently trigger the replacement and eviction of existing data in the L1 cache, leading to cache thrashing and severely impacting access performance; second, typical application scenarios of the CBO.ZERO instruction (such as memory initialization and safe erase) usually do not have strong temporal locality characteristics. Directly using the architecture of ordinary storage instructions to handle such operations not only fails to fully utilize the advantages of the cache hierarchy, but also negatively impacts the overall efficiency of the cache system due to unnecessary cache allocation and replacement operations.

[0081] The read / write unit (LSU) is a functional unit within the CPU specifically responsible for managing and executing all instructions related to memory access. The LSU's tasks can include the following three aspects:

[0082] Executing memory access instructions: When the CPU executes an instruction to read data from memory, the LSU is responsible for calculating the effective address, accessing the cache or main memory, and finally retrieving the target data and writing it to the specified register R1. When the CPU executes an instruction to write data to memory, the LSU is responsible for calculating the effective address and finally writing the data in register R2 to the corresponding address in the cache or main memory.

[0083] Managing the storage buffer: The LSU can contain a storage buffer. The address and data of the STORE instruction are first quickly stored here, and then asynchronously written to the cache in the background.

[0084] Address translation and permission checks: Before accessing memory, the LSU needs to work with the MMU to translate the virtual address in the instruction into a physical address. Simultaneously, it checks whether the current instruction has permission to access that memory address; if a rule is violated, an exception is triggered.

[0085] The memory address buffer is a component of the memory buffer. The memory buffer is a key structure within the LSU, used to decouple the execution phase of the pipeline from the slower cache / memory access phase. It typically consists of two parts: a memory address buffer, used to cache the physical address and related control information of STORE-type instructions (including CBO.ZERO); and a memory data buffer, used to cache the actual data to be written by STORE-type instructions. When a STORE instruction is executed, its address is placed in the memory address buffer, and the data is placed in the memory data buffer. This allows instructions to quickly retire from the execution unit without waiting for data to be actually written to the cache, thus improving performance. Simultaneously, it helps maintain the order of memory operations within the memory model. When a subsequent LOAD instruction needs to read data, the LSU first checks the memory address buffer for a matching, earlier STORE instruction. If found, it can directly retrieve the latest data from the memory data buffer—a STORE-TO-LOAD Forwarding (STLF) process—without accessing the cache.

[0086] A cache block is the smallest unit for data reading, writing, and management in the CPU cache. The size of each cache block is fixed during CPU design, with a common size of 64 bytes. All cache operations, whether reading, writing, or zeroing (CBO.ZERO), are performed on the entire cache block. When the CPU needs to access a single byte, it must load the entire cache block containing that byte from memory into the cache. In addition to storing data, each cache block is also labeled and has status bits. The label identifies the memory address from which the data block originated; the status bits maintain consistency in a multi-core environment.

[0087] Figure 2 This is a flowchart of a cache block zeroing method provided in the embodiments of this specification. Figure 3 This is a schematic diagram of the overall logic flow of a cache block zeroing method provided in the embodiments of this specification. In specific implementation, it includes the following steps:

[0088] S201: Obtain a cache block clearing microinstruction carrying parameters, the parameters including physical address but excluding data.

[0089] S202: Write the physical address into the storage address buffer.

[0090] S203: Match the corresponding cache block in the cache according to the physical address in the storage address buffer.

[0091] S204: Write data 0 to the cache block.

[0092] The zeroing instruction, CBO.ZERO, carries data that is fixed at 0. In existing technologies, executing this instruction requires storing all zero data into the data buffer of the memory buffer, leading to two significant drawbacks: First, a CBO.ZERO instruction needs to be split into multiple micro-operations (e.g., 4 parts) and sent to the read-write unit (LSU), causing instruction decomposition and reassembly overhead and reducing execution performance; second, writing all zero data to the data buffer generates considerable dynamic power consumption and occupies limited data buffer entries, reducing its effective utilization and thus affecting the overall CPU performance.

[0093] In some embodiments, step S201 may specifically include: decoding the CBO.ZERO instruction into a single zeroing microinstruction that does not contain a data payload. This microinstruction only carries the target physical address, thereby avoiding the splitting of the instruction into multiple microinstructions due to the transmission of all-zero data at the architectural level, eliminating the scheduling overhead introduced by splitting and reassembling, and significantly improving instruction throughput. In addition, the significant reduction in the number of microinstructions reduces the occupation of backend execution ports and out-of-order schedulers, allowing computing resources to be more concentrated on effective operations and improving the overall efficiency of the pipeline.

[0094] In some embodiments, step S202 may specifically include sending the zeroing microinstruction to the LSU. Upon receiving it, the LSU only writes the address information to the storage address buffer without performing any write operation on the storage data buffer. This method effectively avoids the circuit switching power consumption caused by moving all-zero data, significantly reducing the dynamic power consumption of this stage. Simultaneously, since it does not occupy data buffer entries, more buffer resources can be freed up for storage instructions that actually contain data, reducing the risk of pipeline blockage caused by a full data buffer, thereby improving the system performance and resource utilization of the CPU when handling mixed loads.

[0095] A data buffer entry is the smallest unit of storage in the processor's storage data buffer. The entire storage data buffer may contain only a few dozen such entries. Once all entries are full, subsequent store-type instructions cannot be dispatched and executed, causing the pipeline to stall until an entry is freed.

[0096] In some embodiments, step S203 may specifically include: the LSU queries the cache to see if a matching cache block exists based on the physical address in the storage address buffer. If a corresponding cache block exists, the LSU obtains its location and status information to prepare for subsequent zero-value writing.

[0097] In some embodiments, step S204 may specifically include: after successfully locating the target cache block, the LSU controls the cache data array to directly clear the corresponding cache block to zero. During this process, the data bus does not need to transmit all-zero data, and all clearing operations are completed locally inside the cache controller. This not only avoids unnecessary signal toggling on the data bus and reduces system-level power consumption, but also further shortens the operation latency and improves execution efficiency.

[0098] The cache controller is a hardware unit within the CPU that manages the cache memory. Its responsibilities include receiving access requests, addressing data, performing read and write operations, and maintaining data consistency in a multi-core environment. It does not directly store data but acts as the central control unit for the cache array, managing the entire process of data location, reading, updating, and replacement.

[0099] As the instruction dispatch and scheduling center, the LSU is responsible for receiving, sorting, and dispatching all LOAD and STORE instructions. It handles virtual-to-physical address translation, permission verification, and manages storage buffers to achieve efficient pipeline operation. The cache controller, as the resource execution unit, allows the LSU to perform specific cache line addressing, tag matching, data read / write, and consistency state maintenance based on the physical addresses in the storage buffers.

[0100] In some embodiments, the parameters in step S201 may also include the instruction type of the CBO.ZERO instruction. This type identifier can be used to explicitly distinguish at the microarchitectural level whether the operation is a special instruction for clearing cache blocks.

[0101] Based on this, in step S202, after the LSU receives the microinstruction, in addition to writing the target physical address into the memory address buffer, it can also simultaneously record the type identifier of the CBO.ZERO instruction in the corresponding entry of the address buffer. This design allows the memory address buffer to not only maintain address information but also serve as a control signaling carrier for identifying and scheduling special memory operations.

[0102] Furthermore, in step S204, the LSU can identify the current operation as CBO.ZERO based on the instruction type identifier recorded in the memory address buffer, and then directly initialize the corresponding cache block to zero in the cache data array, without having to read and transfer all-zero data from the data buffer via the data bus as in traditional memory instructions. This mechanism achieves functional equivalence while effectively avoiding redundant driving and transmission of all-zero data, reducing dynamic power consumption and alleviating bus bandwidth pressure, thus providing synergistic benefits for CPU performance improvement and energy efficiency optimization.

[0103] In some embodiments, in step S203, the cache includes at least a Level 1 cache, a Level 2 cache, and a Level 3 cache. Based on this, in step 203, matching the corresponding cache block in the cache according to the physical address in the storage address buffer can specifically include: searching in the Level 1 cache for a cache block that matches the physical address in the storage address buffer and is in a writable state.

[0104] The Level 1 cache is the closest and fastest cache to the computing unit (such as the ALU), integrated within each CPU core. Level 1 cache is extremely fast but has a small capacity. The Level 2 cache is larger and slightly slower than Level 1 cache. Level 2 cache has a larger capacity and is slower than Level 1 cache, but still much faster than main memory. The Level 3 cache has the largest capacity but is the slowest. It coordinates data exchange between different cores and acts as the last buffer before accessing main memory.

[0105] Specifically, the LSU can first access and decode the tag array of the L1 cache based on the target physical address obtained from the storage address buffer, and then search for a cache block that matches the physical address. While performing the address matching check, the LSU can also check the consistency status of the cache block in parallel to confirm that it is in a writable state.

[0106] This design, which prioritizes L1 access, fully adheres to the processor's principle of memory locality and speed optimization: if the required cache block already exists in L1 and has write permission, access latency can be minimized, unnecessary lower-level cache lookups can be avoided, thereby significantly improving the execution efficiency of the CBO.ZERO instruction and effectively reducing the overall power consumption of the system.

[0107] The principle of locality of memory access includes two aspects: Temporal locality: If a memory location is accessed, it is likely to be accessed again in the near future. For example, once data is loaded into the cache, it is retained for a period of time for subsequent fast access. Spatial locality: If a memory location is accessed, nearby memory locations are also likely to be accessed soon. For example, when the CPU reads data from memory, it does not read only that one piece of data, but rather loads the entire cache block containing that data into the cache.

[0108] The principle of speed optimization can be summarized as follows: for frequently executed operations, the fastest path should be selected first to minimize latency.

[0109] In some embodiments, writing data 0 into the cache block may include: determining a plurality of instructions to be executed that access the cache block based on the physical address in the storage address buffer; arbitrating the instruction to write data 0 with the plurality of instructions to be executed; and writing data 0 into the cache block after the instruction to write data 0 wins the arbitration.

[0110] When the LSU determines that a write to the L1 cache requires execution of the CBO.ZERO instruction, it can initiate a read request to the memory address buffer. This request carries the index of the corresponding entry in the buffer, ensuring precise location of its storage position. Upon receiving the request, the address buffer will output the physical address information of the target entry and the pre-stored instruction type identifier in parallel within the same clock cycle, achieving synchronous acquisition of address and type information and providing a complete context for subsequent operations.

[0111] The clock cycle is the reciprocal of the CPU's clock speed. For example, a CPU running at 4GHz has a clock cycle of 0.25 nanoseconds. Each clock cycle is a time window during which the circuit state can change. Parallel output within the same clock cycle means that the LSU does not need to wait for the address information to stabilize before initiating the type information read. Both operations are completed simultaneously within the same clock tick.

[0112] The access arbitrator acts as a decision-making and scheduling center within the load storage unit. When multiple requesters compete for the same shared resource, it determines the order in which they can use it. Caches (especially L1 caches) typically have a limited number of access ports (e.g., one read port and one write port). However, within a single clock cycle, the LSU may receive multiple requests simultaneously, such as a CBO.ZERO instruction requesting to write to the cache; a LOAD instruction from the execution unit requesting to read from the cache; and a regular STORE instruction also requesting to write to the cache. They may all want to use the same cache port, but the hardware can typically only serve one at a time within a single cycle. The arbitrator receives access requests from multiple sources simultaneously and prioritizes all these requests according to a pre-defined arbitration strategy. Factors considered in the pre-defined arbitration strategy may include: instruction type: some operations (such as cache consistency maintenance requests) may have the highest priority; age order: to maintain program correctness, instructions that entered the pipeline earlier (older) should generally be processed first; latency: if a request has been rejected for multiple cycles, its priority may be increased to prevent starvation. Based on the sorting results, the arbitrator selects and authorizes a winning request to access the cached resource in each cycle, and tells other requests to wait temporarily.

[0113] After successfully obtaining the address and type information, the LSU submits this zero-value write request to its internal access arbitrator. This arbitrator prioritizes and schedules all access requests (such as regular cache reads and other storage operations) to the same cache port within the current cycle. The arbitration strategy comprehensively considers factors such as instruction type, age order, and wait time to ensure that critical path latency is minimized. Through this integrated arbitration mechanism, concurrent access requests for the same cache resource by the CBO.ZERO instruction and other memory access instructions can be automatically coordinated at the hardware level, effectively avoiding structural conflicts and ensuring smooth pipeline execution and the correct order of cache accesses.

[0114] Once a zero-value write request is arbitrated and authorized, the LSU initiates the actual write process to the L1 cache. Its control logic, based on the type of instruction read, configures the data source selection signal of the cache data path to point to the internal zero-value generator, rather than the storage data buffer relied upon by regular storage instructions. This allows the L1 cache data array to directly receive the internally generated zero-value data stream without waiting for data transfer from the external data buffer, thus completing the zeroing initialization of the target cache block in a highly efficient and energy-saving process.

[0115] In some embodiments, if a corresponding cache block cannot be matched in step S203, the following can be performed: Figure 4 The steps shown are as follows:

[0116] S401: If there is no cache block in the L1 cache that matches the physical address in the storage address buffer and is in a writable state, obtain the first count value of the first counter, which is used to count the executed clear instructions.

[0117] S402: Determine whether the first count value is less than the first write threshold, the first write threshold being used to control the maximum number of consecutive zero-clear instructions written to the L1 cache.

[0118] S403: If so, write data 0 to the first-level cache.

[0119] S404: If not, write the data 0 to the second-level cache or the third-level cache.

[0120] In some embodiments, in step S401, if there is no cache block in the first-level cache that matches the physical address in the storage address buffer and is in a writable state, the first count value of the first counter is obtained, and the first counter is used to count the executed clear instructions.

[0121] If the address comparison circuit determines that there is no valid cache block in the L1 cache that matches the physical address of the CBO.ZERO instruction in the storage address buffer (i.e., an L1 Cache Miss occurs), a counting lookup operation is triggered. This allows access to the first counter, dedicated to counting the number of CBO.ZERO instruction executions, to obtain its current cumulative count. The first counter's counting logic is based on the instruction commit order, automatically incrementing after each CBO.ZERO instruction architecture commit. Through this counting mechanism, the LSU can track the strength and continuity of the current CBO.ZERO instruction stream in real time, providing a quantitative basis for intelligent decisions regarding subsequent cache write strategies.

[0122] In some embodiments, in step S402, it is determined whether the first count value is less than a first write threshold, wherein the first write threshold is used to control the maximum number of consecutive zero-clear instructions written to the L1 cache.

[0123] The first write threshold can serve as a boundary for defining the compatibility between the number of consecutive CBO.ZERO instructions and the size of the L1 cache. Since the L1 cache is the CPU's closest cache to the core, it has a small capacity and is sensitive to access latency. Allowing consecutive CBO.ZERO instruction writes without restriction could lead to frequent replacement of valid data in the L1 cache, causing cache pollution and ultimately reducing overall storage performance. Therefore, the first write threshold can provide a quantitative control standard for the CBO.ZERO write behavior of the L1 cache by setting a maximum number of consecutive writes. For example, the default configuration of 4 times means that when the cumulative number of consecutive CBO.ZERO instructions (i.e., the first counter value) does not exceed 4 times, it can be determined that the current consecutive sequence poses a low risk of polluting the L1 cache, and CBO.ZERO instructions can continue to be directed to the L1 cache for writing; if the cumulative number reaches or exceeds this threshold, it is determined that continuing to write to the L1 cache may affect cache efficiency, and it is necessary to switch to writing to the L2 or L3 cache.

[0124] In some embodiments, in step S403, if the first count value is less than the first write threshold, data 0 is written to the L1 cache.

[0125] If the first count value is less than the first write threshold, the LSU can determine that the current CBO.ZERO instruction stream is still within the capacity of the L1 cache. In this case, even if an L1 cache miss occurs, the LSU will still perform an L1 cache line allocation operation and write the data 0 into the newly allocated L1 cache block.

[0126] In some embodiments, in step S404, if the first count value is greater than or equal to the first write threshold, data 0 is written to the L2 cache or the L3 cache.

[0127] If the first count value is greater than or equal to the first write threshold, the LSU will actively avoid writing to the L1 cache and instead write the data 0 to the L2 or L3 cache. This strategy switching aims to protect the L1 cache's working set from the impact of large-scale zeroing operations. Specifically, the further selection of the write target between L2 and L3 can be allocated based on the L2 cache's write limits: for medium-length continuous streams, write to the L2 cache to balance latency and bandwidth; for extremely long continuous streams, write directly to the L3 cache to minimize L2 cache bandwidth usage. This hierarchical decision-making mechanism can intelligently balance CPU cache efficiency and memory subsystem load while maintaining the zeroing function.

[0128] In some embodiments, step S403 may include: reading the instruction type from the storage address buffer; and writing data 0 into the first-level cache according to the instruction type.

[0129] The LSU can read the type identifier of the current instruction from the corresponding entry in the memory address buffer. When it confirms that the identifier represents a CBO.ZERO instruction, it triggers a dedicated zero-value write path, directly writing the data 0 to the corresponding target block in the L1 cache. Unlike traditional memory operations, this process completely bypasses the step of reading operands from the memory data buffer. Instead, the LSU sends an explicit zero-clearing control signal to the cache controller, and the cache data array completes the zero-value initialization of the specified block locally. By identifying the instruction type and enabling the dedicated path, the entire process of transferring all-zero data from the data buffer to the cache via the bus is avoided, eliminating the dynamic power consumption generated by address decoding, data driving, and bus flipping during this process, thus achieving a significant improvement in energy efficiency.

[0130] In some embodiments, step S404 may include: determining whether the first count value is less than a second write threshold; the second write threshold is used to control the maximum number of consecutive zero-clear instructions written to the first-level cache and the second-level cache; if yes, write data 0 to the second-level cache; if no, write data 0 to the third-level cache.

[0131] The second write threshold defines the maximum cumulative number of consecutive zeroing instructions that can be written to the L1 and L2 caches. When it is determined that the current count value of the first counter is not lower than the first write threshold, meaning the number of consecutive CBO.ZERO instructions has exceeded the appropriate write range for the L1 cache, LUSU will further use the second write threshold as the decision boundary to determine the write target for the next level. The second write threshold plays a crucial role: it defines the upper limit of the total amount of consecutive CBO.ZERO instructions allowed to be written to the intermediate and high-speed caches (i.e., L1 and L2). Unlike the first write threshold, which only manages the L1 cache, the second write threshold manages both L1 and L2 cache resources from a system-level perspective. Its purpose is to prevent cache pollution in the L2 cache due to excessive and continuous zeroing operations, thereby ensuring the overall storage efficiency and data locality of the intermediate and high-speed cache levels.

[0132] If the current count value is less than the second write threshold, it indicates that although consecutive CBO.ZERO operations are no longer suitable for writing all of them to L1, their overall scale is still within the combined capacity of L1 and L2 caches. At this time, LSU will redirect the zeroing operation to the L2 cache, achieving lower access latency than L3 while effectively protecting the more valuable L1 cache resources.

[0133] If the current count value is greater than or equal to the second write threshold, it means that the continuous CBO.ZERO instruction stream has put potential pressure on the medium and high-speed cache levels. At this time, LSU will switch its decision to write to the L3 cache. Although the L3 cache access latency is relatively high, its large capacity can better absorb large-scale, batch zeroing operations, avoiding its continuous interference with high-value working set data in the L1 and L2 caches, and maintaining the computational efficiency of the processor core from a global perspective.

[0134] By introducing a second write threshold, a progressive write decision mechanism of L1->L2->L3 is constructed. This design can dynamically adjust its write target according to the continuous intensity of zeroing operations, achieving precise protection of limited and valuable medium-to-high-speed cache resources, effectively suppressing cache pollution, and ensuring the performance of core workloads. Furthermore, this mechanism does not simply push all operations exceeding the threshold to the highest-latency L3 cache, but instead establishes an intermediate buffer (L2 cache) through the second threshold. This is crucial for medium-length continuous zeroing flows, enabling them to achieve better write latency than L3 while avoiding impacting L1, thereby optimizing the overall system throughput and average response time.

[0135] Overall, this dual-threshold-based two-level decision-making mechanism, through fine-grained flow control and cache hierarchy management, significantly improves the overall efficiency of the cache subsystem and the comprehensive performance of the processor while ensuring the correctness of CBO.ZERO functionality.

[0136] In some embodiments, step S404 may further include: if there is no cache block in the secondary cache that matches the physical address in the storage address buffer, then read the instruction type from the storage address buffer; and write the data 0 into the corresponding cache block in the tertiary cache according to the instruction type.

[0137] When the LSU determines that the value 0 of the CBO.ZERO instruction needs to be written to the L3 cache, and detects that there is no cache block in the L2 cache that matches the physical address information (PA) of the CBO.ZERO instruction in the storage buffer, it can read the instruction type information and drive the L3 cache to write the value 0. Specifically, before triggering the L3 cache write, the L2 cache can perform address matching checks. After the LSU sends the PA of the CBO.ZERO instruction to the L2 cache, the L2 cache's TAG array will locate the target cache group based on the group index in the PA, and then compare the TAG fields of all paths in that group with the TAG fields of the PA bit by bit. If the TAGs of all paths do not match the PA, the L2 cache will send a no-matching-block signal to the LSU and trigger the skip-L2 allocation logic. After receiving the no-matching-block signal from the L2 cache, the LSU will immediately initiate a read operation of the CBO.ZERO instruction type information in the storage buffer. The LSU control logic module can configure the L3 cache data source selection signal to the internal zero generator, rather than the storage data buffer data of the ordinary STORE instruction, based on the type information being read. This ensures that the L3 cache does not wait for external data input, but directly uses the internally generated 0 value and writes the 0 to the specified cache block.

[0138] TAG is the high-order part of the physical address, and its function is to uniquely identify which address in main memory the data stored in the current cache block belongs to.

[0139] The TAG field can be a physical storage area specifically used to store its TAG value in the metadata area of ​​each individual cache block.

[0140] A TAG array is a hardware storage structure consisting of the collection of all TAG fields in the cache. It is an independent, high-speed memory array. TAG arrays can provide TAG matching query capabilities in parallel. The organization of the TAG array directly corresponds to the cache mapping method. In an N-way set-associative cache, each set index corresponds to N TAG fields, which are placed side-by-side in hardware for parallel comparison.

[0141] In some embodiments, step S404 may further include: if there is a cache block in the secondary cache that matches the physical address in the storage address buffer and the cache block is in a writable state, then read the instruction type from the storage address buffer; and write the data 0 into the cache block in the secondary cache according to the instruction type.

[0142] When the LSU determines that the CBO.ZERO instruction needs to be written to the L3 cache, but detects a cache block in the L2 cache that matches the instruction's PA and is in a writable state, it can prioritize writing the 0 value to the L2 cache instead of directly writing to L3. Before triggering the L3 write, the L2 cache performs address matching and writable status checks. Based on the PA of the CBO.ZERO instruction, the target cache group can be located and the TAGs compared bit by bit to confirm the existence of a cache block that perfectly matches the PA. The status bits of the matching block can also be read; if the status is writable, an L2 cache writable signal is sent back to the LSU, and access permissions to the cache block are locked. Upon receiving the L2 cache writable signal, the LSU immediately initiates a read operation of the CBO.ZERO instruction type information in the storage buffer. The LSU's control logic module can configure the L2 cache data source selection signal to the internal zero generator, rather than the storage data buffer data of the ordinary STORE instruction, based on the type information being read. This ensures that the L2 cache does not wait for external data input, directly uses the internally generated 0 value, and writes the 0 to the specified cache block. This design follows the basic rule of guiding the L3 cache when the current count value of the first counter is greater than or equal to the second write threshold, and optimizes the writing to the L2 cache first when the L2 cache hits a writable value. Without breaking the hierarchical decision-making logic, it reduces latency by utilizing existing L2 cache resources and achieves a balance between rule rigidity and scenario flexibility.

[0143] In some embodiments, the first write threshold is the associativity of the L1 cache.

[0144] Associativity refers to the number of cache blocks (ways) contained in each cache set in the L1 cache. For example, in a 4-way set-associative L1 cache, each set contains 4 ways, which can store cache blocks with 4 different tags. Associativity directly determines the number of independent cache blocks that each L1 cache set can hold, and also indirectly affects the cache hit rate and replacement frequency. The higher the associativity, the more cache blocks each set can store, and the lower the probability of cache block conflicts within the same address range, but the hardware complexity and access latency also increase accordingly.

[0145] By setting the first write threshold to the associativity, excessive occupation of a single cache block by the CBO.ZERO instruction can be avoided. Since the CBO.ZERO instruction is usually executed with contiguous addresses, its target address is likely to map to the same or adjacent L1 cache groups. If the first write threshold is greater than the associativity (e.g., a threshold of 5 for a 4-way associative L1 cache), five consecutive CBO.ZERO instructions may cause all four ways in the same set to be occupied by zeroed cache blocks. If other critical data (such as frequently accessed instructions or ordinary storage data) needs to be written to this set later, cache replacement will be triggered, replacing the newly written zeroed cache block. This not only renders the CBO.ZERO instruction's write operation invalid (i.e., it is replaced before being accessed after being zeroed), but also increases the access latency of other data. By setting the threshold to associativity, such as a threshold of 4 for 4-way associativity, consecutive CBO.ZERO instructions will occupy at most all Ways within the same Set. If a new zeroing instruction arrives, the system will determine that it exceeds the write range of the L1 cache based on the threshold and redirect subsequent instructions to the L2 cache. This avoids the cache blocks of the same Set being repeatedly replaced, ensuring that each Set of the L1 cache can handle a reasonable number of zeroing operations without affecting the storage of other critical data.

[0146] Furthermore, this design simplifies the replacement strategy and hardware implementation of the L1 cache. For example, when the first write threshold equals the associativity, the LSU does not need to maintain the Way count occupied by the CBO.ZERO instruction. It only needs to compare the current count value of the first counter with the associativity to determine whether to switch the write level. If the current count value is less than the associativity, it means that the Set mapped by the current zeroing instruction still has free Ways, and writing to L1 can continue. If the current count value equals the associativity, it means that the Way of the corresponding Set has been filled, and it needs to switch to L2. This threshold setting based on associativity is deeply coupled with the hardware structure of the L1 cache, requiring no additional configuration parameters or logical judgments, reducing the complexity of hardware design. At the same time, it ensures that the threshold is completely matched with the actual carrying capacity of the L1 cache, avoiding cache pollution caused by an excessively large threshold or underutilization of L1 cache resources due to an excessively small threshold.

[0147] In some embodiments, the second write threshold is determined by the following formula: alloc_l2_threshold=(L2_C / L1_C)*alloc_l1_threshold; where alloc_l2_threshold represents the write threshold of the L2 cache, L2_C represents the cache capacity of the L2 cache, L1_C represents the cache capacity of the L1 cache, and alloc_l1_threshold represents the write threshold of the L1 cache.

[0148] The capacity of the L2 cache is typically much larger than that of the L1 cache. For example, if the L1 cache has a capacity of 32KB and the L2 cache has a capacity of 256KB, the capacity ratio is 8:1. The number of consecutive CBO.ZERO instructions that the L2 cache can handle should also be increased proportionally. If the first write threshold (alloc_l1_threshold) for the L1 cache is 4, then the write threshold for the L2 cache should be scaled up to "8*4=32" according to the capacity ratio. This ensures that the number of zeroing instructions handled by the L2 cache matches its own capacity, avoiding underutilization of L2 cache resources due to a threshold that is too small (e.g., still set to 4), or excessive occupation of the L2 cache by zeroing instructions due to a threshold that is too large (e.g., set to 64), affecting the processing of Miss requests from other cores or the L1 cache.

[0149] L1_C and L2_C represent the actual capacities of the L1 and L2 caches, respectively. Their ratio (L2_C / L1_C) reflects the capacity multiple of the L2 cache relative to the L1 cache. This ratio essentially reflects the theoretical carrying capacity multiple of the L2 cache for consecutive CBO.ZERO instructions. A larger capacity should theoretically accommodate more consecutive zeroing operations, providing a physical basis for threshold scaling. The first write threshold represents the maximum number of consecutive CBO.ZERO instructions allowed to be written to the L1 cache, directly determining the upper limit of streaming zeroing operations that the L1 cache can handle. The second write threshold, as a calculated result, represents the maximum number of consecutive CBO.ZERO instructions allowed to be written to the L2 cache. Its value is bound to the first write threshold through a capacity ratio, ensuring that the second write threshold is neither too large, leading to resource waste, nor too small, limiting the execution of streaming operations.

[0150] By scaling the capacity ratio, the proportion of CBO.ZERO instructions in the L2 cache is ensured to remain consistent with that in the L1 cache. This avoids overload (e.g., the second write threshold is much larger than the capacity ratio, causing a large number of zeroing instructions to occupy the L2 cache and affect other operations) or underload (e.g., the second write threshold is too small, failing to fully utilize the capacity advantage of the L2 cache) caused by threshold mismatch in a certain cache level. Furthermore, if the cache capacity changes, such as disabling part of the L2 cache in low-power mode and reducing L2_C from 256KB to 128KB, the capacity ratio can be recalculated in real time, and the second write threshold updated to ensure that the second write threshold always matches the current cache capacity, maintaining resource balance across different operating modes.

[0151] In some embodiments, the current count value of a second counter is obtained, the second counter being used to count instructions that are not CBO.ZERO instructions and are not write instructions.

[0152] The current count value of the second counter can be obtained. This second counter can precisely count other types of micro-operations (UOPs) that are not CBO.ZERO instructions and are not cache block size write instructions. Specifically, whenever the LSU completes the execution of a micro-operation that meets the characteristics of a non-CBO.ZERO instruction and is not a cache block size write instruction, the second counter can trigger an increment operation and update the current count value in real time. Its count value can essentially characterize the execution frequency of non-contiguous memory operations in the system. A higher count value indicates more scattered memory operations executed by the system per unit time, indirectly reflecting a weaker continuity in the current memory operation sequence; conversely, a lower count value means a lower proportion of non-contiguous memory operations, and the memory sequence is more likely to exhibit continuous and regular characteristics.

[0153] In some embodiments, if the current count value of the first counter is greater than or equal to the first count threshold, the second counter is reset.

[0154] The first counter counts consecutively executed CBO.ZERO instructions, and its count directly reflects the continuous length of the current CBO.ZERO instruction sequence. When the current count value of the first counter is detected to be greater than or equal to the first counting threshold, it can be determined that the LSU has entered a streaming memory mode consisting of multiple consecutive CBO.ZERO instructions. In this mode, memory operations are executed continuously at a fixed cache block granularity, and the goal is to clear the data, exhibiting strong continuity and regularity. At this time, to avoid interference from previously recorded non-continuous operation history in determining the current streaming mode, a reset operation of the second counter can be triggered. Specifically, the count value of the second counter can be cleared to zero, erasing historical counting records. The reset operation of the second counter can reinitialize the counting base of non-streaming instructions. In other words, during the continuous streaming storage mode, even if there are occasional small numbers of non-continuous storage operations, counting from zero can avoid mode misjudgment caused by historical accumulated values, ensuring that the continuous state of the current streaming mode can be accurately tracked, and providing accurate counting basis for subsequent CBO.ZERO instruction cache write level (such as whether to write directly to L2 / L3 Cache) decisions.

[0155] In some embodiments, if the current count value of the second counter is equal to the second count threshold, the first counter is reset.

[0156] The count value of the second counter can be used as an indicator to determine whether the LSU has exited the streaming memory mode. When the current count value of the second counter is detected to be equal to the second count threshold, it indicates that a sufficient number of non-CBO.ZERO instructions and non-cache block case instructions have been executed within the current time period. The concentrated occurrence of these two types of operations means that the continuity of the memory operation sequence has been broken, the streaming memory mode originally composed of continuous CBO.ZERO instructions has ended, and the system has entered a non-streaming memory scenario, such as scattered ordinary STORE instructions, mixed-type memory operations, etc. To terminate the current streaming pattern recognition state and prepare for the next streaming pattern detection, the first counter can be reset. Specifically, the count value of the first counter can be cleared to zero, and the sequence detection state of CBO.ZERO instructions can be reinitialized. The reset operation of the first counter can promptly cut off invalid streaming pattern tracking. In other words, when non-continuous operations have reached a threshold, continuing to retain the previously accumulated consecutive CBO.ZERO counts from the first counter can lead to mode judgment errors for subsequent CBO.ZERO instructions, such as misjudging scattered CBO.ZERO instructions as streaming mode. By resetting the first counter, it can be ensured that the consecutive count of the next CBO.ZERO instruction starts from zero, allowing the system to accurately detect the new streaming storage mode again and avoiding cache write policy errors caused by historical count residues (such as misleading non-streaming CBO.ZERO instructions to be written to L2 / L3 cache).

[0157] In some embodiments, after writing data 0 to the first-level cache, the second-level cache, or the third-level cache, the first count value of the first counter is incremented by 1.

[0158] When the CBO.ZERO instruction successfully writes data 0 into any level of the L1, L2, or L3 cache, the system can trigger the increment of the current count value of the first counter by 1. This ensures that the count value of the first counter accurately reflects the number of consecutive CBO.ZERO instructions that have been effectively executed, and avoids counting deviations caused by abnormal scenarios such as write failures or retries.

[0159] In some embodiments, step S20 may further include: if there is a cache block in the first-level cache that matches the physical address in the storage address buffer and the cache block is in a non-writable state, sending a cache miss instruction to the second-level cache; and writing data 0 into the cache block in the first-level cache according to the writable instruction returned by the second-level cache.

[0160] When an L1 cache contains a block that matches the CBO.ZERO directive PA, but that block is in a writable state, the writability issue can be resolved through interaction with the L2 cache before a zero-value write is performed. Specifically, this can involve: First, the LSU generates a cache miss request. Upon receiving the request, the L2 cache parses the identifier field and enters a state repair process, making the L1 cache block matching the CBO.ZERO directive PA writable. After completing the state repair, the L2 cache returns a writable response to the L1 cache. Upon receiving the writable response, the L1 cache first completes state and data repair. After repair, the L1 cache sends a ready signal to the LSU, indicating that a zero-value write is possible. Subsequently, the LSU triggers a zero-value write process consistent with the write process in the writable state. An internal zero generator generates all-zero data, which is then written to the writable cache block.

[0161] In some embodiments, the above-described cache block zeroing method is not only applicable to the RISC-V architecture, but also adaptable to other instruction set architectures with similar cache block zeroing functionality, such as the x86 and ARM architectures. The core mechanisms of this method—including address matching, stream pattern detection, and multi-level cache write strategies—serve as a general microarchitectural implementation approach, enabling cross-platform application in any processor design that supports cache block operations or has equivalent zero-value storage instructions.

[0162] As can be seen from the cache block clearing method provided in the embodiments of this specification above, the embodiments of this specification can obtain a cache block clearing microinstruction carrying parameters, the parameters including a physical address but excluding data; write the physical address into a storage address buffer; match the corresponding cache block in the cache according to the physical address in the storage address buffer; and write the data 0 into the cache block. In terms of power consumption optimization, since the microinstruction itself does not carry data and completely bypasses access to the storage data buffer during execution, it completely eliminates the large-scale circuit switching power consumption associated with all-zero data read / write operations. At the same time, this mechanism ensures that the clearing operation does not require driving and transmitting a large number of all-zero bits on the processor's internal bus. This not only significantly reduces the dynamic power consumption of the bus interface but also effectively alleviates bus congestion, freeing up valuable bandwidth for other critical data accesses. In terms of hardware resource utilization, for the valuable and limited resource of the storage data buffer, by making the clearing instruction run completely independently of this resource, the limited buffer entries are reserved for ordinary storage instructions that truly need to temporarily store data. This design directly reduces the risk of pipeline blockage caused by a full data buffer, comprehensively improves resource utilization efficiency, and significantly enhances the overall performance of the CPU when handling mixed workloads.

[0163] Based on the above-described cache block clearing method, this specification also provides embodiments of a cache block clearing device. For example... Figure 5 As shown, the cache block clearing device 500 may specifically include the following modules:

[0164] The acquisition module 501 is used to acquire a cache block clearing micro-instruction carrying parameters, wherein the parameters include physical addresses but do not include data.

[0165] The first write module 502 is used to write the physical address into the storage address buffer.

[0166] The matching module 503 is used to match the corresponding cache block in the cache according to the physical address in the storage address buffer.

[0167] The second write module 504 is used to write data 0 into the cache block.

[0168] In some embodiments, the parameters further include an instruction type. Based on this, the first write module 502 described above can specifically be used for:

[0169] Write the instruction type into the storage address buffer.

[0170] In some embodiments, the cache includes at least a level 1 cache, a level 2 cache, and a level 3 cache. Based on this, the matching module 503 described above can specifically be used for:

[0171] The cache block in the first-level cache that matches the physical address in the storage address buffer and is in a writable state is searched.

[0172] In some embodiments, the matching module 503 described above can also be used for:

[0173] If there is no cache block in the L1 cache that matches the physical address in the storage address buffer and is in a writable state, obtain the first count value of the first counter, which is used to count the executed clear instructions;

[0174] Determine whether the first count value is less than the first write threshold, the first write threshold being used to control the maximum number of consecutive zero-clear instructions written to the L1 cache;

[0175] If so, write data 0 to the first-level cache;

[0176] If not, write the data 0 to the second-level cache or the third-level cache.

[0177] In some embodiments, the matching module 503 described above can also be used for:

[0178] Read the instruction type from the memory address buffer;

[0179] According to the instruction type, write data 0 into the first-level cache.

[0180] In some embodiments, the matching module 503 described above can also be used for:

[0181] Determine whether the first count value is less than the second write threshold; the second write threshold is used to control the maximum number of consecutive zero-clear instructions written to the L1 cache and L2 cache;

[0182] If so, write the data 0 to the second-level cache;

[0183] If not, write the data 0 to the level 3 cache.

[0184] In some embodiments, the matching module 503 described above can also be used for:

[0185] If there is no cache block in the L2 cache that matches the physical address in the storage address buffer, then the instruction type is read from the storage address buffer;

[0186] According to the instruction type, data 0 is written to the corresponding cache block in the level 3 cache.

[0187] In some embodiments, the matching module 503 described above can also be used for:

[0188] If a cache block exists in the L2 cache that matches the physical address in the storage address buffer, and the cache block is writable, then the instruction type is read from the storage address buffer.

[0189] According to the instruction type, write data 0 into the cache block in the second-level cache.

[0190] In some embodiments, the first write threshold is the associativity of the first-level cache;

[0191] The second write threshold is determined by the following formula:

[0192] alloc_l2_threshold=(L2_C / L1_C)*alloc_l1_threshold;

[0193] In the formula, alloc_l2_threshold represents the write threshold of the L2 cache, L2_C represents the cache capacity of the L2 cache, L1_C represents the cache capacity of the L1 cache, and alloc_l1_threshold represents the write threshold of the L1 cache.

[0194] In some embodiments, the matching module 503 described above can also be used for:

[0195] Obtain the second count value of the second counter, which is used to count instructions that are neither clear instructions nor write instructions;

[0196] If the first count value is greater than or equal to the first count threshold, the second counter is reset;

[0197] If the second count value is equal to the second count threshold, the first counter is reset.

[0198] In some embodiments, the matching module 503 described above can also be used for:

[0199] After writing the data 0 to the first-level cache, second-level cache, or third-level cache, increment the first count value of the first counter by 1.

[0200] In some embodiments, the matching module 503 described above can also be used for:

[0201] If a cache block exists in the first-level cache that matches the physical address in the storage address buffer, and the cache block is in a non-writable state, a cache miss instruction is sent to the second-level cache.

[0202] Based on the writable instruction returned by the second-level cache, the data 0 is written to the cache block in the first-level cache.

[0203] In some embodiments, the matching module 503 described above can also be used for:

[0204] Based on the physical address in the storage address buffer, determine multiple instructions to be executed to access the cache block;

[0205] Arbitrate the instruction that writes data 0 with the plurality of instructions to be executed;

[0206] Once the instruction to write data 0 wins the arbitration, data 0 will be written to the cache block.

[0207] As can be seen from the cache block clearing device provided in the embodiments of this specification above, the embodiments of this specification can obtain a cache block clearing microinstruction carrying parameters, the parameters including a physical address but excluding data; write the physical address into a storage address buffer; match the corresponding cache block in the cache according to the physical address in the storage address buffer; and write the data 0 into the cache block. Regarding power consumption optimization, since the microinstruction itself does not carry data and completely bypasses access to the storage data buffer during execution, it completely eliminates the large-scale circuit switching power consumption associated with all-zero data read / write operations. Simultaneously, this mechanism ensures that the clearing operation does not require driving and transmitting a large number of all-zero bits on the processor's internal bus. This not only significantly reduces the dynamic power consumption of the bus interface but also effectively alleviates bus congestion, freeing up valuable bandwidth for other critical data accesses. Regarding hardware resource utilization, for the valuable and limited resource of the storage data buffer, by making the clearing instruction run completely independently of this resource, the limited buffer entries are reserved for ordinary storage instructions that truly need to temporarily store data. This design directly reduces the risk of pipeline blockage caused by a full data buffer, comprehensively improves resource utilization efficiency, and significantly enhances the overall performance of the CPU when handling mixed workloads.

[0208] In existing CBO.ZERO technology, LOAD instructions issued to the LSU later can only be executed after the CBO.ZERO instructions have finished writing to the L1 Cache, resulting in low performance for LOAD instructions. To address this issue, this specification also provides a method for implementing read instructions, which includes, in practice, methods such as... Figure 6 The steps shown are as follows:

[0209] S601: Match the target physical address of the read instruction with the physical address of the zeroing instruction recorded in the memory address buffer that precedes the read instruction.

[0210] S602: If a zeroing instruction with a matching physical address exists, the data 0 is returned to the read instruction according to the instruction type of the zeroing instruction.

[0211] In the existing technology, the sequence of instructions issued to the LSU, arranged from oldest to youngest, can be as follows:

[0212] CBO.ZERO A;

[0213] CBO.ZERO B;

[0214] LOAD A;

[0215] LOAD B;

[0216] The CBO.ZERO and LOAD instructions are sent to the LSU out of order by the CPU. This can lead to situations where the CBO.ZERO instruction hasn't yet been executed in the LSU before the LOAD instruction begins execution. For example, when the LOAD A instruction is executed, if it detects a CBO.ZERO A instruction at the same address in the SB (Buffer Block), it cannot execute and must wait for the CBO.ZERO instruction to write 0 to the cache before the LOAD instruction can be executed. Therefore, in current technology, younger LOAD instructions must wait until older CBO.ZERO instructions have finished writing to the L1 cache before they can be executed, resulting in lower performance for LOAD instructions.

[0217] Therefore, when a LOAD instruction is issued after a CBO.ZERO instruction, the addresses PA_LOAD and PA_CBO of the CBO.ZERO instruction can be obtained respectively. CBO.ZERO performs zeroing on a block-by-block basis (e.g., 64B), while the LOAD instruction's access granularity may be byte, half-word, or word (e.g., 4B). A match requires that the access range of the LOAD instruction is entirely within the address range of the cache block processed by the CBO.ZERO instruction.

[0218] For example, if the address PA_CBO of CBO.ZERO is 0x2000 (corresponding to a block range of 0x2000~0x203F), and the address PA_LOAD accessed by the LOAD instruction is 0x2008 (a 4-byte range of 0x2008~0x200B), then it is considered a match; if PA_LOAD is 0x2040, then it is out of range and does not match. Furthermore, the system performs a bit-by-bit comparison of the high-order address bits of PA_LOAD and PA_CBO, i.e., the portion excluding the cache block offset. If the high-order address bits are completely identical, and the LOAD access does not exceed the CBO.ZERO block range, then it is considered an address match; otherwise, it is not a match.

[0219] If multiple CBO.ZERO instructions exist in the memory buffer, the LSU can check them sequentially from newest to oldest, prioritizing the matching of the CBO.ZERO instruction closest to LOAD. When an address match is found, a STLF-like optimization mechanism (CBO.ZERO-TO-LOAD Forwarding) is triggered: the LOAD instruction does not need to access the cache; instead, the zero data generator in the LSU directly generates all-zero data (e.g., 32-bit or 64-bit all-zeros) of the required LOAD access granularity (e.g., 4B or 8B), ensuring data width matching and avoiding transmission errors caused by inconsistent bit widths. This zero value is directly returned to the LOAD instruction. By avoiding redundant cache accesses, in scenarios where CBO.ZERO guarantees the target region is zero, LOAD instruction latency is significantly reduced, easing cache access pressure and thus improving overall CPU execution efficiency.

[0220] As can be seen from the implementation method of the write instruction provided in the embodiments of this specification above, the embodiments of this specification can perform a match check between the target physical address of the read instruction and the physical address of the clear instruction recorded in the memory address buffer that precedes the read instruction; if a clear instruction with a matching physical address exists, data 0 is returned to the read instruction according to the instruction type of the clear instruction. Zero-latency data forwarding is achieved through address matching checks. When the physical address of the read instruction matches the address of an earlier, incomplete clear instruction, the read instruction does not need to wait for the clear instruction to be actually executed and written to the cache, and can immediately obtain data from the memory address buffer. This completely eliminates the inherent latency caused by accessing the cache array and even the lower-level memory, transforming a complete memory read operation into a direct register read, improving instruction throughput and program execution speed. By avoiding such unnecessary cache access, significant dynamic power saving is achieved. Traditional read instruction execution requires activating large-scale circuits such as the word lines and bit lines of the cache, resulting in huge power consumption. After a successful address match, subsequent access to the cache data array is directly blocked, eliminating the need for these high-power units to operate. At the same time, since there is no need to read data from the cache, signal switching activity on the internal data bus is reduced, thus reducing power consumption at the system level.

[0221] Based on the above-described cache block clearing method, this specification also provides embodiments of a cache block clearing device. For example... Figure 7 As shown, the read instruction implementation device 700 may specifically include the following modules:

[0222] The matching module 701 is used to perform a matching check between the target physical address of the read instruction and the physical address of the clear instruction recorded in the memory address buffer that precedes the read instruction.

[0223] The return module 702 is used to return data 0 to the read instruction if a clear instruction with a matching physical address exists, based on the instruction type of the clear instruction.

[0224] This specification also provides a processor for executing the above-described cache block clearing method and the above-described read instruction implementation method.

[0225] Furthermore, embodiments of this specification provide a chip including the processor described above for implementing the cache block clearing method and the read instruction method.

[0226] It should be understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this specification.

[0227] It should also be understood that, in the embodiments of this specification, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this specification generally indicates that the preceding and following related objects have an "or" relationship.

[0228] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0229] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0230] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0231] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational tasks to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The task is a function specified in one or more boxes.

[0232] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for clearing cache blocks, characterized in that, include: Obtain a cache block clearing microinstruction carrying parameters, wherein the parameters include the physical address but do not include the data; Write the physical address into the storage address buffer; Match the corresponding cache block in the cache based on the physical address in the storage address buffer; Write the data 0 into the cache block.

2. The method according to claim 1, characterized in that, The parameters also include the instruction type; The method further includes: Write the instruction type into the storage address buffer.

3. The method according to claim 1, characterized in that, The cache includes at least a level 1 cache, a level 2 cache, and a level 3 cache; The step of matching the corresponding cache block in the cache according to the physical address in the storage address buffer includes: The cache block in the first-level cache that matches the physical address in the storage address buffer and is in a writable state is searched.

4. The method according to claim 3, characterized in that, The method further includes: If there is no cache block in the L1 cache that matches the physical address in the storage address buffer and is in a writable state, obtain the first count value of the first counter, which is used to count the executed clear instructions; Determine whether the first count value is less than the first write threshold, the first write threshold being used to control the maximum number of consecutive zero-clear instructions written to the L1 cache; If so, write data 0 to the first-level cache; If not, write the data 0 to the second-level cache or the third-level cache.

5. The method according to claim 4, characterized in that, Writing data 0 to the first-level cache includes: Read the instruction type from the memory address buffer; According to the instruction type, write data 0 into the first-level cache.

6. The method according to claim 4, characterized in that, The step of writing data 0 to the second-level cache or the third-level cache includes: Determine whether the first count value is less than the second write threshold; the second write threshold is used to control the maximum number of consecutive zero-clear instructions written to the L1 cache and L2 cache; If so, write the data 0 to the second-level cache; If not, write the data 0 to the level 3 cache.

7. The method according to claim 6, characterized in that, The step of writing data 0 to the three-level cache includes: If there is no cache block in the L2 cache that matches the physical address in the storage address buffer, then the instruction type is read from the storage address buffer; According to the instruction type, data 0 is written to the corresponding cache block in the level 3 cache.

8. The method according to claim 7, characterized in that, The step of writing data 0 to the three-level cache also includes: If a cache block exists in the L2 cache that matches the physical address in the storage address buffer, and the cache block is writable, then the instruction type is read from the storage address buffer. According to the instruction type, write data 0 into the cache block in the second-level cache.

9. The method according to claim 7, characterized in that, The first write threshold is the associativity of the L1 cache; The second write threshold is determined by the following formula: alloc_l2_threshold=(L2_C / L1_C)*alloc_l1_threshold; In the formula, alloc_l2_threshold represents the write threshold of the L2 cache, L2_C represents the cache capacity of the L2 cache, L1_C represents the cache capacity of the L1 cache, and alloc_l1_threshold represents the write threshold of the L1 cache.

10. The method according to claim 4, characterized in that, The method further includes: Obtain the second count value of the second counter, which is used to count instructions that are neither clear instructions nor write instructions; If the first count value is greater than or equal to the first count threshold, the second counter is reset; If the second count value is equal to the second count threshold, the first counter is reset.

11. The method according to claim 4, characterized in that, The method further includes: After writing the data 0 to the first-level cache, second-level cache, or third-level cache, increment the first count value of the first counter by 1.

12. The method according to claim 3, characterized in that, The method further includes: If a cache block exists in the first-level cache that matches the physical address in the storage address buffer, and the cache block is in a non-writable state, a cache miss instruction is sent to the second-level cache. Based on the writable instruction returned by the second-level cache, the data 0 is written to the cache block in the first-level cache.

13. The method according to claim 3, characterized in that, Writing data 0 to the cache block includes: Based on the physical address in the storage address buffer, determine multiple instructions to be executed to access the cache block; Arbitrate the instruction that writes data 0 with the plurality of instructions to be executed; Once the instruction to write data 0 wins the arbitration, data 0 will be written to the cache block.

14. A method for implementing a read instruction, characterized in that, include: The target physical address of the read instruction is matched and checked against the physical address of the zeroing instruction recorded in the memory address buffer that precedes the read instruction. If a zeroing instruction with a matching physical address exists, the data 0 is returned to the read instruction according to the instruction type of the zeroing instruction.

15. A processor, characterized in that, The processor is used to perform the method according to any one of claims 1-14.

16. A chip, characterized in that, Includes the processor as described in claim 15.

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