GPU instruction execution method and device, computer equipment, medium and program product

Abstract

The invention provides a GPU instruction execution method and device, computer equipment, a medium and a program product, and relates to the technical field of computers, in particular to the fields of GPU instruction scheduling and execution and the like, and the implementation scheme comprises the steps that a first instruction of a first thread bundle and first register data are obtained; rearranging effective bits in the first register data to the front end to generate rearranged first register data; based on the rearranged first register data, storing a first operand required by the effective thread to execute the first instruction into a first retention stack; establishing a mapping table to record a serial number corresponding relation of each thread before and after rearrangement; transmitting the first operand to a first operation unit to execute a first operation; writing the operation result back to a target storage position corresponding to the effective thread based on the mapping table; and transmitting the second operand stored in the second reservation stack to the unoccupied arithmetic unit to execute the second operation in the same clock period during the execution of the first operation.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, particularly to the fields of GPU instruction scheduling and execution, and especially to a GPU instruction execution method, apparatus, computer device, computer-readable storage medium, and computer program product. Background Technology

[0002] Current mainstream GPUs are based on the SIMT (Single Instruction, Multithreaded) architecture, using thread bundles as the basic execution unit. Multiple threads within a thread bundle execute the same instruction within the same clock cycle. When the program reaches a branch logic, the GPU uses a predicate execution mechanism, marking the valid or invalid state of each thread through a predicate register. Only the results of threads with valid states are written back to the register, while the results of invalid threads are discarded. However, this mechanism only filters invalid results during the write-back phase and cannot prevent invalid threads from participating in the complete instruction execution flow. Invalid threads still occupy the computational resources of the arithmetic units and reserve stack storage resources, resulting in a decrease in the effective utilization of the arithmetic units. At the same time, since all arithmetic units within the same thread bundle must execute the same instruction within the same clock cycle, when some threads are invalid, the arithmetic units occupied by invalid threads cannot be used to execute other ready instructions, causing a decrease in instruction issuance efficiency. Therefore, how to optimize the occupation of computational resources by invalid threads and improve the instruction issuance efficiency of GPU instruction execution has become an important technical research direction. Summary of the Invention

[0003] This disclosure provides a GPU instruction execution method, apparatus, computer device, computer-readable storage medium, and computer program product.

[0004] According to one aspect of this disclosure, a GPU instruction execution method is provided, comprising: acquiring a first instruction to be executed by a first thread bundle and first register data, wherein the first register data is used to indicate the state of each thread in the first thread bundle under the execution of the first instruction, and each bit of the first register data corresponds one-to-one with each thread in the first thread bundle; traversing each bit of the first register data, rearranging the bits indicating that the thread state is valid to the front and close together to generate rearranged first register data; based on the rearranged first register data, storing the first operands required by the threads in the first thread bundle that are in a valid state to execute the first instruction into a first reserved stack; and establishing a mapping table, the mapping table being used to record each thread in the first thread bundle. The process establishes a correspondence between the rearranged numbering and the original numbering before rearrangement; transfers the first operand from the first reserved stack to at least one first arithmetic unit to execute the first operation corresponding to the first instruction; based on the correspondence recorded in the mapping table, writes the operation result output by at least one first arithmetic unit back to the target storage location corresponding to the thread whose state is valid in the first thread bundle before rearrangement; and during the execution of the first operation, within the same clock cycle, in response to the second instruction being fetched and the second operand required to execute the second instruction being stored in the second reserved stack, transfers the second operand to at least one second arithmetic unit to execute the second operation corresponding to the second instruction, wherein at least one second arithmetic unit includes an unoccupied arithmetic unit.

[0005] In some embodiments, storing the first operand required for a thread in the first thread bundle to execute a first instruction into a first reserved stack based on the rearranged first register data includes: reading the first operand required for a thread in the first thread bundle to execute a first instruction from the original register module based on the rearranged first register data; and storing the first operand into the first reserved stack.

[0006] In some embodiments, the raw register module includes a register file module and a source data cache module. The register file module consists of multiple independently addressed memory banks, and the source data cache module is used to cache data read from the register file module.

[0007] In some embodiments, the first operand includes at least two operands. Reading the first operand required by a thread in a first thread bundle that is in a valid state to execute a first instruction from the original register module includes: reading the required first operand from the source data cache module and the register file module respectively in response to determining that the addresses of at least two operands in the first operand are mapped to the same memory bank in a plurality of independently addressed memory banks; and reading the required first operand from the register file module in response to determining that the addresses of all operands in the first operand are mapped to different memory banks in a plurality of independently addressed memory banks.

[0008] In some embodiments, the result of the first operation after execution includes at least one sub-operation result, each sub-operation result corresponding one-to-one with a thread in the first thread bundle that is in a valid state. Based on the correspondence recorded in the mapping table, the operation result output by at least one first operation unit is written back to the target storage location corresponding to the thread in the first thread bundle that is in a valid state before the rearrangement. This includes: based on the number of each thread in the first thread bundle that is in a valid state after the rearrangement, looking up the mapping table to determine the original number of each thread in the first thread bundle that is in a valid state before the rearrangement; determining the target storage location to be written back for each sub-operation result based on the original number; and writing each sub-operation result into the corresponding target storage location.

[0009] In some embodiments, before generating the rearranged first register data, the GPU instruction execution method further includes: counting bits in the first register data that indicate a valid thread state to obtain a total number of valid threads; and determining the number of at least one first arithmetic unit required to execute the first instruction based on the total number of valid threads and the maximum thread capacity of a single arithmetic unit, wherein the number of first arithmetic units is associated with the ratio of the total number of valid threads to the maximum thread capacity of a single arithmetic unit.

[0010] According to one aspect of this disclosure, a GPU instruction execution apparatus is provided, comprising: a data acquisition module configured to acquire a first instruction to be executed by a first thread bundle and first register data, wherein the first register data is used to indicate the state of each thread in the first thread bundle under the execution of the first instruction, and each bit of the first register data corresponds one-to-one with each thread in the first thread bundle; a data arrangement module configured to traverse each bit of the first register data and rearrange the bits indicating that the thread state is valid to the front and close together to generate rearranged first register data; a data storage module configured to store the first operands required by the threads in the first thread bundle that are in a valid state to execute the first instruction into a first reserved stack based on the rearranged first register data; and a mapping table establishment module configured to establish a mapping table for recording the state of the first thread bundle. The program includes: a mapping between the rearranged and original thread numbers in each thread bundle; a first operation module configured to transfer a first operand from a first reserved stack to at least one first operation unit to execute a first operation corresponding to a first instruction; a result write-back module configured to write the operation result output by at least one first operation unit back to the target storage location corresponding to the thread in the first thread bundle that is valid before rearrangement, based on the mapping recorded in the mapping table; and a second operation module configured to, during the execution of the first operation, within the same clock cycle, in response to the second instruction being fetched and the second operand required to execute the second instruction being stored in a second reserved stack, transfer the second operand to at least one second operation unit to execute a second operation corresponding to the second instruction, wherein at least one second operation unit includes an unoccupied operation unit.

[0011] According to another aspect of this disclosure, a computer device is provided, comprising: at least one processor; and a memory having a computer program stored thereon, wherein the computer program, when executed by the at least one processor, causes the at least one processor to perform the methods provided above in this disclosure.

[0012] According to another aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0013] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, causes the processor to perform the methods provided above in this disclosure.

[0014] According to one or more embodiments of this disclosure, the effective utilization rate of computing units and instruction issuance efficiency can be improved by rearranging the threads in a thread bundle that are in an active state to free up idle computing units for use by other instructions.

[0015] These and other aspects of this disclosure will be apparent from the embodiments described below, and will be elucidated with reference to the embodiments described below. Attached Figure Description

[0016] The accompanying drawings exemplify embodiments and form part of the specification, serving together with the textual description to explain exemplary implementations of the embodiments. The illustrated embodiments are for illustrative purposes only and do not limit the scope of this disclosure. Throughout the drawings, the same reference numerals refer to similar but not necessarily identical elements.

[0017] Figure 1 This is a flowchart illustrating a GPU instruction execution method according to an exemplary embodiment.

[0018] Figure 2 This is a schematic diagram illustrating the generation of rearranged first register data according to an exemplary embodiment.

[0019] Figure 3 This diagram illustrates the allocation of computing units in a scenario where the effective thread ratio is extremely high, according to an exemplary embodiment.

[0020] Figure 4 This is a schematic diagram illustrating the writing of operation results based on a mapping table according to an exemplary embodiment.

[0021] Figure 5 This is a schematic diagram illustrating the collaborative relationship between modules according to an exemplary embodiment.

[0022] Figure 6 This is a schematic block diagram illustrating a GPU instruction execution apparatus according to an exemplary embodiment.

[0023] Figure 7 An example configuration of a computer device that can be used to implement the methods described herein is shown. Detailed Implementation

[0024] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0025] In this disclosure, unless otherwise stated, the use of terms such as "first," "second," etc., to describe various elements is not intended to limit the positional, temporal, or importance relationships of these elements; such terms are merely used to distinguish one element from another. In some examples, the first element and the second element may refer to the same instance of that element, while in other cases, based on the context, they may refer to different instances.

[0026] The terminology used in the description of the various examples described in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context explicitly indicates otherwise, an element may be one or more unless the number of elements is specifically limited. As used herein, the term "multiple" means two or more, and the term "based on" should be interpreted as "at least partially based on". Furthermore, the terms "and / or" and "at least one of..." cover any one of the listed items and all possible combinations thereof.

[0027] In related technologies, mainstream GPUs are based on the SIMT architecture, using thread bundles as the basic execution unit. Multiple threads within a thread bundle execute the same instruction within the same clock cycle. When the program executes an instruction containing branching logic, the GPU uses a predicate execution mechanism to handle branching. A predicate register marks the valid or invalid state of each thread within the thread bundle. After computation, only the results of valid threads are written back to the register, while the results of invalid threads are discarded. However, this predicate execution mechanism suffers from wasted computational resources and low instruction issuance efficiency.

[0028] First, the predicate execution mechanism can only filter the results of invalid threads during the write-back phase; it cannot prevent invalid threads from participating in the complete instruction execution process. Invalid threads still occupy the computational resources of the arithmetic unit and reserve stack storage space, consuming the same hardware resources as valid threads but producing no effective output. This causes the effective utilization rate of the arithmetic unit to decrease significantly as the proportion of invalid threads increases.

[0029] Secondly, since all computational units within the same thread bundle must execute the same instructions within the same clock cycle, when some threads become invalid, the computational units occupied by these invalid threads cannot be allocated by the scheduler to other ready instructions, resulting in idle computational units waiting. In branch-intensive application scenarios, the proportion of effective threads within a thread bundle will be reduced, and a large number of computational units will be performing invalid operations, affecting the parallel computing performance and overall computing power utilization of the GPU.

[0030] To address this, embodiments of this disclosure propose a more efficient GPU instruction execution method. By rearranging the threads within a thread bundle based on the state of the first register data before instruction execution, effective threads are aggregated and occupy only the required number of computational units. Simultaneously, a mapping table is established to ensure that the computation results can be accurately written back to the storage location corresponding to the original thread. This reduces the occupation of computational resources by invalid threads and allows the freed-up computational units to be made available for other ready instructions to be executed in parallel within the same clock cycle. Thus, without increasing the number of hardware computational units, the effective computation volume completed per unit time is increased, thereby improving the effective utilization rate of the GPU's computational units and the instruction issuance efficiency in branch instruction scenarios.

[0031] Figure 1 This is a flowchart illustrating a GPU instruction execution method according to an exemplary embodiment.

[0032] like Figure 1 As shown, the GPU instruction execution method includes steps S101 to S107.

[0033] In step S101, the first instruction to be executed by the first thread bundle and the first register data are obtained. The first register data is used to indicate the state of each thread in the first thread bundle when executing the first instruction. Each bit of the first register data corresponds one-to-one with each thread in the first thread bundle.

[0034] In the example, when the GPU instruction scheduling unit prepares to launch a task, it first obtains the first instruction to be executed by the first thread bundle and the corresponding first register data. The first register data can be a predicate register, whose bit width is the same as the number of threads in the thread bundle. For example, a thread bundle containing 32 threads corresponds to 32 bits of first register data, where each bit corresponds one-to-one with a thread, indicating the thread's status when executing the current instruction. A value of 1 indicates that the thread is a valid thread and needs to participate in the instruction's computation; a value of 0 indicates that the thread is an invalid thread and does not need to participate in the computation. For example, when processing branch instructions, the bit of even-numbered threads can be set to 1, and the bit of odd-numbered threads can be set to 0, resulting in 32 bits of first register data of 0x5555_5555. By obtaining this register data, subsequent steps can determine which threads actually need to occupy computational resources, providing a basis for rearranging operations and grouping execution.

[0035] In step S102, each bit of the first register data is traversed, and the bits indicating that the thread status is valid are rearranged to the front and arranged closely together to generate the rearranged first register data.

[0036] In the example, after obtaining the first register data, each bit of the data can be iterated through. Bits with a value of 1 (i.e., the bits corresponding to threads with a valid state) are moved sequentially to the front of the data. For example, starting from bit 0, the data is iterated bit by bit. Each time a bit with a value of 1 is encountered, it is moved to the currently available frontmost empty position. For instance, if bit 0 is "1", it is placed in the position of bit 0; if bit 1 is "0", it is skipped; if bit 2 is "1", it is placed in the position of bit 1; if bit 3 is "0", it is skipped; if bit 4 is "1", it is placed in the position of bit 2, and so on, until all bits have been iterated through. After the iteration is complete, all bits with a value of 1 are sequentially filled into the front positions and are adjacent to each other, while all bits with a value of 0 are moved to the back positions, thus generating a rearranged set of register data. During the rearrangement process, the operands of the threads corresponding to each bit also move synchronously with the bit, maintaining a one-to-one correspondence between bits and operands. Taking the 32-bit first register data 0x5555_5555 as an example, after rearranging, the first 16 bits are all 1s and the last 16 bits are all 0s, becoming 0xFFFF_0000. The purpose of this step is to gather the valid threads scattered in various locations together, so that the operands corresponding to the valid threads can be loaded onto the reserved stack and sent to the arithmetic unit in subsequent processes, while the operands of invalid threads do not need to be read and processed, which can reduce the consumption of computing resources by invalid threads.

[0037] In step S103, based on the rearranged first register data, the first operands required for the thread in the first thread bundle that is in a valid state to execute the first instruction are stored in the first reserved stack.

[0038] In the example, after the rearrangement, the bits with a value of 1 in the rearranged register data are concentrated at the front. The threads corresponding to these bits are the threads whose status is valid and need to actually participate in the operation. The first operand can refer to the data needed by the arithmetic unit when executing the first instruction. At this time, the first operands required by these threads with valid status to execute the current instruction are read and stored in the reserved stack, waiting to be dispatched to the arithmetic unit for execution. The operands of invalid threads are not read, and their corresponding reserved stacks are not loaded with data. Taking the 32-bit first register data 0x5555_5555 as an example, after rearrangement it becomes 0xFFFF_0000. Then the first 16 bits are valid bits, corresponding to the data volume of 2 SIMD8 subgroups (containing 8 threads in the single instruction multiple data execution subgroup). Therefore, only the first operands of these 16 threads with valid status need to be stored in the 2 reserved stacks respectively, and the remaining reserved stacks remain empty.

[0039] In step S104, a mapping table is established to record the correspondence between the rearranged number of each thread in the first thread bundle and the original number before rearrangement.

[0040] In the example, while performing the rearrangement operation, a mapping table can be established to record the correspondence between the thread numbers before and after the rearrangement. Since the rearrangement changes the thread order, the thread corresponding to the i-th position in the rearranged first register data may not be the original thread numbered i. Therefore, a mapping table is needed to record which original thread number corresponds to the i-th position in the rearranged first register data. For example, still using the 32-bit first register data 0x5555_5555 as an example, after rearrangement it becomes 0xFFFF_0000. Then it's necessary to record that the thread numbered 0 after rearrangement corresponds to the original thread numbered 0, the thread numbered 1 after rearrangement corresponds to the original thread numbered 2, the thread numbered 2 after rearrangement corresponds to the original thread numbered 4, and so on. Because the operation results are generated according to the rearranged order, a mapping table is necessary to accurately write each result back to its original thread number's target storage location, ensuring the correctness of the execution results.

[0041] In step S105, the first operand in the first reserved stack is transferred to at least one first arithmetic unit to execute the first operation corresponding to the first instruction.

[0042] In the example, once the first operands of valid threads in the reserved stack are loaded and ready, the instruction scheduler transmits these operands to the corresponding arithmetic units via the dispatcher to execute the operation specified by the current instruction. Since the thread status is only partially represented in the reserved stack after the rearrangement, the actual number of arithmetic units required is less than the total number of arithmetic units corresponding to a single thread bundle. For example, if 16 out of 32 threads are valid, corresponding to two SIMD8 subgroups, the rearrangement occupies only two reserved stacks. The operations of all valid threads can be completed by transmitting the operands from these two reserved stacks to two arithmetic units, instead of requiring all four arithmetic units as in the traditional architecture. After receiving the operands, the two arithmetic units perform the first operation specified by the first instruction, such as floating-point addition, in parallel on the data of each group of eight threads and output the result.

[0043] In step S106, based on the correspondence recorded in the mapping table, the operation result output by at least one first operation unit is written back to the target storage location corresponding to the thread whose state is valid in the first thread bundle before rearrangement.

[0044] In the example, after the arithmetic unit completes its operation, it needs to write the results back to the target storage location corresponding to each thread with a valid state in the storage device. Since the arithmetic unit processes operands corresponding to threads with valid states after rearrangement, the order of the thread numbers corresponding to the output results is not consistent with the original thread numbers before rearrangement. If the results are directly written back to the register file in the output order, it will result in the wrong thread's storage address. Therefore, during the write-back, a mapping table needs to be consulted. Based on the correspondence between the rearranged thread numbers and the original thread numbers before rearrangement, each operation result is transferred to the correct target storage location. For example, the operation result of thread number 1 after rearrangement, after consulting the mapping table, indicates that its corresponding original thread number is 2. Therefore, this result is written to the target storage location corresponding to the original thread number 2.

[0045] In step S107, during the execution of the first operation, within the same clock cycle, in response to the second instruction being fetched and the second operand required to execute the second instruction being stored in the second reserved stack, the second operand is transferred to at least one second operation unit to execute the second operation corresponding to the second instruction, wherein at least one second operation unit includes an unoccupied operation unit.

[0046] In the example, while the first instruction of the current thread bundle is executing its first operation using a portion of the arithmetic units, the instruction scheduler can detect that some arithmetic units remain idle. If, at this time, the second operand of another instruction (i.e., the second instruction) is already loaded and ready in another reserved stack (i.e., the second reserved stack), the instruction scheduler can transfer the second operand from the second reserved stack to an idle arithmetic unit via the dispatcher within the same clock cycle, executing the operation corresponding to the second instruction. The second instruction can come from another pending instruction within the same thread bundle, or from an instruction in another thread bundle, provided that its operand is ready and there are idle arithmetic units available. For example, after the rearrangement operation, only 16 threads in the thread bundle corresponding to the current first instruction are in a valid state, occupying 2 arithmetic units and the corresponding 2 reserved stacks, leaving the remaining 2 arithmetic units idle. If, at this time, all threads in the other thread bundle corresponding to the other instruction have also been rearranged and 16 threads are in a valid state, and their operands have been loaded into the other two reserved stacks, then the instruction scheduler can transfer the operands in these two reserved stacks to the two idle arithmetic units, so that the operations corresponding to the two instructions can be executed within the same clock cycle. Through this mechanism, arithmetic units that were originally idle due to invalid threads in the traditional architecture can execute other valid operations within the same clock cycle, allowing the operations of the two instructions to be performed simultaneously in time.

[0047] Therefore, by rearranging and aggregating the valid bits in the first register data, threads with valid states occupy a portion of the arithmetic units and reserve the stack, while invalid threads do not consume computational resources. Simultaneously, a mapping table records the correspondence between the thread numbers before and after the rearrangement, ensuring that the results are accurately written back to the original thread's target storage location after computation. Based on this, the instruction scheduler can allocate the idle arithmetic units after rearrangement to other ready instructions for execution within the same clock cycle, achieving instruction dual-issue. This fully utilizes the arithmetic units that were previously idle due to invalid threads, improving the effective utilization rate of the arithmetic units and the instruction issuance efficiency.

[0048] Figure 2 This is a schematic diagram illustrating the generation of rearranged first register data according to an exemplary embodiment.

[0049] like Figure 2As shown, the first stage represents the original state before rearrangement. A thread bundle contains 32 threads, represented by white squares numbered "T0-T31". These 32 threads are divided into four SIMD8 subgroups, from left to right: T0-T7, T8-T15, T16-T23, and T24-T31. d0-d31 represent the first operands corresponding to each thread, each corresponding to a thread number. In the diagram, "1" or "0" represents the data in the first register, also corresponding to a thread number; "1" indicates the thread is valid, and "0" indicates the thread is invalid. The second stage is the internal rearrangement stage within each SIMD8 subgroup. Within each SIMD8 subgroup, bits with a value of 1 and their corresponding operands in the first register data are moved to the first four positions of that subgroup, while bits with a value of 0 and their corresponding operands are moved to the last four positions. Taking the first subgroup as an example, if the data in the first register changes from 10101010 to 11110000, the corresponding first operand order is d0, d1, d2, d3, d4, d5, d6, d7. After rearrangement, it becomes d0, d2, d4, d6, d1, d3, d5, d7. The other three subgroups perform the same internal rearrangement operation, with the first four bits representing valid threads and the last four bits representing invalid threads. In the third stage, the valid threads in the first half of each of the four subgroups are arranged across subgroups to the front. The first four significant bits (1111) of the first subgroup and the first four significant bits (1111) of the second subgroup are arranged into a complete set of eight significant bits (11111111), with the corresponding first operands being d0, d2, d4, d6, d8, d10, d12, and d14. The first four significant bits (1111) of the third subgroup and the first four significant bits (1111) of the fourth subgroup are arranged into another complete set of eight significant bits (11111111), with the corresponding first operands being d16, d18, d20, d22, d24, d26, d28, and d30. Meanwhile, the invalid threads in the latter half of each subgroup are also arranged into two groups. After rearrangement, the first two groups consist entirely of threads in a valid state. Their corresponding first operands are transferred to the two first arithmetic units (ALUs) marked below for execution: d0, d2, d4, d6, d8, d10, d12, and d14 are transferred to ALU 1, and d16, d18, d20, d22, d24, d26, d28, and d30 are transferred to ALU 2. Since the latter two groups are invalid threads, they do not transfer operands to ALUs, and their corresponding ALUs are idle and can be allocated to other instructions.

[0050] Figure 3 This diagram illustrates the allocation of computing units in a scenario where the effective thread ratio is extremely high, according to an exemplary embodiment.

[0051] like Figure 3 As shown, a single thread bundle contains 32 threads, represented by white squares numbered "T0-T31". These 32 threads are divided into four SIMD8 subgroups. The data represented by "1" or "0" in the diagram corresponds to the first register data, with each subgroup numbered one-to-one. "1" indicates the corresponding thread is active, and "0" indicates the corresponding thread is inactive. This architecture has four arithmetic units: Arithmetic Unit 1, Arithmetic Unit 2, Arithmetic Unit 3, and Arithmetic Unit 4. Currently, three thread bundles reside (Thread Bundle 1, Thread Bundle 2, and Thread Bundle 3), all executing the same code containing if-else branch logic. In this scenario, 31 threads in each thread bundle satisfy the if condition (state 1), and only one thread satisfies the else condition (state 0), resulting in the 32-bit first register data being 0xFFFF_FFFE. Therefore, each thread bundle needs to execute two instructions (instruction 1 for the if branch and instruction 2 for the else branch), for a total of six instructions across the three thread bundles.

[0052] In this extreme case of a very high percentage of active threads, for instruction 1, each thread bundle has 31 active threads. Dividing these into groups of 8 threads requires 4 computation units (31 / 8 rounded up to 4). The first 3 computation units each handle 8 active threads, and the 4th unit handles 7 active threads and 1 inactive thread. Since all 4 computation units are occupied, instruction 1 cannot free up any computation units after rearrangement. For instruction 2, each thread bundle has only 1 active thread. After rearrangement, this active thread only needs to occupy 1 computation unit. Therefore, the execution process is as follows: In the first clock cycle, instruction 1 from thread bundle 1 is issued to all 4 computation units for execution, with 31 active threads occupying all units; in the second clock cycle, instruction 1 from thread bundle 2 is issued to all 4 computation units for execution, again with 31 active threads occupying all units; in the third clock cycle, instruction 1 from thread bundle 3 is issued to all 4 computation units for execution, again with 31 active threads occupying all units. In the fourth clock cycle, each of the two instructions, thread bundle 1 and thread bundle 2, has only one active thread and requires only one execution unit. Based on instruction dual-spreading (two instructions can be executed within the same clock cycle), the instruction scheduler can simultaneously issue these two instructions to two execution units for execution. That is, it can issue instruction 2 from thread bundle 1 to execution unit 3 and instruction 2 from thread bundle 2 to execution unit 4 within the same cycle. In the fifth clock cycle, instruction 2 from thread bundle 3 is issued to execution unit 4. Thus, all six instructions are executed within five clock cycles, significantly improving the execution efficiency of the computing units compared to the traditional architecture where six instructions require six clock cycles.

[0053] In some embodiments, storing the first operand required for a thread in the first thread bundle to execute a first instruction into a first reserved stack based on the rearranged first register data includes: reading the first operand required for a thread in the first thread bundle to execute a first instruction from the original register module based on the rearranged first register data; and storing the first operand into the first reserved stack.

[0054] In the example, after the rearrangement operation, the bits indicating validity (1) in the rearranged first register data are concentrated at the front. Based on this, the threads whose states are valid and their corresponding first operands can be determined. The original register module can refer to the hardware storage structure that stores the general-purpose register data of each thread in the thread bundle. Each thread has its own independent storage area, meaning each thread can read its corresponding operand from the original register module. When reading the first operand, for the threads corresponding to the bits with a value of 1 in the rearranged first register data, the first operands required by these threads to execute the current instruction are read from the original register module. After reading, the first operands of these valid threads are stored in the reserved stack, awaiting dispatch to the arithmetic unit for execution.

[0055] Therefore, by limiting the reading range of the first operand to threads with a valid state, the access bandwidth pressure and power consumption of the register file are reduced, while the amount of reserved stack space is also reduced, providing a basis for allocating idle computing resources to other instructions in the future.

[0056] In some embodiments, the raw register module includes a register file module and a source data cache module. The register file module consists of multiple independently addressed memory banks, and the source data cache module is used to cache data read from the register file module.

[0057] In the example, the raw register module can include a register file module and a source data cache module in hardware, and may also include other storage devices. The register file module is the main storage structure for storing thread operands, consisting of multiple independently addressed memory banks, each of which can be accessed independently for reading and writing. This multi-memory bank design allows operands from multiple threads to be read in parallel within the same clock cycle, thus matching the operand requirements of the arithmetic unit. The source data cache module can be placed in the register read path, and its function is specifically configured to temporarily cache data that has been successfully read from the register file module in previous execution cycles. When the same data needs to be read again subsequently, it can be directly retrieved from the source data cache module without repeatedly accessing the register file module.

[0058] In the example, when an instruction needs to read multiple source operands, these operands may be distributed across different memory banks in the register file module, or they may happen to be mapped to the same memory bank. Since each memory bank only supports one read operation per clock cycle, if the addresses of two or more operands are mapped to the same memory bank, a memory bank conflict will occur, preventing these operands from being read simultaneously in the same cycle. They must be read sequentially over multiple cycles. Therefore, a source data cache module can be introduced. When an operand is read from the register file module for the first time, the data is simultaneously written to the source data cache module for caching. Subsequently, if another operand to be read later happens to be located in the same memory bank and conflicts with the cached data, the cached operand can be read from the source data cache module, while the other operand is read from the register file module. The two reads use different data paths and do not conflict with each other.

[0059] Therefore, by introducing a source data caching module, it is possible to complete the reading of all required operands within a single clock cycle, avoiding additional waiting cycles caused by memory conflicts.

[0060] In some embodiments, the first operand includes at least two operands. Reading the first operand required by a thread in a first thread bundle that is in a valid state to execute a first instruction from the original register module includes: reading the required first operand from the source data cache module and the register file module respectively in response to determining that the addresses of at least two operands in the first operand are mapped to the same memory bank in a plurality of independently addressed memory banks; and reading the required first operand from the register file module in response to determining that the addresses of all operands in the first operand are mapped to different memory banks in a plurality of independently addressed memory banks.

[0061] In the example, an instruction typically requires multiple operands for computation; for instance, a floating-point multiply-accumulate instruction requires three operands. When reading these operands from the raw register module, the first step is to determine which memory banks in the register file module each operand's address maps to. When all operand addresses map to different memory banks, since each memory bank can be read independently, all operands can be read directly from the register file module in parallel within the same clock cycle. When at least two operand addresses map to the same memory bank, these operands cannot be read from the register file module simultaneously because a single memory bank can only be read once per cycle. In this case, since the source data cache module contains historical data read from the register file module, one operand can be read from the register file module, and the other operand from the source data cache module. These two read paths operate in parallel, ensuring that all operands can still be read within the same clock cycle, thus avoiding memory bank conflicts.

[0062] Therefore, by reading operands from the source data cache module and the register file module respectively when a memory conflict occurs, the waiting caused by multiple operands being mapped to the same memory bank is avoided, thereby improving read efficiency.

[0063] In some embodiments, the result of the first operation after execution includes at least one sub-operation result, each sub-operation result corresponding one-to-one with a thread in the first thread bundle that is in a valid state. Based on the correspondence recorded in the mapping table, the operation result output by at least one first operation unit is written back to the target storage location corresponding to the thread in the first thread bundle that is in a valid state before the rearrangement. This includes: based on the number of each thread in the first thread bundle that is in a valid state after the rearrangement, looking up the mapping table to determine the original number of each thread in the first thread bundle that is in a valid state before the rearrangement; determining the target storage location to be written back for each sub-operation result based on the original number; and writing each sub-operation result into the corresponding target storage location.

[0064] In the example, after the arithmetic unit completes its operation, each thread whose status is valid during the operation can generate a sub-operation result. Since the rearrangement operation changes the order of thread numbers, the write-back phase needs to use a mapping table to restore the correct correspondence between each sub-operation result and the original thread.

[0065] In the example, for each thread with a valid state, the thread's number after rearrangement is first obtained. This number is then used as an index to look up the mapping table and retrieve the thread's original number before rearrangement. Once the original number is obtained, the target storage location corresponding to that original number can be determined, and the sub-operation result is then written to that location. For example, for the thread with a rearranged number of 1, looking up the mapping table reveals that its corresponding original number is 2. Therefore, the sub-operation result should be written back to the target storage location of the original thread with the number 2 in the storage device. By performing the above lookup and write-back operations on the sub-operation results of all valid threads one by one, it is ensured that each operation result accurately returns to the target storage location corresponding to its original thread, ensuring that the rearrangement operation does not affect the correctness of the program execution result.

[0066] Therefore, by looking up the mapping table based on the rearranged number to obtain the original number, and determining the target storage location based on the original number, the result of each sub-operation can be accurately written into the target storage location corresponding to the thread whose state is valid before the rearrangement.

[0067] Figure 4 This is a schematic diagram illustrating the writing of operation results based on a mapping table according to an exemplary embodiment.

[0068] like Figure 4 As shown, the upper part represents the original state of the thread bundle before rearrangement. A thread bundle contains 32 threads, represented by white squares labeled "T0-T31". The white squares T0-T31 represent the original thread numbers. These 32 threads are divided into four SIMD8 subgroups, from left to right: T0-T7, T8-T15, T16-T23, and T24-T31. The "1" or "0" in the diagram represents the data in the first register, corresponding one-to-one with the thread number. "1" indicates the corresponding thread is active, and "0" indicates the corresponding thread is inactive. The lower part represents the state after the rearrangement operation. The position of the original thread number changes with the rearrangement of the active bits in the first register data. The rearranged thread numbers are represented by gray squares T0-T31. Taking the first group as an example, the first 8 positions of the rearranged thread numbers are T0, T1, T2, T3, T4, T5, T6, and T7 (all valid threads), while the original thread numbers corresponding to these 8 positions are T0, T2, T4, T6, T8, T10, T12, and T14, respectively. The double-headed arrows indicate that during the write-back, the operation result of the rearranged thread number T0 is written back to the target storage location corresponding to the original thread number T0, the operation result of the rearranged thread number T1 is written back to the target storage location corresponding to the original thread number T2, the operation result of the rearranged thread number T2 is written back to the target storage location corresponding to the original thread number T4, and so on.

[0069] In some embodiments, before generating the rearranged first register data, the GPU instruction execution method further includes: counting bits in the first register data that indicate a valid thread state to obtain a total number of valid threads; and determining the number of at least one first arithmetic unit required to execute the first instruction based on the total number of valid threads and the maximum thread capacity of a single arithmetic unit, wherein the number of first arithmetic units is associated with the ratio of the total number of valid threads to the maximum thread capacity of a single arithmetic unit.

[0070] In the example, before performing the rearrangement operation, the bits representing the valid thread status in the first register data are counted to obtain the total number of valid threads in the thread bundle under the current instruction. After obtaining the total number of valid threads, this number is compared with the maximum number of threads that a single arithmetic unit can support to determine how many arithmetic units are actually needed to execute the current instruction. For example, in an architecture where each arithmetic unit supports 8 threads, if the total number of valid threads is 16, then 2 arithmetic units are needed; if the total number of valid threads is 24, then 3 arithmetic units are needed. The purpose of this step is to determine in advance the number of arithmetic units and the corresponding reserved stack size required in subsequent processes, so that subsequent steps such as operand loading and arithmetic unit allocation have a clear basis for resource allocation.

[0071] Therefore, by determining the number of first arithmetic units actually required to execute the first instruction based on the total number of threads in a valid state and the maximum thread capacity of a single arithmetic unit, it is possible to avoid allocating unnecessary computing resources to threads in an invalid state, so that idle arithmetic units can be used to concurrently execute the second operation corresponding to the second instruction within the same clock cycle.

[0072] Figure 5 This is a schematic diagram illustrating the collaborative relationship between modules according to an exemplary embodiment.

[0073] like Figure 5As shown, the instruction scheduling unit, as the control core of the entire architecture, first issues an instruction and simultaneously transfers the first register data of the thread bundle corresponding to the instruction to the thread / first operand rearrangement module. At the same time, the instruction scheduling unit controls the reading of the first operands required by each thread to execute the instruction from the register file, source data cache module, or other memory. The read first operands are synchronously cached in the source data cache module. When subsequent read operations encounter memory conflicts, the cached data can be directly retrieved from the source data cache module. The thread / first operand rearrangement module rearranges the first register data and operands according to the valid or invalid status of each bit in the first register data. Bits indicating valid thread status are arranged at the front, and the first operands corresponding to threads with valid status after rearrangement are stored in the corresponding reserved stack. Operands of invalid threads are not operated on. Since dual instruction issuance is supported, the number of reserved stacks is 8. After the operands in the reserved stacks are ready, the dispatcher transfers them to the corresponding arithmetic units for execution. Since threads with valid status only occupy a portion of the arithmetic units, the remaining free arithmetic units can be allocated by the instruction scheduling unit to other ready instructions. After the operation is completed, the result is written back to the target storage location corresponding to the thread whose state was valid before the rearrangement, according to the correspondence between the numbers before and after the rearrangement recorded in the mapping table, under the control of the instruction scheduling unit, or written to other memory as needed.

[0074] Embodiments of this disclosure also provide a GPU instruction execution apparatus.

[0075] Figure 6 This is a schematic block diagram illustrating a GPU instruction execution device 600 according to an exemplary embodiment.

[0076] In some embodiments, the GPU instruction execution device 600 may include a data acquisition module 601, a data arrangement module 602, a data storage module 603, a mapping table establishment module 604, a first operation module 605, a result write-back module 606, and a second operation module 607.

[0077] The data acquisition module 601 is configured to acquire the first instruction to be executed by the first thread bundle and the first register data, wherein the first register data is used to indicate the state of each thread in the first thread bundle when executing the first instruction, and each bit of the first register data corresponds one-to-one with each thread in the first thread bundle.

[0078] The data arrangement module 602 is configured to traverse each bit of the first register data and rearrange the bits indicating that the thread status is valid to the front and close together to generate the rearranged first register data.

[0079] The data storage module 603 is configured to store the first operands required for the thread in the first thread bundle to execute the first instruction into the first reserved stack based on the rearranged first register data.

[0080] The mapping table creation module 604 is configured to create a mapping table that records the correspondence between the rearranged numbers of each thread in the first thread bundle and the original numbers before rearrangement.

[0081] The first arithmetic module 605 is configured to transfer a first operand from a first reserved stack to at least one first arithmetic unit to execute a first arithmetic operation corresponding to a first instruction.

[0082] The write-back module 606 is configured to write the operation result output by at least one first operation unit back to the target storage location corresponding to the thread whose state is valid in the first thread bundle before rearrangement, based on the correspondence recorded in the mapping table.

[0083] The second arithmetic module 607 is configured to, during the execution of the first arithmetic operation, within the same clock cycle, in response to the second instruction being acquired and the second operand required to execute the second instruction being stored in the second reserved stack, transfer the second operand to at least one second arithmetic unit to execute the second arithmetic operation corresponding to the second instruction, wherein the at least one second arithmetic unit includes an unoccupied arithmetic unit.

[0084] It should be understood that Figure 6 The data acquisition module 601, data arrangement module 602, data storage module 603, mapping table creation module 604, first operation module 605, result write-back module 606, and second operation module 607 shown can respectively correspond to the following... Figure 1 The operations of steps S101, S102, S103, S104, S105, S106, and S107 are shown. Therefore, the details of each aspect will not be elaborated here.

[0085] In some embodiments, the data storage module 603 may include a data reading module 6031 and a data writing module 6032. The data reading module 6031 may be configured to read, based on rearranged first register data, the first operand required for a thread in the first thread bundle to execute a first instruction from the original register module. The data writing module 6032 may be configured to store the first operand into a first reserved stack.

[0086] In some embodiments, the data reading module 6031 may include a first reading module 6031a and a second reading module 6031b. The first reading module 6031a may be configured to read the required first operands from the source data cache module and the register file module respectively, in response to determining that the addresses of at least two operands in the first operands are mapped to the same memory bank among multiple independently addressed memory banks. The second reading module 6031b may be configured to read the required first operands from the register file module in response to determining that the addresses of all operands in the first operands are mapped to different memory banks among multiple independently addressed memory banks.

[0087] In some embodiments, the result of the first operation includes at least one sub-operation result, each sub-operation result corresponding one-to-one with a thread in the first thread bundle that is in a valid state. The result write-back module 606 may include a number lookup module 6061, a location determination module 6062, and a result writing module 6063. The number lookup module 6061 may be configured to look up a mapping table based on the rearranged number of each thread in the first thread bundle that is in a valid state before rearrangement to determine the original number of each thread in the first thread bundle that is in a valid state before rearrangement. The location determination module 6062 may be configured to determine the target storage location to be written back for each sub-operation result based on the original number. The result writing module 6063 may be configured to write each sub-operation result to the corresponding target storage location.

[0088] In some embodiments, before generating the rearranged first register data, the GPU instruction execution method further includes a thread determination module 608 and a unit determination module 609. The thread determination module 608 can be configured to count bits in the first register data that indicate a valid thread state to obtain the total number of valid threads. The unit determination module 609 can be configured to determine the number of at least one first arithmetic unit required to execute the first instruction based on the total number of valid threads and the maximum thread capacity of a single arithmetic unit, wherein the number of first arithmetic units is associated with the ratio of the total number of valid threads to the maximum thread capacity of a single arithmetic unit.

[0089] While specific functions have been discussed above with reference to specific modules, it should be noted that the functions of the modules discussed herein can be divided into multiple modules, and / or at least some functions of multiple modules can be combined into a single module. The specific actions performed by the modules discussed herein include the specific module itself performing the action, or alternatively, the specific module calling or otherwise accessing another component or module that performs the action (or performs the action in conjunction with the specific module). Therefore, a specific module performing an action can include the specific module performing the action itself and / or another module that performs the action, called or otherwise accessed by the specific module.

[0090] It should also be understood that the above regarding Figure 6 The described modules can be implemented in hardware or in hardware in combination with software and / or firmware. For example, these modules can be implemented as computer program code / instructions configured to execute in one or more processors and stored in a computer-readable storage medium. Alternatively, these modules can be implemented as hardware logic / circuit. For example, these modules can be implemented together in a System on Chip (SoC). An SoC may include an integrated circuit chip (which includes one or more components in a processor (e.g., a Central Processing Unit (CPU), microcontroller, microprocessor, digital signal processor (DSP), etc.), memory, one or more communication interfaces, and / or other circuitry) and may optionally execute received program code and / or include embedded firmware to perform functions.

[0091] According to one aspect of this disclosure, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0092] According to one aspect of this disclosure, a non-transitory computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0093] According to one aspect of this disclosure, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above.

[0094] In the following text, combined with Figure 7 Illustrative examples describing such computer devices, non-transitory computer-readable storage media, and computer program products.

[0095] Figure 7 An example configuration of a computer device 700 that can be used to implement the methods described herein is shown.

[0096] Computer device 700 can be a variety of different types of devices. Examples of computer device 700 include, but are not limited to: desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablet computers, cellular or other wireless phones (e.g., smartphones), notebook computers, mobile stations), wearable devices (e.g., glasses, watches), entertainment devices (e.g., entertainment appliances, set-top boxes communicatively coupled to a display device, game consoles), televisions or other display devices, automotive computers, and so on.

[0097] Computer device 700 may include at least one processor 702, memory 704, communication interfaces(s) 706, display device 708, other I / O devices 710, and one or more mass storage devices 712 capable of communicating with each other, such as via system bus 714 or other suitable connections.

[0098] Processor 702 may be a single processing unit or multiple processing units, and all processing units may include single or multiple computing units or multiple cores. Processor 702 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operating instructions. Among other capabilities, processor 702 may be configured to acquire and execute computer-readable instructions stored in memory 704, mass storage device 712, or other computer-readable media, such as program code of operating system 716, program code of application program 718, program code of other program 720, etc.

[0099] Memory 704 and mass storage device 712 are examples of computer-readable storage media for storing instructions that are executed by processor 702 to perform the various functions described above. For example, memory 704 can generally include both volatile and non-volatile memory (e.g., RAM, ROM, etc.). Furthermore, mass storage device 712 can generally include hard disk drives, solid-state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CDs, DVDs), storage arrays, network-attached storage, storage area networks, etc. Both memory 704 and mass storage device 712 can be collectively referred to herein as memory or computer-readable storage media, and can be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code, which can be executed by processor 702 as a specific machine configured to perform the operations and functions described in the examples herein.

[0100] Multiple programs may be stored on mass storage device 712. These programs include operating system 716, one or more application programs 718, other programs 720, and program data 722, and they may be loaded into memory 704 for execution. Examples of such application programs or program modules may include computer program logic (e.g., computer program code or instructions) of the methods described herein and / or other embodiments described herein.

[0101] Although Figure 7 The data is illustrated as being stored in memory 704 of computer device 700, but the operating system 716, application program 718, other programs 720, and program data 722, or portions thereof, may be implemented using any form of computer-readable medium accessible by computer device 700. As used herein, "computer-readable medium" includes at least two types of computer-readable media: computer-readable storage media and communication media.

[0102] Computer-readable storage media include volatile and non-volatile, removable and non-removable media implemented by any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, DVD, or other optical storage devices, magnetic cassettes, magnetic tapes, disk storage devices or other magnetic storage devices, or any other non-transmission medium that can be used to store information for access by computer devices. In contrast, communication media can embody computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms. Computer-readable storage media as defined herein do not include communication media.

[0103] One or more communication interfaces 706 are used for exchanging data with other devices, such as via a network, direct connection, etc. Such communication interfaces can be one or more of the following: any type of network interface (e.g., a network interface card (NIC)), wired or wireless (such as IEEE 802.11 Wireless LAN (WLAN)) wireless interface, Wi-MAX interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth. TMInterfaces include near field communication (NFC) interfaces. Communication interface 706 facilitates communication across various network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. Communication interface 706 can also provide communication with external storage devices (not shown) such as storage arrays, network-attached storage, storage area networks, etc.

[0104] In some examples, a display device 708, such as a monitor, may be included for displaying information and images to the user. Other I / O devices 710 may be devices that receive various inputs from the user and provide various outputs to the user, and may include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, and so on.

[0105] The technologies described herein can be supported by these various configurations of computer device 700, and are not limited to specific examples of the technologies described herein. For example, the functionality can also be implemented wholly or partially on a “cloud” using a distributed system. A cloud includes and / or represents a platform for resources. The platform abstracts the underlying functionality of the cloud’s hardware (e.g., servers) and software resources. Resources may include applications and / or data that can be used when performing computational processing on a server remote from computer device 700. Resources may also include services provided via the Internet and / or via subscriber networks such as cellular or Wi-Fi networks. The platform can abstract resources and functionality to connect computer device 700 to other computer devices. Therefore, the implementation of the functionality described herein can be distributed throughout the cloud. For example, the functionality can be implemented partly on computer device 700 and partly through a platform that abstracts the functionality of the cloud.

Claims

1. A GPU instruction execution method, characterized in that, The method includes: Obtain the first instruction to be executed by the first thread bundle and the first register data, wherein the first register data is used to indicate the state of each thread in the first thread bundle when executing the first instruction, and each bit of the first register data corresponds one-to-one with each thread in the first thread bundle; Iterate through each bit of the first register data, rearrange the bits that indicate the thread status as valid to the front and close together to generate the rearranged first register data; Based on the rearranged first register data, the first operands required for the thread in the first thread bundle that is in a valid state to execute the first instruction are stored in the first reserved stack; Establish a mapping table, which is used to record the correspondence between the rearranged number of each thread in the first thread bundle and the original number before rearrangement; The first operand in the first reserved stack is transferred to at least one first arithmetic unit to execute the first operation corresponding to the first instruction; Based on the correspondence recorded in the mapping table, the operation results output by at least one first operation unit are written back to the target storage location corresponding to the thread whose state is valid in the first thread bundle before rearrangement; and During the execution of the first operation, within the same clock cycle, in response to the second instruction being fetched and the second operand required to execute the second instruction being stored in the second reserved stack, the second operand is transferred to at least one second operation unit to execute the second operation corresponding to the second instruction, wherein the at least one second operation unit includes an unoccupied operation unit.

2. The method according to claim 1, characterized in that, The step of storing the first operands required for the threads in the first thread bundle that are in a valid state to execute the first instruction into the first reserved stack based on the rearranged first register data includes: Based on the rearranged first register data, the first operand required for the thread in the first thread bundle that is in a valid state to execute the first instruction is read from the original register module; and Store the first operand into the first reserved stack.

3. The method according to claim 2, characterized in that, The original register module includes a register file module and a source data cache module. The register file module consists of multiple independently addressed memory banks, and the source data cache module is used to cache data read from the register file module.

4. The method according to claim 3, characterized in that, The first operand includes at least two operands. Reading the first operand required for the thread in the first thread bundle that is in a valid state to execute the first instruction from the original register module includes: In response to determining that at least two of the first operands have addresses mapped to the same memory bank among the plurality of independently addressed memory banks, the required first operands are read from the source data cache module and the register file module, respectively; and In response to determining that the addresses of all operands in the first operand are respectively mapped to different memory banks in the plurality of independently addressed memory banks, the required first operand is read from the register file module.

5. The method according to claim 1, characterized in that, The result of the first operation includes at least one sub-operation result, each sub-operation result corresponding one-to-one with a thread in the first thread bundle that is in a valid state. The step of writing the operation result output by the at least one first operation unit back to the target storage location corresponding to the thread in the first thread bundle that is in a valid state before rearrangement, based on the correspondence recorded in the mapping table, includes: Based on the number of each thread in the first thread bundle that is in a valid state after rearrangement, the original number of each thread in the first thread bundle that is in a valid state before rearrangement is determined by looking up the mapping table. The target storage location for writing back the result of each sub-operation is determined based on the original number; and Write the result of each sub-operation to the corresponding target storage location.

6. The method according to any one of claims 1 to 5, characterized in that, Before generating the rearranged first register data, the method further includes: Count the bits in the first register data that indicate a valid thread status to obtain the total number of valid threads; and Based on the total number of effective threads and the maximum thread capacity of a single arithmetic unit, the number of at least one first arithmetic unit required to execute the first instruction is determined, wherein the number of the first arithmetic units is associated with the ratio of the total number of effective threads to the maximum thread capacity of a single arithmetic unit.

7. A GPU instruction execution device, characterized in that, The device includes: The data acquisition module is configured to acquire a first instruction to be executed by the first thread bundle and first register data, wherein the first register data is used to indicate the state of each thread in the first thread bundle when executing the first instruction, and each bit of the first register data corresponds one-to-one with each thread in the first thread bundle; The data arrangement module is configured to traverse each bit of the first register data and rearrange the bits indicating that the thread status is valid to the front and close together to generate the rearranged first register data. The data storage module is configured to store the first operands required for the thread in the first thread bundle that is in a valid state to execute the first instruction into the first reserved stack based on the rearranged first register data. The mapping table creation module is configured to create a mapping table, which is used to record the correspondence between the rearranged number of each thread in the first thread bundle and the original number before the rearrangement. The first arithmetic module is configured to transfer the first operand in the first reserved stack to at least one first arithmetic unit to execute the first arithmetic operation corresponding to the first instruction; The result write-back module is configured to, based on the correspondence recorded in the mapping table, write back the operation results output by at least one first operation unit to the target storage location corresponding to the thread whose state is valid in the first thread bundle before rearrangement; and The second arithmetic module is configured to, during the execution of the first arithmetic operation, within the same clock cycle, in response to the second instruction being acquired and the second operand required to execute the second instruction being stored in the second reserved stack, transfer the second operand to at least one second arithmetic unit to execute the second arithmetic operation corresponding to the second instruction, wherein the at least one second arithmetic unit includes an unoccupied arithmetic unit.

8. A computer device, characterized in that, The computer device includes: At least one processor; A memory having a computer program stored thereon, wherein, when executed by the at least one processor, the computer program causes the at least one processor to perform the method of any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, causes the processor to perform the method of any one of claims 1-6.

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