Chip computing power dynamic scheduling method based on proportional stress point

Abstract

The invention discloses a chip computing power dynamic scheduling method based on proportional stress points, and relates to the technical field of chip computing power optimization and integrated circuit control. According to the method, a proportion reference model between chip operation parameters is established, operation data such as load, frequency, power consumption and temperature are collected in real time, proportion stress points influencing system stability are identified, and dynamic allocation and scheduling of computing power resources are carried out on the basis of the proportion stress points. And when the operation proportion deviates from the safety interval, operations such as migration, frequency limiting and load convergence are automatically carried out on the multi-core computing power, so that the chip always works in the optimal proportion interval. According to the method, the power consumption fluctuation and the performance jitter can be reduced while the computing power efficiency is ensured, the service life of the chip is prolonged, and the method is suitable for real-time computing power scheduling of various general and special computing chips such as a CPU, a GPU and an NPU.

Description

1. Technical Field

[0001] This invention relates to the fields of chip computing power scheduling, integrated circuit control, and artificial intelligence computing power optimization. Specifically, it relates to a dynamic chip computing power scheduling method based on proportional stress points, which is applicable to load allocation, power consumption control, and performance scheduling of various computing chips such as CPUs, GPUs, NPUs, and ASICs. 2. Background Technology

[0002] Current chip computing power scheduling often employs fixed thresholds, fixed priorities, or average allocation modes, which can easily lead to the following problems under complex load scenarios: 1. Over-concentration of computing power allocation can cause localized overheating and power consumption spikes, while over-dispersion can result in overall low efficiency; 2. There is a lack of accurate identification of critical bottleneck nodes in the system, causing scheduling actions to lag behind load changes and resulting in untimely responses; 3. Traditional algorithms target "full load" or "fixed ratio," failing to consider the chip's stable range and critical stress points under different loads, which can easily lead to performance fluctuations, uncontrolled power consumption, or accelerated lifespan degradation. Existing technologies fail to identify critical stress points in the system from the underlying proportional relationships, making it difficult to achieve a dynamic optimal balance between performance, power consumption, and stability. 3. Summary of the Invention

[0003] This invention proposes a dynamic chip computing power scheduling method based on the principles of proportional philosophy and stress point identification. By collecting chip operating data in real time, it establishes a proportional model between computing power load, power consumption, temperature, and bandwidth, identifies proportional stress points, and achieves dynamic, adaptive, and low-jitter computing power allocation. The invention includes the following core steps: 1. Establishing a multi-dimensional operating parameter proportional benchmark model for the chip, including the proportional relationships between parameters such as core count, frequency, load rate, temperature, power consumption, and data throughput; 2. Real-time collection of current operating parameters, calculation of the deviation between the actual ratio and the benchmark ratio, and identification of proportional stress points, i.e., key proportional nodes that decisively affect the overall system stability and efficiency; 3. Dynamically allocating computing resources according to the stress point type: allocating computing power tilt to high-priority tasks and converging computing power for non-critical tasks to avoid overall proportional imbalance; 4. Setting a safe proportional range, automatically reducing frequency or limiting current when scheduling actions approach the critical ratio to prevent entering an unstable range; 5. Periodically updating the proportional model to adapt to scenarios such as chip aging, changes in ambient temperature, and task type switching to maintain long-term optimal scheduling performance. The beneficial effects of this invention are as follows: 1. It uses proportional stress points as the core scheduling basis, rather than simple average or full-load operation, which significantly improves the overall efficiency of the chip; 2. It dynamically responds to load changes, reduces power consumption waste and performance fluctuations, and extends the stable working life of the chip; 3. It is compatible with multi-core and heterogeneous chip architectures and can be widely used in mobile terminals, server terminals, edge computing and AI inference chips; 4. The scheduling logic is lightweight, with low computational overhead, does not occupy a lot of additional computing power, and is suitable for hardware-level real-time scheduling. 4. Detailed Implementation

[0004] 1. Upon chip power-on initialization, a preset proportional baseline is read, and an initial proportional model is established, including the normal operating proportional range, the warning proportional range, and the critical stress proportional threshold. 2. During operation, load, frequency, temperature, and power consumption data for each core are collected at fixed time slices, and normalized to form a real-time proportional vector. 3. The system compares the real-time proportional vector with the baseline model, calculates the deviation, and locates the current stress point: - If the load ratio of a certain core is too high, it is determined to be a computing power concentration stress point; - If the overall power consumption ratio exceeds the threshold, it is determined to be a power consumption over-limit stress point; - If the temperature rise rate does not match the load ratio, it is determined to be a heat dissipation imbalance stress point. 4. Scheduling strategies are executed according to the stress point type: - For computing power concentration stress points, some load is migrated to low-load cores to maintain a balanced multi-core ratio; - For power consumption over-limit stress points, the frequency of non-critical tasks is reduced proportionally to reduce total power consumption; - For heat dissipation imbalance stress points, priority is given to ensuring the computing power of critical modules, and the utilization rate of non-real-time tasks is limited. 5. After scheduling is complete, record the new running ratio, update the model weights, and achieve continuous iterative optimization.

Claims

1. A method for dynamic scheduling of chip computing power based on proportional stress points, characterized in that, The chip load is normalized to a continuous proportional value of [0,1], and the computing power resources are adaptively adjusted based on the stress points in the proportional range.

2. The method according to claim 1, characterized in that, The stress points include at least three levels of proportional thresholds: low-load stress points, balanced stress points, and high-load stress points.

3. The method according to claim 1, characterized in that, The scheduling includes: the number of computing cores enabled, operating frequency, operating voltage, data bandwidth, and power consumption mode.

4. The method according to claim 1, characterized in that, The computing power adjustment is smooth and continuous within the proportional range, without any abrupt changes.

5. An artificial intelligence chip, characterized in that, The computing power dynamic scheduling method based on proportional stress points as described in any one of claims 1-4 is adopted.