Register allocation method, computing device, storage medium and computer program product

Abstract

The embodiment of the invention provides a register allocation method, which is characterized in that when a weight is set for an edge in a target network, the weight is positively correlated with the distance between the edge and a key point, and the weight between nodes and the distance between a target position and the key point are simultaneously activated through explicit constraint of an energy function in iterative optimization. The target network can automatically arrange an overflow or reloading instruction at a code position closer to a key operation during iterative convergence, so that after the lifetime is segmented, the byreg interval is as short as possible, a physical register can be used by more variables, and the pressure of the physical register and the overflow instruction are reduced. In general, the register allocation method ensures that the finally determined target position not only can relieve physical register conflicts, but also can effectively reduce invalid register occupation time caused by the fact that an instruction insertion point is too far away from a key point, so that memory access overhead is reduced on the whole, and the utilization rate and execution performance of the register are improved.

Description

Technical Field

[0001] This specification relates to the field of computer application technology, specifically to compilation technology in the field of computer application technology, and more specifically to a register allocation method, computing device, storage medium, and computer program product. Background Technology

[0002] Register allocation is a key optimization step in the compiler backend. Its core task is to map virtual registers (virtual registers can be used to store variables, so in this process, virtual registers correspond to variables) in the program to a limited number of physical registers, minimizing the memory overflow overhead caused by insufficient physical registers, and thus improving execution efficiency.

[0003] When there are insufficient available physical registers, the compiler needs to temporarily store some variables in memory. This process is called spilling. When a variable spills into memory, the program can only read it from memory to use it, which greatly reduces the program's execution efficiency. Therefore, planning reasonable spill / reload locations during register allocation to improve the efficiency of physical register usage is key to improving program performance. Summary of the Invention

[0004] This specification provides a register allocation method, computing device, storage medium, and computer program product to improve the efficiency of physical register usage, thereby improving program execution efficiency.

[0005] To achieve the above technical objectives, the embodiments of this specification provide the following technical solutions: Firstly, one embodiment of this specification provides a register allocation method, including: When allocating physical registers for a pending lifetime, if no allocable physical register exists, the target lifetime is determined within the lifetime of the already allocated physical registers; the lifetime corresponds to the virtual register and is used to characterize the active range of the virtual register. A target network is constructed based on the edge graph corresponding to the target lifetime; the target network includes multiple nodes and multiple edges connecting the nodes, the nodes represent edge bundles, the edges represent basic blocks, the weight of the edges is positively correlated with the distance from the edges to key points, and the key points are the locations of the definition instructions or usage instructions of the virtual registers corresponding to the target lifetime; The target network is iterated to determine the target position in the target network that minimizes the energy function. The target position is the position where a target instruction is inserted, and the target instruction is an overflow instruction or a reload instruction. The value of the energy function is positively correlated with a first target parameter, which includes at least one of the weight between two simultaneously activated nodes and the distance between the target position and the key point. The state representation of the activated node occupies the physical register.

[0006] Secondly, one embodiment of this specification also provides a computing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the register allocation method described above.

[0007] Thirdly, one embodiment of this specification also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the register allocation method described above.

[0008] Fourthly, embodiments of this specification provide a computer program product or computer program, the computer program product including a computer program stored in a computer-readable storage medium; the processor of the computer device reads the computer program from the computer-readable storage medium, and when the processor executes the computer program, it implements the steps of the register allocation method described above. Optionally, the computer program may be stored in a computer-readable storage medium or in the cloud; the processor of the computer device reads the computer program from the readable storage medium or in the cloud.

[0009] As can be seen from the above technical solution, the embodiments of this specification provide a register allocation method. During implementation, when allocating physical registers for a lifetime to be allocated, if no allocable physical register exists, a target lifetime is determined within the lifetime of already allocated physical registers. A target network is constructed based on the edge graph corresponding to the target lifetime, and the target network is iterated to determine the target position that minimizes the energy function. The target position is the location where the target instruction is inserted. Thus, because the weights of the edges in the target network are positively correlated with the distance from the edge to the key point, and the weights between nodes and the distance between the target position and the key point are explicitly constrained by the energy function during iterative optimization, the target network can automatically arrange overflow or reload instructions (i.e., target instructions) closer to the code position of the key operation (i.e., definition or usage instructions) during iterative convergence. This ensures that after the lifetime is divided, the interval (i.e., the byreg interval) where virtual registers (variables) are allocated to physical registers is as short as possible, allowing more variables to use the physical registers and reducing physical register pressure and overflow instructions. In summary, the register allocation method provided in this specification ensures that the final determined target location can both alleviate physical register conflicts and effectively reduce the invalid register occupation time caused by the instruction insertion point being too far from the critical point, thereby reducing memory access overhead and improving register utilization and program execution performance overall. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments or prior art of this specification, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this specification. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the segmentation location.

[0012] Figure 2 This is a flowchart illustrating a register allocation method provided for an embodiment of this specification.

[0013] Figure 3 This is a schematic diagram illustrating the process of generating a side graph based on a control flow graph, as provided in the embodiments of this specification.

[0014] Figure 4 This is a schematic diagram of the control flow graph and side bundle graph provided for the embodiments of this specification.

[0015] Figure 5 This is a schematic diagram illustrating the state update process provided for embodiments of this specification.

[0016] Figure 6 A schematic diagram of the structure of the computing device provided for the embodiments of this specification. Detailed Implementation

[0017] Unless otherwise defined, the technical or scientific terms used in the embodiments of this specification shall have the ordinary meaning understood by one of ordinary skill in the art to which this specification pertains. The terms "first," "second," and similar terms used in the embodiments of this specification do not indicate any order, quantity, or importance, but are merely used to avoid confusion of constituent elements.

[0018] Unless the context otherwise requires, throughout this specification, "a plurality of" means "at least two," and "including" is interpreted as open-ended or encompassing, that is, "including, but not limited to." In the description of this specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this specification. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example.

[0019] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this specification, and not all embodiments. Based on the embodiments in this specification, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this specification.

[0020] Overview In system software tools, the compiler's role is to translate high-level programming language source code into machine code that the machine can directly understand and execute. During the compiler's operation, it first converts the source code into an intermediate representation (IR) that is independent of specific hardware. Then, it performs optimizations on this intermediate representation, such as removing unnecessary code, simplifying calculations, and optimizing loops. Finally, the compiler backend converts the optimized intermediate representation into machine instructions specific to the architecture. In this process, the compiler backend handles core tasks such as instruction selection, instruction scheduling, and register allocation. Specifically, during register allocation, the compiler backend needs to determine how to map the vast number of virtual registers (which can be used to hold program variables) to the very limited number of physical registers in the processor. The goal is to keep as many variables as possible in the fast-read / write registers while satisfying instruction semantics, reducing data interaction with slow memory and thus greatly improving program efficiency.

[0021] Register allocation, a critical optimization task in the compiler backend, aims to efficiently manage virtual registers within a program using a limited number of physical registers, while minimizing memory overflow overhead caused by insufficient registers. Traditional algorithms, such as graph coloring, construct a conflict graph and attempt to allocate registers by coloring them. However, in complex control flows and dynamic code models, this method is prone to getting stuck in local optima. While efficient, linear scanning algorithms often result in suboptimal allocations due to simplified active interval analysis. To balance performance and complexity, LLVM (Low Level Virtual Machine) introduces the Greedy Register Allocation algorithm, whose core idea lies in multi-stage dynamic optimization and refined cost modeling. This algorithm first maps virtual registers to active intervals (or lifespans) covering their entire lifecycle. It then calculates the priority of each interval based on instruction flow topology and loop structure, and gradually resolves conflicts through global allocation and local repair strategies. During this process, the algorithm prioritizes allocating physical registers to active intervals with short lifecycles, high-frequency access, or deep nested loops. For conflicting intervals, it employs a lifespan splitting technique, only overflowing overlapping portions into memory, rather than abandoning the entire register binding. This strategy significantly reduces memory access latency on the critical path, while leveraging a dynamic cost model to weigh the cost of overflows. For example, for variables on hot loop paths, overflows may be avoided even if their priority is low, thus maintaining execution efficiency.

[0022] At the implementation level, the greedy register allocation algorithm improves allocation quality through multi-level optimization. First, it constructs a heuristic priority function based on factors such as active interval length, usage density, and instruction latency, dynamically adjusting the allocation order to adapt to different code characteristics. Second, it introduces interval merging technology to merge adjacent or partially overlapping intervals to reduce physical register usage. Furthermore, the algorithm employs fine-grained cost evaluation in overflow decisions, comprehensively considering the memory latency characteristics of the target architecture, register pressure distribution, and the execution probability of basic code blocks, thereby optimizing performance at both local and global levels. For example, when two active intervals conflict in instruction segment [15, 25], the algorithm may only split the conflicting sub-interval of one interval, rather than completely depriving it of its register eligibility, and minimize the overflow operation by inserting targeted load / store instructions. This flexibility allows the greedy register allocation algorithm to remain efficient when handling irregular control flows (such as numerous conditional branches or exception handling). When the lifetime needs to be segmented, the Hopfield network is used to iteratively calculate the position of the lifetime segmentation, dividing the lifetime into two parts: byreg (the interval where virtual registers (variables) are allocated to physical registers) and bystack (the interval where variables overflow into memory).

[0023] However, analysis reveals significant limitations in greedy register allocation algorithms used in large-scale code and complex control flow scenarios. Specifically, when abstracting virtual registers (or variables) into lifetimes, the specific use / def location information of the virtual registers is lost. Traditional methods rely on bundle graphs to group virtual registers with overlapping lifetimes, combining Hopfield networks to optimize lifetime segmentation. However, this method is based solely on static lifetime overlap analysis and fails to fully consider the dynamic usage characteristics of registers in the code, such as the location distribution, access frequency, and instruction dependencies of use and def instructions. Taking virtual registers in a loop as an example, virtual registers used at different locations within the loop all have a lifetime of the entire loop when generating their lifetimes, resulting in consistent segmentation schemes. However, finer-grained segmentation based on specific usage locations is necessary to achieve optimal performance under various conditions.

[0024] refer to Figure 1 , Figure 1 In the diagram, R1 and R2 represent two virtual registers (variables). The orange bar below R1 indicates its lifetime, and the green bar below R2 indicates its lifetime. Figure 1 The left side is a schematic diagram of the control flow graph. The numbers in the boxes represent different nodes, and each node represents a basic block. The numbers in the circles (e.g., ①, ②, etc.) represent different edges, and the edges represent the jump relationships between basic blocks. Meanwhile, Figure 1 In the control flow diagram, the location of the definition instruction for R1 is marked with orange "def", and the location of the usage instruction for R1 is marked with orange "use"; the location of the definition instruction for R2 is marked with green "def", and the location of the usage instruction for R2 is marked with green "use". From Figure 1 The control flow graph shows that the def and use statements in R1 and R2 are both located within loops, and from... Figure 1 It can be seen that the lifetimes of R1 and R2 span the entire loop. In this case, without interference from other factors, because the information about the positions of `def` and `use` is lost during their lifetimes, related techniques will obtain the same segmentation result when dividing these two lifetimes, such as... Figure 1The red "spill" and "reload" symbols indicate the locations where overflow instructions are inserted. Overflow instructions are used to save the current value of a variable from a register to memory when physical registers are insufficient. "Reload" indicates the locations where reload instructions are inserted. Reload instructions are used to load the value of a variable that has overflowed into memory back into the register when its value is needed. Under this partitioning, R1 and R2 are in the position from def to spill (e.g., ...). Figure 1 (T1 and T3 phases in the middle) or reload to use (e.g.) Figure 1 In the code segment (stages T2 and T4), there are no other use points, but a physical register is allocated as a byreg interval. This occupation of the physical register causes other instructions in this interval to lack a physical register. That is, in stages T1 and T2, R1 is not used by the program, but it still occupies a physical register, making it unusable by other variables in stages T1 and T2. Similarly, in stage T3 (which overrides stage T4), R2 is not used by the program, but it still occupies a physical register, making it unusable by other variables in stage T3. Physical registers are relatively scarce resources; occupying a physical register without using it is a huge waste of scarce resources, which may lead to more overflows in this interval. Therefore, for R1 and R2, the positions of their def and use operations should be considered: spill as early as possible after the def, and reload as late as possible before the use operation. Figure 1 The positions of "better spill" and "better reload" are shown in the diagram. Orange "better spill" and "better reload" indicate better positions for inserting overflow instructions and reloading instructions within the lifetime of R1, respectively, while green "better spill" and "better reload" indicate better positions for inserting overflow instructions and reloading instructions within the lifetime of R2, respectively. This reduces the length of the physical register range occupied, providing more allocable physical registers for more instructions (the physical registers originally occupied by R1 and R2 between "better spill" and "better reload" can be allocated to other variables), reducing register pressure and overflow instructions.

[0025] Based on the above concept, this specification provides a register allocation method. During implementation, when allocating physical registers for a lifetime to be allocated, if no allocable physical register exists, a target lifetime is determined within the lifetimes of already allocated physical registers. A target network is constructed based on the edge graph corresponding to the target lifetime, and the target network is iterated to determine the target position that minimizes the energy function. The target position is the location where the target instruction is inserted. Thus, because the weights of the edges in the target network are positively correlated with the distance from the edge to the key point, and the weights between nodes and the distance between the target position and the key point are explicitly constrained by the energy function during iterative optimization, the target network can automatically arrange overflow or reload instructions (i.e., target instructions) closer to the code position of the critical operation (i.e., definition or usage instructions) during iterative convergence. This ensures that after the lifetime is divided, the interval (i.e., the byreg interval) in which virtual registers (variables) are allocated to physical registers is as short as possible, allowing more variables to use the physical registers and reducing physical register pressure and overflow instructions. In summary, the register allocation method provided in this specification ensures that the final determined target location can both alleviate physical register conflicts and effectively reduce the invalid register occupation time caused by the instruction insertion point being too far from the critical point, thereby reducing memory access overhead and improving register utilization and program execution performance overall.

[0026] Based on the above concept, this specification provides a register allocation method, which will be described exemplarily below with reference to the accompanying drawings.

[0027] Exemplary methods This specification provides a register allocation method, such as... Figure 2 As shown, it includes: S201: When allocating a physical register for a pending lifetime, if no allocable physical register exists, the target lifetime is determined within the lifetime of the already allocated physical register; the lifetime corresponds to the virtual register and is used to characterize the active range of the virtual register. S202: Construct a target network based on the edge graph corresponding to the target lifetime; the target network includes multiple nodes and multiple edges connecting the nodes, the nodes represent edge bundles, the edges represent basic blocks, the weight of the edges is positively correlated with the distance from the edges to key points, and the key points are the locations of the definition instructions or usage instructions of the virtual registers corresponding to the target lifetime; S203: Iterate the target network to determine the target position in the target network that minimizes the energy function. The target position is the position where a target instruction is inserted. The target instruction is an overflow instruction or a reload instruction. The value of the energy function is positively correlated with a first target parameter. The first target parameter includes at least one of the weight between two simultaneously activated nodes and the distance between the target position and the key point. The state representation of the activated node occupies the physical register.

[0028] Before going into detail about each step, let's first introduce the terms that may be involved: Spill: During register allocation, when physical registers are insufficient, the operation saves the current value of a variable (virtual register) from the physical register to memory (usually the stack space). Instructions that instruct the hardware to perform an overflow operation are called overflow instructions.

[0029] Reload: When a variable that has overflowed into memory needs to be used again, its value is loaded back from memory into a physical register. The instruction that instructs the hardware to perform a reload operation is called a reload instruction.

[0030] Def (definition location, or definition point): The location in the program where the instruction that assigns a new value to a variable (i.e., the definition instruction) is located.

[0031] Use (or point of use): The location in the program where the instruction to read the value of a variable (i.e., the use instruction) is located.

[0032] A control flow graph (CFG) is a graphical representation of a program. Nodes in the CFG represent basic blocks, which can be a sequence of instructions executed sequentially. Edges in the CFG represent control flow transfers (such as jumps, branches, and loops) between basic blocks. CFGs can be used for program analysis, optimization, and code generation.

[0033] Edge Bundle Graph: A graph structure that abstracts the control flow graph. It groups and merges the edge sets in a traditional control flow graph, forming coarser-grained edge bundle nodes to represent aggregated regions of control flow transitions in a program. In an edge bundle graph, each node represents an edge bundle, which is the basic node of the graph and represents a set of control flow edges with similar properties. Edge bundles can be divided into in-bundles and out-bundles. All edges flowing into the same basic bundle are grouped into an in-bundle, and all edges flowing out of the same basic bundle are grouped into an out-bundle. Edges in an edge bundle graph represent basic bundles, and edges can connect two nodes. Edge bundle graphs can aggregate fine-grained control flow edges into regions, simplifying the partitioning of the decision space.

[0034] Live Interval / Range: The instruction range from when a variable is first defined to when it is last used. Within this range, the variable's value must be retained (in physical registers or memory).

[0035] Virtual Register / Variable: A variable is a named storage location in a high-level language that can be converted into a virtual register at the compiler backend. A virtual register is an abstract register in the compiler's intermediate representation, used to hold variables or intermediate values. A virtual register is the direct object of register allocation.

[0036] Live Range Splitting is a technique that divides a contiguous lifetime into multiple sub-ranges. Its purpose is to only overflow a portion of the sub-ranges into memory, rather than the entire lifetime, thereby reducing overflow overhead. The key decision is to choose where to insert the target instructions (i.e., overflow instructions and reload instructions).

[0037] Hopfield networks: a type of recurrent artificial neural network that can consist of symmetrically connected binary neurons and exhibits convergence characteristics that minimize energy. In this specification, it can be used to optimize the selection of lifetime split points.

[0038] Physical registers are a limited number of actual registers in the hardware that executes the program. They are accessed extremely quickly, but are scarce resources. The purpose of register allocation is to map the vast number of virtual registers in the program to a limited number of physical registers.

[0039] After the compiler backend performs pass optimizations such as instruction selection and instruction scheduling, it enters the register allocation stage. In this stage, actual physical registers are allocated to each virtual register. At this point, the compiler collects the virtual registers used and defined by each instruction based on machine instructions, and generates lifetimes based on the lifetime range of each register. For lifetimes, the original definition and usage location of the virtual registers are obscured, focusing only on the start and end positions of their lifetimes. In step S201, physical registers can be allocated sequentially for each lifetime. This allocation process can be based on lifetime priority. When there are not enough registers to allocate (i.e., no allocable physical registers), additional lifetime elimination and splitting processing is performed. In an optional implementation, the situation where no allocable physical registers exist is limited. Specifically, when allocating physical registers for a lifetime to be allocated, if all physical registers are allocated to other lifetimes that conflict with the lifetime to be allocated, then it is determined that no allocable physical registers exist. Among them, lifetime conflict refers to the overlap of the lifetimes of two or more virtual registers on the program's execution timeline, that is, they both hold valid data that needs to be accessed at the same time.

[0040] If the lifetimes of two virtual registers A and B partially overlap in time (e.g., A is active during instructions 10-50, and B is active during instructions 30-80), they cannot share the same physical register during the overlap period (instructions 30-50). This is because a physical register can only store one value at a time. Forcing allocation to the same physical register would result in one of the values ​​being incorrectly overwritten. Therefore, the core principle when allocating physical registers in step S201 is: the same physical register can only be allocated to lifetimes that do not conflict with each other. At any point during register allocation, each physical register has already been allocated to one or more non-conflicting lifetimes (these lifetimes are staggered in time, so the same physical register can be safely reused). However, if, when allocating physical registers to a lifetime to be allocated, all physical registers are allocated to other lifetimes that conflict with them, this indicates that no lifetime can reuse the same physical register with the lifetime to be allocated. Therefore, it is necessary to determine the target lifetime and perform subsequent segmentation processing on it.

[0041] In one implementation, to reduce the expected performance loss of overflowing virtual registers corresponding to the lifetime into memory, the lifetime with the lowest overflow weight among the lifetimes of allocated physical registers can be determined as the target lifetime. The overflow weight is positively correlated with the usage frequency of the virtual registers corresponding to the lifetime. Thus, the lower the overflow weight, the lower the usage frequency of the virtual registers corresponding to the lifetime. Determining the lifetime with the lowest overflow weight as the target lifetime can minimize the direct performance loss caused by dividing the target lifetime.

[0042] Combination Figure 3 and Figure 4 First, we will introduce the feasible process of constructing an edge graph based on a control flow graph. Figure 3 In the control flow graph, BBi represents different basic blocks. Each basic block has its own outflow bundle and inflow bundle. Adjacent outflow bundles and inflow bundles on the same edge are combined into an edge bundle. An edge bundle has two main characteristics: 1. Edges flowing out of the same basic block belong to the same edge bundle; 2. Edges flowing into the same basic block belong to the same edge bundle. This transforms the control flow graph into an edge bundle graph for iterative calculation of the splitting position. When determining the edge bundle graph, it is necessary to consider the state of the target lifetime being eliminated in step S201. This state can include the set of lifetimes with allocated physical registers, the basic blocks related to the target lifetime, and the def / use positions and frequency information of the virtual registers corresponding to the target lifetime.

[0043] Figure 4 The control flow graph and side graph representing the same program segment are shown. Figure 4 In a control flow graph, the numbers within rectangles represent control flow graph nodes, and the numbers within circles represent control flow graph edges. In an edge bundle graph, the numbers within circles represent edge bundle graph nodes.

[0044] After obtaining the edge graph corresponding to the target lifetime, the target network can be constructed. In the target network, the distance from an edge to a key point can refer to the number of instructions between the edge and the key point. Accordingly, in this specification, unless otherwise specified, the term "distance" can refer to the "number of instructions".

[0045] In step S203, during the iteration of the target network, a better target position is sought. In this process, the energy function can be used to guide the algorithm to find the split point closest to the key point in order to compress the byreg interval. In general, in the implementation of the register allocation method provided in this specification, when allocating physical registers for the lifetime to be allocated, if there are no allocable physical registers, the target lifetime is determined in the lifetime of the already allocated physical registers. The target network is constructed based on the side graph corresponding to the target lifetime, and the target network is iterated to determine the target position in the target network that minimizes the energy function. The target position is the position where the target instruction is inserted. Thus, by setting weights for edges in the target network that are positively correlated with the distance from the edge to the key point, and by explicitly constraining the weights between nodes and the distance between the target location and the key point through an energy function during iterative optimization, the target network can automatically arrange overflow or reload instructions (i.e., target instructions) closer to the code location of the critical operation (i.e., definition or usage instructions) during iterative convergence. This ensures that after the lifetime is divided, the interval (i.e., byreg interval) in which virtual registers (variables) are allocated to physical registers is as short as possible, allowing more variables to use the physical registers and reducing physical register pressure and overflow instructions. In summary, the register allocation method provided in this specification ensures that the final determined target location can both alleviate physical register conflicts and effectively reduce the invalid register occupation time caused by the instruction insertion point being too far from the key point, thereby reducing memory access overhead and improving register utilization and program execution performance overall.

[0046] In one implementation, the state of the node represents the occupancy status of the physical registers in the region corresponding to the edge represented by the node during the target lifetime. The target location includes an overflow location and a reload location. The target location is the boundary edge between nodes with different node states. After iterating over the target network, the process further includes: Perform a state update process to correct the overflow position toward the direction of the defined instruction, and / or to correct the reload position toward the direction of the used instruction.

[0047] After step S203, an optimal solution (i.e., one with the minimum energy function) is found. However, due to considerations such as stability in the target network iteration, the generated target position may not be the best choice from the perspective of the overall control flow. That is, through steps S201-S203, the solution with the lowest overall energy function (i.e., the overall optimal solution) is found, but it may not be optimal for a specific local target position. Therefore, in this embodiment, a state update process is performed to attempt to correct the overflow position towards the defined instruction, and / or correct the reload position towards the used instruction, thereby further compressing the register occupancy range, allowing more instructions to use the physical registers, and improving program execution efficiency.

[0048] In one implementation, a feasible state update process is provided, the state update process comprising: Traverse the node from the overflow position along the first direction, traverse the node from the reload position along the second direction, and when the node meets a predetermined condition, update the state of the node from the first state to the second state; the first state ensures that the physical register is occupied, and the second state indicates that the physical register is idle; the first direction includes the direction pointing to the defined instruction, and the second direction includes the direction pointing to the used instruction; The predetermined conditions include: a first condition and a second condition, wherein the first condition includes: the edge bundle represented by the currently traversed node is connected to the first basic block, and the state of the downstream node is the second state, the first basic block is a basic block related to the definition instruction or the usage instruction, and the downstream node is a node adjacent to the currently traversed node and located in the second direction. The second condition includes: the basic block representing the edge connection of the currently traversed node is a second basic block, and the second basic block is a basic block with a single entry or a single exit. Based on the updated node status, correct the target positions.

[0049] For example, suppose the target network has the following topology: def → [edge bundle A=1] → [edge bundle B=1] → use.

[0050] To set sideband A to zero, the state of sideband B needs to be checked: if sideband B = 0, then A can be set to zero (because the downstream register is no longer in use); if sideband B = 1, then A cannot be set to zero (otherwise, the transmission of the active value will be interrupted). (See reference) Figure 5 , Figure 5This diagram illustrates how the target position (specifically the overflow position) is updated from basic block 10 (spill in bb.10) to basic block 2 (spill in bb.2) through an iterative process.

[0051] In this implementation, by introducing a first condition and a second condition, the safety control and effectiveness guarantee of the correction process are achieved in principle. Specifically, the first condition requires that the current node is connected to the critical operation point (the basic block where the definition or use instruction is located) and that the downstream node is in an idle state. This ensures in principle that the correction operation will not disrupt the availability of registers on the critical path, avoiding program errors caused by prematurely releasing registers. Simultaneously, the second condition requires that the basic block connected to the node has a single entry or single exit. This means that the correction only occurs in code regions with simple control flow structures, avoiding the introduction of inconsistent register states in complex control flows (such as loops and branches), thereby ensuring the safety of the correction operation. Under the combined constraints of these two conditions, the state update process can safely, effectively, and accurately push overflow and reload locations closer to the critical operation point, thereby minimizing the physical register occupancy range, releasing more physical register resources, and improving overall allocation efficiency while ensuring program correctness.

[0052] In one implementation, the register allocation method further includes: Based on the corrected target locations, calculate the cost score corresponding to each target location. The cost score is positively correlated with the computational resource overhead caused by inserting the target instruction at each target location. The optimal target location is determined based on the cost score corresponding to each target location.

[0053] By evaluating the computational resource overhead of inserting the target instruction at each target location through overhead scoring, the optimal target location with the minimum overhead is determined from the target locations, so as to achieve the goal of inserting the target instruction at the optimal target location with the minimum performance loss.

[0054] In one implementation, the overhead score is positively correlated with a second target parameter, which includes a first parameter and / or a second parameter. The first parameter includes the expected execution frequency of the basic block where the target location is located, and the second parameter includes the distance between the basic block location where the target location is located and the definition instruction, as well as the distance between the target location and the last used instruction.

[0055] In this implementation, the overhead score is explicitly defined to be positively correlated with execution frequency and distance parameters. This ensures the objectivity and comprehensiveness of the evaluation process in principle: through the frequency parameter, the system can identify and avoid inserting high-overhead overflow / reload instructions on program hotspot paths; through the distance parameter (distance to the defined point or last-use point), the system can directly measure and minimize unnecessary register occupancy windows. Combining frequency and distance for comprehensive scoring allows the algorithm to balance the contradiction between "reducing extra operations in high-frequency regions" and "minimizing the local overhead of short-distance segmentation." The direct result is that the system can reliably select the optimal position with the least impact on the overall program performance from all candidate positions obtained after the aforementioned steps, which are safe and have shortened occupancy windows, thereby minimizing the performance loss caused by segmenting the target lifetime.

[0056] Alternatively, in one implementation, the cost score can be calculated based on the following formula: Here, Cost represents the overhead score, and S represents the base block location of the target location. This score is determined by two parts: first, the expected execution frequency (freq(S)) of the base block where the target location is located. The higher the execution frequency, the greater the potential impact of inserting the target instruction (overflow instruction or reload instruction) at this location on the overall performance; second, the instruction distance from the target location to the nearest critical point, which is the smaller of the distance from the target location to the location of the defining instruction (def(R)) and the distance to the location of the last used instruction (nearly_use(R)). The shorter this distance, the smaller the unnecessary physical register occupancy area caused by the split.

[0057] During the evaluation process, target locations with lower overhead scores are prioritized. Therefore, candidate locations with lower expected execution frequency and closer proximity to the critical point will receive higher priority. For example, a target location with lower expected execution frequency and adjacent to the location of the used instruction will have a significantly lower overhead score than another location with higher execution frequency but farther from the critical point. This balances the conflict between "avoiding the insertion of extra instructions in high-frequency execution regions" and "minimizing invalid register usage caused by the split point being too far from the critical point."

[0058] In one implementation, the weight of the edge is also positively correlated with the expected execution frequency of the basic block represented by the edge, and / or the weight of the edge is also negatively correlated with the maximum value of a first frequency and a second frequency, wherein the first frequency is the expected execution frequency of the basic block containing the definition instructions of the virtual register corresponding to the target lifetime, and the second frequency is the expected execution frequency of the basic block containing all usage instructions of the virtual register corresponding to the target lifetime.

[0059] In this embodiment, the weight of the edge is positively correlated with the distance from the edge to the key point, and the weight of the edge is also positively correlated with the expected execution frequency of the basic block represented by the edge. Furthermore, the weight of the edge is negatively correlated with the maximum value of the first and second frequencies. Thus, the weight of the edge can simultaneously quantify and reflect the execution heat and positional characteristics of the code region. During the iteration process of the target network, the energy function, being positively correlated with the edge weight, imposes a stronger penalty on edges with high execution frequencies and edges far from the key point. The direct result is that the iteration process automatically suppresses the activation of nodes at code locations with high execution frequencies or far from the key point, thereby driving the final determined target location (i.e., the location where the overflow instruction or reload instruction is inserted) to be biased towards code regions with lower execution frequencies and closer to the key operation point. Based on this, the method achieves automatic optimization and screening of the target instruction insertion location, effectively avoiding the introduction of high-overhead memory operations on program hotspot paths and minimizing the time window when physical registers are invalidally occupied, thereby reducing the overall performance loss caused by inserting the target instruction at the target location.

[0060] In one implementation, the weight of the edge can be calculated using the following formula: ; in, Denotes the edge, R represents the expected execution frequency of the basic block represented by the edge, and R represents the target lifetime. This indicates the location of the instruction defining the target lifetime. The location of the usage instructions indicating the target lifetime. This indicates the location of the last used command in the target's lifetime. Indicates the first frequency. Indicates the second frequency. This represents the maximum value of the first and second frequencies. This represents the distance from the edge to the key point (specifically, the definition point); This represents the distance from the edge to the key point (specifically, the last point used). This represents the maximum distance from an edge to a key point. This indicates the total length of the target's lifespan. This represents the frequency component in the weights. This represents the distance component in the weights. This represents the weight of the edge.

[0061] In one implementation, a feasible iterative process for the target network is provided, specifically including: Nodes in the target network are assigned initial state values, which are determined based on the topological position of the edge bundles represented by the node in the control flow graph, and are randomly generated within a preset probability distribution range. Based on the activation function, the state values ​​of each node are iteratively updated. In each iteration, the energy function is calculated until the energy function converges. The activation function is used to determine the new state value of the node based on the sum of the inputs of the node. The sum of the inputs is an intermediate value used to determine the direction of the state update of the node.

[0062] In this embodiment, by explicitly assigning initial state values ​​to nodes based on their topological locations and with randomness, and iteratively updating the state based on an activation function until the energy function converges, the entire iterative process possesses both directional guidance and global search robustness. The initial state values, determined by topological location, ensure that the search starting point matches the program control flow structure. Simultaneously, employing an activation function based on the sum of node inputs for state updates and continuously optimizing the energy function until convergence provides a convergent mathematical optimization mechanism, ensuring that the final determined target location is a stable solution that has undergone sufficient search and optimization, thereby improving the reliability and quality of the partitioning scheme. Optionally, in one embodiment, the activation function can be a sigmoid function.

[0063] In one implementation, the activation function specifically includes: a penalty term, a distance term, and a bias term, wherein, in the penalty term, for any two adjacent nodes that are simultaneously in an active state, the higher the weight of their connecting edge, the greater the contribution to the energy function. In the distance term, for a node in an active state, the greater the distance from its corresponding edge bundle to the key point, the greater its contribution to the energy function. The bias term is positively correlated with the degree of lifespan.

[0064] In this implementation, the penalty term penalizes the active nodes connected by high-weight edges, directly suppressing the simultaneous occupation of registers in regions with high execution frequency or far from the critical point, thereby guiding the split point to avoid high-overhead code regions. The distance term penalizes the distance from the active node to the critical point, directly pushing the split point as close as possible to the definition point or usage point, effectively shortening the invalid occupation window of physical registers. The bias term is positively correlated with the lifetime length, making long-lived nodes more inclined to maintain register occupation, avoiding unnecessary frequent splits. The combined effect of these three terms allows the energy function to comprehensively balance region overhead, distance overhead, and lifetime length, thereby driving the iterative process to find the overall optimal split position, reducing overflow overhead while taking into account the reasonable handling of different lifetime characteristics.

[0065] In one implementation, the step of iteratively updating the state values ​​of each node based on an activation function, and calculating the energy function in each iteration until the energy function converges, includes: Calculate the sum of inputs for the current node, which is the difference between the sum of the input values ​​of all neighboring nodes and the bias term of the current node. The current node is the node in the current iteration, and the bias term of the current node is positively correlated with the length of its lifetime. The input value of each neighboring node is the product of its state value and the connection weight, where the connection weight is the weight of the edge between the current node and its neighboring nodes. Based on the sum of the inputs to the current node, and using the activation function, determine the new state value of the current node; Calculate the difference between the new state value of the current node and the state value in the previous iteration. When the difference is greater than a first threshold, update the state value of the current node to the new state value. When the difference is less than or equal to the first threshold and the first cumulative count is less than the second threshold, the state value of the current node is not updated. The first cumulative count is the number of times the difference of the current node is less than or equal to the first threshold during the iteration process. When the difference is less than or equal to the first threshold and the first cumulative number is greater than or equal to the second threshold, the state value of the current node is updated to a new state value. After one round of iteration is completed, the energy function of the target network is calculated. If the second cumulative number is greater than or equal to the third threshold, the energy function is determined to be converged and the iteration process is terminated. The second cumulative number is the number of consecutive times that the energy fluctuation is less than the fluctuation threshold. The energy fluctuation is the difference between the energy function calculated after the current round of iteration and the energy function calculated after the previous round of iteration.

[0066] In this embodiment, the state value of each node in the target network can be 0 or 1, where 0 indicates that the node is not occupying a physical register, and 1 indicates that the node is occupying a physical register.

[0067] In this implementation, firstly, the calculation method for the total input is clearly defined (accumulated input values ​​of neighboring nodes minus the bias), ensuring that state update decisions are based on complete local connectivity information and lifetime characteristics. Secondly, a dynamic update threshold mechanism based on differences is introduced: when the state change is significant (difference greater than the first threshold), updates are performed immediately to ensure rapid iteration; when the change is small (difference less than or equal to the first threshold), updates are performed only after accumulating a certain number of iterations (the second threshold), effectively avoiding oscillations caused by noise fluctuations and enhancing iteration stability. Finally, convergence is determined based on multiple consecutive (the third threshold) energy fluctuations being less than the fluctuation threshold, ensuring that the network reaches a true steady state rather than a temporary stagnation. These rules work together to enable the iteration process to converge to a high-quality solution in a stable and reliable manner within a reasonable computational cost, thereby guaranteeing the effectiveness and practicality of the final partitioning scheme.

[0068] Exemplary device In one exemplary embodiment of this specification, a register allocation apparatus is also provided, the register allocation apparatus comprising: The first module is used to determine the target lifetime within the lifetime of the already allocated physical registers if no allocable physical registers exist when allocating physical registers for the lifetime to be allocated; the lifetime corresponds to the virtual register and is used to characterize the active range of the virtual register. The second module is used to construct a target network based on the edge graph corresponding to the target lifetime; the target network includes multiple nodes and multiple edges connecting the nodes, the nodes represent edge bundles, the edges represent basic blocks, the weight of the edges is positively correlated with the distance from the edges to key points, and the key points are the location of the definition instructions or the location of the usage instructions of the virtual registers corresponding to the target lifetime; The third module is used to iterate over the target network to determine the target position in the target network that minimizes the energy function. The target position is the position where a target instruction is inserted, and the target instruction is an overflow instruction or a reload instruction. The value of the energy function is positively correlated with a first target parameter, which includes at least one of the weight between two simultaneously activated nodes and the distance between the target position and the key point. The state representation of the activated node occupies the physical register.

[0069] For specific limitations regarding the register allocation device, please refer to the limitations regarding the register allocation method above, which will not be repeated here. Each module in the aforementioned register allocation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in the computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0070] Exemplary computing device Another embodiment of this application also proposes a computing device, see [link to relevant documentation] Figure 6 As shown, an exemplary embodiment of this specification also provides a computing device, including: a memory and a processor, the memory storing a computer program, the processor executing the computer program and performing the steps in the register allocation method according to various embodiments of this specification described above.

[0071] The internal structure of the computing device can be as follows: Figure 6 As shown, the computing device includes a processor, memory, network interface, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The network interface is used to communicate with external terminals via a network connection. When the computer program is executed by the processor, it follows the steps of the register allocation methods according to various embodiments of this specification described in the above embodiments.

[0072] The processor may include the main processor, as well as baseband chips, modems, etc.

[0073] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0074] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0075] Input devices may include devices that receive data and information input by the user, such as keyboards, mice, cameras, scanners, light pens, voice input devices, touch screens, pedometers, or gravity sensors.

[0076] Output devices may include devices that allow information to be output to the user, such as displays, printers, speakers, etc.

[0077] The communication interface may include any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, Radio Access Network (RAN), Wireless Local Area Network (WLAN), etc.

[0078] The computing device may also include a display component and a voice component. The display component may be a liquid crystal display screen or an e-ink display screen. The input device of the computing device may be a touch layer covering the display component, or a button, trackball or touchpad set on the casing of the computing device, or an external keyboard, touchpad or mouse, etc.

[0079] Those skilled in the art will understand that Figure 6 The structures shown are merely block diagrams of some structures related to the solutions in this specification and do not constitute a limitation on the computing devices on which the solutions in this specification are applied. Specific computing devices may include more or fewer components than those shown in the figures, or combine certain components, or have different component arrangements.

[0080] Exemplary computer program products and storage media In addition to the methods and devices described above, the register allocation methods provided in the embodiments of this specification can also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the register allocation methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0081] The aforementioned computer program product can be implemented through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0082] The computer program product described herein can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments described herein. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0083] Furthermore, embodiments of this specification also provide a computer-readable storage medium having a computer program stored thereon, the computer program being executed by a processor of the steps in the register allocation methods according to various embodiments of this specification as described in the "Exemplary Methods" section above.

[0084] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this specification can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0085] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0086] The embodiments described above are merely illustrative of several implementation methods outlined in this specification. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the solutions provided in this specification. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this specification, and these all fall within the scope of protection of this specification. Therefore, the scope of protection for this patent should be determined by the appended claims.

Claims

1. A register allocation method, characterized in that, include: When allocating physical registers for a pending lifetime, if no allocable physical registers exist, the target lifetime is determined within the lifetime of the already allocated physical registers. The lifetime corresponds to the virtual register and is used to characterize the active range of the virtual register; A target network is constructed based on the edge graph corresponding to the target lifetime; the target network includes multiple nodes and multiple edges connecting the nodes, the nodes represent edge bundles, the edges represent basic blocks, the weight of the edges is positively correlated with the distance from the edges to key points, and the key points are the locations of the definition instructions or usage instructions of the virtual registers corresponding to the target lifetime; The target network is iterated to determine the target position in the target network that minimizes the energy function. The target position is the position where a target instruction is inserted, and the target instruction is an overflow instruction or a reload instruction. The value of the energy function is positively correlated with a first target parameter, which includes at least one of the weight between two simultaneously activated nodes and the distance between the target position and the key point. The state representation of the activated node occupies the physical register.

2. The method according to claim 1, characterized in that, The state of the node represents the occupancy status of the physical registers in the region corresponding to the edge represented by the node during the target lifetime. The target location includes the overflow location and the reload location. The target location is the boundary edge between nodes with different states. After iterating over the target network, the process further includes: Perform a state update process to correct the overflow position toward the direction of the defined instruction, and / or to correct the reload position toward the direction of the used instruction.

3. The method according to claim 2, characterized in that, The state update process includes: Traverse the node from the overflow position along the first direction, traverse the node from the reload position along the second direction, and when the node meets a predetermined condition, update the state of the node from the first state to the second state; the first state ensures that the physical register is occupied, and the second state indicates that the physical register is idle; the first direction includes the direction pointing to the defined instruction, and the second direction includes the direction pointing to the used instruction; The predetermined conditions include: a first condition and a second condition, wherein the first condition includes: the edge bundle represented by the currently traversed node is connected to the first basic block, and the state of the downstream node is the second state, the first basic block is a basic block related to the definition instruction or the usage instruction, and the downstream node is a node adjacent to the currently traversed node and located in the second direction. The second condition includes: the basic block representing the edge connection of the node currently being traversed is a second basic block, and the second basic block is a basic block with a single entry or a single exit. Based on the updated node status, correct the target positions.

4. The method according to claim 2, characterized in that, Also includes: Based on the corrected target locations, calculate the cost score corresponding to each target location. The cost score is positively correlated with the computational resource overhead caused by inserting the target instruction at each target location. The optimal target location is determined based on the cost score corresponding to each target location.

5. The method according to claim 4, characterized in that, The overhead score is positively correlated with a second target parameter, which includes a first parameter and / or a second parameter. The first parameter includes the expected execution frequency of the basic block where the target location is located, and the second parameter includes the distance between the basic block location where the target location is located and the definition instruction, as well as the distance between the target location and the last usage instruction.

6. The method according to any one of claims 1 to 5, characterized in that, The weight of the edge is also positively correlated with the expected execution frequency of the basic block represented by the edge, and / or the weight of the edge is also negatively correlated with the maximum value of the first frequency and the second frequency, where the first frequency is the expected execution frequency of the basic block containing the definition instructions of the virtual register corresponding to the target lifetime, and the second frequency is the expected execution frequency of the basic block containing all usage instructions of the virtual register corresponding to the target lifetime.

7. The method according to any one of claims 1 to 5, characterized in that, The iteration of the target network includes: Nodes in the target network are assigned initial state values, which are determined based on the topological position of the edge bundles represented by the node in the control flow graph, and are randomly generated within a preset probability distribution range. Based on the activation function, the state values ​​of each node are iteratively updated. In each iteration, the energy function is calculated until the energy function converges. The activation function is used to determine the new state value of the node based on the sum of the inputs of the node. The sum of the inputs is an intermediate value used to determine the direction of the state update of the node.

8. The method according to claim 7, characterized in that, The activation function specifically includes a penalty term, a distance term, and a bias term. In the penalty term, for any two adjacent nodes that are simultaneously active, the higher the weight of their connecting edge, the greater their contribution to the energy function. In the distance term, for a node in an active state, the greater the distance from its corresponding edge bundle to the key point, the greater its contribution to the energy function. The bias term is positively correlated with the degree of lifespan.

9. The method according to claim 7, characterized in that, The step of iteratively updating the state values ​​of each node based on the activation function, and calculating the energy function in each iteration until the energy function converges, includes: Calculate the sum of inputs for the current node, which is the difference between the sum of the input values ​​of all neighboring nodes and the bias term of the current node. The current node is the node in the current iteration, and the bias term of the current node is positively correlated with the length of its lifetime. The input value of each neighboring node is the product of its state value and the connection weight, where the connection weight is the weight of the edge between the current node and its neighboring nodes. Based on the sum of the inputs to the current node, and using the activation function, determine the new state value of the current node; Calculate the difference between the new state value of the current node and the state value in the previous iteration. When the difference is greater than a first threshold, update the state value of the current node to the new state value. When the difference is less than or equal to the first threshold and the first cumulative count is less than the second threshold, the state value of the current node is not updated. The first cumulative count is the number of times the difference of the current node is less than or equal to the first threshold during the iteration process. When the difference is less than or equal to the first threshold and the first cumulative number is greater than or equal to the second threshold, the state value of the current node is updated to a new state value. After one round of iteration is completed, the energy function of the target network is calculated. If the second cumulative number is greater than or equal to the third threshold, the energy function is determined to be converged and the iteration process is terminated. The second cumulative number is the number of consecutive times that the energy fluctuation is less than the fluctuation threshold. The energy fluctuation is the difference between the energy function calculated after the current round of iteration and the energy function calculated after the previous round of iteration.

10. The method according to any one of claims 1 to 5, characterized in that, When allocating physical registers for a pending lifetime, if no allocable physical register exists, determining the target lifetime within the lifetime of already allocated physical registers includes: When allocating physical registers for a pending lifetime, if all physical registers are allocated to other lifetimes that conflict with the pending lifetime, then it is determined that there are no physical registers available for allocation. Within the lifetime of allocated physical registers, the lifetime with the lowest overflow weight is determined as the target lifetime, where the overflow weight is positively correlated with the usage frequency of the virtual registers corresponding to the lifetime.

11. A computing device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the register allocation method according to any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the register allocation method according to any one of claims 1 to 10.

13. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the register allocation method as described in any one of claims 1 to 10.

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