Memory management method, memory storage device and memory control circuit unit

Abstract

The invention provides a memory management method, a memory storage device and a memory control circuit unit. The memory management method comprises the following steps: forming a first code word by using first virtual data and first data read from a rewritable nonvolatile memory module; executing a first decoding operation according to the first virtual data to update the first virtual data so as to obtain second virtual data; forming a second code word by the first data and the second virtual data; and performing a second decoding operation according to the second codeword.

Description

Technical Field

[0001] This invention relates to a memory management technology, and more particularly to a memory management method, a memory storage device, and a memory control circuit unit. Background Technology

[0002] The rapid growth of portable electronic devices such as mobile phones and laptops in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for integration into the aforementioned portable electronic devices due to their non-volatile data, low power consumption, small size, and lack of mechanical structure.

[0003] To maintain data reliability, the data is encoded to generate corresponding error correction codes before being stored in the rewritable non-volatile memory module. The error correction codes are then stored in the rewritable non-volatile memory module along with the corresponding data. In some cases, to accommodate the actual writable length, a portion of the error correction code (or data) is deleted before being stored in the rewritable non-volatile memory module. Subsequently, when the data and error correction codes are read from the rewritable non-volatile memory module, dummy data can be added to fill in the missing error correction code (or data), thus allowing the dummy data, the data read from the rewritable non-volatile memory module, and the error correction codes to form a complete codeword.

[0004] In traditional iterative decoding operations, each iteration is performed based on a complete codeword. However, errors in virtual data are difficult to converge, leading to increased iteration counts and low decoding efficiency. Summary of the Invention

[0005] This invention provides a memory management method, a memory storage device, and a memory control circuit unit, which can improve decoding speed.

[0006] An exemplary embodiment of the present invention provides a memory management method for a rewritable non-volatile memory module, and the memory management method includes: forming a first codeword by combining first virtual data and first data read from the rewritable non-volatile memory module; performing a first decoding operation based on the first virtual data to update the first virtual data, thereby obtaining second virtual data; forming a second codeword by combining the first data and the second virtual data; and performing a second decoding operation based on the second codeword.

[0007] In one exemplary embodiment of the present invention, the first data consists of written data and parity data, and a portion of the written data or parity data has been deleted.

[0008] In one exemplary embodiment of the present invention, the first virtual data is used as part of the data.

[0009] In an exemplary embodiment of the present invention, the memory management method further includes: performing an encoding operation on the written data to generate parity data; deleting a portion of the data in the written data or parity data, and then storing the written data and parity data of the deleted portion of the data, or the parity data and written data of the deleted portion of the data, into a rewritable non-volatile memory module.

[0010] In an exemplary embodiment of the present invention, the step of performing a first decoding operation based on the first virtual data includes: in response to the deletion of a portion of the parity data, forming an error correction code with the parity data of the deleted portion and the first virtual data, and performing a first decoding operation on the first virtual data using the error correction code.

[0011] In an exemplary embodiment of the present invention, the step of performing a first decoding operation based on the first virtual data includes: in response to the deletion of part of the written data, using parity data as an error correction code, and performing a first decoding operation on the first virtual data using the error correction code.

[0012] In one exemplary embodiment of the present invention, the first decoding operation and the second decoding operation use the same parity check matrix.

[0013] In one exemplary embodiment of the present invention, the log-likelihood ratio (LLR) corresponding to the first virtual data is zero.

[0014] In one exemplary embodiment of the present invention, the absolute value of the log-probability ratio corresponding to the second virtual data is greater than the absolute value of the log-probability ratio corresponding to the first virtual data.

[0015] In one exemplary embodiment of the present invention, the decoding algorithm corresponding to the first decoding operation is different from the decoding algorithm corresponding to the second decoding operation.

[0016] In one exemplary embodiment of the present invention, the first decoding operation is a bit-flipping decoding operation.

[0017] In an exemplary embodiment of the present invention, the memory management method further includes: in a bit-flipping decoding operation, in response to the number of non-zero checksums associated with bits in the first virtual data being greater than a preset threshold, flipping the value of the bit.

[0018] In one exemplary embodiment of the present invention, the second decoding operation is a low-density parity-check (LDPC) decoding operation.

[0019] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is connected to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is configured to combine first virtual data and first data read from the rewritable non-volatile memory module to form a first codeword. The memory control circuit unit is further configured to perform a first decoding operation based on the first virtual data to update the first virtual data, thereby obtaining second virtual data. The memory control circuit unit is further configured to combine the first data and the second virtual data to form a second codeword. The memory control circuit unit is further configured to perform a second decoding operation based on the second codeword.

[0020] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to perform an encoding operation on the written data to generate parity data. The memory control circuit unit is further configured to delete a portion of the written data or parity data, and then store the deleted portion of the written data and parity data, or the deleted portion of the parity data and the written data, into a rewritable non-volatile memory module.

[0021] In an exemplary embodiment of the present invention, in response to the deletion of a portion of the parity data, the memory control circuit unit is further configured to form an error correction code with the parity data of the deleted portion of the data and the first virtual data, and to perform a first decoding operation on the first virtual data using the error correction code.

[0022] In an exemplary embodiment of the present invention, in response to the deletion of part of the written data, the memory control circuit unit is further configured to use parity data as an error correction code and perform a first decoding operation on the first virtual data using the error correction code.

[0023] In an exemplary embodiment of the present invention, in the bit-flipping decoding operation, in response to the number of non-zero checksums associated with bits in the first virtual data being greater than a preset threshold, the memory control circuit unit is also used to flip the value of the bit.

[0024] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is connected to a connection interface unit. The memory interface is connected to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used to assemble a first codeword from first virtual data and first data read from the rewritable non-volatile memory module. The memory management circuit is also used to perform a first decoding operation based on the first virtual data to update the first virtual data, thereby obtaining second virtual data. The memory management circuit is also used to assemble a second codeword from the first data and the second virtual data. The memory management circuit is also used to perform a second decoding operation based on the second codeword.

[0025] In one exemplary embodiment of the present invention, the memory management circuit is further configured to perform an encoding operation on the written data to generate parity data. The memory management circuit is further configured to delete a portion of the written data or parity data, and then store the deleted portion of the written data and parity data, or the deleted portion of the parity data and the written data, into a rewritable non-volatile memory module.

[0026] In an exemplary embodiment of the present invention, in response to the deletion of a portion of the parity data, the memory management circuit further uses the parity data of the deleted portion of the data and the first virtual data to form an error correction code, and uses the error correction code to perform a first decoding operation on the first virtual data.

[0027] In an exemplary embodiment of the present invention, in response to the deletion of part of the written data, the memory management circuit is further configured to use parity data as an error correction code and to perform a first decoding operation on the first virtual data using the error correction code.

[0028] In an exemplary embodiment of the present invention, in the bit-flipping decoding operation, in response to the number of non-zero checksums associated with bits in the first virtual data being greater than a preset threshold, the memory management circuit is also used to flip the value of the bits.

[0029] Based on the above, the memory management method, memory storage device, and memory control circuit unit of the present invention perform a decoding operation based only on virtual data before performing a decoding operation based on the complete codeword, in order to attempt to converge errors in the virtual data (i.e., improve the reliability of the virtual data), thereby avoiding the increased number of iterations due to the virtual data and improving the decoding speed. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a host system, memory storage device, and input / output (I / O) device according to an exemplary embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0035] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram illustrating the management of the first codeword and the second codeword according to an exemplary embodiment of the present invention;

[0037] Figure 8 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Detailed Implementation

[0038] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0039] Generally, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit). The memory storage device can be used with a host system to enable the host system to write data to or read data from the memory storage device.

[0040] Figure 1 This is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 This is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0041] Please refer to Figure 1 and Figure 2The host system 11 may include a processor 111, random access memory (RAM) 112, read-only memory (ROM) 113, and a data transfer interface 114. The processor 111, RAM 112, ROM 113, and data transfer interface 114 may be connected to a system bus 110.

[0042] In one exemplary embodiment, the host system 11 can be connected to the memory storage device 10 via a data transmission interface 114. For example, the host system 11 can store data to or read data from the memory storage device 10 via the data transmission interface 114. Furthermore, the host system 11 can be connected to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to or receive input signals from the I / O device 12 via the system bus 110.

[0043] In one exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transfer interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. Through the data transfer interface 114, the motherboard 20 may be connected to the memory storage device 10 via wired or wireless means.

[0044] In one exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid-state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a WiFi wireless fax memory storage device, a Bluetooth memory storage device, or a Bluetooth Low Energy (BLE) memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be connected via the system bus 110 to various I / O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0045] In one exemplary embodiment, the host system 11 is a computer system. In another exemplary embodiment, the host system 11 may be any system capable of substantially cooperating with a memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 may each include… Figure 3 The memory storage device 30 and the host system 31.

[0046] Figure 3 This is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 3 The memory storage device 30 can be used in conjunction with the host system 31 to store data. For example, the host system 31 can be a digital camera, camcorder, communication device, audio player, video player, or tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0047] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4 The memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable non-volatile memory module 43.

[0048] The connection interface unit 41 is used to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0049] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 43 according to the instructions of the host system 11.

[0050] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0051] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, thereby retrieving the one or more bits stored in that memory cell.

[0052] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If each memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0053] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0054] Figure 5 This is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Please refer to... Figure 5 The memory control circuit unit 42 includes a memory management circuit 51, a host interface 52, and a memory interface 53.

[0055] The memory management circuit 51 controls the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has multiple control instructions, and these control instructions are executed when the memory storage device 10 is operating to perform operations such as writing, reading, and erasing data. The following description of the operation of the memory management circuit 51 is equivalent to the description of the operation of the memory control circuit unit 42.

[0056] In one exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware form. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read-only memory (not shown), and these control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0057] In one exemplary embodiment, the control instructions of the memory management circuit 51 may also be stored in program code form in a specific area of ​​the rewritable non-volatile memory module 43 (e.g., a system area in the memory module dedicated to storing system data). Furthermore, the memory management circuit 51 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). Specifically, this read-only memory has a boot code, and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes this boot code to load the control instructions stored in the rewritable non-volatile memory module 43 into the random access memory of the memory management circuit 51. Subsequently, the microprocessor unit executes these control instructions to perform operations such as writing, reading, and erasing data.

[0058] In one exemplary embodiment, the control instructions for the memory management circuit 51 can also be implemented in hardware. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, memory write circuit, memory read circuit, memory erase circuit, and data processing circuit are connected to the microcontroller. The memory cell management circuit manages the memory cells or groups of memory cells in the rewritable non-volatile memory module 43. The memory write circuit issues a sequence of write instructions to the rewritable non-volatile memory module 43 to write data into the rewritable non-volatile memory module 43. The memory read circuit issues a sequence of read instructions to the rewritable non-volatile memory module 43 to read data from the rewritable non-volatile memory module 43. The memory erase circuit issues a sequence of erase instructions to the rewritable non-volatile memory module 43 to erase data from the rewritable non-volatile memory module 43. The data processing circuit is used to process data to be written to and read from the rewritable non-volatile memory module 43. The write instruction sequence, read instruction sequence, and erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 43 to perform corresponding write, read, and erase operations. In an exemplary embodiment, the memory management circuit 51 may also issue other types of instruction sequences to the rewritable non-volatile memory module 43 to instruct it to perform corresponding operations.

[0059] The host interface 52 is connected to the memory management circuitry 51. The memory management circuitry 51 can communicate with the host system 11 through the host interface 52. The host interface 52 can be used to obtain and identify instructions and data from the host system 11. For example, instructions and data from the host system 11 can be transmitted to the memory management circuitry 51 through the host interface 52. Furthermore, the memory management circuitry 51 can transmit data to the host system 11 through the host interface 52. In this exemplary embodiment, the host interface 52 is compatible with the PCI Express standard. However, it should be understood that the invention is not limited thereto, and the host interface 52 may also be compatible with SATA, PATA, IEEE 1394, USB, SD, UHS-I, UHS-II, MS, MMC, eMMC, UFS, CF, IDE, or other suitable data transmission standards.

[0060] The memory interface 53 is connected to the memory management circuit 51 and is used to access the rewritable non-volatile memory module 43. For example, the memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53. That is, data to be written to the rewritable non-volatile memory module 43 is converted into a format acceptable to the rewritable non-volatile memory module 43 via the memory interface 53. Specifically, if the memory management circuit 51 needs to access the rewritable non-volatile memory module 43, the memory interface 53 will transmit a corresponding instruction sequence. For example, these instruction sequences may include write instruction sequences indicating the writing of data, read instruction sequences indicating the reading of data, erase instruction sequences indicating the erasure of data, and corresponding instruction sequences indicating various memory operations (e.g., changing the read voltage level or performing garbage collection (GC) operations, etc.). These instruction sequences are generated by the memory management circuit 51 and transmitted to the rewritable non-volatile memory module 43 via the memory interface 53. These instruction sequences may include one or more signals or data on the bus. These signals or data may include instruction codes or program codes. For example, a read instruction sequence may include information such as the read identification code and memory address.

[0061] In one exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54, a buffer memory 55, and a power management circuit 56.

[0062] Error checking and correction circuit 54 is connected to memory management circuit 51 and is used to perform error checking and correction operations to ensure data integrity. Specifically, when memory management circuit 51 obtains a write command from host system 11, error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code to rewritable non-volatile memory module 43. Subsequently, when memory management circuit 51 reads data from rewritable non-volatile memory module 43, it simultaneously reads the corresponding error correcting code and / or error detecting code for this data, and error checking and correction circuit 54 performs error checking and correction operations on the read data based on the error correcting code and / or error detecting code.

[0063] The buffer memory 55 is connected to the memory management circuit 51 and is used to cache data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power supply of the memory storage device 10.

[0064] In one exemplary embodiment, Figure 4 The rewritable non-volatile memory module 43 may include a flash memory module. In one exemplary embodiment, Figure 4 The memory control circuit unit 42 may include a flash memory controller. In one exemplary embodiment, Figure 5 The memory management circuit 51 may include a flash memory management circuit.

[0065] Figure 6 This is a schematic diagram illustrating the management of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Please refer to... Figure 6 The memory management circuit 51 can logically group the physical cells 610(0)~610(B) in the rewritable non-volatile memory module 43 into the storage area 601 and the spare area 602.

[0066] In one exemplary embodiment, an entity unit refers to an entity address or an entity programmable unit. In one exemplary embodiment, an entity unit may also consist of multiple consecutive or non-consecutive entity addresses. In one exemplary embodiment, an entity unit may also refer to a virtual block (VB). A virtual block may include multiple entity addresses or multiple entity programmable units. In one exemplary embodiment, a virtual block may include one or more entity erase units.

[0067] The physical units 610(0) to 610(A) in storage area 601 are used to store user data (e.g., from...) Figure 1 (User data of host system 11). For example, entity units 610(0) to 610(A) in storage area 601 may store valid and invalid data. Entity units 610(A+1) to 610(B) in free area 602 do not store data (e.g., valid data). For example, if an entity unit does not store valid data, this entity unit may be associated (or added) to free area 602. In addition, entity units (or entity units that do not store valid data) in free area 602 may be erased. When new data is written, one or more entity units may be retrieved from free area 602 to store this new data. In an exemplary embodiment, free area 602 is also referred to as a free pool.

[0068] The memory management circuit 51 can configure logic units 612(0)~612(C) to map physical units 610(0)~610(A) in memory area 601. In one exemplary embodiment, each logic unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In one exemplary embodiment, a logic unit may also correspond to a logical programmable unit or consist of multiple consecutive or non-consecutive logical addresses.

[0069] It should be noted that a logical unit can be mapped to one or more entity units. If an entity unit is currently mapped to a logical unit, it means that the data currently stored in this entity unit includes valid data. Conversely, if an entity unit is not currently mapped to any logical unit, it means that the data currently stored in this entity unit is invalid data.

[0070] The memory management circuit 51 can record management data (also known as logic-to-entity mapping information) describing the mapping relationship between logic units and physical units in at least one logic-to-entity mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 can access the rewritable non-volatile memory module 43 according to the information in this logic-to-entity mapping table.

[0071] In one exemplary embodiment, the error checking and correction circuit 54 may include an encoding circuit 541, a decoding preprocessing circuit 542, and a decoding circuit 543. The encoding circuit 541 is used to encode data. The decoding preprocessing circuit 542 and the decoding circuit 543 are used to decode data. In one exemplary embodiment, the encoding circuit 541, the decoding preprocessing circuit 542, and the decoding circuit 543 may also be combined into a single encoding / decoding circuit.

[0072] In one exemplary embodiment, before the memory management circuit 51 writes data to the rewritable non-volatile memory module 43, the data is first encoded to generate corresponding parity data. The data and parity data are then stored in the rewritable non-volatile memory module 43. The data that the memory management circuit 51 intends to write to the rewritable non-volatile memory module 43 (also referred to as write data) can be, for example, user data written by the host system 11 or management data of the memory management circuit 51. When the memory management circuit 51 wants to read a physical cell, it can read the data in the physical cell and its corresponding parity data. The decoding circuit 543 in the error checking and correction circuit 54 can perform a decoding operation based on the parity data and the data read from the physical cell to detect and correct errors in the data.

[0073] In one exemplary embodiment, before the memory management circuit 51 writes data (also referred to as write data) to the rewritable non-volatile memory module 43, the data is first encoded to generate corresponding parity data. The data and parity data are then stored in the physical cells of the rewritable non-volatile memory module 43. Since the size of the physical cells is fixed, to accommodate the current writable length, a portion of the data (or parity data) is first deleted to form partial data (or partial parity data). Then, the partial data and the complete parity data (or partial parity data and the complete data) are stored in the physical cells. When the memory management circuit 51 wants to read the physical cell, it can read the data and its corresponding parity data from the physical cell and add dummy data (also referred to as first dummy data) of the same size as the deleted partial data. The error checking and correction circuit 54 can perform a decoding operation based on the dummy data, the data read from the physical cell, and the parity data to detect and correct errors in the data. That is, the dummy data can be used, for example, as the aforementioned partial data. In one exemplary embodiment, if a portion of the parity data is deleted, the virtual data can be combined with the parity data read from the physical unit (i.e., the partial parity data) to form a parity data with the same data length as the original parity data (i.e., the reconstructed parity data). Then, the error checking and correction circuit 54 can perform a decoding operation based on the reconstructed parity data and the written data. In another exemplary embodiment, if a portion of the written data is deleted, the virtual data can be combined with the written data read from the physical unit (i.e., the partial written data) to form a written data with the same data length as the original written data (i.e., the reconstructed written data). Then, the error checking and correction circuit 54 can perform a decoding operation based on the reconstructed written data and the parity data.

[0074] In one exemplary embodiment, the error checking and correction circuit 54 uses a low-density parity-check code for encoding and decoding. In a low-density parity-check code, a check matrix (also called a parity check matrix) is used to define a valid codeword. The parity check matrix is ​​denoted as H, and the codeword as CW. According to the following equation (1), if the product of the parity check matrix H and the codeword CW is zero, then CW is a valid codeword. The operator × represents matrix multiplication modulo 2. In other words, the null space of matrix H contains all valid codewords. However, this invention does not limit the content of the codeword CW. For example, the codeword CW can also include error correction codes or error checking codes generated by any algorithm.

[0075]

[0076] In one exemplary embodiment, the codeword CW may include information bits and parity bits, i.e., the codeword CW may be represented as [MP]. Vector M is composed of information bits. Vector P is composed of parity bits. Vector M is also called written data (or data to be encoded). Vector P is also called parity data. In a codeword, parity bits (i.e., parity data) are used to protect information bits (i.e., written data) and can be regarded as error correction codes or error checking codes generated corresponding to information bits. Furthermore, protecting information bits, for example, means maintaining the correctness of information bits. For example, when information bits are read from the rewritable non-volatile memory module 43, the parity bits corresponding to this information bit can be used to correct any errors that may exist in the information bit.

[0077] In one exemplary embodiment, the codeword CW may include information bits, parity bits, and dummy bits; that is, the codeword CW may be represented as [MPV] or [MVP]. Vector M is composed of information bits. Vector P is composed of parity bits. Vector V is composed of dummy bits. Vector M is also called written data (or data to be encoded). Vector P is also called parity data. Vector V is also called dummy data. In a codeword, dummy bits (i.e., dummy data) are used to fill the data length of deleted information bits (i.e., written data) or to fill the data length of deleted parity bits (i.e., parity data). In one exemplary embodiment, if some bits (i.e., some data) of the parity bits (i.e., parity data) are deleted, the codeword CW may be represented as [MPV], and the parity bits and dummy bits may be combined into new parity bits (i.e., new error correction codes or error checking codes). Accordingly, vectors P and V can be merged into vector P', and codeword CW can be represented as [MP']. Vector P' can be used to correct any errors that may exist in vector M. In another exemplary embodiment, if some bits (i.e., some data) in the information bits (i.e., written data) are deleted, codeword CW can be represented as [MVP]. The information bits and virtual bits can be merged into new information bits. Accordingly, vectors M and V can be merged into vector M', and codeword CW can be represented as [M'P]. Vector P can be used to correct any errors that may exist in vector M'.

[0078] In one exemplary embodiment, when decoding a codeword CW, a parity check operation is first performed on the codeword CW, for example, by multiplying the matrix H with the codeword CW to produce a vector (hereinafter referred to as S, as shown in equation (2) below). Each element in the vector S is also called a syndrome. The vector S is also called the syndrome data. If the vector S is a zero vector (i.e., every element in the vector S is zero), the codeword CW can be output directly. If the vector S is not a zero vector (i.e., at least one element in the vector S is not zero), it indicates that there is at least one error in the codeword CW and the codeword CW is not a valid codeword. If the codeword CW is not a valid codeword, the error checking and correction circuit 54 can perform a decoding operation to attempt to correct the error in the codeword CW.

[0079]

[0080] In one exemplary embodiment, the error checking and correction circuit 54 performs an iterative decoding operation. An iterative decoding operation is used to decode a piece of data from the rewritable non-volatile memory module 43. The decoding unit is, for example, a codeword. In an iterative operation, a parity check operation to check the correctness of the data and a decoding operation to correct errors in the data are repeatedly executed until decoding is successful or the number of iterations reaches a termination number. Specifically, if the number of iterations reaches this termination number, it indicates decoding failure, and the error checking and correction circuit 54 stops decoding. The value of the termination number can be designed according to actual needs, and the present invention is not limited thereto. Furthermore, if the parity check operation determines that there are no errors in the data, the error checking and correction circuit 54 outputs the data.

[0081] In one exemplary embodiment, the error checking and correction circuit 54 supporting low-density parity checking codes can use reliability information to perform the decoding operation. The reliability information can be, for example, the Log Likelihood Ratio (LLR). Specifically, during the decoding operation, the error checking and correction circuit 54 (or the decoding circuit 543) can use the LLR to decode the data read by the memory management circuit 51.

[0082] In one exemplary embodiment, the larger the absolute value of the logarithmic probability ratio (which may be positive or negative) corresponding to a data point (or bit value), the higher the reliability of the data, meaning that the data bit value has a high probability of being correct. Conversely, the smaller the absolute value of the logarithmic probability ratio corresponding to the data, the lower the reliability of the data, meaning that the data bit value has a high probability of being incorrect. For example, when the logarithmic probability ratio is 0, it means that the probability of the corresponding data point (or bit value) being 0 is the same as the probability of it being 1. For example, when the logarithmic probability ratio is positive and the larger the value, the higher the probability of the corresponding data point (or bit value) being 1. For example, when the logarithmic probability ratio is negative and the smaller the value, the higher the probability of the corresponding data point (or bit value) being 0. The range of the logarithmic probability ratio is determined by the bit width supported by the decoding circuit 543 of the error checking and correction circuit 54. Taking a bit width of 5 bits as an example, the range of the logarithmic probability ratio is -15 to +15.

[0083] Figure 7 This is a schematic diagram illustrating the management of the first codeword and the second codeword according to an exemplary embodiment of the present invention. Please refer to... Figure 7 Suppose that the first data 701 read from the rewritable non-volatile memory module 43 is missing a first part (e.g., 4 bits), wherein the first data 701 consists of write data and parity data, and in order to accommodate the actual writable length, one of the write data and parity data is deleted from the first part.

[0084] The memory management circuit 51 can combine first virtual data D1 (e.g., "0000") of the same size as the first part and first data 701 (e.g., "101100101011") to form a first codeword to fill in the deleted first part. Generally, the virtual data D1 is preset to 0 (i.e., "0000"), and the logarithmic probability ratio corresponding to the virtual data D1 is also preset to "0, 0, 0, 0". To further explain, since the probability value of the actually deleted part of the data (i.e., the first part missing from the first data 701) being 0 or the probability value of being 1 should be the same, the logarithmic probability ratio corresponding to the virtual data D1 filled in by the memory management circuit 51 should be preset to "0, 0, 0, 0". In addition, the first data 701 read from the rewritable non-volatile memory module 43 has a certain degree of reliability. Therefore, the logarithmic probability ratio corresponding to the first data 701 can be expressed as "+8, -8, +8, +8, -8, -8, +8, -8, +8, -8, +8, -8, +8, +8".

[0085] In one exemplary embodiment, the decoding preprocessing circuit 542 first performs a parity check on the first codeword to generate parity data. If the parity data is zero, it indicates that the first codeword has no errors, and the decoding preprocessing circuit 542 can directly output the first codeword. Conversely, if the parity data is not zero, the decoding preprocessing circuit 542 can perform a decoding operation (also called the first decoding operation) based on the virtual data D1 to update the virtual data D1. The decoding preprocessing circuit 542 can perform a decoding operation based on the virtual data D1 to attempt to correct errors in the virtual data D1, so that the errors in the virtual data D1 tend to converge. Further explanation: since the reliability of the virtual data D1 supplemented by the memory management circuit 51 is lower than the reliability of the first data 701 read from the rewritable non-volatile memory module 43, the virtual data D1 may need to be decoded multiple times to converge. If the complete first codeword is directly decoded, the high number of iterations and low decoding efficiency will result due to the difficulty in converging the virtual data D1. Therefore, the memory management circuit 51 (decoding preprocessing circuit 542) can first perform a first decoding operation based on the virtual data D1 to increase the reliability of the virtual data D1, thereby achieving the effect of improving the decoding speed.

[0086] In one exemplary embodiment, the error checking and correction circuit 54 can be used to perform bit-flipping decoding operations and / or low-density parity-checking decoding operations, wherein during the bit-flipping decoding operation, the error checking and correction circuit 54 does not need to use the logarithmic probability ratio. Further, in the bit-flipping operation, the decoding preprocessing circuit 542 only needs to consider the number of non-zero checksums associated with each bit in the codeword. If the number of non-zero checksums associated with a bit is greater than a preset threshold, it indicates that the probability of error for this bit is extremely high, and the decoding preprocessing circuit 542 can flip the value of this bit.

[0087] For example, suppose matrix H is:

[0088]

[0089] The codeword CW consists of 16 elements (e.g., 16 bits):

[0090]

[0091] Then vector S is a vector containing 4 elements:

[0092]

[0093] Vector S can be expanded into four verification equations:

[0094]

[0095] If vector S is a zero vector (i.e., every element in vector S is zero), the codeword CW can be directly output. If vector S is not a zero vector (i.e., at least one element in vector S is not zero), the error checking and correction circuit 54 can calculate the number of non-zero checksums among all checksums associated with each bit in the codeword (i.e., the number of invalid checksums among all check equations associated with each bit in the codeword), and determine whether this number is greater than a preset threshold. Using bit b1 as an example, the check equations (checksums) associated with bit b1 are s3 and s4. Assuming that checksums s3 and s4 are both non-zero, the number of invalid (non-zero) check equations (checksums) associated with bit b1 is 2. The error checking and correction circuit 54 can further determine whether this number (i.e., 2) is greater than a preset threshold (e.g., 1), and in response to this number being greater than the preset threshold, the value of bit b1 is flipped. The same logic applies to bits b2 to b9, so it will not be repeated here. Furthermore, the value of the preset threshold can be designed according to actual needs, and the present invention does not impose any limitations.

[0096] In one exemplary embodiment, the decoding preprocessing circuit 542 may first perform a bit-flipping decoding operation (also known as a first decoding operation) based on the virtual data D1 to update the virtual data D1 to virtual data D2 (also known as second virtual data). Figure 7 As shown, the virtual data D1 consists of 4 bits (i.e., "0 0 0 0"). When decoding a first codeword, if the checksum data is not zero, the decoding preprocessing circuit 542 can only count the number of non-zero checksums among all checksums associated with each bit of the virtual data D1 in the first codeword, without counting the bits in the first data, to improve decoding speed. The decoding preprocessing circuit 542 can calculate the number of non-zero checksums among all checksums associated with each bit of the virtual data D1, and perform bit flipping in response to this number being greater than a preset threshold. Figure 7 For example, if the number of non-zero checksums associated with the first bit in virtual data D1 is greater than a preset threshold, the decoding preprocessing circuit 542 can flip the value of the first bit in virtual data D1 to 1. Conversely, if the number of non-zero checksums associated with other bits in virtual data D1 is not greater than the preset threshold, the decoding preprocessing circuit 542 does not flip the values ​​of other bits in virtual data D1.

[0097] Subsequently, the decoding preprocessing circuit 542 can assemble the first data 701 and the virtual data D2 into a second codeword, and provide the second codeword to the decoding circuit 543. It should be noted that since the decoding preprocessing circuit 542 only performs the first decoding operation on the virtual data D1, the reliability of the first data 701 remains unchanged, and the reliability of the virtual data D1 (i.e., virtual data D2) after the first decoding operation increases. In other words, the logarithmic probability ratio corresponding to the first data 701 of the second codeword is equal to the logarithmic probability ratio corresponding to the first data 701 of the first codeword, and the absolute value of the logarithmic probability ratio corresponding to the virtual data D2 of the second codeword (e.g., "+5, -5, -5, -5") is greater than the absolute value of the logarithmic probability ratio corresponding to the virtual data D1 of the first codeword.

[0098] Next, the decoding circuit 543 performs a parity check on the second codeword to generate parity data. If the parity data is zero, it indicates that there is no error in the second codeword, and the decoding circuit 543 can directly output the second codeword.

[0099] On the other hand, if the parity check data is not zero, the decoding circuit 543 can perform a decoding operation (also called the second decoding operation) based on the second codeword, where the first decoding operation and the second decoding operation use the same parity check matrix. The second decoding operation is a low-density parity check decoding operation. The decoding circuit 543 can use the reliability information (i.e., the logarithmic probability ratio) corresponding to the second codeword to perform the second decoding operation based on the second codeword, thereby attempting to correct errors in the second codeword. If all errors in the second codeword are corrected, the memory management circuit 51 (error checking and correction circuit 54) can output the second codeword. Conversely, if the errors in the second codeword have not been completely corrected, the memory management circuit 51 can determine whether the current iteration count has reached the termination count. If the current iteration count has reached the termination count, it indicates that decoding has failed, and the error checking and correction circuit 54 will stop decoding the first data 701. Conversely, if the current iteration count has not reached the termination count, the decoding preprocessing circuit 542 can perform a first decoding operation on the virtual data D2 to converge the errors in the virtual data D2 and update the codeword. Then, the decoding circuit 543 performs a second decoding operation based on the updated codeword, and iterates until it is determined that the decoding is successful (i.e., the codeword is output) or the decoding fails (i.e., the iteration count has reached the termination count).

[0100] Based on the above, the error checking and correction circuit 54 can first perform the first decoding operation based only on the virtual data D1 with low reliability to converge the errors in the virtual data D1, and then combine the updated virtual data D1 (i.e., virtual data D2) with the first data 701 read from the rewritable non-volatile memory module 43 to form a second codeword, and then perform the second decoding operation based on the second codeword, which can improve the decoding speed.

[0101] It is worth noting that the decoding algorithm corresponding to the first decoding operation is different from the decoding algorithm corresponding to the second decoding operation. The first decoding operation is a bit-flipping decoding operation. The second decoding operation is a low-density parity-check decoding operation based on reliability information (i.e., the logarithmic probability ratio). The decoding preprocessing circuit 542 can first perform a bit-flipping decoding operation based on the virtual data D1 to improve the reliability of the virtual data D1. Then, the decoding circuit 543 can perform a low-density parity-check decoding operation based on reliability information based on the second codeword composed of the virtual data D2 with higher reliability (i.e., the virtual data D1 after the bit-flipping decoding operation) and the first data 701. In this way, both the decoding success rate and the decoding speed can be improved.

[0102] Figure 8 This is a flowchart illustrating a memory management method according to an exemplary embodiment of the present invention. Please refer to... Figure 8 In step S801, the first virtual data D1 and the first data 701 read from the rewritable non-volatile memory module 43 are combined to form a first codeword. In step S802, a first decoding operation is performed based on the first virtual data D1 to update the first virtual data D1, thereby obtaining the second virtual data D2. In step S803, the first data 701 and the second virtual data D2 are combined to form a second codeword. In step S804, a second decoding operation is performed based on the second codeword. However, Figure 8 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 8 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figure 8 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0103] In summary, the memory management method, memory storage device, and memory control circuit unit provided in the exemplary embodiments of the present invention improve the decoding speed by performing the decoding operation based only on virtual data before performing the decoding operation based on the complete codeword.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method for a rewritable non-volatile memory module, the memory management method comprising: The first virtual data and the first data read from the rewritable non-volatile memory module are combined to form the first codeword; Perform a first decoding operation based on the first virtual data to update the first virtual data, thereby obtaining the second virtual data; Combine the first data and the second virtual data to form a second codeword; and Perform a second decoding operation based on the second codeword.

2. The memory management method according to claim 1, wherein the first data consists of write data and parity data, and a portion of the write data or the parity data has been deleted.

3. The memory management method according to claim 2, wherein the first virtual data is used as the partial data.

4. The memory management method according to claim 2, further comprising: The written data is encoded to generate the parity data; The data in the written data or the parity data is deleted, and then the written data and the parity data, or the parity data and the written data, are stored in the rewritable non-volatile memory module.

5. The memory management method according to claim 2, further comprising: In response to the deletion of the parity data, the parity data with the deleted portion of data is combined with the first virtual data to form an error correction code, and the first decoding operation is performed on the first virtual data using the error correction code.

6. The memory management method according to claim 2, further comprising: In response to the deletion of the written data, the parity data is used as an error correction code, and the first decoding operation is performed on the first virtual data using the error correction code.

7. The memory management method according to claim 1, wherein the first decoding operation and the second decoding operation use the same parity check matrix.

8. The memory management method according to claim 1, wherein the logarithmic probability ratio corresponding to the first virtual data is zero.

9. The memory management method according to claim 1, wherein the absolute value of the logarithmic probability ratio corresponding to the second virtual data is greater than the absolute value of the logarithmic probability ratio corresponding to the first virtual data.

10. The memory management method according to claim 1, wherein the decoding algorithm corresponding to the first decoding operation is different from the decoding algorithm corresponding to the second decoding operation.

11. The memory management method according to claim 1, wherein the first decoding operation is a bit-flipping decoding operation.

12. The memory management method according to claim 11, further comprising: In the bit-flipping decoding operation, the value of the bit is flipped in response to the number of non-zero checksums associated with the bit in the first virtual data being greater than a preset threshold.

13. The memory management method according to claim 1, wherein the second decoding operation is a low-density parity check decoding operation.

14. A memory storage device, comprising: Connect the interface unit to the host system; Rewritable non-volatile memory module; as well as The memory control circuit unit is connected to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to: The first virtual data and the first data read from the rewritable non-volatile memory module are combined to form the first codeword. A first decoding operation is performed based on the first virtual data to update the first virtual data, thereby obtaining the second virtual data. The first data and the second virtual data are combined to form the second codeword. Perform a second decoding operation based on the second codeword.

15. The memory storage device of claim 14, wherein the first data comprises write data and parity data, and a portion of the write data or the parity data has been deleted.

16. The memory storage device of claim 15, wherein the first virtual data is used as the partial data.

17. The memory storage device according to claim 15, wherein the memory control circuit unit is further configured to: The written data is encoded to generate the parity data; The data in the written data or the parity data is deleted, and then the written data and the parity data, or the parity data and the written data, are stored in the rewritable non-volatile memory module.

18. The memory storage device according to claim 15, wherein the memory control circuit unit is further configured to: In response to the deletion of the parity data, the parity data with the deleted portion of data is combined with the first virtual data to form an error correction code, and the first decoding operation is performed on the first virtual data using the error correction code.

19. The memory storage device according to claim 15, wherein the memory control circuit unit is further configured to: In response to the deletion of the written data, the parity data is used as an error correction code, and the first decoding operation is performed on the first virtual data using the error correction code.

20. The memory storage device of claim 14, wherein the first decoding operation and the second decoding operation use the same parity check matrix.

21. The memory storage device of claim 14, wherein the logarithmic probability ratio corresponding to the first virtual data is zero.

22. The memory storage device of claim 14, wherein the absolute value of the logarithmic probability ratio corresponding to the second virtual data is greater than the absolute value of the logarithmic probability ratio corresponding to the first virtual data.

23. The memory storage device according to claim 14, wherein the decoding algorithm corresponding to the first decoding operation is different from the decoding algorithm corresponding to the second decoding operation.

24. The memory storage device according to claim 14, wherein the first decoding operation is a bit-flipping decoding operation.

25. The memory storage device according to claim 24, wherein the memory control circuit unit is further configured to: In the bit-flipping decoding operation, the value of the bit is flipped in response to the number of non-zero checksums associated with the bit in the first virtual data being greater than a preset threshold.

26. The memory storage device of claim 14, wherein the second decoding operation is a low-density parity check decoding operation.

27. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising: The host interface connects to the connection interface unit; A memory interface is provided for connecting the rewritable non-volatile memory module. as well as The memory management circuit is connected to the host interface and the memory interface. The memory management circuit mentioned above is used for: The first virtual data and the first data read from the rewritable non-volatile memory module are combined to form the first codeword. A first decoding operation is performed based on the first virtual data to update the first virtual data, thereby obtaining the second virtual data. The first data and the second virtual data are combined to form the second codeword. Perform a second decoding operation based on the second codeword.

28. The memory control circuit unit of claim 27, wherein the first data consists of write data and parity data, and a portion of the write data or the parity data has been deleted.

29. The memory control circuit unit of claim 28, wherein the first virtual data is used as the partial data.

30. The memory control circuit unit according to claim 28, wherein the memory management circuit is further configured to: The written data is encoded to generate the parity data; The data in the written data or the parity data is deleted, and then the written data and the parity data, or the parity data and the written data, are stored in the rewritable non-volatile memory module.

31. The memory control circuit unit according to claim 28, wherein the memory management circuit is further configured to: In response to the deletion of the parity data, the parity data with the deleted portion of data is combined with the first virtual data to form an error correction code, and the first decoding operation is performed on the first virtual data using the error correction code.

32. The memory control circuit unit according to claim 28, wherein the memory management circuit is further configured to: In response to the deletion of the written data, the parity data is used as an error correction code, and the first decoding operation is performed on the first virtual data using the error correction code.

33. The memory control circuit unit of claim 27, wherein the first decoding operation and the second decoding operation use the same parity check matrix.

34. The memory control circuit unit of claim 27, wherein the logarithmic probability ratio corresponding to the first virtual data is zero.

35. The memory control circuit unit according to claim 27, wherein the absolute value of the logarithmic probability ratio corresponding to the second virtual data is greater than the absolute value of the logarithmic probability ratio corresponding to the first virtual data.

36. The memory control circuit unit according to claim 27, wherein the decoding algorithm corresponding to the first decoding operation is different from the decoding algorithm corresponding to the second decoding operation.

37. The memory control circuit unit according to claim 27, wherein the first decoding operation is a bit-flipping decoding operation.

38. The memory control circuit unit according to claim 37, wherein the memory management circuit is further configured to: In the bit-flipping decoding operation, the value of the bit is flipped in response to the number of non-zero checksums associated with the bit in the first virtual data being greater than a preset threshold.

39. The memory control circuit unit according to claim 27, wherein the second decoding operation is a low-density parity check decoding operation.

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