Cache consistency control method, consistency directory and processor chip

Abstract

The embodiment of the invention provides a cache consistency control method, a consistency directory and a processor chip, and the method comprises the steps: responding to an access request of a first core for a target cache line for the first time, and distributing a first directory entry in the consistency directory; the first directory entry is used for recording an address tag of the target cache line and a first sharer; the first sharer comprises the first core; in response to an access request of a second core to the target cache line, distributing a second directory entry in the consistency directory; the second directory entry is used for recording a target path pointer and a second sharer; the target path pointer points to the first directory entry; the second sharer comprises the second core; the number of the second cores is greater than or equal to 1. According to the embodiment of the invention, the cache line copy position under the many-core condition can be accurately represented while a relatively low width of a single directory entry is kept, so that the hardware overhead can be saved, and the system performance can be improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a cache coherency control method, a coherency catalog, and a processor chip. Background Technology

[0002] In multi-core processor systems, each core typically has its own private cache to improve data access speed. However, when multiple cores simultaneously access and modify the same data in shared memory, data inconsistencies may arise between the private caches. Therefore, cache coherence protocols are needed to ensure correct execution.

[0003] In cache coherence protocols, the coherence directory is widely used to track the distribution of shared data across core caches. A cache line may be shared by multiple cores, in which case each core's private cache contains a copy of that cache line. To represent all possible copy locations (i.e., all possible sharing scenarios for the cache line), a bit vector with a length equal to the number of processor cores is needed. This causes the directory entry width to increase with the number of cores, making it difficult to scale to many-core processors.

[0004] As processors enter the many-core era, with the number of cores increasing to hundreds or even thousands, traditional directory structures face a dilemma: if accurate records are maintained, the width of directory entries increases linearly with the number of cores, resulting in excessive hardware overhead and impacting system performance. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a cache consistency control method that overcomes or at least partially solves the above problems. This method can accurately represent the cache line copy location in a multi-core scenario while maintaining a low single directory entry width, thereby saving hardware overhead and improving system performance.

[0006] Accordingly, embodiments of the present invention also provide a consistency catalog and processor chip to ensure the implementation and application of the above methods.

[0007] In a first aspect, embodiments of the present invention disclose a cache consistency control method, the method comprising: In response to the first core's initial access request to the target cache line, a first directory entry is allocated in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; In response to a second core's access request to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

[0008] Secondly, embodiments of the present invention disclose a consistency catalog applied to a multi-core processor system, the consistency catalog comprising: Directory storage, configured to store multiple directory entries; and The directory controller, coupled to the directory storage, is configured as follows: In response to the first core's initial access request to the target cache line, a first directory entry is allocated in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; In response to a second core's access request to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

[0009] Thirdly, embodiments of the present invention disclose a processor chip, comprising: Multiple processor cores, each core including a private cache for storing copies of cache lines; On-chip network, providing interconnect communication paths between the multiple processor cores and the consistency catalog subsystem; and The consistency catalog subsystem, coupled to the on-chip network, is configured as follows: In response to the first core's initial access request to the target cache line, a first directory entry is allocated in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; In response to a second core's access request to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

[0010] The embodiments of the present invention have the following advantages: This invention uses multiple directory entries to record the distribution information of cache line replicas at the same address, and only records the address label in the first directory entry. For example, for the target cache line corresponding to address A, only the address label of address A is recorded in the first directory entry, and only a few bits are used in the second directory entry to record the target path pointer, pointing to the first directory entry where the address label of address A is stored. Thus, the first directory entry can be found through the target path pointer in the second directory entry to obtain the memory address in the address label. This invention avoids storing the address label in each directory entry. Storing the address label typically requires 30 bits, while storing the path pointer only requires a few bits; for example, in a 16-way system, the path pointer only requires 4 bits. Storing the same information requires fewer directory entries, and the width of a single directory entry is lower. Therefore, this invention can accurately represent the cache line replica location in a many-core scenario while maintaining a low width of a single directory entry, thereby saving hardware overhead and improving system performance. Attached Figure Description

[0011] Figure 1 This is a flowchart illustrating the steps of an embodiment of the cache consistency control method of the present invention; Figure 2 This is a schematic diagram of the format of a first directory item in Example 1 of the present invention; Figure 3 This is a schematic diagram of the format of a second directory item in Example 1 of the present invention; Figure 4 This is a schematic diagram of the format of each directory item in an example of the present invention; Figure 5 This is a schematic diagram of allocating and updating directory entries in Example 2 of the present invention. Figure 6 This is a structural block diagram of an embodiment of the cache consistency control device of the present invention; Figure 7 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Detailed Implementation

[0012] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0013] The terms "first," "second," etc., used in the specification and claims of this invention are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, the first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In embodiments of this invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0014] Reference Figure 1 The diagram illustrates a flowchart of an embodiment of a cache consistency control method according to the present invention. The method may include the following steps: Step 101: In response to the first core's first access request to the target cache line, allocate a first directory entry in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; Step 102: In response to the second core's access request to the target cache line, allocate a second directory entry in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

[0015] The cache consistency control method provided in this invention can be applied to multi-core processor systems. A multi-core processor system refers to a computing system integrating multiple processor cores, each of which can independently execute instructions and has concurrent access requirements to shared memory. Each core contains a private cache for storing copies of cache lines; a cache line is a data block of fixed size in the system's main memory. Multiple cores are interconnected via an on-chip network and share the system's main memory. The system further includes a consistency catalog subsystem, which maintains the distribution information of the copies of the cache lines in the private cache through the consistency catalog. The multi-core processor system can be a single multi-core chip or a multi-processor system composed of multiple chips, covering computing devices such as servers, personal computers, and embedded devices.

[0016] Each processor core can independently execute program instructions, process data, and includes a private Level 1 cache (L1 cache) and Level 2 cache (L2 cache). The multi-core processor system may further include a shared LLC (Last Level Cache), which is accessed by all cores via an on-chip network.

[0017] It should be noted that this application does not limit the specific cache hierarchy. The private cache can be single-level (e.g., L1 cache only) or multi-level (e.g., L1 and L2 caches); the L2 cache can be private to each core or shared by a cluster of multiple cores; the last-level cache can be chip-level shared or distributed. Regardless of the cache hierarchy, as long as multiple private caches exist and data consistency needs to be maintained among them, the technical solution provided in this application is applicable.

[0018] It is understood that the multi-core processor system may contain 2, 4, 8, 16, 32, 64 or more cores, and increasing the number of cores does not affect the applicability of the technical solution of this application. The consistency directory uses an on-chip SRAM (Static Random-Access Memory) as a carrier, and each directory entry in the directory is used to maintain the distribution information of a copy of a cache line in the private cache. The consistency directory can be centralized or distributed, and can be integrated into an LLC or used as an independent module.

[0019] Furthermore, the consistency catalog subsystem may include a consistency catalog and a catalog controller; the catalog controller is used to maintain the consistency catalog in response to the kernel's access request for cached lines, including allocating catalog entries, updating sharer information in catalog entries, and invalidating catalog entries, etc.

[0020] The objective of this invention is to accurately represent the location of cache line replicas in a many-core scenario while maintaining a low width for a single directory entry. Based on this, in this embodiment, the directory entries of the consistency directory include a first directory entry and a second directory entry.

[0021] The first directory entry can be used to record the address tag of a cache line (e.g., the target cache line) and a corresponding sharer. The first directory entry can be used when the target cache line has only one copy. When the number of copies of the target cache line is greater than one, one first directory entry and at least one second directory entry can be used. The second directory entry can be used to record the path pointer (e.g., the target path pointer) pointing to the corresponding first directory entry and at least one sharer.

[0022] Recording sharers can be done through methods such as recording sharer pointers, recording a list of sharer pointers, or recording a sharer vector. A sharer pointer uniquely identifies a sharer (i.e., a processor core), and this pointer can be a core identifier (Core ID) or a core sequence number. A sharer vector is a vector where each bit indicates whether a core is a sharer.

[0023] In response to the first core's initial access request to the target cache line, the consistency catalog subsystem allocates a first catalog entry in the consistency catalog; the first catalog entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core.

[0024] It should be noted that the first core and the second core can be any core in the multi-core processor system. The target cache line can be any cache line in the system's main memory.

[0025] In Example 1, in response to the first access request from the first core (e.g., cpu0) to the target cache line corresponding to address A, a first directory entry is allocated in the consistency directory. This first directory entry records the address label of the target cache line and the first sharer. The access request refers to a read request. For example, the first directory entry uses a sharer pointer to record the first sharer, and this sharer pointer points to the first core (cpu0). The address label can be the high-order bits of the memory address of the target cache line (e.g., address A).

[0026] Reference Figure 2 The diagram illustrates the format of a first directory entry in Example 1.

[0027] Next, in response to an access request from a second core (such as CPU1) to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to... Figure 2 The first directory entry; the second sharer includes the second core (cpu1). For example, if the second directory entry uses a sharer pointer list to record the second sharer, then the sharer pointer list contains pointers to cpu1.

[0028] Reference Figure 3 The diagram illustrates the format of a second directory entry in Example 1.

[0029] It should be noted that, in this embodiment of the invention, the first sharer refers to the sharer of the target cache line recorded in the first directory entry (such as cpu0 in Example 1). For the target cache line, after the first directory entry is created, as the number of replicas increases, a second directory entry may be created. The second directory entry may only record the second sharer and not the first sharer (such as cpu0 in Example 1). Figure 3 (As shown); or, in addition to recording the second sharer, the second directory entry may also record the first sharer again (as shown). Figure 3 (Not shown). In this embodiment of the invention, whether or not the sharer is recorded repeatedly does not affect the correctness of the consistency directory. When a copy of the target cache line becomes invalid, all duplicate records can be cleared simultaneously. Therefore, this embodiment of the invention does not restrict whether the sharer is recorded repeatedly in the directory entry.

[0030] For the same target cache line, if there are more than 1 replicas, one first directory entry and at least one second directory entry can be allocated. Each second directory entry contains a target path pointer to the corresponding first directory entry.

[0031] It is understandable that the above explanation uses the cache line corresponding to address A as an example. For any cache line, such as the cache line corresponding to address B, the process of generating a directory entry when the kernel accesses that cache line is similar.

[0032] This invention uses multiple directory entries to record the distribution information of cache line replicas at the same address, and records the address label only in the first directory entry. For example, for the target cache line corresponding to address A, only the address label of address A is recorded in the first directory entry, and only a few bits are used in the second directory entry to record the target path pointer, pointing to the first directory entry where the address label of address A is stored. Thus, the first directory entry can be found through the target path pointer in the second directory entry to obtain the memory address corresponding to the address label. This invention avoids storing the address label in each directory entry. Storing the address label typically requires 30 bits, while storing the path pointer only requires a few bits; for example, in a 16-way system, the path pointer only requires 4 bits. Storing the same information requires fewer directory entries, and the width of a single directory entry is lower. Therefore, this invention can accurately represent the cache line replica location in a many-core scenario while maintaining a low width of a single directory entry, thereby saving hardware overhead and improving system performance.

[0033] Furthermore, in this embodiment of the invention, the directory entries of the consistency directory also include empty directory entries. The empty directory entries do not record any sharers and can be assigned.

[0034] Furthermore, each directory entry in the consistency directory may include a format identifier, which indicates the type of the directory entry; the type includes, but is not limited to, a first directory entry, a second directory entry in a first format, a second directory entry in a second format, or an empty directory entry.

[0035] In an optional embodiment of the present invention, when the number of the second cores does not exceed a preset value, the second directory entry is in a first format, in which a pointer list is used to record the second sharers; or... When the number of the second cores exceeds a preset value, the second directory entry is in a second format. The second directory entry in the second format also includes a segment identifier and a sharer vector corresponding to the segment identifier; wherein, different segment identifiers specify multiple different processor cores; each bit of the sharer vector is used to indicate a second sharer.

[0036] For example, the sharer vector can take the form of a bitmap, which is a data structure consisting of multiple binary bits, where each bit corresponds to a processor core, and the value of the bit (0 / 1) is used to indicate whether the corresponding core holds a copy of the corresponding cache line.

[0037] Reference Figure 4 The diagram illustrates the format of each directory item in an example of the present invention. Figure 4 As shown, the consistency directory can include directory entries in the following four formats: Invalid format (00): indicates that the directory entry is invalid or empty.

[0038] Tag format (01): This indicates that the directory entry records an address tag and a sharer of the target cache line corresponding to that address tag. The tag format directory entry is the first directory entry, or simply a tag directory entry.

[0039] Finite pointer format (10): indicates that the directory entry records a target path pointer and one or more sharers of the target cache line corresponding to the address label in the first directory entry pointed to by the target path pointer.

[0040] Segment vector format (11): This indicates that the directory entry records a target path pointer, a segment identifier, and a sharer vector corresponding to the segment identifier; the sharer vector records one or more sharers of the target cache line corresponding to the address label in the first directory entry pointed to by the target path pointer, and the one or more sharers belong to the processor core corresponding to the segment identifier.

[0041] Among them, 00, 01, 10 and 11 are format identifiers, indicating the type of directory entry.

[0042] To further improve the range of processor cores that the present invention can accurately represent, the embodiments of the present invention provide two formats of second directory entries: a first format of second directory entries and a second format of second directory entries. The first format of second directory entries is the directory entry of the above-mentioned finite pointer format (10), which is also referred to as the finite pointer directory entry for ease of description below. The second format of second directory entries is the directory entry of the above-mentioned segment vector format (11), which is also referred to as the segment vector directory entry for ease of description below.

[0043] The main difference between finite pointer directory entries and segment vector directory entries is that the former uses a list of sharer pointers to record sharers, while the latter uses a segment vector (i.e., a sharer vector) to record sharers.

[0044] When there are only one copy of the target cache line, a single first directory entry can be used. When the number of copies of the target cache line is small (e.g., not exceeding the preset value), a first directory entry and at least one finite pointer directory entry can be used. When the number of copies of the target cache line is large (e.g., exceeding the preset value), a first directory entry and at least one segment vector directory entry can be used.

[0045] The maximum number of second cores that can be recorded in the sharer pointer list in the finite pointer directory entry is a preset value. When the number of second cores accessing the same target cache line exceeds the preset value, the segment vector directory entry can be used instead. The segment vector directory entry also includes a segment identifier and the sharer vector corresponding to the segment identifier.

[0046] The segment vector directory entry records the second sharer of a target cache line using a segment vector. A segment vector refers to dividing the entire core set into multiple segments, with each segment using a vector to indicate whether a core within that segment holds a copy of a particular cache line. Taking a multi-core processor system with 16 cores (e.g., CPU0 to CPU15) as an example, the 16 cores are divided into two segments, called segment 0 and segment 1. Segment 0 covers CPU0 to CPU7, and segment 1 covers CPU8 to CPU15. Segment 0 uses a vector to indicate whether any core in CPUs 0 to 7 holds a copy of a particular cache line. Segment 1 uses a vector to indicate whether any core in CPUs 8 to 15 holds a copy of a particular cache line. For example, each bit in the vector corresponds to a core; a bit of 0 indicates that the core does not hold a copy of the cache line, and a bit of 1 indicates that the core holds a copy of the cache line.

[0047] For example, in Example 1, suppose CPU1 accesses the target cache line, and then CPU3 and CPU5 access the target cache line. Assuming a target cache line can create a maximum of finite pointer directory entries, with a default value of 2, the number of second cores holding copies of the target cache line is 3 (CPU1, CPU3, and CPU5), exceeding the default value. The finite pointer directory entries are insufficient, and segment vector directory entries are needed. For example, we can... Figure 3 The second directory entry shown is converted from the first format to the second format, that is, the finite pointer directory entry is converted into a segment vector directory entry. The converted directory entry includes a target path pointer, pointing to the corresponding first directory entry; it also includes a segment identifier (such as the identifier of segment 0) and the sharer vector corresponding to the segment identifier, such as 00101010. For example, it is agreed that the least significant bit (the rightmost bit) is bit 0, and the bits increment sequentially to the left. The sharer vector 00101010 corresponds to cpu0 to cpu7 from bit 0 to bit 7, that is, bit 0 corresponds to cpu0, bit 1 corresponds to cpu1, and so on. The first, third, and fifth bits of the sharer vector 00101010 are set to 1, and the remaining bits are 0, indicating that the sharers of the target cache line include cpu1, cpu3, ​​and cpu5.

[0048] In an optional embodiment of the present invention, the first directory entry may further include a status identifier, which is used to record the consistency status of the target cache line. Specifically, any cache consistency protocol such as MESI or MOESI can be used; the technical solution of this application does not depend on a specific protocol.

[0049] The four letters in the MESI protocol represent four states. M stands for Modified, meaning the data in the cache line has been modified but not yet written back to main memory; it can also be understood as dirty data. E stands for Exclusive, meaning the data in the cache line exists only in the current CPU's cache and is consistent with the data in main memory. S stands for Shared, meaning the data in the cache line exists in multiple CPU caches and is consistent with the data in main memory. I stands for Invalidated, meaning the data in the cache line is invalid and cannot be read. The MOESI protocol adds an Owned (O) state to the MESI protocol. O represents data shared across multiple caches and is considered dirty data; only one cache is responsible for eventually writing it back to main memory.

[0050] In this embodiment of the invention, the status identifier in the first directory entry is determined by a consistency protocol. For example, in Example 1, when CPU0 accesses the target cache line, a first directory entry is created, and the status identifier in that first directory entry is set to status E. When other processor cores subsequently access the target cache line, the status identifier in the first directory entry is updated to status S.

[0051] Furthermore, the consistency directory can adopt a multi-group structure, with each group including at least one directory entry. Each directory entry in each group corresponds to the same index. The index is used to locate the corresponding target group when searching the consistency directory. This embodiment of the invention does not limit the number of paths in each group; it is typically determined based on the chip specifications, such as 4 to 32 paths, but more or fewer are also possible. The number of groups is determined based on the size of the core's private cache, and it is generally necessary to ensure that the total number of directory entries in the consistency directory is not less than the number of lines in the core's private cache.

[0052] Furthermore, the consistency catalog may include an SRAM array with a group-associative or mode-skewed associative structure; the SRAM array includes multiple SRAM rows, each SRAM row corresponding to a group in the consistency catalog; each SRAM row is divided into multiple storage areas, each storage area being used to independently store a catalog entry.

[0053] The SRAM array is divided into multiple path storage regions, each containing multiple SRAM rows, and each SRAM row is used to independently store a directory entry. SRAM rows with the same index in each storage region correspond to a group in the consistent directory. The path and group partitioning is orthogonal.

[0054] Using the consistency directory and cache consistency control method of this invention, regardless of whether a group-associative structure or a mode-skewed associative structure is adopted, it is possible to accurately represent the cache line copy location in a multi-core scenario while maintaining a low single directory entry width, thereby saving hardware overhead and improving system performance.

[0055] In Example 2, in response to the first core (e.g., CPU0)'s initial access request to the target cache line corresponding to address A, a first directory entry, i.e., a directory entry in label format (01), is allocated in the consistency directory. The address label and sharer pointer of the target cache line are recorded in this first directory entry; the sharer pointer points to the first core (CPU0). Then, in response to the second core (e.g., CPU1 and CPU3)'s access request to the target cache line, a finite pointer directory entry is allocated in the consistency directory; a target path pointer and a list of sharer pointers are recorded in this finite pointer directory entry; the target path pointer points to the first directory entry; the list of sharer pointers contains pointers to each second core (e.g., pointers to CPU1 and CPU3). Next, in response to the second core (e.g., CPU5)'s access request to the target cache line, where the number of second cores exceeds a preset value, the finite pointer directory entry is converted into a segment vector directory entry. Since the second sharers (CPU1, CPU3, and CPU5) correspond to the same segment identifier, only one segment vector directory entry is needed. Specifically, the original limited pointer directory entry can be overwritten using this segment bit vector directory entry. This segment bit vector directory entry records the target path pointer, the segment identifier (e.g., the identifier for segment 0), and the sharer vector corresponding to that segment identifier (e.g., 00101010). Finally, in response to CPU8's access request to the target cache line, since CPU8 corresponds to segment 1, which exceeds the core range supported by segment 0, a new segment bit vector directory entry needs to be allocated. This segment bit vector directory entry records the target path pointer, the segment identifier (e.g., the identifier for segment 1), and the sharer vector corresponding to that segment identifier (e.g., 00000001, indicating that CPU8 is a sharer).

[0056] It should be noted that in Example 2 above, the sharer vector corresponding to segment 0 corresponds to cpu0 to cpu7 from position 0 to position 7, respectively. The sharer vector corresponding to segment 1 corresponds to cpu8 to cpu15 from position 0 to position 7, respectively. That is, position 0 in sharer vector 00000001 corresponds to cpu8, and the value of position 0 is 1, indicating that cpu8 holds the target cache line.

[0057] It is understood that the number of segments in Example 2 above is only for illustrative purposes. In actual implementation, the number of segments can be expanded according to the increase in the number of cores.

[0058] Reference Figure 5 The diagram illustrates the assignment and updating of directory entries in Example 2. In this example, a group contains 3 paths, such as path 0, path 1, and path 2. Figure 5The first line in the code responds to a request from CPU0 to access the target cache line by allocating an empty directory entry for path 0, creating the state after the first directory entry is generated. At this point, the directory entries for paths 1 and 2 are still empty. The second line responds to requests from CPUs 1 and 3 to access the target cache line by allocating an empty directory entry for path 1, creating the state after a finite pointer directory entry is generated. At this point, the directory entry for path 2 is still empty. The third line responds to a request from CPU 5 to access the target cache line by converting the finite pointer directory entry for path 1 into a segment vector directory entry. The fourth line responds to a request from CPU 8 to access the target cache line by allocating an empty directory entry for path 2, creating the state after a new segment vector directory entry is generated. Figure 5 As shown, each line represents the status of the directory entry for address A in each path's possible storage location.

[0059] It should be noted that, Figure 5 The four rows shown represent that at any given time, only one of the four rows may be in the state shown in the four rows, and does not mean that all four rows may appear simultaneously.

[0060] In an optional embodiment of the present invention, the method may further include: Step S11: In response to the request of the first target core to remove the target cache line from its private cache, search for a first target directory entry in the consistency directory based on the target address of the target cache line; the address tag recorded in the first target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the first target directory entry points to the first directory entry whose address tag matches; and the first target directory entry records the first target core. Step S12: Clear the record information of the first target core from each first target directory entry.

[0061] In a multi-core processor system, each processor core has a limited private cache capacity. When the first target core (cpu0, for example) needs to load new data and its private cache capacity is insufficient, an existing cache line will be selected for eviction according to the replacement algorithm. If the evicted cache line contains the target cache line, the target cache line will be removed from the first target core's private cache, and the first target core will send a removal notification to the consistency catalog subsystem to update the catalog entry corresponding to the target cache line.

[0062] by Figure 5 The target cache line for CPU8 accessing address A is shown below ( Figure 5Taking the result of line 4 as an example, suppose the first target core (cpu0 for example) wants to remove the target cache line from its private cache. In response to the request from the first target core to remove the target cache line from its private cache, the first target directory entry is searched in the consistency directory based on the target address of the target cache line.

[0063] Furthermore, the method may also include: When searching the consistency directory based on the target address, the target group is located according to the index corresponding to the target address; and the target directory entry with the matching address tag is determined in the target group according to the address tag corresponding to the target address.

[0064] The target address can be a memory access address issued by the processor core, such as address A. This memory access address is typically divided into three fields: address tag, index, and offset. The address tag (e.g., the high-order bits) uniquely identifies a cache line in the cache or directory. The index (e.g., the middle bits) is used to select a specific group within the directory storage array. The offset (e.g., the low-order bits) is used to select a specific byte or word within the cache line (not used in directory lookups).

[0065] For example, in response to a request from a first target core to remove the target cache line from its private cache, the request carries a target address such as address A. Address tags and indexes can be extracted from address A. Based on the index extracted from address A, the consistency directory can be searched to locate the target group that matches that index. Based on the address tags extracted from address A, a search is conducted in the target group to find a matching directory entry with a matching address tag.

[0066] Specifically, to find a target group based on a specified address tag (such as the address tag extracted from address A), the following rules can be used to determine if a directory entry has been matched: if a directory entry in the target group has a format identifier of 01, and the address tag recorded in that directory entry matches the specified address tag, then the directory entry has been matched; or, if a directory entry in the target group has a format identifier of 10 or 11, and the target path pointer in that directory entry points to the first directory entry in the target group whose address tag has been matched (i.e., the address tag recorded in that first directory entry matches the specified address tag), then the directory entry has been matched. Figure 5 The three directory entries in line 4 shown represent all the hit directory entries in the target group. Furthermore, among these three hit directory entries, only the first directory entry of path 0 records the first target core (cpu0). Therefore, the first directory entry of path 0 is determined to be the first target directory entry. The record information of cpu0 is cleared from this first target directory entry, which means clearing the sharer pointer pointing to cpu0.

[0067] Furthermore, the method may also include: when the sharer pointer in the first directory entry corresponding to the target cache line is null, and the sharer pointer list in the second directory entry corresponding to the target cache line is not null, selecting a sharer from the sharer pointer list and moving it into the first directory entry.

[0068] For example, in this example, after clearing the sharer pointer pointing to cpu0 from the first directory entry of road 0, a sharer can be selected from the sharer pointer list of the finite pointer directory entry of road 1 (which records cpu1, cpu3, ​​and cpu5) and moved into the first directory entry of road 0. This embodiment of the invention does not restrict the selection method; it can be random or sequential. For example, if cpu1 is selected, the sharer pointer recorded in the updated first directory entry of road 0 will point to cpu1, and the sharer pointer list of the updated finite pointer directory entry of road 1 will record cpu3 and cpu5. It should be noted that after selecting a sharer from the sharer pointer list of the finite pointer directory entry and moving it into the corresponding first directory entry, the sharer can be removed from the finite pointer directory entry or retained. For example, the sharer pointer list of the updated finite pointer directory entry of road 1 will still record cpu1, cpu3, ​​and cpu5. Duplicate records do not affect the correctness of this scheme; when the first target core removes the target cache line from its private cache, the above steps can simultaneously clear duplicate records.

[0069] It is understandable that updating a directory entry means overwriting the original directory entry with the updated one. For example, the updated first directory entry for road 0 overwrites the original first directory entry for road 0; the updated finite pointer directory entry for road 1 overwrites the original finite pointer directory entry for road 1.

[0070] Due to the temporal locality of program execution, an evicted target cache line may be accessed again by the first target core in the future. When this happens, the first target core will initiate a read request for that target cache line, retrieving a valid copy from other cores' private caches, shared last-level caches, or main memory via the cache consistency protocol, and loading it into its private cache. The consistency catalog subsystem will then update the catalog entry accordingly, re-registering the first target core as a sharer of that target cache line.

[0071] Furthermore, after updating the directory entries, for a target cache line, if it has only one segment vector directory entry remaining, and the number of sharers recorded in that segment vector directory entry does not exceed the preset value, then that segment vector directory entry can be converted into a finite pointer directory entry to save storage overhead. Alternatively, for a target cache line, if there are multiple segment vector directory entries, and the sum of the number of sharers recorded in these segment vector directory entries does not exceed the preset value, then one of the segment vector directory entries can be converted into a finite pointer directory entry, making the remaining segment vector directory entries invalid to save storage overhead.

[0072] In an optional embodiment of the present invention, the method may further include: Step S21: In response to the request from the second target core to perform a write operation on the target cache line, search for a second target directory entry in the consistency directory based on the target address of the target cache line; the address tag recorded in the second target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the second target directory entry points to the first directory entry whose address tag matches; and the second target entry records the second target core. Step S22: Clear all second directory entries in the second target directory, keep only the first directory entries, and modify the first sharer in the retained first directory entries to the second target core.

[0073] In a multi-core processor system, when a second target core (e.g., CPU1) needs to perform a write operation on a target cache line (address A), it must ensure that it obtains exclusive access to the cache line before writing to avoid data inconsistency. The consistency catalog subsystem is responsible for coordinating this process.

[0074] In response to a request from the second target core to perform a write operation on the target cache line, the request carries a target address, such as address A. Address tags and indexes can be extracted from address A. Based on the index extracted from address A, the consistency directory is searched, and the target group that matches the index can be located. Based on the address tags extracted from address A, a matching directory entry is determined within the target group. If the matching directory entry records the second target core, it is determined to be the second target directory entry.

[0075] If a second target directory entry is found indicating that another core holds a copy of the target cache line, a notification is sent to these cores, requesting them to mark their local copies as invalid. Each core returns an acknowledgment after processing. Upon receiving acknowledgments from all cores, the second target core (cpu1) is notified that it can perform a write operation to address A. The consistency directory subsystem updates the directory entries, clearing all second directory entries in the second target directory entry, retaining only the first directory entry, and changing the first sharer in the retained first directory entry to the second target core (cpu1), such as changing the sharer pointer to cpu1, and changing the consistency state in the first directory entry to state E. The cleared second directory entries become empty directory entries and can be reassigned.

[0076] by Figure 5 Taking the result after CPU8 accesses the target cache line at address A as an example, suppose the second target core (CPU1 for example) wants to perform a write operation to address A. In response to the second target core's request to perform a write operation on the target cache line, the second target directory entry is searched in the consistency directory based on the target address of the target cache line; if found... Figure 5 The three directory entries in line 4 are shown. Clear the segment vector directory entries for road 1 and road 2, keeping only the first directory entry for road 0. Modify the sharer pointer in the retained first directory entry to point to cpu1. The address label in the first directory entry remains the address label corresponding to address A. Modify the status flag in the first directory entry from status S to status E.

[0077] In summary, this embodiment of the invention uses multiple directory entries to record the distribution information of cache line replicas at the same address, and only records the address label in the first directory entry. For example, for the target cache line corresponding to address A, only the address label of address A is recorded in the first directory entry, and only a few bits are needed in the second directory entry to record the target path pointer, pointing to the first directory entry where the address label of address A is stored. Thus, the first directory entry can be found through the target path pointer in the second directory entry to obtain the memory address in the address label. This embodiment of the invention avoids storing the address label in each directory entry. Storing the address label typically requires 30 bits, while storing the path pointer only requires a few bits; for example, in a 16-way system, the path pointer only requires 4 bits. Storing the same information requires fewer directory entries, and the width of a single directory entry is lower. Therefore, through this embodiment of the invention, the location of cache line replicas in a many-core scenario can be accurately represented while maintaining a low width of a single directory entry, thereby saving hardware overhead and improving system performance.

[0078] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0079] Reference Figure 6 The diagram illustrates a structural block diagram of an embodiment of a cache consistency control device according to the present invention. The device may include: The first allocation module 601 is configured to allocate a first directory entry in the consistency directory in response to the first core's first access request to the target cache line; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; The second allocation module 602 is used to allocate a second directory entry in the consistency directory in response to the access request of the second core to the target cache line; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

[0080] Optionally, if the number of the second cores does not exceed a preset value, the second directory entry is in a first format, in which a pointer list is used to record the second sharers; or, When the number of the second cores exceeds a preset value, the second directory entry is in a second format. The second directory entry in the second format also includes a segment identifier and a sharer vector corresponding to the segment identifier; wherein, different segment identifiers specify multiple different processor cores; each bit of the sharer vector is used to indicate a second sharer.

[0081] Optionally, the device further includes: The first lookup module is configured to, in response to a request from the first target core to remove the target cache line from its private cache, search for a first target directory entry in the consistency directory based on the target address of the target cache line; the address tag recorded in the first target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the first target directory entry points to the first directory entry whose address tag matches; and the first target directory entry records the first target core. The first update module is used to clear the record information of the first target core from each first target directory entry.

[0082] Optionally, the device further includes: The second lookup module is used to respond to a request from the second target core to perform a write operation on the target cache line, and to search for a second target directory entry in the consistency directory based on the target address of the target cache line; the address tag recorded in the second target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the second target directory entry points to the first directory entry whose address tag matches; and the second target entry records the second target core. The second update module is used to clear all second directory entries in the second target directory, retain only the first directory entries, and modify the first sharer in the retained first directory entries to the second target core.

[0083] Optionally, the consistency directory adopts a multi-group structure, each group including at least one directory entry, and the directory entries in each group correspond to the same index; the device further includes: The lookup module is used to locate the target group based on the index corresponding to the target address when looking up the consistency directory based on the target address; and to determine the hit directory entry with the address tag matching the address tag in the target group based on the address tag corresponding to the target address.

[0084] Optionally, each directory entry in the consistency directory includes a format identifier, which indicates the type of the directory entry; the type includes a first directory entry, a second directory entry in a first format, a second directory entry in a second format, or an empty directory entry.

[0085] Optionally, the first directory entry may further include a status identifier, which is used to record the consistency status of the target cache line.

[0086] Optionally, the consistency catalog includes a group-associative or mode-skewed associative SRAM array; the SRAM array includes multiple SRAM rows, each SRAM row corresponding to a group in the consistency catalog; each SRAM row is divided into multiple storage areas, each storage area being used to independently store a catalog entry.

[0087] This invention uses multiple directory entries to record the distribution information of cache line replicas at the same address, and only records the address label in the first directory entry. For example, for the target cache line corresponding to address A, only the address label of address A is recorded in the first directory entry, and only a few bits are used in the second directory entry to record the target path pointer, pointing to the first directory entry where the address label of address A is stored. Thus, the first directory entry can be found through the target path pointer in the second directory entry to obtain the memory address in the address label. This invention avoids storing the address label in each directory entry. Storing the address label typically requires 30 bits, while storing the path pointer only requires a few bits; for example, in a 16-way system, the path pointer only requires 4 bits. Storing the same information requires fewer directory entries, and the width of a single directory entry is lower. Therefore, this invention can accurately represent the cache line replica location in a many-core scenario while maintaining a low width of a single directory entry, thereby saving hardware overhead and improving system performance.

[0088] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0089] This invention provides a consistency catalog, characterized in that it is applied to a multi-core processor system, and the consistency catalog includes: Directory storage, configured to store multiple directory entries; and The directory controller, coupled to the directory storage, is configured as follows: In response to the first core's initial access request to the target cache line, a first directory entry is allocated in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; In response to a second core's access request to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

[0090] This invention provides a processor chip, comprising: Multiple processor cores, each core including a private cache for storing copies of cache lines; On-chip network, providing interconnect communication paths between the multiple processor cores and the consistency catalog subsystem; and The consistency catalog subsystem, coupled to the on-chip network, is configured as follows: In response to the first core's initial access request to the target cache line, a first directory entry is allocated in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; In response to a second core's access request to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

[0091] Reference Figure 7 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. Figure 7 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to perform the steps of the cache coherence control method of the aforementioned embodiment.

[0092] This invention provides a non-transitory computer-readable storage medium that, when the instructions in the storage medium are executed by a terminal's program or processor, enables the terminal to perform the steps of the cache coherence control method described in the foregoing embodiments. The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0093] Those skilled in the art will understand that embodiments of the present invention can be provided as a cache consistency control method, apparatus, consistency catalog, electronic device, or computer program product. Therefore, embodiments of the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0094] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0095] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0096] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0097] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0098] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A cache consistency control method, characterized in that, The method includes: In response to the first core's initial access request to the target cache line, a first directory entry is allocated in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; In response to a second core's access request to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

2. The method according to claim 1, characterized in that, If the number of the second cores does not exceed the preset value, the second directory entry is in the first format, and in the first format, a pointer list is used to record the second sharer; or, When the number of the second cores exceeds a preset value, the second directory entry is in a second format. The second directory entry in the second format also includes a segment identifier and a sharer vector corresponding to the segment identifier; wherein, different segment identifiers specify multiple different processor cores; each bit of the sharer vector is used to indicate a second sharer.

3. The method according to claim 1, characterized in that, The method further includes: In response to a request from a first target core to remove the target cache line from its private cache, a first target directory entry is searched in the consistency directory based on the target address of the target cache line; the address tag recorded in the first target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the first target directory entry points to the first directory entry whose address tag matches; and the first target entry records the first target core. Clear the record information of the first target core from each first target directory entry.

4. The method according to claim 1, characterized in that, The method further includes: In response to a request from the second target core to perform a write operation on the target cache line, a second target directory entry is searched in the consistency directory based on the target address of the target cache line; the address tag recorded in the second target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the second target directory entry points to the first directory entry whose address tag matches; and the second target entry records the second target core. Clear all second directory entries in the second target directory, keep only the first directory entries, and change the first sharer in the kept first directory entries to the second target core.

5. The method according to claim 1, characterized in that, The consistency directory adopts a multi-group structure, each group including at least one directory entry, and the directory entries in each group correspond to the same index; the method further includes: When searching the consistency directory based on the target address, the target group is located according to the index corresponding to the target address; Based on the address tag corresponding to the target address, determine the matching directory entry in the target group whose address tag matches.

6. The method according to claim 1, characterized in that, Each directory entry in the consistency directory includes a format identifier, which indicates the type of the directory entry; the type includes a first directory entry, a second directory entry in a first format, a second directory entry in a second format, or an empty directory entry.

7. The method according to claim 1, characterized in that, The first directory entry also includes a status identifier, which is used to record the consistency status of the target cache line.

8. The method according to claim 1, characterized in that, The consistency catalog includes a group-associative or mode-skewed associative SRAM array; the SRAM array includes multiple SRAM rows, each SRAM row corresponding to a group in the consistency catalog; each SRAM row is divided into multiple storage areas, each storage area is used to independently store a catalog entry.

9. A consistent directory, characterized in that, The consistency catalog, applied to multi-core processor systems, includes: Directory storage, configured to store multiple directory entries; and The directory controller, coupled to the directory storage, is configured as follows: In response to the first core's initial access request to the target cache line, a first directory entry is allocated in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; In response to a second core's access request to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

10. The consistency catalog according to claim 9, characterized in that, If the number of the second cores does not exceed the preset value, the second directory entry is in the first format, and in the first format, a pointer list is used to record the second sharer; or, When the number of the second cores exceeds a preset value, the second directory entry is in a second format. The second directory entry in the second format also includes a segment identifier and a sharer vector corresponding to the segment identifier; wherein, different segment identifiers specify multiple different processor cores; each bit of the sharer vector is used to indicate a second sharer.

11. The consistency catalog according to claim 9, characterized in that, The directory controller is also configured to: In response to a request from the first target core to remove the target cache line from its private cache, the first target directory entry is searched in the consistency directory based on the target address of the target cache line; The address tag recorded in the first target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the first target directory entry points to the first directory entry whose address tag matches; and the first target directory entry records the first target core; the record information of the first target core is cleared from each first target directory entry.

12. The consistency catalog according to claim 9, characterized in that, The directory controller is also configured to: In response to a request from the second target core to perform a write operation on the target cache line, a second target directory entry is searched in the consistency directory based on the target address of the target cache line; the address tag recorded in the second target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the second target directory entry points to the first directory entry whose address tag matches; and the second target directory entry records the second target core; all second directory entries in the second target directory entry are cleared, only the first directory entry is retained, and the first sharer in the retained first directory entry is modified to the second target core.

13. A processor chip, characterized in that, include: Multiple processor cores, each core including a private cache for storing copies of cache lines; On-chip network provides interconnect communication paths between the multiple processor cores and the consistency catalog subsystem; as well as The consistency catalog subsystem, coupled to the on-chip network, is configured as follows: In response to the first core's initial access request to the target cache line, a first directory entry is allocated in the consistency directory; the first directory entry is used to record the address label of the target cache line and the first sharer; the first sharer includes the first core; In response to a second core's access request to the target cache line, a second directory entry is allocated in the consistency directory; the second directory entry is used to record the target path pointer and the second sharer; the target path pointer points to the first directory entry; the second sharer includes the second core; the number of the second core is greater than or equal to 1.

14. The processor chip according to claim 13, characterized in that, If the number of the second cores does not exceed the preset value, the second directory entry is in the first format, and in the first format, a pointer list is used to record the second sharer; or, When the number of the second cores exceeds a preset value, the second directory entry is in a second format. The second directory entry in the second format also includes a segment identifier and a sharer vector corresponding to the segment identifier; wherein, different segment identifiers specify multiple different processor cores; each bit of the sharer vector is used to indicate a second sharer.

15. The processor chip according to claim 13, characterized in that, The consistency catalog subsystem is also configured as follows: In response to a request from the first target core to remove the target cache line from its private cache, the first target directory entry is searched in the consistency directory based on the target address of the target cache line; The address tag recorded in the first target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the first target directory entry points to the first directory entry whose address tag matches; and the first target directory entry records the first target core; the record information of the first target core is cleared from each first target directory entry.

16. The processor chip according to claim 13, characterized in that, The consistency catalog subsystem is also configured as follows: In response to a request from the second target core to perform a write operation on the target cache line, a second target directory entry is searched in the consistency directory based on the target address of the target cache line; the address tag recorded in the second target directory entry matches the address tag corresponding to the target address, or the target path pointer recorded in the second target directory entry points to the first directory entry whose address tag matches; and the second target entry records the second target core. Clear all second directory entries in the second target directory, keep only the first directory entries, and change the first sharer in the kept first directory entries to the second target core.

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