FPGA (Field Programmable Gate Array) hardware acceleration adaptive data distribution method and equipment based on multi-dimensional state perception and storage medium

Abstract

The invention relates to the technical field of spaceflight electronics, in particular to an FPGA hardware acceleration adaptive data distribution method and device based on multi-dimensional state awareness and a storage medium, and the method comprises the following steps: S1, directly sampling four-dimensional state parameters of each SATA channel through a hardware register; s2, a lookup table is used for replacing a hardware calculation engine of a multiplier to fuse and calculate the parameters, and a dynamic weight coefficient is generated; s3, based on the weight coefficient, adaptively distributing the input data flow to each SATA channel through a two-stage distribution mechanism; and S4, dynamically correcting the evaluation parameters through closed-loop feedback, and starting a progressive degradation strategy when the channel is abnormal. The method is completely implemented on the FPGA hardware level, the problem that a traditional static strategy cannot adapt to SSD real-time performance fluctuation is solved, lossless and low-delay disk dropping of 10G Ethernet full-speed data is achieved, and the method has the advantages of being high in reliability and long in service life.

Description

Technical Field

[0001] This invention relates to the field of aerospace electronics technology, and in particular to a method, device and storage medium for FPGA hardware-accelerated adaptive data distribution based on multi-dimensional state awareness. Background Technology

[0002] In response to the call for integrated space-ground networking and routing switching, demands for inter-satellite connectivity and intelligent aerospace have emerged. Traditional spaceborne computer systems typically employ commercial processors (such as PowerPC and ARM) combined with radiation hardening measures. However, due to the unique characteristics of the space environment (such as single-event effects and total dose radiation), the reliability of commercial chips is insufficient to meet the requirements of long-term on-orbit missions. Furthermore, traditional spaceborne systems face the following technical bottlenecks in areas such as storage management, mission scheduling, and fault-tolerant design: With the development of aerospace technology, the amount of data generated by modern spacecraft (including satellites, deep space probes, and manned spacecraft) is growing exponentially. Payloads such as high-resolution optical remote sensing, synthetic aperture radar (SAR), hyperspectral imaging, and space science experiments commonly use 10 Gigabit (10.3125 Gbps) Ethernet interfaces to output data. However, spaceborne storage systems face unique challenges: Poor adaptability to extreme environments: Existing spaceborne storage systems mostly adopt static redundancy design. In the environment of space radiation and drastic temperature changes (-55℃ to +85℃), the performance of SSDs degrades inconsistently, resulting in a decrease of more than 40% in the overall system throughput, and failing to guarantee continuous 10G full line-speed data writing to the disk.

[0003] The effects of radiation are severe: Spacecraft are exposed to high-energy particle radiation during their on-orbit operation, causing SSDs to experience bit flips, bad block growth, and other problems. Traditional storage controllers lack real-time sensing and adaptive mechanisms for radiation effects, resulting in SSD failure rates as high as 15-25% in typical Earth orbit missions (3-5 years).

[0004] Strict energy constraints: Spaceborne systems are energy-intensive. Existing 10G data recording solutions typically have excessive cache (>8GB DDR3) and redundant controllers, resulting in power consumption exceeding the limit by 30-40%, which does not meet the strict power consumption budget of spacecraft.

[0005] High autonomy requirements: Spacecraft cannot be physically maintained while in orbit. The failure recovery of existing systems (such as NASA's open-source SpaceCube 2.0) relies on ground commands, and the recovery time can be as long as several hours, resulting in the loss of critical scientific data.

[0006] Uneven data value: The value of data varies greatly in space missions. For example, planetary surface images in deep space exploration and gamma-ray burst events in astronomical observations are far more valuable than conventional state data. However, existing systems use a "first-in, first-out" strategy and cannot dynamically allocate storage resources according to scientific value.

[0007] Long lifespan challenge: Modern space missions have extended cycles (such as the Chang'e lunar exploration program and the Tianwen Mars exploration program), requiring storage systems to operate continuously for 5-10 years, while the design life of traditional SATA SSDs is only 2-3 years, which is further shortened in the space radiation environment.

[0008] Therefore, there is an urgent need for an adaptive data distribution architecture based on multi-dimensional state awareness that can be autonomously implemented at the FPGA hardware level, specifically designed for space environment optimization, to meet the high reliability data recording requirements of spacecraft under harsh conditions such as radiation, temperature changes, and energy constraints. Summary of the Invention

[0009] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a hardware-accelerated adaptive data distribution method for FPGAs based on multi-dimensional state awareness, comprising the following steps: S1: Configure the sampling period of the multi-dimensional state perception unit, directly sample the internal signals of N SATA controllers through hardware registers, and collect the four-dimensional state parameters of each SATA channel in real time, where N≥4. The four-dimensional state parameters include command queue status, device internal status, physical layer performance indicators and temperature resource status. S2: The hardware-accelerated state evaluation unit uses a dedicated hardware computing engine that replaces the multiplier with a lookup table to perform fusion calculations on the four-dimensional state parameters and generate N dynamic weight coefficients that characterize the real-time processing capability of each SATA channel. S3: Based on the dynamic weight coefficient, the two-level data distribution execution unit performs periodic data stream coarse-grained allocation through the first-level distribution module and performs microsecond-level real-time fine-grained adjustment by monitoring the instantaneous FIFO level through the second-level distribution module, thereby distributing the input data stream to the N SATA channels. S4: The closed-loop feedback optimization unit continuously calculates the throughput deviation between the actual throughput and the expected throughput of each SATA channel. Based on the throughput deviation, it dynamically corrects the evaluation parameters of the state evaluation unit using a hardware-implemented gradient descent algorithm. When a channel anomaly is detected, a progressive degradation strategy is initiated.

[0010] Preferably, in step S1, the four-dimensional status parameters of each SATA channel are collected in real time, including: The count of incomplete write commands, reg_sata_pending_cmd_cnt[i], is collected from the request queue module rqueue via hardware registers. The command queue depth is obtained from the allocation list module alloc_list. The command completion latency distribution value, reg_sata_cmd_latency_histogram[i][3:0], is also calculated. The garbage collection status flag reg_sata_gc_active[i] is extracted by parsing the SATA protocol features, the SSD health parameters are parsed from the device identification completion flag reg_sata_dev_identify_done[i], and the write amplification factor reg_write_amp_factor[i][7:0] is calculated based on the historical write mode; The link layer error count is collected from the SATA central controller module sata_ctrl_central, the physical layer real-time throughput value reg_sata_phy_throughput[i][15:0] is calculated, and the retransmission rate reg_sata_retry_ratio[i][7:0] is calculated based on the SATA protocol retransmission mechanism. SSD temperature data is collected via the I2C bus controller module IIC_TOP, and the water mark level value reg_fifo_watermark_level[i][11:0] of each SATA channel's dedicated FIFO is monitored. Based on the FIFO occupancy rate and processing latency, the cache pressure index reg_cache_pressure_index[i][7:0] is calculated, where i is the SATA channel index, 0≤i <N。

[0011] Preferably, in step S2, the four-dimensional state parameters are fused and calculated to generate N dynamic weighting coefficients characterizing the real-time processing capability of each SATA channel, including: The four-dimensional state parameters The normalization parameter is obtained by mapping linear normalization to a uniform dimension of 0-255. The normalization formula is as follows: Where j = 1, 2, 3, 4 correspond to the four dimensions mentioned above. and These are the historical minimum and maximum values ​​of the j-th dimension state parameter Pj, respectively; The normalization parameter As address indexes, four weight lookup tables LUT_j, pre-stored in the FPGA's on-chip memory BRAM, are used for parallel lookups. Each LUT_j stores the weight coefficients K_j and the normalization parameter. The pre-calculated product result; The hardware adder tree sums the outputs of the four lookup tables LUT_j and calculates the basic weight values. As shown below: ,in The preset baseline weight value; The basic weight values ​​are smoothed using a first-order IIR exponential filter. Perform filtering to obtain filter weight values. The filtering formula is: Where α is the smoothing factor, This represents the filter weight value from the previous cycle; Set a minimum guaranteed weight threshold MIN_WEIGHT. When the filtered weight value weight_filtered is less than the minimum guaranteed weight threshold MIN_WEIGHT, set it to MIN_WEIGHT as the final dynamic weight coefficient.

[0012] Preferably, in step S3, data allocation is performed based on dynamic weighting coefficients, including: The primary distribution module, based on the dynamic weight coefficients of each SATA channel, uses a weighted round-robin algorithm to coarsely allocate the input data stream with an allocation period T_a, determining the data stream allocation ratio for each SATA channel. As shown below: ,in, Let i be the dynamic weighting coefficient for the i-th SATA channel. The sum of dynamic weighting coefficients for all SATA channels, 1μs≤T_a≤100μs; The secondary distribution module monitors the water level status of the dedicated FIFO of each SATA channel in real time. When the water level of the FIFO of any SATA channel exceeds the preset high threshold, data redirection is triggered within the response time Δt, where the response time Δt≤200ns. The data redirection decision selects an alternative data transmission path from the backup SATA channel with the highest current dynamic weight coefficient and whose FIFO level has not exceeded the limit, and forwards the subsequent input data stream of the channel whose FIFO level has exceeded the limit to the selected backup channel.

[0013] Preferably, in step S4, the evaluation parameters are dynamically corrected using a hardware-implemented gradient descent algorithm, including: The closed-loop feedback optimization unit calculates the actual throughput of each SATA channel every T milliseconds. Compared with expected throughput relative deviation The deviation formula is: The value of T is in the range of 1 ≤ T ≤ 100; The weight coefficients Kj of the state evaluation unit are updated using a hardware-implemented least mean square algorithm, and the update formula is as follows: , where μ is the configurable learning rate, Let j be the normalized value of the state parameter of the j-th dimension corresponding to the i-th SATA channel, where j=1,2,3,4 correspond to the four dimensions of the four-dimensional state parameter.

[0014] Preferably, in step S4, initiating the gradual degradation strategy includes: When the closed-loop feedback optimization unit detects M consecutive CRC check errors in a certain SAT channel, a progressive channel degradation strategy is initiated, where M ≥ 3; The progressive channel degradation strategy is implemented as follows: when a CRC check error is detected for the first time, the dynamic weight coefficient of the channel is reduced by a first percentage. Subsequently, each time a CRC check error is detected, the dynamic weight coefficient of the channel is reduced by a higher percentage in turn, until the Mth consecutive CRC check error is detected. At this point, the dynamic weight coefficient of the channel is set to zero, and the channel is completely isolated, and no new input data stream is allocated to it. After isolating the channel, the closed-loop feedback optimization unit redistributes the unprocessed data in the isolated channel to other healthy SATA channels.

[0015] Preferably, prior to step S1, a priority processing method for data value perception is also included: High-speed data streams are received through a 10G Ethernet data access unit, and the application characteristics of each data packet in the high-speed data stream are parsed by the Application Oriented Service Framework (AOS). Based on a preset rule base, data packets are assigned any one of three service quality levels: high, medium, or low, according to the application characteristics. During the data allocation process performed by the two-level data distribution execution unit, a minimum bandwidth is preset to guarantee high-priority data based on the allocated quality of service level.

[0016] Preferably, it also includes learning parameter optimization: Record the correspondence between historical status parameters and throughput deviations of each SATA channel to form a status transition pattern library; The system load data is analyzed by a hardware-implemented pattern recognition unit to identify the periodic characteristics and trends of the system load. Based on the identified features and trends, predict the load change trend in the near future; Based on the load change prediction results, the weight coefficients in the state assessment unit or the data distribution strategy of the two-level data distribution execution unit are adjusted in advance to achieve predictive load balancing.

[0017] Based on the same concept, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions, which, when executed by the processor, cause the processor to perform the steps of a multi-dimensional state-aware FPGA hardware-accelerated adaptive data distribution method as described in the embodiments.

[0018] Based on the same concept, the present invention also provides a storage medium storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of a multi-dimensional state-aware FPGA hardware-accelerated adaptive data distribution method as described in any one embodiment.

[0019] Compared with the prior art, the beneficial effects of the present invention are: (1) This invention uses a multi-dimensional state perception unit with a configurable sampling period to directly collect four-dimensional state parameters of each SATA channel, namely command queue status, device internal status, physical layer performance indicators and temperature resource status, through hardware registers. This enables comprehensive and accurate perception of the health status and real-time performance of the storage channel, solving the problem that traditional static strategies cannot adapt to dynamic factors such as SSD internal GC, temperature changes and link fluctuations, and laying a precise data foundation for adaptive decision-making.

[0020] (2) This invention uses a dedicated computing engine with a lookup table instead of a multiplier to perform fusion calculations on multidimensional parameters through a hardware-accelerated state evaluation unit, generating dynamic weight coefficients. Combined with a two-level data distribution execution unit (coarse-grained periodic allocation and fine-grained real-time adjustment), it realizes data distribution decision-making and execution at the nanosecond to microsecond level. All of this is completed at the FPGA hardware level without processor intervention, thereby achieving a continuous system throughput of over 9.5Gbps while ensuring extremely low latency, and solving the performance bottleneck of lossless 10G Ethernet full-speed data write-to-disk.

[0021] (3) This invention continuously calculates performance deviations through a closed-loop feedback optimization unit and dynamically corrects evaluation parameters using a hardware-implemented gradient descent algorithm. At the same time, it initiates a progressive degradation strategy when an abnormality is detected in a channel, thereby realizing online self-optimization of system parameters and intelligent and smooth isolation of faulty channels. This ensures the stability and high reliability of the overall throughput of the system under long-term operation or individual channel performance degradation scenarios, and meets the long lifespan requirements of the storage system for autonomous and reliable operation in harsh environments such as aerospace and industry. Attached Figure Description

[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0023] Figure 1 This is an architecture diagram of an FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness, according to the present invention. Figure 2 This is a flowchart of an FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness, according to the present invention. Figure 3 This is a detailed structural diagram of the multidimensional state sensing unit of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Obviously, the described embodiments are only some, not all, of the embodiments described in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without creative effort are within the scope of protection of this application.

[0025] Those skilled in the art will understand that, unless otherwise stated, the singular forms “a” and “an” used herein, and “the”, may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0026] First Embodiment Please see Figure 1As shown, the implementation of this embodiment is based on a dedicated FPGA hardware-accelerated adaptive data distribution architecture, which mainly consists of the following core units: a 10G Ethernet data access unit, a multi-dimensional state perception unit, a hardware-accelerated state evaluation unit, a two-level data distribution execution unit, a closed-loop feedback optimization unit, and an 8-bay SATA storage unit.

[0027] The 10G Ethernet data access unit includes: a 10G Ethernet physical layer interface (multi_axi_10g_ethernet.v), a MAC layer processing module, an AOS (Application-Oriented Services) framework (aos_deframe.v), a priority marking module, and a flow control module (aos_token_bucket.v). This unit enables full-speed 10G Ethernet data reception, identifies the application characteristics of data packets through the AOS framework, and allocates high, medium, and low quality-of-service levels according to preset policies.

[0028] The multi-dimensional state awareness unit includes four state acquisition modules: a command queue state acquisition module, a device internal state acquisition module, a physical layer performance indicator acquisition module, and a temperature resource state acquisition module. Each module directly samples the internal signals of the SATA controller through hardware registers, with a sampling period configurable from 1 to 100 ns.

[0029] The hardware-accelerated state evaluation unit includes: a parameter normalization module, weight coefficient storage, a lookup table calculation engine, an exponential smoothing filter, and a minimum guaranteed weight limiter. This unit achieves weight calculation with nanosecond-level response, reducing resource consumption by 25% compared to traditional multipliers.

[0030] The two-level data distribution execution unit includes a first-level distribution module (read_list.v) and a second-level distribution module (bqueue.v). The first-level distribution module implements coarse-grained allocation with a 100µs cycle based on dynamic weight coefficients, while the second-level distribution module monitors the FIFO level to achieve fine-grained adjustment with a 200ns response.

[0031] The closed-loop feedback optimization unit includes a performance monitoring module, a parameter adjustment module, and an anomaly handling module, enabling millisecond-level parameter self-optimization and second-level anomaly recovery.

[0032] The 8-bay SATA storage unit includes: a central control module (sata_ctrl_central.v), 8 bay control modules (sata_ctrl_disk.v), and a physical layer interface, supporting parallel writing of 8 SATA SSDs.

[0033] Please see Figure 2As shown, this embodiment provides an FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness, specifically optimized for spacecraft in the space environment. It addresses existing technologies' shortcomings in radiation environment adaptability, low energy efficiency, weak autonomous recovery capabilities, and insufficient data value differentiation. This method achieves 10G full-line-speed lossless data storage, while also possessing radiation hardening characteristics, ultra-low power consumption mode, autonomous fault recovery, and scientific data priority protection capabilities, meeting the long-life requirements of 5-10 years for space missions. The method includes the following steps: S0: Prioritizing the processing of data value perception: High-speed data streams are received through a 10G Ethernet data access unit, and the application-oriented service framework (AOS) parses the application characteristics of each data packet in the high-speed data stream. Specifically, in this embodiment, the 10G Ethernet data access unit is implemented as follows: 10 Gigabit Ethernet data enters the FPGA through an SFP+ optical module and is parsed into a 64 / 66b encoded data stream by the 10G MAC controller. The AOS framework performs deep parsing of the data stream. In the protocol parsing stage, the Ethernet header (14 bytes), IP header (20 bytes), and TCP / UDP header (8-20 bytes) are identified through a state machine, and the source / destination MAC address, source / destination IP address, protocol type, and port number are extracted. In the application feature extraction stage, application features are matched according to a preset rule base: engineering telemetry, raw observations, reconstructed data, and payload data; the VCID and data type fields in the frame header are parsed. Based on a preset rule base, data packets are assigned any one of three service quality levels: high, medium, and low, according to application characteristics. Specifically, in this embodiment, priority is assigned based on application characteristics: high priority: image data (payload data) of key areas such as national borders and disaster monitoring; medium priority: engineering telemetry and raw observation data; low priority: reconstructed data. During the data allocation process performed by the two-level data distribution execution unit, a minimum bandwidth is preset to ensure high-priority data based on the allocated quality of service level. Specifically, in this embodiment, a token bucket algorithm implemented in hardware is used to allocate different token issuance rates to different priorities. The high-priority token bucket has a large capacity and is replenished quickly, ensuring that critical data is not discarded.

[0034] S1: Configure the sampling period of the multi-dimensional state perception unit. The internal signals of N SATA controllers are directly sampled through hardware registers to collect the four-dimensional state parameters of each SATA channel in real time, where N≥4. The four-dimensional state parameters include command queue status, device internal status, physical layer performance indicators and temperature resource status. Specifically, in this embodiment, all state parameters are directly sampled through hardware registers to avoid software polling overhead. The sampling period can be configured to 10μs to meet the real-time requirements of 10G networks.

[0035] Please see Figure 3 As shown, in step S1, the four-dimensional status parameters of each SATA channel are collected in real time, including: The count of incomplete write commands, reg_sata_pending_cmd_cnt[i], is collected from the request queue module rqueue via hardware registers. The command queue depth is obtained from the allocation list module alloc_list. The command completion latency distribution value, reg_sata_cmd_latency_histogram[i][3:0], is also calculated. The garbage collection status flag reg_sata_gc_active[i] is extracted by parsing the SATA protocol features, the SSD health parameters are parsed from the device identification completion flag reg_sata_dev_identify_done[i], and the write amplification factor reg_write_amp_factor[i][7:0] is calculated based on the historical write mode; The link layer error count is collected from the SATA central controller module sata_ctrl_central, the physical layer real-time throughput value reg_sata_phy_throughput[i][15:0] is calculated, and the retransmission rate reg_sata_retry_ratio[i][7:0] is calculated based on the SATA protocol retransmission mechanism. SSD temperature data is collected via the I2C bus controller module IIC_TOP, and the water mark level value reg_fifo_watermark_level[i][11:0] of each SATA channel's dedicated FIFO is monitored. Based on the FIFO occupancy rate and processing latency, the cache pressure index reg_cache_pressure_index[i][7:0] is calculated, where i is the SATA channel index, 0≤i <N。

[0036] S2: The hardware-accelerated state evaluation unit uses a dedicated hardware computing engine that replaces multipliers with lookup tables to perform fusion calculations on four-dimensional state parameters and generate N dynamic weight coefficients that characterize the real-time processing capabilities of each SATA channel.

[0037] Preferably, in step S2, the four-dimensional state parameters are fused and calculated to generate N dynamic weighting coefficients characterizing the real-time processing capability of each SATA channel, including: Four-dimensional state parameters The normalization parameter is obtained by mapping linear normalization to a uniform dimension of 0-255. The normalization formula is as follows: Where j=1, 2, 3, 4 correspond to four dimensions. and These are the state parameters of the j-th dimension. The historical minimum and historical maximum values; normalized parameters As address indexes, four weight lookup tables LUT_j, pre-stored in the FPGA's on-chip memory BRAM, are used for parallel lookups. Each LUT_j stores the weight coefficients K_j and the normalization parameters. Specifically, in this embodiment, the weight coefficients Kj of the four dimensions are stored in the on-chip RAM of the FPGA and can be dynamically adjusted through the sata_10g_myreg.v register interface. The default values ​​are: command queue status: K1=0.4, device internal status: K2=0.3, physical layer performance: K3=0.2, temperature resources: K4=0.1; The hardware adder tree sums the outputs of the four lookup tables LUT_j and calculates the basic weight values. As shown below: ,in For the preset baseline weight values, specifically, in this embodiment, four 256×256 lookup tables LUT_j are constructed to pre-store all Kj× The result is that the computation delay is only 3 clock cycles; The basic weight values ​​are smoothed using a first-order IIR exponential filter. Perform filtering to obtain filter weight values. The filtering formula is: ,in The filter weight value of the previous cycle is α, which is a smoothing factor that can be configured (0.2-0.8) and is implemented through a shift adder to avoid consuming multiplier resources. Set the minimum guaranteed weight threshold MIN_WEIGHT = 25 (corresponding to 10% of the base bandwidth). When the filter weight value weight_filtered is less than the minimum guaranteed weight threshold MIN_WEIGHT, force it to be set to MIN_WEIGHT as the final dynamic weight coefficient to prevent the channel from starving.

[0038] S3: The two-level data distribution execution unit is based on dynamic weight coefficients. It performs coarse-grained allocation of periodic data streams through the first-level distribution module and performs microsecond-level real-time fine-grained adjustment by monitoring the instantaneous FIFO level through the second-level distribution module, thereby distributing the input data streams to N SATA channels.

[0039] Preferably, in step S3, data allocation is performed based on dynamic weighting coefficients, including: The primary distribution module, based on the dynamic weighting coefficients of each SATA channel, uses a weighted round-robin algorithm to coarsely allocate the input data stream at an allocation period T_a, determining the data stream allocation ratio for each SATA channel. As shown below: ,in, Let i be the dynamic weighting coefficient for the i-th SATA channel. The sum of dynamic weight coefficients for all SATA channels, 1μs≤T_a≤100μs. Specifically, in this embodiment, the 10G input data stream is proportionally allocated to 8 channels with an allocation period of 100μs. 20% of the total bandwidth is reserved for high-priority data and allocated according to the channel weight ratio. The secondary distribution module monitors the water level status of the dedicated FIFO of each SATA channel in real time. When the water level of the FIFO of any SATA channel exceeds the preset high threshold, data redirection is triggered within the response time Δt, where the response time Δt≤200ns. Specifically, in this embodiment, the bqueue.v module implements microsecond-level adjustment and monitors the FIFO water level of each channel in real time. When the water level exceeds the threshold (80%), redirection is triggered, and an alternative path is obtained from the backup channel with the highest weight. The redirection decision is implemented through a state machine without external intervention. High-priority data has the right to be exempted from redirection, ensuring that the latency is controllable. In the 10G full line speed test, the two-level distribution mechanism works together. The primary distribution handles the stable load, and the secondary distribution absorbs the burst traffic to ensure that the system does not lose packets. The data redirection decision selects an alternative data transmission path from the backup SATA channel with the highest current dynamic weight coefficient and whose FIFO level has not exceeded the limit, and forwards the subsequent input data streams of the channel whose FIFO level has exceeded the limit to the selected backup channel.

[0040] S4: The closed-loop feedback optimization unit continuously calculates the throughput deviation between the actual throughput and the expected throughput of each SATA channel. It uses a hardware-implemented gradient descent algorithm to dynamically correct the evaluation parameters of the state evaluation unit based on the throughput deviation, and initiates a gradual degradation strategy when a channel anomaly is detected.

[0041] Preferably, in step S4, the evaluation parameters are dynamically corrected using a hardware-implemented gradient descent algorithm, including: The closed-loop feedback optimization unit calculates the actual throughput of each SATA channel every T milliseconds. Compared with expected throughput relative deviation The deviation formula is: The value of T ranges from 1 to 100. Specifically, in this embodiment, the relative deviation between the actual throughput and the expected throughput of each channel is calculated every 10ms. The least mean square algorithm implemented in hardware is used to update the weight coefficients Kj of the state evaluation unit. The update formula is as follows: Where μ is the configurable learning rate, μ is (0.01-0.1), Let j be the normalized value of the state parameter of the j-th dimension corresponding to the i-th SATA channel, where j=1,2,3,4 correspond to the four dimensions of the four-dimensional state parameter.

[0042] Preferably, in step S4, a gradual degradation strategy is initiated, including: When the closed-loop feedback optimization unit detects M consecutive CRC check errors in a certain SAT channel, a progressive channel degradation strategy is initiated, where M ≥ 3; The progressive channel degradation strategy is implemented as follows: when a CRC check error is detected for the first time, the dynamic weight coefficient of the channel is reduced by a first percentage. Subsequently, each time a CRC check error is detected, the dynamic weight coefficient of the channel is reduced by a higher percentage, until the Mth consecutive CRC check error is detected. At this point, the dynamic weight coefficient of the channel is set to zero, and the channel is completely isolated, ceasing the allocation of any new input data streams to it. Specifically, in this embodiment, when there are 5 consecutive CRC errors, progressive degradation is initiated. For the 1st-2nd errors, the weight is reduced by 20%. For the 3rd-4th errors, the weight is reduced by 50%, and an alarm is issued. For the 5th error, the weight is set to 0, the channel is completely isolated, and the data to be processed is distributed to other channels to ensure that 10G of data is not lost. After isolating the channel, the closed-loop feedback optimization unit redistributes the unprocessed data in the isolated channel to other healthy SATA channels.

[0043] Preferably, it also includes learning parameter optimization: Record the correspondence between historical status parameters and throughput deviations of each SATA channel to form a status transition pattern library; The system load data is analyzed by a hardware-implemented pattern recognition unit to identify the periodic characteristics and trends of the system load. Based on the identified features and trends, predict the load change trend in the near future; Based on the load change prediction results, the weight coefficients in the state assessment unit or the data distribution strategy of the two-level data distribution execution unit are adjusted in advance to achieve predictive load balancing.

[0044] In the application scenario of Earth observation remote sensing satellite data: On a high-resolution optical remote sensing satellite, this architecture is deployed in the onboard data processing unit to receive 10G of panchromatic and multispectral payload data. The AOS framework is customized for identification. High priority: Images of national border areas, disaster monitoring areas, and military-sensitive areas. Medium priority: routine land observations, cloud-covered areas Low priority: Ocean background, polar ice cap (routine monitoring) Spatial environment adaptability configuration: For sun-synchronous orbits (500-800 km), a radiation threshold of 50 krad / year is set. Temperature compensation range: -45℃ to +65℃ Power consumption budget: 32W maximum, 16W for normal tasks, 10W for safe mode On-orbit test results (simulation): Average throughput: 9.6Gbps (96% line speed), sufficient for recording 12TB of raw image data per day. Fault recovery: In a simulated single-event upset event, channel switching is completed within 120ms with no data loss. Energy efficiency: Compared to traditional solutions, this method saves 230 kWh of electricity over a 3-year mission, equivalent to reducing the area of ​​solar panels by 1.8 m². 2 Data priority guarantee: 100% complete image recording of disaster areas; 5% compression rate improvement allowed in normal areas under extreme conditions. In the application scenario of deep space probe scientific data: In a Mars exploration mission, this architecture is used to record integrated data from hyperspectral imagers, lidar, and space environment probes. The AOS framework is configured to recognize: High priority: evidence of water on the Martian surface, areas of methane anomalies, and the initial stages of dust storms. Medium priority: Conventional topographic mapping, atmospheric vertical profiling Low priority: Repeated calibration data, background spatial environment Spatial environment adaptability configuration: For deep space radiation environments (estimated total dose of 150 krad), triple-modular redundancy critical control logic is employed. Temperature range: -55℃ to +70℃ (extreme temperatures in Mars orbit) Ground-free intervention design: Autonomous fault recovery capability required >99.9% Lifespan requirement: 8 years of continuous operation Ground simulation test results: Sustained throughput: 9.5Gbps, meeting the requirements for multi-payload collaborative data acquisition. Radiation tolerance: During 150 krad accelerated testing, the system throughput remained >90% of line rate. Lifespan Prediction: Through write balancing and predictive channel management, the equivalent lifespan of the SSD is extended to 9.2 years. Key data protection: High-value scientific data is 100% preserved under system pressure.

[0045] Achieving key performance indicators for aerospace environments: In an 8-bay SATA system implemented on a Xilinx Virtex FPGA (V7), this architecture achieves the following performance indicators: Temperature range: -55℃ to +85℃ for full-function operation, -60℃ to +90℃ for safe operation. Power consumption characteristics: 10G full load: 32W (including FPGA, DDRIII, 8 SSDs, SFP and related power supply chips) 5G medium load: 16W Safe mode (critical data only): 10W Reliability metrics: MTBF (Mean Time Between Failures): >150,000 hours Data integrity: 10-18 (bit error rate) Single point of failure tolerance: Supports the complete failure of any one or more SSDs; in the event of multiple failures, the total input bandwidth must be reduced. This embodiment has wide applicability in the aerospace field, and specific application scenarios include: (1) Earth observation satellites: applied to high-resolution optical, SAR, and hyperspectral imaging satellites to ensure the lossless recording of high-value data such as land monitoring, disaster early warning, and environmental assessment.

[0046] (2) Deep space exploration missions: applicable to lunar, Mars and asteroid probes. When communication windows are limited, the data priority mechanism ensures that the data with the highest scientific value is transmitted first, so as to maximize the scientific output of the exploration mission.

[0047] (3) Space station scientific experiments: Deployed in the experimental module of the Chinese space station, it supports high-bandwidth data recording for experiments such as microgravity materials science, space life science, and basic physics, and adapts to the complex electromagnetic environment of the space station and temperature fluctuations during orbit changes.

[0048] (4) Space science satellites: used for astronomical observation (such as subsequent models of the Hard X-ray Modulation Telescope), space environment detection and other missions, to capture transient astronomical phenomena and space weather events, and to ensure that key scientific events are not lost through the rapid response capability of this architecture.

[0049] (5) Military reconnaissance satellites: applied to military remote sensing systems, they ensure the complete recording of data on sensitive areas and abnormal activities through autonomous priority identification, while maintaining stable storage performance in electronic warfare environments.

[0050] (6) Space telemetry and control system: a space-to-ground data relay system deployed at ground telemetry and control stations, which processes high-speed downlink data streams, provides a highly reliable data cache for the deep space network, and supports 24 / 7 uninterrupted operation.

[0051] This invention meets the development requirements of high reliability, long lifespan, and autonomy for spacecraft data systems, filling a gap in China's field of high-speed adaptive storage technology for spaceborne systems. Through radiation-hardened design, ultra-low power management, and an autonomous fault recovery mechanism, it solves the core data recording challenges in space missions, demonstrating significant technological innovation and strategic value.

[0052] Second Embodiment Based on the same concept, this embodiment also provides a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the processor performs the steps of a multi-dimensional state-aware FPGA hardware-accelerated adaptive data distribution method as described in the embodiment.

[0053] Based on the same concept, the present invention also provides a storage medium storing computer-readable instructions, characterized in that, when the computer-readable instructions are executed by one or more processors, the one or more processors cause the one or more processors to perform the steps of a multi-dimensional state-aware FPGA hardware-accelerated adaptive data distribution method as described in any one of the embodiments.

[0054] It is understood that, for the aforementioned FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness, if all of them are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer server or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0055] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0056] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A hardware-accelerated adaptive data distribution method for FPGA based on multi-dimensional state awareness, characterized in that, Includes the following steps: S1: Configure the sampling period of the multi-dimensional state perception unit, directly sample the internal signals of N SATA controllers through hardware registers, and collect the four-dimensional state parameters of each SATA channel in real time, where N≥4. The four-dimensional state parameters include command queue status, device internal status, physical layer performance indicators and temperature resource status. S2: The hardware-accelerated state evaluation unit uses a dedicated hardware computing engine that replaces the multiplier with a lookup table to perform fusion calculations on the four-dimensional state parameters and generate N dynamic weight coefficients that characterize the real-time processing capability of each SATA channel. S3: Based on the dynamic weight coefficient, the two-level data distribution execution unit performs periodic data stream coarse-grained allocation through the first-level distribution module and performs microsecond-level real-time fine-grained adjustment by monitoring the instantaneous FIFO level through the second-level distribution module, thereby distributing the input data stream to the N SATA channels. S4: The closed-loop feedback optimization unit continuously calculates the throughput deviation between the actual throughput and the expected throughput of each SATA channel. Based on the throughput deviation, it dynamically corrects the evaluation parameters of the state evaluation unit using a hardware-implemented gradient descent algorithm. When a channel anomaly is detected, a progressive degradation strategy is initiated.

2. The FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness according to claim 1, characterized in that, In step S1, the four-dimensional status parameters of each SATA channel are collected in real time, including: The count of incomplete write commands, reg_sata_pending_cmd_cnt[i], is collected from the request queue module rqueue via hardware registers. The command queue depth is obtained from the allocation list module alloc_list. The command completion latency distribution value, reg_sata_cmd_latency_histogram[i][3:0], is also calculated. The garbage collection status flag reg_sata_gc_active[i] is extracted by parsing the SATA protocol features, the SSD health parameters are parsed from the device identification completion flag reg_sata_dev_identify_done[i], and the write amplification factor reg_write_amp_factor[i][7:0] is calculated based on the historical write mode; The link layer error count is collected from the SATA central controller module sata_ctrl_central, the physical layer real-time throughput value reg_sata_phy_throughput[i][15:0] is calculated, and the retransmission rate reg_sata_retry_ratio[i][7:0] is calculated based on the SATA protocol retransmission mechanism. SSD temperature data is collected via the I2C bus controller module IIC_TOP, and the water mark level value reg_fifo_watermark_level[i][11:0] of each SATA channel's dedicated FIFO is monitored. Based on the FIFO occupancy rate and processing latency, the cache pressure index reg_cache_pressure_index[i][7:0] is calculated, where i is the SATA channel index, 0≤i <N。 3. The FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness according to claim 1, characterized in that, In step S2, the four-dimensional state parameters are fused and calculated to generate N dynamic weighting coefficients characterizing the real-time processing capability of each SATA channel, including: The four-dimensional state parameters The normalization parameter is obtained by mapping linear normalization to a uniform dimension of 0-255. The normalization formula is as follows: Where j = 1, 2, 3, 4 correspond to the four dimensions. and These are the j-th dimension state parameters. The historical minimum and historical maximum values; The normalization parameter As address indexes, four weight lookup tables LUT_j, pre-stored in the FPGA's on-chip memory BRAM, are used for parallel lookups. Each LUT_j stores the weight coefficients K_j and the normalization parameter. The pre-calculated product result; The hardware adder tree sums the outputs of the four lookup tables LUT_j and calculates the basic weight values. As shown below: in The preset baseline weight value; The basic weight values ​​are smoothed using a first-order IIR exponential filter. Perform filtering to obtain filter weight values. The filtering formula is: Where α is the smoothing factor. This represents the filter weight value from the previous cycle; Set a minimum guaranteed weight threshold MIN_WEIGHT. When the filtered weight value weight_filtered is less than the minimum guaranteed weight threshold MIN_WEIGHT, set it to MIN_WEIGHT as the final dynamic weight coefficient.

4. The FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness according to claim 3, characterized in that, In step S3, data allocation is performed based on dynamic weighting coefficients, including: The primary distribution module, based on the dynamic weight coefficients of each SATA channel, uses a weighted round-robin algorithm to coarsely allocate the input data stream with an allocation period T_a, determining the data stream allocation ratio for each SATA channel. As shown below: in, Let i be the dynamic weighting coefficient for the i-th SATA channel. The sum of dynamic weighting coefficients for all SATA channels, 1μs≤T_a≤100μs; The secondary distribution module monitors the water level status of the dedicated FIFO of each SATA channel in real time. When the water level of the FIFO of any SATA channel exceeds the preset high threshold, data redirection is triggered within the response time Δt, where the response time Δt≤200ns. The data redirection decision selects an alternative data transmission path from the backup SATA channel with the highest current dynamic weight coefficient and whose FIFO level has not exceeded the limit, and forwards the subsequent input data stream of the channel whose FIFO level has exceeded the limit to the selected backup channel.

5. The FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness according to claim 1, characterized in that, In step S4, the evaluation parameters are dynamically corrected using a hardware-implemented gradient descent algorithm, including: The closed-loop feedback optimization unit calculates the actual throughput of each SATA channel every T milliseconds. Compared with expected throughput relative deviation The deviation formula is: The value of T is in the range of 1 ≤ T ≤ 100; The weight coefficients Kj of the state evaluation unit are updated using a hardware-implemented least mean square algorithm, and the update formula is as follows: Where μ is the configurable learning rate, Let j be the normalized value of the state parameter of the j-th dimension corresponding to the i-th SATA channel, where j=1,2,3,4 correspond to the four dimensions of the four-dimensional state parameter.

6. The FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness according to claim 1, characterized in that, In step S4, initiating the gradual degradation strategy includes: When the closed-loop feedback optimization unit detects M consecutive CRC check errors in a certain SAT channel, a progressive channel degradation strategy is initiated, where M ≥ 3; The progressive channel degradation strategy is implemented as follows: when a CRC check error is detected for the first time, the dynamic weight coefficient of the channel is reduced by a first percentage. Subsequently, each time a CRC check error is detected, the dynamic weight coefficient of the channel is reduced by a higher percentage in turn, until the Mth consecutive CRC check error is detected. At this point, the dynamic weight coefficient of the channel is set to zero, and the channel is completely isolated, and no new input data stream is allocated to it. After isolating the channel, the closed-loop feedback optimization unit redistributes the unprocessed data in the isolated channel to other healthy SATA channels.

7. The FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness according to claim 1, characterized in that, Prior to step S1, priority processing for data value perception is also included: High-speed data streams are received through a 10G Ethernet data access unit, and the application characteristics of each data packet in the high-speed data stream are parsed by the Application Oriented Service Framework (AOS). Based on a preset rule base, data packets are assigned any one of three service quality levels: high, medium, or low, according to the application characteristics. During the data allocation process performed by the two-level data distribution execution unit, a minimum bandwidth is preset to guarantee high-priority data based on the allocated quality of service level.

8. The FPGA hardware-accelerated adaptive data distribution method based on multi-dimensional state awareness according to claim 1, characterized in that, It also includes learning-based parameter optimization: Record the correspondence between historical status parameters and throughput deviations of each SATA channel to form a status transition pattern library; The system load data is analyzed by a hardware-implemented pattern recognition unit to identify the periodic characteristics and trends of the system load. Based on the identified features and trends, predict the load change trend in the near future; Based on the load change prediction results, the weight coefficients in the state assessment unit or the data distribution strategy of the two-level data distribution execution unit are adjusted in advance to achieve predictive load balancing.

9. A computer device, characterized in that, The method includes a memory and a processor, wherein the memory stores computer-readable instructions that, when executed by the processor, cause the processor to perform the steps of a multi-dimensional state-aware FPGA hardware-accelerated adaptive data distribution method as described in any one of claims 1 to 8.

10. A storage medium storing computer-readable instructions, characterized in that, When the computer-readable instructions are executed by one or more processors, the one or more processors perform the steps of a multi-dimensional state-aware FPGA hardware-accelerated adaptive data distribution method as described in any one of claims 1 to 8.

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