A specification key generation method and device for DC-DC converter topology library processing

Abstract

The application discloses a specification key generation method and device for DC-DC converter topology library processing, which is generated from the connection relationship data and port definition of a topology to be processed, and sequentially completes graph model construction, element multi-attribute coding, version mapping management, specification regulation, specification key record generation, analysis review and structure analysis, realizes de-duplication and stable indexing, structure interpretation and sub-module boundary display, and structure similarity measurement based on specification expression for classification or screening. The application generates a deterministic specification key as a database primary key, realizes equivalent topology stable same key storage, and the specification key explicitly retains a parallel level, which can be analyzed as a hierarchical tree to output an interpretable structure grouping, and calculates the structure similarity of two specification keys, forms a complete closed loop in the uniqueness, reversibility, interpretability and engineering auditability of topology expression, and supports specification storage, analysis review and structure analysis application of the topology library.

Description

Technical Field

[0001] This invention relates to the field of power electronic topology modeling and computer-aided analysis, and in particular to a method and apparatus for generating canonical keys for DC-DC converter topology library processing. Background Technology

[0002] In recent years, computer-aided or artificial intelligence methods have been able to generate a large number of candidate topologies for power electronic converters in a short period of time, making the construction and automatic screening of topology libraries a common need. However, candidate topologies often contain a large number of equivalent topologies or topologies with highly similar structures. Without an effective topology specification representation and a stable indexing mechanism, this will lead to increased redundancy within the library, decreased screening efficiency, and increased costs of repeated analysis. Traditional topology analysis methods based on functional module decomposition decompose complex converters into several basic functional units (such as buck / boost basic units), understand the topology by identifying and combining functional modules, and perform classification analysis. The decomposition process relies on expert heuristic rules and lacks a unified standard. When faced with a large number of candidate topologies, it is inefficient, lacks stability and consistency, and is difficult to form a unique and verifiable specification representation for database-level deduplication and retrieval.

[0003] Existing graph theory and computer-aided equivalence identification methods, such as loop matching-based methods, transform topological information into a loop set / matching problem. By searching and matching, they determine the existence of equivalence relationships, achieving a certain degree of automation. However, these methods rely on exhaustive or high-cost searches, and their efficiency decreases as topological complexity increases, hindering large-scale processing and rapid filtering of topology libraries. Graph modeling-based topology simplification / comparison methods transform circuits into graph structures, merging or simplifying them according to rules, and then comparing or further calculating the simplification results. This can reduce structural redundancy and improve subsequent processing efficiency, but often requires calculating and comparing complex algebraic expressions or structural relationships, making engineering implementation cumbersome. Furthermore, without a deterministic normalized output mechanism, the same topology may produce different representations under different traversal or simplification orders, hindering stable indexing and deduplication.

[0004] To avoid exhaustive search and improve discrimination efficiency, some studies combine graph theory and number theory, assigning prime weights to components and forming standardized expressions. This transforms equivalence discrimination into graph isomorphism judgment, improving the automation and efficiency of equivalence recognition to some extent. However, the generated expressions often lack direct physical structural interpretability, making it difficult to provide quantifiable structural similarity, which is not conducive to further topological classification, similarity retrieval ranking, and component role analysis. Furthermore, in engineering applications, there are still shortcomings in the extension and unambiguous encoding mechanisms for multiple component attributes (such as orientation and port role).

[0005] With the development of neural network technology, existing research has explored the use of graph neural networks and other models to extract circuit / topology features. These models use the circuit topology as a graph input model, and after training, output embeddings or features for classification / recognition, achieving strong feature representation capabilities for certain tasks. However, these models exhibit a certain degree of black-box nature, potentially posing challenges in verification, accountability, and auditability in engineering scenarios. This is detrimental to topology library processing workflows that require verifiable, interpretable, and reversible verification.

[0006] In summary, existing technologies are limited by applicable conditions or efficiency issues (such as duality / module decomposition / exhaustive matching), or have shortcomings in terms of the uniqueness of canonical representation, interpretability of expression, and reversible verification and engineering auditability. To meet the needs of large-scale application of topology libraries, a unified method is still needed that can achieve unambiguous encoding of multiple attributes, generation of deterministic canonical expressions, reversible decoding verification, and can be used as a stable method for database primary key insertion, deduplication, and indexing. Summary of the Invention

[0007] The problem to be solved by this invention is to provide a method and apparatus for generating canonical keys for DC-DC converter topology library processing. By generating deterministic canonical keys as database primary keys, equivalent topology stable input can be stored in the database. At the same time, the canonical keys explicitly preserve the series and parallel hierarchy, can be parsed into a hierarchical tree to output interpretable structural groupings, and can calculate the structural similarity between two canonical keys.

[0008] This invention adopts the following technical solution: a method for generating canonical keys for DC-DC converter topology library processing, comprising the following steps:

[0009] Step 1: Obtain the topology input of the DC-DC converter to be analyzed, including connection relationship data, port definitions and key functional nodes, perform preprocessing and consistency verification, and obtain the component set, connection point set V, port set T and key node set K;

[0010] Step 2: Construct an undirected weighted graph model, express the connection relationship of the topological input through the graph structure, and use undirected edges to carry directional attributes;

[0011] Step 3: Encode each component and extract the type code. and direction encoding The port domain label is determined by combining the port set T. Generate extended feature tags Obtain component properties A unique index is generated by performing reversible bijective encoding through multi-level nesting. ;

[0012] Step 4: Create a unique index Component properties The mapping is written into a versionable attribute dictionary, and a port signature and a key node set K are generated for each topology instance for versioned mapping management.

[0013] Step 5: Based on the undirected weighted graph model, simplify by round to obtain a unique and verifiable canonical key under the constraints of the same port set T and key node set K;

[0014] Step 6: Generate and output canonical key records, including: canonical key, dictionary version, and minimum metadata;

[0015] Step 7: Perform syntax parsing and consistency verification on the canonical keys, restore the serial-parallel hierarchical tree, and output the least conflicting subexpression. In the topology library application, the canonical keys are used as the database primary keys for index storage. When inserting data into the database, the canonical keys are used to determine whether duplicates are present and incremental insertion is performed. When querying, the canonical keys are used to quickly locate the topology entries and output the corresponding canonical key records and verification results. Based on the restored serial-parallel hierarchical tree, the submodule boundaries, serial-parallel combination relationships, and key node and port participation information corresponding to each level of brackets are output, providing structural interpretability and similarity measurement.

[0016] As a preferred embodiment, in step 1, the connection relationship data includes: a component list, an electrical node identifier (net) connected to each component endpoint, and component attribute fields, represented by a netlist, a connection matrix, or an adjacency matrix;

[0017] The key functional nodes are either annotated by the user or automatically generated by the system according to preset rules; if they do not exist, they are empty sets.

[0018] The consistency verification includes: port definition integrity, node identifier validity and uniqueness, component endpoint reference node existence, and component attribute field value location check.

[0019] As a preferred embodiment, in step 2, the undirected weighted graph model maps each connection point in the set of connection points V to a graph node, and maps each electrical element to a graph edge connecting its two electrical nodes.

[0020] The graph edge carries a weight field, which is composed of an index code value generated by reversible mapping of the element attributes, and is used to express the unique identity and attributes of the element.

[0021] For components with direction or polarity, the direction or polarity is represented by ordered pairs of the component's endpoints, which are determined by the netlist endpoint order or the device symbol definition and are encoded in direction during canonical key generation. Curing.

[0022] As a preferred option, in step 3, the component properties are... Pairing function via Cantor A unique index is obtained by reversibly bijectively encoding the nested multi-element structure. , the unique index The weights of the corresponding components in the graph model are stored for subsequent normalization merging and decoding verification.

[0023] As a preferred option, the simplification by round in step 5 is performed as follows:

[0024] Step 5.1: In each round, first identify all parts that can be connected in parallel and merge them using the preset parallel connector; then identify all parts that can be connected in series and merge them using the preset series connector. Before each merge, write each object participating in the merge as a subexpression string with a fixed format, and write the leaf object as its index. Substructures are written as parenthesized parallel-parallel expressions, using default parallel and serial connectors and including the index of the leaf node. ;

[0025] Step 5.2: Perform a deterministic sorting of the objects to be merged according to the standard sort key:

[0026] First, sort the subexpression strings in ascending lexicographical order; if the sorting results are the same, further determine the sorting order by leaf number in ascending order, subtree height in ascending order, operator signature lexicographical order, and stable hash value in ascending order; then connect them in the sorted order to generate new substructures;

[0027] Step 5.3: Repeat steps 5.1 to 5.2 until no further simplification is possible, resulting in a unique and verifiable canonical key under the constraints of the same port set T and key node set K.

[0028] As a preferred embodiment, in step 6, the canonical key record includes the following fields:

[0029] Canonical key: Used as the key for deduplication and indexing in the topology library;

[0030] The minimum metadata required for decoding and consistency verification includes: unique indexes. Component attribute mapping version number or dictionary ID, port signature, and key node reserved markers;

[0031] Error location fields when decoding or verification fails include: reason for failure, conflict location, and minimum conflict subexpression.

[0032] As a preferred embodiment, the syntax parsing and consistency verification in step 7 are performed as follows:

[0033] Perform top-down syntax parsing on the canonical keys and restore the serial-parallel hierarchical tree according to operator precedence and bracket structure;

[0034] index at the leaf The inverse mapping is used to generate component attributes, and the port signature, port domain marker, and key node retention marker are combined to generate a normalized equivalent topology and verification results.

[0035] For non-pure serial-parallel substructures in the input, the interface and signature of the unreduced subgraph are used as placeholders. In the reduction, the signature of the unreduced subgraph is regarded as a super component and participates in subsequent reduction, canonical key generation and consistency verification. It does not promise to restore the original node number and all internal details to avoid pseudo-conflicts caused by differences in input labels.

[0036] Furthermore, in step 7, the structural interpretation and similarity measurement are performed using the following methods:

[0037] Based on the hierarchical tree obtained from the parsing, the submodule boundaries, serial and parallel combination relationships, and the participation of key nodes or ports corresponding to each level of brackets are output, providing structural interpretability.

[0038] Construct subtree fingerprint vectors for the syntax trees corresponding to the two canonical keys: For each node u in the syntax tree, calculate the subtree structure fingerprint rooted at u and with a depth not exceeding D. Generate node labels using bottom-up deterministic relabeling and a fixed hash function H, including:

[0039] Leaf node labels: ;

[0040] Internal node labels: ;

[0041] in, Indicates a fixed hash function. Indicates the leaf node identifier. This indicates the index marker of the leaf element corresponding to node u; This indicates the port field label of the element corresponding to node u; This indicates the extended function marker of the element corresponding to node u; Indicates the operator type corresponding to the internal node u. When concatenating, the preset concatenation operator is used; when parallelizing, the preset parallel operator is used. It is a child node of node u, and the order of the child nodes is fixed according to the deterministic sorting result when the canonical key is generated; Represents child nodes Tags;

[0042] Collect the labels of each node as subtree fingerprints within the depth range of 1 to D, and count the occurrence of each fingerprint. Weight the counts according to depth, port domain and key node participation to form a sparse vector X.

[0043] The structural similarity between two topologies is defined as the weighted cosine similarity of sparse vectors X. The fingerprint of the common subtree with the largest contribution is backtracked into the corresponding subexpression, and the reasons for similarity and common submodules are output.

[0044] The present invention also provides: a canonical key generation device for DC-DC converter topology library processing, used to implement the aforementioned method, comprising:

[0045] The topology input and preprocessing module is used to acquire the topology input of the DC-DC converter to be analyzed and perform preprocessing.

[0046] The graph construction module is used to construct an undirected weighted graph model, which expresses the connection relationships of the topological input through the graph structure.

[0047] The component multi-attribute reversible encoding module is used to encode each component, obtain the component's multiple attributes, and perform reversible bijective encoding through multi-element nesting to generate a unique index;

[0048] The attribute dictionary and versioning management module is used to write the mapping of index and component attributes into a versionable attribute dictionary, and generate port signatures and key node set tagging information for each topology instance for versioned mapping management.

[0049] The deterministic series-parallel reduction module is used to generate canonical keys based on the canonical sorting key and the rule of parallel connection first and then series connection.

[0050] The canonical key record generation module is used to generate and output canonical key records, including: canonical key, dictionary version, and minimum metadata;

[0051] The canonical key parsing and consistency verification module is used to restore the normalized equivalent topology based on the canonical key record and output the minimum conflict subexpression;

[0052] The structure interpretation and similarity calculation module is used to output the submodule boundaries corresponding to the bracket level and calculate the structure similarity based on the subtree fingerprint vector.

[0053] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0054] 1. Unambiguous and Interpretable: This invention uses a reversible pairing index combined with a deterministic normalization reduction mechanism to explicitly represent parallel / series combinations with structural symbols and perform standardized sorting, avoiding ambiguity and conflict at the representation level between different combinations, and supporting reliable in-library deduplication and consistency verification; moreover, the expressions explicitly preserve the series and parallel hierarchical structure, and brackets / operators can correspond to physical groups, facilitating functional unit identification and structural review.

[0055] 2. Uniqueness and Consistency: This invention uses serial and parallel rule sets, port / critical node constraints, and deterministic specification sorting to output the same specification key at the representation level for equivalent / isomorphic topologies; this specification key can be used as the primary key / hash index of the topology library to achieve fast deduplication, version management, and incremental storage.

[0056] 3. Measurable structural similarity: On the same canonical expression object, this invention extracts multi-scale subtree fingerprints from the syntax tree and constructs a sparse vector X. The normalized similarity is obtained by using weighted cosine similarity, which can be used for topological classification, nearest neighbor screening and common substructure analysis, while keeping the results interpretable and auditable (it can output the subexpression corresponding to the common subtree with the largest contribution).

[0057] 4. Reversibility and Verifiability: This invention can restore the canonical key to a series-parallel hierarchical structure through top-down parsing and reverse map the index to the element attribute; under the same port signature and key node constraints, it can realize bidirectional consistency verification and difference location of the canonical key and the normalized topology.

[0058] 5. Scalability and maintainability: Through the hierarchical design of multi-attribute, reversible paired indexes and index-attribute mapping, this invention only requires expanding the attribute dictionary and index mapping when adding new device categories, orientation types or port roles, without relying on a major rewrite of the existing rule set, thus reducing engineering maintenance costs.

[0059] 6. Indexability and Efficiency: The canonical key of this invention can be directly used as the primary key / hash key of the topology library for storage and querying. It supports incremental deduplication and can achieve difference location and engineering troubleshooting through the minimum conflict subexpression during consistency verification. At the same time, for topologies that can be decomposed into serial and parallel structures, the reduction process will reduce the number of substructures after each merging. Compared with pairwise graph isomorphism / exhaustive matching, it can significantly reduce the average computational cost of deduplication within the library and deduplication judgment during the database entry, and is suitable for batch processing and online entry of large-scale candidate topologies. Attached Figure Description

[0060] Figure 1 This is a flowchart of the key generation method of the present invention;

[0061] Figure 2 This is a schematic diagram illustrating the transformation of a typical Buck topology into an undirected weighted graph in an embodiment of the present invention;

[0062] Figure 3 This is a simplified diagram of a typical Buck topology in parallel configuration in an embodiment of the present invention;

[0063] Figure 4 This is a simplified schematic diagram of a typical Buck topology in series in an embodiment of the present invention;

[0064] Figure 5This is a schematic diagram of typical Buck topology decoding and verification in an embodiment of the present invention. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the application will be further described in detail below with reference to the accompanying drawings. The described embodiments are only a part of the embodiments involved in this invention. All non-innovative embodiments based on these embodiments by other researchers in the art are within the protection scope of this invention. Furthermore, the step numbers in the embodiments of this invention are only set for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0066] This invention provides a method for generating canonical keys for processing DC-DC converter topology libraries. Targeting series-parallel DC-DC converter topology libraries, it enables deduplication and stable indexing during database entry, structural interpretation and submodule boundary display, and structural similarity measurement based on canonical expressions for classification or filtering. By generating deterministic canonical keys as database primary keys, equivalent stable topologies are entered into the database simultaneously. Furthermore, the canonical keys explicitly preserve the series-parallel hierarchy, can be parsed into a hierarchical tree to output interpretable structural groupings, and structural similarity can be calculated for two canonical keys.

[0067] The specific process is as follows: Figure 1 As shown, it includes the following steps:

[0068] S1. Topology Input and Preprocessing: Obtain the topology input of the DC-DC converter to be analyzed, including connection relationship data, port definitions and key functional nodes, perform preprocessing and consistency verification, and obtain the component set, connection point set V, port set T and key node set K.

[0069] S2. Graph Model Construction: Construct an undirected weighted graph model, express the connection relationship of the topological input through the graph structure, and use undirected edges to carry directional attributes;

[0070] S3. Component Multi-Attribute Coding: Encode each component and extract the type code. and direction encoding The port domain label is determined by combining the port set T. Generate extended feature tags Obtain component properties A unique index is generated by performing reversible bijective encoding through multi-level nesting. ;

[0071] S4. Versioned Mapping Management: This will manage the generated index. Component properties The mapping is written into a versionable attribute dictionary, and a port signature and a key node set K are generated for each topology instance for versioned mapping management.

[0072] S5. Deterministic normative constraints: Based on the undirected weighted graph model, the normative keys are simplified by round to obtain unique and verifiable normative keys under the constraints of the same port set T and key node set K.

[0073] S6. Canonical key generation and output, including: canonical key, dictionary version and minimum metadata;

[0074] S7. Parsing and Structure Analysis: Perform syntax parsing and consistency verification on the canonical keys, restore the serial and parallel hierarchical tree, output the least conflicting subexpression, locate the conflict and calculate the similarity.

[0075] Further, anomaly detection and reprocessing are performed: consistency checks and conflict judgments are conducted on the verification results obtained in step S7; when a verification failure or conflict is detected, the corresponding reprocessing process is triggered according to the anomaly type. If the anomaly originates from abnormal input data, the process returns to step S1 to reprocess the input; if the anomaly originates from abnormal component attribute extraction or encoding, the process returns to step S3 to re-extract and encode the attributes; if the anomaly originates from an inconsistent index dictionary, the process returns to step S4 to re-map the index; if the anomaly originates from an unstable reduction process, the process returns to step S5 to re-process the reduction.

[0076] In one embodiment of the present invention, the specific implementation is as follows:

[0077] 1. Topology Input:

[0078] The input data is a DC-DC topology description data packet, which includes topology connection relationship data (component list, electrical node identifier net connected to the endpoints of each component, and component attribute fields). The connection relationship data can be obtained by converting netlist representation, connection matrix representation, adjacency matrix representation, or equivalent forms. It also includes port and reference node definitions (at least Vin+, Vin-, Vout+, Vout-, GND / reference node, and allows expansion of the port set according to system conventions) as well as node semantic tags and a key node set K (marking port nodes, reference nodes, and functional nodes such as control / sampling / switching drive gates; K is a set of nodes that are forcibly reserved and do not participate in simplification; if there is no K, it is an empty set).

[0079] The output is a canonical key record (CKR), where: the canonical key is used for deduplication and indexing of the topology library; the mapping table / port signature / critical node marker is used to restore the normalized equivalence structure and perform consistency verification; and a locatable error message is returned when the verification fails.

[0080] 2. Coding Implementation:

[0081] (1) Attribute encoding: type encoding Direction coding Map according to preset dictionary; port domain marking Mapped according to preset dictionary (e.g., Vin field, Vout field, GND field, SW field, and default 0); Extended function flags Each dictionary is version-managed in the system according to a preset dictionary mapping (e.g., critical node association, controlled / driven related, etc.; if none, it is 0).

[0082] (2) Index generation: The element attributes are generated by using the nested Cantor pairing function π. Mapped to natural number index And can restore each attribute through inverse operation;

[0083] The index formula is:

[0084] .

[0085] (3) Encoding and storage: Indexing the obtained natural numbers The weights are stored as the corresponding edges in the graph model and associated with the corresponding leaf nodes to ensure that the encoding is compact, reversible, and does not rely on large number operations.

[0086] (4) Inverse mapping: During decoding, read the natural number index stored in the leaf node or the corresponding edge. and to Perform the inverse operation of the reversible bijective encoding to restore the component properties. This allows the restoration of component type, orientation, port field, and function flags, which are then used for consistency verification.

[0087] 3. Details of rule simplification implementation:

[0088] In this embodiment, the parallel connector is " The concatenation operator is "". ".

[0089] (1) Parallel identification: If two edges / substructures connect the same pair of nodes, they are considered as parallel candidates; merged into " The expression is used, and a deterministic canonical sorting key is used to ensure stable output.

[0090] (2) Serialization Identification (Port / Functional Node Constraints): If a node v has a degree of 2 and v is only used to connect two edges or substructures, and v does not belong to the port set T (Vin+, Vin-, Vout+, Vout-, GND / reference node, etc.) and does not belong to the critical node set K (such as sampling / control / drive gates, etc., nodes labeled by the user or system), then it is considered a serialization candidate; merged into " The expression is used, and a deterministic canonical sorting key is used to ensure stable output. Ports and critical nodes are forcibly preserved to avoid merging critical semantics, which would cause the canonical key to lose circuit semantics.

[0091] (3) Iterative strategy and deterministic normalization: The simplification priority is fixed as parallel first and then series, and it is iterated in rounds: after each round of series simplification, it is checked again to see if a new parallel simplifiable structure is generated, until there is no simplifiable structure.

[0092] Parentheses are used to record the order and level of merging. To ensure deterministic output, the substructures generated by each merge are sorted using a uniform sorting key, and when the sorting results are the same, symmetrical or duplicate branches are handled through multi-level backup decision rules, thereby eliminating differences in node numbering and traversal order.

[0093] (4) Termination condition: The process terminates when the graph is reduced to a single equivalent structure or when no further series-parallel patterns satisfying the rules can be found. The output canonical key is the normalization result.

[0094] (5) Declaration of normalization invariance: Under the premise of satisfying the serial-parallel identification conditions and the port / critical node constraints being consistent, the output normalization key remains consistent for any node numbering method, component traversal order, or equivalent simplification execution order in the same topology. Each parallel or serial merging reduces the number of reducible substructures in the current graph, thus terminating the reduction process within a finite number of steps; at the same time, by fixing the simplification priority and normalization sorting, order-related redundancy is eliminated, making the normalization result verifiable and stable for use as a database primary key.

[0095] (6) Applicable graph types and serial-parallel decomposition instructions: The above parallel / serial simplification rules apply to DC-DC topological subgraphs that can be decomposed into two-port serial-parallel (SP) structures. The simplification process can be regarded as constructing a serial-parallel decomposition tree (SP-tree): parallel corresponds to P nodes, and serial corresponds to S nodes; the canonical key can be regarded as the canonical serialization representation of the serial-parallel decomposition tree, thereby enhancing the auditability and consistency of the method.

[0096] (7) Boundary and non-simplifiable processing: When a node with a degree of 2 appears but belongs to a shared / bridged key node (sampling point, control node or three-port shared node across multiple functional branches), it is forcibly retained according to the key node constraint and serial simplification is not performed; when the topology contains non-pure serial-parallel structures (bridge, ring, multi-port coupled substructure) which makes it impossible to continue reduction, the partial canonical key and unreduced subgraph signature are output.

[0097] The unreduced subgraph signature uses a deterministic canonical labeling algorithm to generate a unique identifier for the unreduced subgraph under its boundary port / critical node constraints; in the specification, the unreduced subgraph signature is regarded as a super component and participates in subsequent specification, canonical key generation and consistency verification, thereby maintaining engineering applicability and result determinism.

[0098] 4. Expression decoding:

[0099] Using a top-down parsing approach, the steps are as follows:

[0100] (1) Starting with the outermost parentheses and connectors, construct the syntax tree for the canonical keys;

[0101] (2) Connect the parallel connector " "Nodes are interpreted as parallel branches, connecting them to serial connectors." "Node" is interpreted as a series connection;

[0102] (3) Recursively expand until the leaf node, the leaf node corresponds to the component attribute. Natural number index obtained by invertible mapping ;

[0103] (4) Indexes at leaf nodes Perform reverse mapping to restore attributes such as component type, orientation, port field, and function tag, and generate topological connection relationships by combining the syntax tree structure;

[0104] (5) When an index appears If there is no mapping, mismatched bracket levels, inconsistent port signatures, or conflicting constraints of critical nodes, the failure reason and location information will be returned, and the minimum conflict subexpression will be output for project troubleshooting.

[0105] Application 1: Canonical key generation, database deduplication, and consistency verification for Buck topology.

[0106] by Figure 2 Taking the typical Buck topology shown as an example, components are edges and connection points are nodes. The input netlist includes: input voltage source V, switch S, diode D, inductor L, capacitor C and load R, and gives the node identifier net to which each component is connected.

[0107] Figure 2 Examples of component types and direction codes are shown in Tables 1 and 2 below. Examples of unmarked or ordinary internal components are shown in Table 3 below. The numbers 83, 17, 109, 113, 31, and 7 represent the edge weight values ​​corresponding to the switch S, inductor L, input voltage source V, diode D, capacitor C, and load resistor R, respectively. The edge weight values ​​are composed of the index code values ​​generated by reversibly mapping the corresponding component attributes.

[0108] Table 1:

[0109]

[0110] Table 2:

[0111]

[0112] Table 3:

[0113]

[0114] The port set T includes at least Vin+, Vin-, Vout+, Vout-, and GND; the critical node set K is an empty set in this embodiment, or the switch node SW is marked as a critical node to avoid being connected in series (both cases can be handled according to the rules of this invention).

[0115] Steps S1 to S2: Map each net to a graph node according to the netlist, and map each two-end element to a graph edge connecting its two ends net; for directional elements (S, D), form ordered pairs (a→b) according to the device endpoint definition as directional semantics, and still use undirected edges to carry the connection relationship.

[0116] Step S3: Extract type code for each component With direction encoding The port domain label is determined based on whether it is connected to a port node or a reference node. Simultaneously generate functional tags. (For example: devices connected to the SW node can be denoted as) (The rest are 0). Index obtained through reversible bijective encoding and the index Write the leaf node into the canonical expression.

[0117] Steps S4 to S6: Perform deterministic reduction according to the priority of parallel connection first and then series connection.

[0118] First, identify the parallel substructure formed by the output terminals R and C to obtain the subexpression. Subsequently, this substructure is connected in series with inductor L to obtain... ;in, , , This indicates the leaf index corresponding to terminal R, terminal C, and inductor L.

[0119] On the input side, switch S and voltage source V are combined in series. Then, diode D is combined with the two branches mentioned above as an independent branch according to the parallel connection rule, and finally, the canonical bond of the Buck topology is obtained. :

[0120] ;

[0121] in, , , The leaf indices corresponding to the switch S, voltage source V, and diode D obtained in step 3 are defined by the parentheses and operators, which explicitly record the physical series and parallel connection levels.

[0122] During the reduction process, the participating objects in each parallel or series connection are sorted according to the canonical sort key. Therefore, even if the netlist node numbers or traversal order are different, the same result can still be obtained. .

[0123] In this embodiment, the parallel simplification result is as follows: Figure 3 As shown, Figure 3 This demonstrates the process of identifying and simplifying parallel substructures on the output side of a Buck topology. The objects participating in the parallel connection are deterministically ordered according to the canonical sort key, and the connection is established using the connector "". Generate parallel subexpressions.

[0124] In this embodiment, the cascade simplification result is as follows: Figure 4 As shown, Figure 4 This illustrates the process of identifying and simplifying serial substructures in a Buck topology. Under the constraints of port nodes and critical nodes, the objects participating in the serial arrangement are deterministically ordered according to the canonical sort key, and the connection is made using the connector "". Generate concatenated subexpressions.

[0125] Step S7: Upon receipt of goods, Deduplication is performed using the database primary key: if the same canonical key already exists in the database, it is determined to be an equivalent topology and the version number / source record can be updated; otherwise, it is added to the database incrementally as a new entry.

[0126] When a review is required, Perform top-down parsing to recover the hierarchical tree and index each leaf. Inverse mapping back Obtain component attributes and port or key node participation information to generate a normalized equivalent topology for review. If the review fails, output the minimum conflict subexpression to locate the source of the discrepancy.

[0127] In this embodiment, the decoding and verification results are as follows: Figure 5 As shown, Figure 5 The process of parsing the generated canonical keys, remapping the indexes, and performing consistency checks is illustrated to restore the normalized equivalence topology and locate potential conflicts.

[0128] Application 2: Structural Explanation and Similarity Calculation (Buck and Synchronous Buck Variants)

[0129] Taking Buck and its synchronous rectification variant as examples: the only difference between the two is in the output rectifier (diode D is replaced by synchronous switch S2), the rest of the main power path is the same as the filter network. According to the rules of this invention, two canonical keys G1 and G2 are obtained, which share a subexpression. The difference is only reflected in the last leaf node.

[0130] Therefore, it can be directly explained from the specification key: the two circuits share the same filter submodule and input switch-power supply submodule, and differ only in the output rectification implementation.

[0131] Furthermore, multi-scale subtree fingerprints are extracted based on the syntax tree of the two canonical expressions: labels are generated for each node from bottom to top (leaves are component attribute indexes and port fields / key markers, and internal nodes are operators). " (a combination of its child node labels), and in depth Generate a set of subtree fingerprints and their counts within the range, forming a sparse vector X.

[0132] The structural similarity score is obtained by calculating the cosine similarity of two sparse vectors weighted by depth and key node weights. Simultaneously, the common subtree fingerprints with the largest contributions are selected for backtracking to obtain common sub-expressions, which are used to explain the similarity and extract common modules. The processes for canonical key generation, database deduplication, and consistency verification in this application are consistent with those in Application 1, and will not be repeated here.

[0133] In summary, the difference between this invention and the prior art lies in:

[0134] 1) A two-stage mechanism of multi-attribute reversible pairing index → ​​structured canonical key is adopted. The component type / direction / port role / function mark is bound to a unique code through the reversible pairing index, and a verifiable canonical key is formed in the serial and parallel reduction process, thereby realizing the deterministic same key output of equivalent topology, and reserving an interface for adding attributes in the future.

[0135] 2) The output object is a standardized symbolic expression, not just a simplified diagram. The expression explicitly preserves the series and parallel hierarchy, so that each level of brackets / operators corresponds to the physical grouping of the circuit, which facilitates interpretation and engineering analysis.

[0136] 3) The canonical key naturally forms a parsable hierarchical syntax structure, which can be used for consistency verification and difference location: By parsing the bracket / operator hierarchy, the canonical key can be restored to a normalized equivalent topology, and the minimum conflict subexpression can be output for engineering troubleshooting when the verification fails, rather than being limited to equivalence judgment (equal / unequal).

[0137] 4) During the simplification process, the deterministic normalized sorting key eliminates the differences in component substitution and node numbering, making the equivalent topology naturally consistent at the representation level, which can be directly used for hash indexing and deduplication.

[0138] 5) Canonical keys enable storage primary key standardization and unified structural measurement. Canonical keys can be directly used as the database primary key of the topology library for incremental deduplication and rapid location; and using the syntax tree obtained by parsing the same canonical key as input, subtree fingerprint vectors can be directly constructed to support common substructure statistics and structural similarity measurement, thereby realizing the sharing of the same representation object for "storage-review-analysis" and reducing additional feature engineering and redundant modeling.

[0139] 6) The encoding process clearly distinguishes between attribute index generation and canonical key generation. First, a reversible pairing index is used to bind multiple attributes as unique identifiers. Then, in the specification, use the structural connector (" " The use of parentheses to construct canonical keys enables the encoding, interpretation, and inverse transformation rules to be fixed and auditable, avoiding the maintainability risks associated with relying solely on experience-based table lookups or large number calculations.

[0140] 7) Provides a deterministic structural similarity definition based on the syntax tree of canonical expressions. Extracts multi-scale subtree fingerprints (bottom-up relabeling / subtree hash, depth) from the syntax tree of canonical expressions. This process forms a weighted sparse subtree fingerprint vector, and the structural similarity between the two topologies is measured by weighted cosine similarity. This similarity shares the same representation object with the interpretability, and can be traced back to specific common submodules, avoiding reliance on unaudited black-box embeddings or simple sequence matching that is not robust to long sequences.

[0141] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for generating canonical keys for DC-DC converter topology library processing, characterized in that, Includes the following steps: Step 1: Obtain the topology input of the DC-DC converter to be analyzed, including connection relationship data, port definitions and key functional nodes, perform preprocessing and consistency verification, and obtain the component set, connection point set V, port set T and key node set K; Step 2: Construct an undirected weighted graph model, express the connection relationship of the topological input through the graph structure, and use undirected edges to carry directional attributes; Step 3: Encode each component and extract the type code. and direction encoding The port domain label is determined by combining the port set T. Generate extended feature tags Obtain component properties A unique index is generated by performing reversible bijective encoding through multi-level nesting. ; Step 4: Create a unique index Component properties The mapping is written into a versionable attribute dictionary, and a port signature and a key node set K are generated for each topology instance for versioned mapping management. Step 5: Based on the undirected weighted graph model, simplify by round to obtain a unique and verifiable canonical key under the constraints of the same port set T and key node set K; The method for simplifying by round is as follows: Step 5.1: In each round, first identify all parts that can be connected in parallel and merge them using a preset parallel connector; then identify all parts that can be connected in series and merge them using a preset series connector; before each merge, write each object participating in the merge as a subexpression string with a fixed format, and write the leaf object as its index. The substructure is written as a parenthesized series-parallel expression, using parallel and series connectors within the expression, and including the index of the leaf node. ; Step 5.2: Perform a deterministic sorting of the objects to be merged according to the standard sort key: First, sort the subexpression strings in ascending lexicographical order; if the sorting results are the same, further determine the sorting order by leaf number in ascending order, subtree height in ascending order, operator signature lexicographical order, and stable hash value in ascending order; then connect them in the sorted order to generate new substructures; Step 5.3: Repeat steps 5.1 to 5.2 until it can no longer be simplified, and obtain a unique and verifiable canonical key under the constraints of the same port set T and key node set K; Step 6: Generate and output canonical key records, including: canonical key, dictionary version, and minimum metadata; Step 7: Perform syntax parsing and consistency verification on the canonical key, restore the serial-parallel hierarchical tree, and output the least conflicting subexpression; in the topology library application, the canonical key is used as the database primary key for index storage; based on the restored serial-parallel hierarchical tree, output the submodule boundary, serial-parallel combination relationship, and key node and port participation status corresponding to each level of brackets, providing structural interpretability and similarity measurement.

2. The canonical key generation method according to claim 1, characterized in that, In step 1: The connection relationship data includes: a component list, the electrical node identifier net connected to each component endpoint, and component attribute fields, represented by a netlist, a connection matrix, or an adjacency matrix; The key functional nodes are either annotated by the user or automatically generated by the system according to preset rules; if they do not exist, they are empty sets. The consistency verification includes: port definition integrity, node identifier validity and uniqueness, component endpoint reference node existence, and component attribute field value location check.

3. The canonical key generation method according to claim 1, characterized in that, In step 2, the undirected weighted graph model maps each connection point in the set of connection points V to a graph node, and maps each electrical element to a graph edge connecting its two electrical nodes. The graph edge carries a weight field, which is composed of an index code value generated by reversible mapping of the element attributes, and is used to express the unique identity and attributes of the element. For components with direction or polarity, the direction or polarity is represented by ordered pairs of the component's two endpoints. These ordered pairs are determined by the netlist endpoint order or the device symbol definition and are encoded in direction during canonical key generation. Curing.

4. The canonical key generation method according to claim 1, characterized in that, In step 3, the component properties are... Pairing function via Cantor A unique index is obtained by reversibly bijectively encoding the nested multi-element structure. : ； The unique index The weights of the corresponding components in the graph model are stored for subsequent normalization merging and decoding verification.

5. The canonical key generation method according to claim 1, characterized in that, In step 6, the canonical key record includes the following fields: Canonical key: Used as the key for deduplication and indexing in the topology library; The minimum metadata required for decoding and consistency verification includes: unique indexes. The mapping version number or dictionary ID of the component attribute, port signature, and key node reserved marker; Error location fields when decoding or verification fails include: reason for failure, conflict location, and minimum conflict subexpression.

6. The canonical key generation method according to claim 1, characterized in that, In step 7, the syntax parsing and consistency verification are performed as follows: Perform top-down syntax parsing on the canonical keys and restore the serial-parallel hierarchical tree according to operator precedence and bracket structure; index at the leaf The inverse mapping is used to generate component attributes, and the port signature, port domain marker, and key node retention marker are combined to generate a normalized equivalent topology and verification results. For non-pure serial-parallel substructures in the input, the interface and signature of the unreduced subgraph are used as placeholders. In the reduction, the signature of the unreduced subgraph is regarded as a super component and participates in subsequent reduction, canonical key generation and consistency verification. It does not promise to restore the original node number and all internal details to avoid pseudo-conflicts caused by differences in input labels.

7. The canonical key generation method according to claim 6, characterized in that, In step 7, in the topology library application, the canonical key is used as the database primary key for index storage: When goods are received, the normalized key is used to determine whether they are duplicates, and incremental goods receipt management is performed. During the query, the topology entry is quickly located using the canonical key, and the corresponding canonical key record and verification results are output.

8. The canonical key generation method according to claim 6, characterized in that, In step 7, the structural interpretability and similarity measurement are performed using the following methods: Based on the parsed serial-parallel hierarchical tree, the submodule boundary, serial-parallel combination relationship, and participation of key nodes or ports corresponding to each level of brackets are output, providing structural interpretability. Construct subtree fingerprint vectors for the syntax trees corresponding to the two canonical keys: For each node u in the syntax tree, calculate the subtree structure fingerprint rooted at u and with a depth not exceeding D. Generate node labels using bottom-up deterministic relabeling and a fixed hash function H, including: Leaf node labels: ; Internal node labels: ; in, Indicates a fixed hash function. Indicates the leaf node identifier. This indicates the index marker of the leaf element corresponding to node u; This indicates the port field label of the element corresponding to node u; This indicates the extended function marker of the element corresponding to node u; This indicates the operator type corresponding to the internal node u. When concatenating, the concatenation operator is used; when parallelizing, the parallel operator is used. It is a child node of node u, and the order of the child nodes is fixed according to the deterministic sorting result when the canonical key is generated; Represents child nodes Tags; Collect the labels of each node as subtree fingerprints within the depth range of 1 to D, and count the occurrence of each fingerprint. Weight the counts according to depth, port domain and key node participation to form a sparse vector X. The structural similarity between two topologies is defined as the weighted cosine similarity of sparse vectors X. The fingerprint of the common subtree with the largest contribution is backtracked into the corresponding subexpression, and the reasons for similarity and common submodules are output.

9. A canonical key generation apparatus for DC-DC converter topology library processing, used in the method described in any one of claims 1 to 8, characterized in that, include: The topology input and preprocessing module is used to acquire the topology input of the DC-DC converter to be analyzed and perform preprocessing. The graph construction module is used to construct an undirected weighted graph model, which expresses the connection relationships of the topological input through the graph structure. The component multi-attribute reversible encoding module is used to encode each component, obtain the component's multiple attributes, and perform reversible bijective encoding through multi-element nesting to generate a unique index; The attribute dictionary and versioning management module is used to write the mapping of index and component attributes into a versionable attribute dictionary, and generate port signatures and key node set tagging information for each topology instance for versioned mapping management. The deterministic series-parallel reduction module is used to generate canonical keys based on the canonical sorting key and the rule of parallel connection first and then series connection. The canonical key record generation module is used to generate and output canonical key records, including: canonical key, dictionary version, and minimum metadata; The canonical key parsing and consistency verification module is used to restore the normalized equivalent topology based on the canonical key record and output the minimum conflict subexpression; The structure interpretation and similarity calculation module is used to output the submodule boundaries corresponding to the bracket level and calculate the structure similarity based on the subtree fingerprint vector.

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