Processor debugging method, device and equipment and computer readable storage medium
By collecting instruction pipeline status information throughout the entire prototype verification phase of the RISC-V processor and performing host computer simulation execution, the problems of low efficiency and difficulty in fault location of existing debugging schemes are solved, achieving low-intrusion and high-efficiency fault location.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-12
AI Technical Summary
Existing debugging solutions for RISC-V processors are inefficient, difficult to locate faults, cannot be deployed quickly, and are highly intrusive, making it impossible to efficiently and accurately locate the root cause of faults during the prototype verification phase.
During the prototype verification phase of the processor, the entire process of collecting full-dimensional status information of instructions during the execution of each stage of the pipeline is carried out. The program counter value and status information are uploaded to the host computer, and pure software simulation execution is performed using the host computer's dedicated instruction simulator to generate instruction execution benchmark data. Then, a full-dimensional comparison at the instruction level is performed to locate the root cause of the fault.
It achieves low-intrusive debugging, solves the problem of incomplete data acquisition, and accurately locates the root cause of the fault through software and hardware linkage, thereby improving the debugging efficiency and accuracy of prototype verification.
Smart Images
Figure CN122021501A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a processor debugging method, apparatus, device, and computer-readable storage medium. Background Technology
[0002] Among existing debugging technologies, the official debug / trace standard solution for RISC-V (Reduced Instruction Set Computer) has a long development cycle, is complex to implement, and is designed specifically for debugging finished chips after tape-out. It is highly invasive and cannot be quickly deployed in the prototype verification stage. On the other hand, conventional debugging methods used in the prototype verification stage have problems such as limited storage capacity, incomplete debugging data, and delayed analysis, which cannot efficiently distinguish the root cause of the fault. This seriously affects the development and verification efficiency of RISC-V processors and restricts the full realization of its customization advantages.
[0003] Therefore, there is an urgent need for a debugging solution that is suitable for the processor prototype verification stage, is low-intrusive, and provides efficient and accurate fault location, in order to solve the current technical problems of low debugging efficiency and difficulty in fault location. Summary of the Invention
[0004] In view of this, the purpose of the present invention is to provide a processor debugging method, apparatus, device and computer-readable storage medium, which solves the problems of low debugging efficiency and difficulty in fault location in the prior art.
[0005] To address the aforementioned technical problems, this invention provides a processor debugging method, comprising: During the prototype verification phase of the processor, the full-process state information of the instructions during the execution of each stage of the processor pipeline is collected, and the program counter value of the instructions and the full-dimensional state information are uploaded to the host computer. The instruction and raw data are determined based on the program counter value, and the instruction is executed in pure software simulation using the dedicated instruction simulator of the host computer based on the raw data, generating instruction execution benchmark data that matches the dimensions of the full-dimensional status information collection. The instruction execution benchmark data and the full-dimensional status information are compared at the instruction level to locate the root cause of the fault in the processor verification and determine the debugging result.
[0006] On the one hand, during the prototype verification phase of the processor, the entire process of collecting full-dimensional state information of instructions during execution at each stage of the processor pipeline is carried out, and the program counter value of the instructions and the full-dimensional state information are uploaded to the host computer, including: During the prototype verification phase of the processor, the full-scale state information of the instructions is collected throughout the execution process of each stage of the processor pipeline; the pipeline includes the fetch stage, decode stage, issue stage, execution stage, write-back stage, and retirement stage. The full-dimensional status information is stored in the information cache area. When the instruction enters the retirement stage of the pipeline, and is completed and the retirement completion signal is activated, the full-dimensional status information of the instruction in the information cache area is updated to the information storage module. The information storage module uploads all the full-dimensional status information of the instruction, as well as the program counter value of the instruction, to the host computer through the data interface.
[0007] On the one hand, it also includes: When the instruction is executed during the pipeline stage of the processor, a buffer clearing operation occurs, and the full-dimensional status information of the incomplete instructions temporarily stored in the information buffer is cleared.
[0008] On the one hand, it also includes: The storage status of the information buffer is monitored in real time. When the information buffer is full, a pipeline pause signal is output to pause the pipeline at each stage of the processor. Once there is free space in the information buffer, the pipeline pause signal is released and the execution of the pipeline at each stage of the processor resumes.
[0009] On one hand, the instruction and raw data are determined based on the program counter value, and based on the raw data, the instruction is executed in pure software simulation using the host computer's dedicated instruction simulator to generate instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection, including: An address is generated based on the program counter value, and the corresponding instruction is retrieved from the instruction storage module of the dedicated instruction simulator based on the address, and the corresponding original data is retrieved from the data storage module of the dedicated instruction simulator; the instruction storage module and the data storage module are of the same origin as the prototype; Based on the original data and the instructions, pure software simulation execution is performed using the dedicated instruction simulator to generate instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection.
[0010] On the one hand, the instruction execution benchmark data and the full-dimensional status information are compared at the instruction level to locate the root cause of the fault in the processor verification and determine the debugging results, including: The instruction information in the instruction execution benchmark data is compared with the instruction information in the full-dimensional status information. If the comparison is inconsistent, the instruction information is determined to be abnormal. The execution result data in the instruction execution benchmark data is compared with the result data in the full-dimensional status information. If the comparison is inconsistent, the execution result is determined to be abnormal.
[0011] On the one hand, it also includes: Retrieve the corresponding original data from the data storage module of the dedicated instruction simulator, and read the original source data from the data storage of the prototype; The original data is compared with the original source data. If the comparison is inconsistent, the source data is determined to be abnormal.
[0012] The present invention also provides a processor debugging apparatus, comprising: The pipeline execution module is used to collect full-dimensional state information of instructions during the prototype verification phase of the processor, and upload the program counter value of the instructions and the full-dimensional state information to the host computer. The software simulation module is used to determine the instruction and raw data based on the program counter value, and based on the raw data, to perform pure software simulation execution of the instruction using the host computer's dedicated instruction simulator to generate instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection. The comparison module is used to perform instruction-level full-dimensional comparison between the instruction execution benchmark data and the full-dimensional status information, locate the root cause of the fault in the processor verification, and determine the debugging result.
[0013] The present invention also provides a processor debugging device, comprising: Memory, used to store computer programs; A processor for implementing the processor debugging method described above when executing the computer program.
[0014] The present invention also provides a computer-readable storage medium storing computer-executable instructions, which, when loaded and executed by a processor, implement the processor debugging method described above.
[0015] The present invention also provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the steps of the processor debugging method described above.
[0016] As can be seen from the above technical solution, this invention, during the prototype verification stage of the processor, collects full-dimensional state information of instructions during the execution of each stage of the processor pipeline, and uploads the program counter value and full-dimensional state information of the instructions to the host computer; determines the instructions and raw data based on the program counter value, and uses the host computer's dedicated instruction simulator to perform pure software simulation execution of the instructions based on the raw data, generating instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection; and compares the instruction execution benchmark data and the full-dimensional state information at the instruction level to locate the root cause of the fault in the processor verification and determine the debugging results.
[0017] The beneficial effects of this invention are as follows: by collecting full-dimensional status information of the instruction pipeline throughout the entire process and uploading only this information and the program counter value, without any additional logic intervening in the processor core execution, low-intrusion debugging is achieved, and the problem of incomplete data collection is solved; based on the program counter value, the instructions and raw data are determined, and a matching dimension benchmark data is generated through a dedicated simulator on the host computer, realizing software and hardware data linkage and breaking the current situation of data fragmentation; by comparing the benchmark data and full-dimensional status information at the instruction level, the root cause of processor verification faults can be accurately located, solving the problem of difficult fault coupling location, and improving the efficiency and accuracy of prototype verification and debugging.
[0018] In addition, the present invention also provides a processor debugging apparatus, device, and computer-readable storage medium, which also have the above-mentioned beneficial effects. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0020] Figure 1 A flowchart for processor debugging is provided as an embodiment of the present invention; Figure 2 This is an example diagram illustrating the execution of a full-process data acquisition instruction, provided as an embodiment of the present invention. Figure 3 A flowchart illustrating an information storage process provided in an embodiment of the present invention; Figure 4 An example diagram of a storage format provided in an embodiment of the present invention; Figure 5 A flowchart illustrating the comparison of a dedicated instruction simulator provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a processor debugging device provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of a processor debugging device provided in an embodiment of the present invention. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0022] With the rapid development of the RISC-V (Reduced Instruction Set Computer) open-source instruction set architecture, its customizability allows processor designers to flexibly extend hardware functionality for specific application scenarios. However, this flexibility also significantly increases the complexity of hardware-software co-verification, especially in the prototype verification stage, where hardware design flaws and software logic errors are often highly coupled, making problem localization difficult. The contradiction between the design freedom of RISC-V processors and the requirements of hardware-software co-verification has created an urgent need for efficient, low-intrusion debugging solutions. Existing prototype verification methods, due to storage capacity limitations, data fragmentation, and analysis delays, struggle to quickly distinguish between hardware design errors and software logic errors during prototype verification.
[0023] This invention aims to overcome storage bottlenecks and achieve accurate problem localization by using a hardware-level tracing module and a dynamic instruction stream comparison mechanism, providing a simple and effective debugging infrastructure for the RISC-V ecosystem.
[0024] The current RISC-V standard provides debugging suggestions and a trace standard, offering a complete set of debugging methods for RISC-V processor cores. However, these standards have long development cycles, complex implementations, and primarily focus on debugging issues after tape-out, rather than prototyping in the early stages of chip design. They are also highly intrusive and cannot be quickly deployed during the early prototyping and verification process.
[0025] To address the above problems, this invention provides a processor debugging method, for details of which please refer to [reference needed]. Figure 1 , Figure 1 A flowchart illustrating processor debugging is provided as an embodiment of the present invention. The method may include: S101: During the prototype verification phase of the processor, the system collects full-dimensional status information of instructions during the execution of each stage of the processor pipeline and uploads the program counter value and full-dimensional status information of the instructions to the host computer.
[0026] The processor in this embodiment can be a RISC-V processor, that is, a processor designed based on the RISC-V open-source reduced instruction set architecture (ISA). The prototype verification stage in this embodiment refers to the core verification process of the RISC-V processor chip from design to tape-out (mass chip manufacturing), and is also the most critical hardware verification step in the chip design process. The prototype verification stage in this embodiment is a hardware prototype verification stage, such as the FPGA prototype verification stage. Simply put, it involves building a hardware prototype of the processor design using an FPGA (Field-Programmable Gate Array) to comprehensively verify the correctness of the design logic, functional completeness, and operational stability. This embodiment does not limit the upload method; for example, it can be uploaded to a host computer via the JTAG (Joint Test Action Group, an international standard testing protocol) port, or via a dedicated USB (Universal Serial Bus) interface or Ethernet interface.
[0027] In this embodiment, during the FPGA prototype verification stage of the RISC-V processor, an independent information gathering module (specifically including an information capture module, an information storage module, and an information upload module) is added to collect the current state of each stage of the RISC-V processor pipeline. The granularity of this module's collection is the state of a single instruction. This addition can be achieved by treating the information gathering module as a separate, independent hardware logic, synchronously programmed / integrated into the same prototype, but decoupled from the processor core logic hardware and operating in parallel, thus satisfying intrusiveness requirements. For example, it can be hardware-level integrated with the RISC-V processor design logic on the FPGA prototype; alternatively, the module can be bypassed via an interface, without modifying the processor core's RTL (Register Transfer Level) code, avoiding timing violations or area expansion caused by debugging logic insertion. For example, the prototype can connect to the independent information gathering module using an external interface (such as USB, SPI (Serial Peripheral Interface), or Ethernet).
[0028] This step, during the processor hardware prototype verification phase, can be performed non-intrusive data collection by a module deployed on or independently of the prototype carrier. This module collects comprehensive, multi-dimensional state information of instructions at each stage of the processor core pipeline, capturing relevant and result information generated during instruction execution. Simultaneously, it records the program counter (PC) value for each instruction and uploads the bound PC values and comprehensive state information to the host computer. This provides complete, accurate, and corresponding hardware-side execution data for subsequent hardware-software linkage comparison and fault location on the host computer. The entire collection and uploading process does not intervene in or interfere with the core execution logic of the processor core. The comprehensive state information in this embodiment includes, but is not limited to, instruction data, source operands, target operands, operation results, jump results of jump instructions, and opcodes.
[0029] Furthermore, during the processor prototype verification phase, the entire process of collecting full-dimensional state information of instructions during execution at each stage of the processor pipeline is completed. The program counter value and full-dimensional state information of the instructions are then uploaded to the host computer. Specifically, this can include: during the processor prototype verification phase, collecting full-dimensional state information of instructions during execution at each stage of the processor pipeline; the pipeline includes the fetch stage, decode stage, issue stage, execution stage, write-back stage, and retirement stage; storing the full-dimensional state information in an information buffer; when an instruction enters the retirement stage of the pipeline, completes execution, and the retirement completion signal takes effect, updating the full-dimensional state information of the instruction in the information buffer to the information storage module; and uploading all full-dimensional state information of the instructions in the information storage module, as well as the program counter value of the instructions, to the host computer via a data interface.
[0030] For example, this embodiment describes the pipeline structure of a general processor. For customized pipelines, modifications can be made according to the actual situation. Figure 2 As shown, Figure 2 This diagram illustrates a full-process instruction execution acquisition example provided by an embodiment of the present invention. Following the typical six-stage pipeline of an out-of-order processor, it is divided into six stages: instruction fetch, instruction decode, instruction issue, instruction execution, instruction write-back, and instruction retirement. Each stage performs a specific function, and the state of each stage is predictable for different executed instructions. During processor design, it is necessary to evaluate which pipeline information needs to be collected and captured, and to reserve interfaces for these information signals to connect to the information collection module.
[0031] This embodiment also further optimizes the pipeline characteristics of the superscalar out-of-order processor; for details, please refer to [reference needed]. Figure 3 , Figure 3This is a flowchart illustrating an information storage process according to an embodiment of the present invention. Considering that this type of processor pipeline executes multiple instructions in parallel and the execution and completion order of instructions may be out of order, the information collection module specifically records the status information of each instruction in the pipeline in real time through an information buffer. That is, during the prototype verification phase, the information collection module continuously collects information, assembles this information into a data format that is easy to store, stores it in the information buffer, and waits for the retirement completion signal of the current instruction. Then, it can write the information collected for that instruction into the memory through the write-to-store interface to ensure the execution order of the instructions. On the hardware prototype, based on the PC value and full-dimensional status information, a RAM (random access memory) of a certain length and depth can be set to store the collected information. The data storage format can be... Figure 4 Store in the specified format. Figure 4 This is an example diagram of a storage format provided in an embodiment of the present invention. The instruction execution status can be configured according to the length of the status information to be collected.
[0032] Furthermore, it can also include: when a buffer clearing operation occurs during the execution of an instruction at each stage of the processor pipeline, the full-dimensional status information of the incomplete instruction temporarily stored in the information buffer is cleared. In other words, if a flush operation (the flush operation is used to clear data in the buffer to ensure that the data is completely written to the target medium and to avoid data loss) occurs in the pipeline, the information gathering module will simultaneously clear the corresponding data in the information buffer to avoid invalid data being retained; only when the retirement signal of the instruction takes effect, confirming that the instruction has been truly completed, will its status information in the information buffer be updated to the information storage module, thereby ensuring that the recording order of instruction data in the information storage module is consistent with the actual execution order of the processor.
[0033] Furthermore, it can also include: real-time monitoring of the information buffer's storage status; when the information buffer is full, a pipeline pause signal is output to pause the processor's pipeline at each stage; once free space becomes available in the information buffer, the pipeline pause signal is released, and execution of each stage of the processor's pipeline resumes. In other words, when the information buffer is full, the information gathering module outputs a stall signal (a key control signal in the pipeline, i.e., the pipeline pause signal) to pause the processor's pipeline processing; once free storage space becomes available in the information buffer, the stall signal is released to resume normal operation of the processor's pipeline, ensuring complete capture of instruction status information without loss.
[0034] S102: Determine the instruction and raw data based on the program counter value, and based on the raw data, use the host computer's dedicated instruction simulator to perform pure software simulation execution of the instruction, generating instruction execution benchmark data that matches the dimensions of the full-dimensional status information collection.
[0035] This step uses the program counter value uploaded by the prototype / information collection module as a unique index to accurately locate the corresponding instruction and the raw data required for its execution from the local storage sourced from the same hardware prototype. Using a dedicated instruction simulator customized for processor prototype verification on the host computer, the instruction is executed in pure software simulation based on the located raw data. The simulation process strictly follows the RISC-V instruction set standard and does not require replicating the hardware pipeline timing. Finally, instruction execution benchmark data is generated that completely matches the full-dimensional status information collected from the prototype side in terms of data dimensions and field formats. This provides a standard and unified software-side reference for accurate comparison of subsequent software and hardware execution data.
[0036] The instructions obtained from prototype verification are those executed sequentially by the RISC-V core, thus eliminating prediction problems. Furthermore, the dedicated instruction simulator only needs to simulate the execution process of individual instructions and provide their execution status, without requiring the actual program execution. This eliminates the need to replicate the hardware pipeline timing, significantly reducing the simulator's design complexity. The host computer's dedicated instruction simulator is programmed in C to simulate the processor's execution process, including decoding, instruction execution, and data acquisition.
[0037] Furthermore, the above-mentioned method determines the instructions and raw data based on the program counter value, and based on the raw data, uses a dedicated instruction simulator on the host computer to perform pure software simulation execution of the instructions, generating instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection. Specifically, this may include: generating an address based on the program counter value, retrieving the corresponding instruction from the instruction storage module of the dedicated instruction simulator based on the address, and retrieving the corresponding raw data from the data storage module of the dedicated instruction simulator; the instruction storage module and data storage module are from the same source as the prototype; and based on the raw data and instructions, using a dedicated instruction simulator to perform pure software simulation execution, generating instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection.
[0038] Specifically, this step converts the program counter value into the corresponding address, and then retrieves the corresponding instruction from the simulator's instruction storage module and the corresponding raw data from the data storage module based on the address. The simulator's instruction storage module and data storage module are consistent with the storage content of the processor prototype. This can also be accomplished through the stored program's ELF (Executable and Linkable Format, a binary file format mainly used for executable files, object files, dynamic libraries, and kernel dump files). All of this is to ensure that the simulated raw data is indistinguishable from the prototype hardware execution environment. Subsequently, the simulator uses the retrieved instructions as the execution object and the raw data as the execution basis to carry out pure software simulation execution, and finally generates instruction execution benchmark data that completely matches the full-dimensional state information collected from the processor prototype in terms of data dimensions and field formats.
[0039] S103: Compare instruction execution baseline data and full-dimensional status information at the instruction level to locate the root cause of the fault in processor verification and determine the debugging results.
[0040] In this embodiment, the host computer can be equipped with a processor from a conventional device such as a laptop or desktop computer. The operating frequency of such processors can reach 2-3 GHz. Based on this, a dedicated instruction simulator can achieve high-speed simulated execution of instructions. The actual operating frequency of the processor prototype to be verified is usually controlled in a lower range of 50 MHz to 200 MHz, which is much lower than the operating frequency of the host computer processor. Since the clock cycle required for the prototype to process / execute an instruction is much smaller than that of the host computer, the operating speeds of the two can be matched. This allows the simulation execution speed of the host computer to fully match the hardware execution rhythm of the prototype, ensuring that after the prototype completes instruction execution, the host computer can immediately carry out corresponding simulation and data comparison work.
[0041] This comparison step allows for the detection of runtime anomalies such as instruction fetching errors, instruction execution errors, and data fetching errors. It enables immediate halting of the process and allows for analysis and debugging based on the current error information and the preserved instruction execution context. The instruction execution context is stored in the memory of the information collection module. The software program on the host computer can also display the program and assembly code before and after the problematic instruction for user analysis.
[0042] Furthermore, the aforementioned instruction execution benchmark data and full-dimensional status information are compared at the instruction level across all dimensions to pinpoint the root cause of faults in processor verification and determine the debugging results. Specifically, this can include: comparing the instruction information in the instruction execution benchmark data with the instruction information in the full-dimensional status information; if the comparison is inconsistent, the instruction information is determined to be abnormal; comparing the execution result data in the instruction execution benchmark data with the result data in the full-dimensional status information; if the comparison is inconsistent, the execution result is determined to be abnormal. This embodiment, by comparing instruction information and execution result data across dimensions, can quickly and accurately locate the specific anomaly type of the hardware prototype, improving the efficiency and accuracy of fault diagnosis.
[0043] Furthermore, it may also include: retrieving the corresponding original data from the data storage module of the dedicated instruction simulator, and reading the original source data from the prototype's data storage; comparing the original data with the original source data, and if the comparison is inconsistent, determining that the source data is abnormal. The cross-end comparison of source data in this embodiment can accurately identify inconsistencies in the original data on both the software and hardware sides, investigate anomalies from the data source, avoid distortion of subsequent instruction execution comparison results due to source data deviations, and improve the accuracy and comprehensiveness of fault location.
[0044] Furthermore, it may also include: if the instruction is a memory read / write operation, the object data of the memory read / write operation is collected as a dedicated field of full-dimensional status information, and stored in memory with the program counter value as an index; correspondingly, the program counter value and full-dimensional status information including object data and execution result data are uploaded to the host computer. This embodiment also considers that when the instruction executed by the processor prototype includes memory read / write actions, the object data corresponding to the instruction read / write operation will be stored in an independent RAM (random access memory) storage area, and the program counter (PC) value of the instruction will be used as a unique index to achieve precise binding between operation data and instructions; when uploading the PC value of the instruction to the host computer, the bound memory operation object data and the result data after instruction execution will be uploaded simultaneously, ensuring that the host computer can obtain the complete data link from the operation object to the execution result of memory read / write instructions when performing software and hardware data comparison, avoiding the inability to accurately locate the anomaly of memory operation instructions due to the lack of key data.
[0045] Furthermore, the information collection module can also capture the execution status of store-type operations in the processor core in real time and synchronously update the execution results of the operation to the corresponding location in the data storage module of the host computer's dedicated instruction simulator. At the same time, the instruction storage logic of the processor prototype is required to be deterministic to avoid random deviations in the instruction storage content. The host computer synchronously accesses the local instruction storage module through the program counter (PC) value to ensure that the instruction and data storage content on the prototype side and the host computer side are always consistent, providing consistent and unbiased basic data for pure software simulation execution and data comparison.
[0046] Furthermore, it can also include: classifying and labeling the full-dimensional status information and instruction execution benchmark data for storage. Classification dimensions include instruction type, pipeline anomaly type, and data comparison result type. Simultaneously, an index library is established linking PC values to various labeled data types. The host computer supports multi-dimensional data retrieval and backtracking analysis based on PC values, anomaly types, and instruction types using this index library. By classifying and labeling the full volume of collected and simulated data and establishing a linked index library, structured and refined management of verification data is achieved. This overcomes the limitations of single PC value retrieval, supports multi-dimensional rapid retrieval, location, and backtracking of anomaly-related end-to-end data by the host computer, significantly improving the efficiency of fault tracing during processor prototype verification. It also provides structured data analysis basis for processor design optimization, further enhancing the data analysis capabilities of prototype verification.
[0047] The processor debugging method provided in this invention involves collecting full-dimensional state information of instructions during the execution of each stage of the processor pipeline during the prototype verification phase. The program counter value and the full-dimensional state information are then uploaded to a host computer. Based on the program counter value, the instructions and raw data are determined. Using the raw data, a dedicated instruction simulator on the host computer is used to simulate the execution of the instructions in pure software, generating instruction execution benchmark data that matches the dimensions of the collected full-dimensional state information. Finally, the instruction execution benchmark data and the full-dimensional state information are compared at the instruction level to pinpoint the root cause of the fault in the processor verification and determine the debugging results. This method collects full-process, multi-dimensional state information of the instruction pipeline execution during the processor prototype verification phase, comprehensively acquiring core data at each stage of instruction execution, thus solving the problem of incomplete data collection in conventional debugging methods. Simultaneously, it completes hardware-side data output solely by collecting and uploading program counter values and multi-dimensional state information, without any additional hardware logic intervening in the processor's core execution flow, achieving low-intrusion debugging and avoiding the drawbacks of highly invasive and slow-deployment-prone official debugging solutions. Instructions and raw data can be determined based on the program counter value, and pure software simulation execution is performed through a dedicated instruction simulator on a host computer, generating benchmark data that matches the dimensions of the multi-dimensional state information collection. This achieves linkage between software and hardware based on the same source instructions and raw data, breaking the current situation of software and hardware data separation and solving the problem of difficulty in accurate comparison. By comparing the instruction execution benchmark data with the multi-dimensional state information at the instruction level, the root cause of faults in processor verification can be directly located, solving the core problems of difficulty in distinguishing root causes and low debugging efficiency caused by software-hardware fault coupling in existing technologies, significantly improving the efficiency and accuracy of fault location in the processor prototype verification phase.
[0048] For a clearer understanding of this invention, please refer to the following details. Figure 5 , Figure 5 A flowchart illustrating the comparison of the dedicated instruction simulator provided in this embodiment of the invention may specifically include: The simulation process is as follows: (1) On the one hand, the dedicated instruction simulator has an instruction storage module that stores the same instruction files used in FPGA prototype verification; (2) The dedicated instruction simulator generates an address from the instruction file based on the PC value obtained from the prototype, and retrieves instruction information from the instruction file; (3) Compare the instruction information obtained from the instruction file with the instruction information obtained from the prototype. If they are inconsistent, stop the verification and report an exception. (4) On the other hand, the dedicated instruction simulator has a data storage module to store the data stored in memory during prototype verification; (5) The dedicated instruction simulator decodes and executes the instructions obtained from the prototype. If the instructions contain original data, the dedicated instruction simulator retrieves the corresponding data from its own data storage module and compares it with the source data in the execution information obtained from the prototype. If they are inconsistent, an exception is reported and the verification is terminated. (6) The executable program in the dedicated instruction simulator executes the decoded instructions and compares the execution result with the result data obtained from the prototype verification. If they are inconsistent, an exception is reported and the verification is terminated.
[0049] As can be seen, applying this method to the FPGA prototyping stage of RISC-V processor core design can achieve rapid problem localization during FPGA prototyping. Compared to traditional debugging methods (such as JTAG breakpoint debugging), which require pausing processor operation to obtain the state, this method can dynamically capture errors during full-speed operation through instruction-level state capture and real-time comparison mechanisms, avoiding context loss due to pauses. By comparing state snapshots before and after instruction execution, problems can be converged to the single instruction level, significantly improving efficiency compared to traditional log backtracking. The information collection module is accessed via an interface bypass, without modifying the processor core's RTL code, avoiding timing violations or area expansion caused by debugging logic insertion. Through a closed-loop verification mechanism of real-time hardware state mirroring and accurate software model simulation, the pain points of low efficiency, coarse granularity, and high invasiveness in traditional prototype debugging are solved. Its core value lies in elevating hardware debugging to the level of "instruction-level holographic vision," which is particularly suitable for verifying superscalar, multi-core, and safety-critical processor designs, and is expected to become a standardized debugging interface in the RISC-V ecosystem.
[0050] The processor debugging apparatus provided in the embodiments of the present invention will be described below. The processor debugging apparatus described below and the processor debugging method described above can be referred to each other.
[0051] Please refer to the details. Figure 6 , Figure 6 A schematic diagram of a processor debugging device provided in an embodiment of the present invention may include: The pipeline execution module 100 is used to collect full-dimensional state information of instructions during the prototype verification stage of the processor, and upload the program counter value of the instructions and the full-dimensional state information to the host computer. The software simulation module 200 is used to determine the instruction and raw data based on the program counter value, and based on the raw data, to perform pure software simulation execution of the instruction using the dedicated instruction simulator of the host computer, generating instruction execution benchmark data that matches the dimensions of the full-dimensional status information collection. The comparison module 300 is used to perform an instruction-level full-dimensional comparison between the instruction execution benchmark data and the full-dimensional status information, locate the root cause of the fault in the processor verification, and determine the debugging result.
[0052] Based on the above embodiments, the pipeline execution module 100 may include: An execution unit is used to collect the full-dimensional state information of the instruction during the execution of each stage of the processor pipeline during the prototype verification phase of the processor; the pipeline includes a fetch stage, a decode stage, a issue stage, an execution stage, a write-back stage, and a retirement stage. The storage unit is used to store the full-dimensional status information into the information cache area. When the instruction enters the retirement stage of the pipeline, and is completed and the retirement completion signal takes effect, the full-dimensional status information of the instruction in the information cache area is updated to the information storage module. The upload unit is used to upload all the full-dimensional status information of the instruction in the information storage module, as well as the program counter value of the instruction, to the host computer through the data interface.
[0053] Based on the above embodiments, the processor debugging apparatus may further include: The clearing module is used to clear all dimensions of the status information of the incomplete instructions temporarily stored in the information buffer when a clearing buffer operation occurs during the execution of the instruction in each stage of the processor pipeline.
[0054] Based on the above embodiments, the processor debugging apparatus may further include: The monitoring module is used to monitor the storage status of the information buffer in real time. When the information buffer is full, it outputs a pipeline pause signal to pause the pipeline of each stage of the processor. After the information buffer has free space, it releases the pipeline pause signal and resumes the execution of each stage of the processor pipeline.
[0055] Based on the above embodiments, the software simulation module 200 may include: The raw data acquisition unit is used to generate an address based on the program counter value, retrieve the corresponding instruction from the instruction storage module of the dedicated instruction simulator based on the address, and retrieve the corresponding raw data from the data storage module of the dedicated instruction simulator; the instruction storage module and the data storage module are of the same origin as the prototype; The simulation execution unit is used to perform pure software simulation execution based on the original data and the instructions using the dedicated instruction simulator, and generate instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection.
[0056] Based on the above embodiments, the comparison module 300 may include: The first anomaly unit is used to compare the instruction information in the instruction execution benchmark data with the instruction information in the full-dimensional status information. If the comparison is inconsistent, the instruction information is determined to be abnormal. The second anomaly unit is used to compare the execution result data in the instruction execution baseline data with the result data in the full-dimensional status information. If the comparison is inconsistent, the execution result is determined to be abnormal.
[0057] Based on the above embodiments, the processor debugging apparatus may further include: The data acquisition module is used to retrieve the corresponding original data from the data storage module of the dedicated instruction simulator and to read the original source data from the data storage of the prototype. The exception module is used to compare the original data with the original source data. If the comparison is inconsistent, the source data is determined to be abnormal.
[0058] It should be noted that the order of the modules and units in the aforementioned processor debugging device can be changed without affecting the logic.
[0059] The processor debugging device provided in this embodiment of the invention uses a pipeline execution module 100 to collect full-dimensional state information of instructions during the prototype verification stage of the processor, and uploads the program counter value of the instructions and the full-dimensional state information to a host computer. A software simulation module 200 determines the instructions and raw data based on the program counter value, and performs pure software simulation execution of the instructions using a dedicated instruction simulator on the host computer based on the raw data, generating instruction execution benchmark data that matches the dimensions of the collected full-dimensional state information. A comparison module 300 performs a full-dimensional instruction-level comparison between the instruction execution benchmark data and the full-dimensional state information to locate the root cause of the fault in the processor verification and determine the debugging result. This device collects full-process, multi-dimensional state information during the instruction pipeline execution phase of the processor prototype verification stage, comprehensively acquiring core data at each stage of instruction execution. This solves the problem of incomplete data acquisition in conventional debugging methods. Simultaneously, it completes hardware-side data output solely by collecting and uploading program counter values and multi-dimensional state information, without any additional hardware logic intervening in the processor's core execution flow. This achieves low-intrusion debugging, avoiding the drawbacks of highly invasive and slow-deployment-prone official debugging solutions. Instructions and raw data can be determined based on the program counter value, and pure software simulation execution is performed through a dedicated instruction simulator on the host computer. This generates benchmark data matching the dimensions of the multi-dimensional state information collection, enabling software and hardware to work together based on the same source instructions and raw data. This breaks down the current situation of software and hardware data separation and solves the problem of difficulty in accurate comparison. By comparing the instruction execution benchmark data with the multi-dimensional state information at the instruction level, the root cause of faults in processor verification can be directly located. This solves the core problem of difficulty in distinguishing root causes and low debugging efficiency caused by software-hardware fault coupling in existing technologies, significantly improving the efficiency and accuracy of fault location during the processor prototype verification stage.
[0060] Figure 7 This is a schematic diagram of the structure of a processor debugging device provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the processor debugging device includes: Memory 60 is used to store computer programs; The processor 61 is used to implement the steps of the processor debugging method as described in the above embodiments when executing a computer program.
[0061] The processor debugging device provided in this embodiment may include, but is not limited to, smartphones, tablets, laptops, or desktop computers.
[0062] The processor 61 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 61 may be implemented using at least one hardware form selected from Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor, also known as the Central Processing Unit (CPU), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 61 may integrate a Graphics Processing Unit (GPU), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 61 may also include an Artificial Intelligence (AI) processor, which handles computational operations related to machine learning.
[0063] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In this embodiment, the memory 60 is used to store at least the following computer program 601, which, after being loaded and executed by the processor 61, can implement the relevant steps of the processor debugging method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. The operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include, but is not limited to, data related to the processor debugging method.
[0064] In some embodiments, the processor debugging device may further include a display screen 62, an input / output interface 63, a communication interface 64, a power supply 65, and a communication bus 66.
[0065] Those skilled in the art will understand that Figure 7 The structure shown does not constitute a limitation on the processor debugging device and may include more or fewer components than illustrated.
[0066] It is understood that if the processor debugging method in the above embodiments is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the current technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods in the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk, or optical disk, and other media capable of storing program code.
[0067] Based on this, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the processor debugging method described above.
[0068] The following describes a computer program product provided by an embodiment of this application. The computer program product described below can be referred to in conjunction with other embodiments described herein.
[0069] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the aforementioned disclosed processor debugging method.
[0070] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0071] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0072] Finally, it should be noted that in this document, relationships such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.
[0073] The present invention has provided a detailed description of a processor debugging method, apparatus, device, and computer-readable storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A processor debugging method, characterized in that, include: During the prototype verification phase of the processor, the full-process state information of the instructions during the execution of each stage of the processor pipeline is collected, and the program counter value of the instructions and the full-dimensional state information are uploaded to the host computer. The instruction and raw data are determined based on the program counter value, and the instruction is executed in pure software simulation using the dedicated instruction simulator of the host computer based on the raw data, generating instruction execution benchmark data that matches the dimensions of the full-dimensional status information collection. The instruction execution benchmark data and the full-dimensional status information are compared at the instruction level to locate the root cause of the fault in the processor verification and determine the debugging result.
2. The processor debugging method according to claim 1, characterized in that, During the processor prototype verification phase, the entire process of collecting full-dimensional state information of instructions during execution at each stage of the processor pipeline is performed. The program counter values of the instructions and the full-dimensional state information are then uploaded to the host computer, including: During the prototype verification phase of the processor, the full-scale state information of the instructions is collected throughout the execution process of each stage of the processor pipeline; the pipeline includes the fetch stage, decode stage, issue stage, execution stage, write-back stage, and retirement stage. The full-dimensional status information is stored in the information cache area. When the instruction enters the retirement stage of the pipeline, and is completed and the retirement completion signal is activated, the full-dimensional status information of the instruction in the information cache area is updated to the information storage module. The information storage module uploads all the full-dimensional status information of the instruction, as well as the program counter value of the instruction, to the host computer through the data interface.
3. The processor debugging method according to claim 2, characterized in that, Also includes: When the instruction is executed during the pipeline stage of the processor, a buffer clearing operation occurs, and the full-dimensional status information of the incomplete instructions temporarily stored in the information buffer is cleared.
4. The processor debugging method according to claim 2, characterized in that, Also includes: The storage status of the information buffer is monitored in real time. When the information buffer is full, a pipeline pause signal is output to pause the pipeline at each stage of the processor. Once there is free space in the information buffer, the pipeline pause signal is released and the execution of the pipeline at each stage of the processor resumes.
5. The processor debugging method according to claim 1, characterized in that, The instruction and raw data are determined based on the program counter value. Based on the raw data, the instruction is executed using a dedicated instruction simulator on the host computer in pure software simulation, generating instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection, including: An address is generated based on the program counter value, and the corresponding instruction is retrieved from the instruction storage module of the dedicated instruction simulator based on the address, and the corresponding original data is retrieved from the data storage module of the dedicated instruction simulator; the instruction storage module and the data storage module are of the same origin as the prototype; Based on the original data and the instructions, pure software simulation execution is performed using the dedicated instruction simulator to generate instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection.
6. The processor debugging method according to claim 1, characterized in that, The instruction execution benchmark data and the full-dimensional status information are compared at the instruction level to locate the root cause of the fault in the processor verification and determine the debugging results, including: The instruction information in the instruction execution benchmark data is compared with the instruction information in the full-dimensional status information. If the comparison is inconsistent, the instruction information is determined to be abnormal. The execution result data in the instruction execution benchmark data is compared with the result data in the full-dimensional status information. If the comparison is inconsistent, the execution result is determined to be abnormal.
7. The processor debugging method according to claim 1, characterized in that, Also includes: Retrieve the corresponding original data from the data storage module of the dedicated instruction simulator, and read the original source data from the data storage of the prototype; The original data is compared with the original source data. If the comparison is inconsistent, the source data is determined to be abnormal.
8. A processor debugging device, characterized in that, include: The pipeline execution module is used to collect full-dimensional state information of instructions during the prototype verification phase of the processor, and upload the program counter value of the instructions and the full-dimensional state information to the host computer. The software simulation module is used to determine the instruction and raw data based on the program counter value, and based on the raw data, to perform pure software simulation execution of the instruction using the host computer's dedicated instruction simulator to generate instruction execution benchmark data that matches the dimensions of the full-dimensional state information collection. The comparison module is used to perform instruction-level full-dimensional comparison between the instruction execution benchmark data and the full-dimensional status information, locate the root cause of the fault in the processor verification, and determine the debugging result.
9. A processor debugging device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the processor debugging method as described in any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when loaded and executed by a processor, implement the processor debugging method as described in any one of claims 1 to 7.