Automatic generation method and system of memory architecture, medium, program and electronic terminal

Abstract

The invention provides an automatic generation method and system for a memory architecture, a medium, a program and an electronic terminal, and the method comprises the steps: retrieving and extracting at least one candidate storage macro-cell meeting a matching condition from a process library file according to a theoretical process parameter and a theoretical specification of a target memory in a demand information table; and based on a preset generation rule, determining at least one target memory architecture scheme formed by one or more candidate memory macro-units. Therefore, errors caused by human factors such as interface mismatching or signal conflicts are avoided, the efficiency is high, and the labor cost and the time cost of chip debugging and design are substantially reduced.

Description

Technical Field

[0001] This disclosure relates to the field of chip design and manufacturing, and in particular to a method, system, medium, program and electronic terminal for automatically generating memory architectures. Background Technology

[0002] In the chip design and manufacturing process, chip design companies often need to splice together several memory macrocells provided by wafer foundries (such as TSMC, SMIC, etc.) to customize chips with specific performance or functions, thereby meeting the usage requirements of specific application scenarios.

[0003] Because the splicing of storage macrocells involves a large number of complex mathematical calculations and logic designs, the traditional manual splicing method is inefficient and prone to errors. During the design process, even a minor error in bit width calculation or pin typography can lead to serious interface mismatches or signal conflicts. Furthermore, because such low-level errors are often hidden, troubleshooting them later is like finding a needle in a haystack, which not only greatly increases the complexity of debugging but may also cause the entire design process to stall.

[0004] Furthermore, chip development cycles are often lengthy. In the current complex international situation, market fluctuations, supply chain policy adjustments, or geopolitical changes frequently lead to unexpected situations where chip design is interrupted halfway through, forcing a change of wafer foundry. Different wafer foundries and different process nodes (such as 6nm and 12nm) use different manufacturing equipment and have different pre-defined physical rules (i.e., significant differences in process limitations). This results in significant differences in the physical specifications (such as length and width, pin arrangement) and performance characteristics (such as operating voltage, read / write speed, and power consumption) of the memory macrocells produced by different foundries. Therefore, changing wafer foundries often requires redesigning the splicing scheme. Splicing schemes and packaging code designed over weeks or even months become instantly obsolete. Designers are forced to determine the splicing scheme from scratch and rewrite all the code based on the new foundry's supply situation. This repetitive work incurs extremely high human and time costs, severely hindering the time-to-market of chip products. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this disclosure is to provide an automatic generation method, system, medium, program and electronic terminal for memory architecture to solve the aforementioned problems.

[0006] The first aspect of this disclosure provides an automatic generation method for memory architecture, comprising: acquiring a process library file and a target memory requirement information table; retrieving and extracting at least one candidate memory macrocell that meets matching conditions from the process library file based on the theoretical process parameters and theoretical specifications of the target memory in the requirement information table; wherein, the candidate memory macrocell meets the matching conditions if the calibration process parameters and calibration specifications of the candidate memory macrocell meet the requirements of the theoretical process parameters and theoretical specifications of the target memory; and determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells based on preset generation rules; wherein, the generation rules include: performing performance parameter back-calculation on the architecture as a whole to obtain the corresponding actual process parameters and actual specifications, wherein the actual process parameters and actual specifications should meet the requirements of the theoretical process parameters and theoretical specifications; wherein the theoretical specifications, calibration specifications, and actual specifications do not include bit width and depth.

[0007] In some embodiments of this disclosure, when multiple candidate memory macrocells are spliced ​​together to form a target memory architecture, the generation rules further include at least one of the following constraints: splicing follows the principle of prioritizing splicing of similar types; splicing follows the principle of prioritizing splicing of width; the signal fan-out corresponding to the total bit width of the target memory architecture does not exceed a preset maximum fan-out threshold; the number of logic levels corresponding to the total depth of the target memory architecture does not exceed a preset maximum logic level threshold; and the physical aspect ratio of the target memory architecture does not exceed a preset ratio range.

[0008] In some embodiments of this disclosure, the generation rules further include several preference conditions, and the method for determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells includes: generating several initial target memory architecture schemes under the premise of satisfying the theoretical process parameters and theoretical specifications; mapping each preference condition to a corresponding fitness function; iteratively evolving each initial architecture scheme based on a non-dominated sorting genetic algorithm and scoring it according to the fitness function during the evolution process to select a set of candidate architectures on the Pareto optimal boundary; and selecting at least one initial architecture scheme from the set of candidate architectures as the target memory architecture scheme.

[0009] In some embodiments of this disclosure, the preference conditions include at least one of: dynamic power consumption for read / write, static leakage power consumption, critical path latency, physical aspect ratio, and cabling congestion.

[0010] In some embodiments of this disclosure, after determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells, a corresponding file list is generated according to the target memory architecture scheme, and the file list is compiled and verified by a compilation tool. The architecture scheme that passes the compilation verification is retained as the final target memory architecture scheme.

[0011] In some embodiments of this disclosure, the theoretical specifications, calibration specifications, and actual specifications include at least one of the following: clock frequency, read / write latency, dynamic power consumption, static power consumption, physical area, operating voltage, and operating temperature.

[0012] A second aspect of this disclosure provides an automatic generation method system for memory architecture, comprising: an information acquisition module for acquiring a process library file and a target memory requirement information table; a candidate memory macrocell matching module for retrieving and extracting at least one candidate memory macrocell that meets matching conditions from the process library file based on the theoretical process parameters and theoretical specifications of the target memory in the requirement information table; wherein, the candidate memory macrocell meeting the matching conditions means that the calibration process parameters and calibration specifications of the candidate memory macrocell meet the requirements of the theoretical process parameters and theoretical specifications of the target memory; and an architecture scheme generation module for determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells based on preset generation rules; wherein, the generation rules include: performing performance parameter back-calculation on the architecture as a whole to obtain the corresponding actual process parameters and actual specifications, wherein the actual process parameters and actual specifications should meet the requirements of the theoretical process parameters and theoretical specifications; wherein the theoretical specifications, calibration specifications, and actual specifications do not include bit width and depth.

[0013] A third aspect of this disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the automatic generation method of the memory architecture described in any of the preceding claims.

[0014] A fourth aspect of this disclosure provides a computer program product including computer program code that, when run on a computer, causes the computer to implement the automatic generation method of the memory architecture described in any of the preceding claims.

[0015] The fifth aspect of this disclosure provides an electronic terminal including a memory, a processor, and a computer program stored on the memory, wherein the processor executes the computer program to implement the automatic generation method of the memory architecture described in any of the preceding claims.

[0016] As described above, the automatic generation method for memory architecture disclosed herein has the following beneficial effects:

[0017] This method, based on the theoretical process parameters and specifications of the target memory in the requirements information table, retrieves and extracts at least one candidate memory macrocell that meets the matching conditions from the process library file; and, based on preset generation rules, determines at least one target memory architecture scheme composed of one or more of the candidate memory macrocells. In this way, the tedious work that relies heavily on personal experience and meticulousness in existing technologies is replaced by machine processing, avoiding errors caused by human factors such as interface mismatches or signal conflicts. It frees chip designers from tedious low-level logic verification and high-frequency repetitive labor. Furthermore, it only needs to match the target memory requirements information table and process library file, combined with generation rules, to determine a feasible memory architecture construction scheme, resulting in extremely high efficiency and a substantial reduction in the human and time costs of chip debugging and design. When a design manufacturer needs to switch the memory macrocell manufacturer from TSMC to SMIC, it only needs to update the requirements information table and process library file in step S1 to automatically retrieve the new manufacturer's supply and quickly regenerate a matching scheme, greatly improving the product's survival and time-to-market speed in volatile market environments. Attached Figure Description

[0018] Figure 1 The diagram shown is a flowchart illustrating an automatic generation method for a memory architecture according to an embodiment of this disclosure.

[0019] Figure 2 The diagram shown is a flowchart illustrating a method for determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells, according to an embodiment of this disclosure.

[0020] Figure 3 The diagram shown is a structural schematic of an automatic memory architecture generation method system according to an embodiment of this disclosure.

[0021] Figure 4 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of this disclosure. Detailed Implementation

[0022] It should be noted first that:

[0023] 1. The following specific embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can make various modifications, additions, changes, or equivalent substitutions to the above embodiments without departing from the spirit and scope of this disclosure. All technical solutions equivalent to those defined in the claims of this disclosure, or changes that a person skilled in the art can conceive of after reading this disclosure without creative effort, should be covered within the protection scope of this disclosure. The protection scope of this disclosure should be determined by the scope of the claims.

[0024] 2. Where there is no conflict, the various embodiments and features in the embodiments of this disclosure can be combined with each other, and the technical solutions formed by the combination are all considered to be the content of this disclosure. For the sake of brevity, this specification will not exhaustively list all possible combinations, but these combinations are also within the protection scope of this disclosure.

[0025] In this disclosure, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c" can represent a single (a, b, c), two (a and b, a and c, b and c), or three (a, b, and c), that is, a, b, or c can be one of them or a combination of multiples.

[0026] 3. The division of modules (or units) in this embodiment is illustrative and represents only one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of this disclosure can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0027] Furthermore, those skilled in the art will recognize that the various illustrative logic blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0028] 4. In the embodiments of this disclosure, terms such as "zeroth" and "first" are used to distinguish identical or similar items with essentially the same function and effect. For example, "first XX" and "second XX" are merely to distinguish different XXs and do not limit their order, quantity, or execution sequence. Furthermore, terms such as "zeroth" and "first" do not necessarily imply that they are different.

[0029] In this disclosure, the terms "exemplary" or "for example" indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0030] The automatic generation method, system, medium, program, and electronic terminal of the memory architecture proposed in this disclosure will be described below with reference to some embodiments.

[0031] like Figure 1 As shown, the first aspect of this disclosure provides an automatic generation method for memory architecture, comprising: step S1: obtaining a process library file and a target memory requirement information table; step S2: retrieving and extracting at least one candidate memory macrocell that meets matching conditions from the process library file based on the theoretical process parameters and theoretical specifications of the target memory in the requirement information table; wherein, the candidate memory macrocell meeting the matching conditions means that the calibration process parameters and calibration specifications of the candidate memory macrocell meet the requirements of the theoretical process parameters and theoretical specifications of the target memory; and step S3: determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells based on preset generation rules; wherein, the generation rules include: performing performance parameter back-calculation on the architecture as a whole to obtain the corresponding actual process parameters and actual specifications, wherein the actual process parameters and actual specifications should meet the requirements of the theoretical process parameters and theoretical specifications; wherein the theoretical specifications, calibration specifications, and actual specifications do not include bit width and depth.

[0032] This embodiment utilizes the disclosed memory architecture generation method to replace the tedious work in existing technologies, which heavily relies on personal experience and meticulousness, with machine processing. This avoids errors caused by human factors such as interface mismatches or signal conflicts, freeing chip designers from tedious low-level logic verification and high-frequency repetitive labor. Furthermore, it only requires matching the target memory's requirements information table and process library file, combined with generation rules, to determine a feasible memory architecture construction scheme, resulting in extremely high efficiency and a substantial reduction in the human and time costs of chip debugging and design. When a design manufacturer needs to switch the memory macrocell supplier from TSMC to SMIC, it only needs to update the requirements information table and process library file in step S1 to automatically retrieve the new supplier's inventory and quickly regenerate a matching scheme, greatly improving the product's survival and time-to-market speed in volatile market environments.

[0033] In step S1, the process library file and the target memory requirement information table are obtained.

[0034] It should be understood that the process library file is an underlying database provided by the semiconductor foundry, which contains all silicon-proven memory macrocells at the current process node. Each memory macrocell comes with corresponding calibration parameters, such as the physical size, interface characteristics, electrical characteristics, etc., of the memory macrocell. The target memory requirements table, on the other hand, is provided by the chip designer and defines the expected performance parameters of the target memory to be designed.

[0035] In step S2, based on the theoretical process parameters and theoretical specifications of the target memory in the demand information table, at least one candidate memory macrocell that meets the matching conditions is retrieved and extracted from the process library file; wherein, the candidate memory macrocell meets the matching conditions means that the calibration process parameters and calibration specifications of the candidate memory macrocell meet the requirements of the theoretical process parameters and theoretical specifications of the target memory.

[0036] The theoretical process parameters refer to the hard constraints of the manufacturing process dimensions expected to be achieved by the target memory, such as process nodes. The theoretical specifications refer to the indicators of the overall operating performance of the target memory architecture, such as clock frequency, read / write latency, dynamic power consumption, static power consumption, physical area, operating voltage, and operating temperature. It should be emphasized that the theoretical specifications do not include the bit width and depth of the target memory. That is, the overall capacity (bit width and depth) of the storage macrocell is not considered in the search and matching process in step S2. This is because, in chip design, due to the special application requirements brought about by specific application scenarios, it is usually not possible to directly use a single storage macrocell as the target memory. It is often necessary to combine multiple types of storage macrocells or multiple storage macrocells of the same type together to form the target memory. Therefore, in the step of screening candidate storage macrocells, the bit width and depth of individual candidate macrocells are not required.

[0037] The matching criteria refer to the fact that the calibration process parameters and specifications of the candidate memory macrocell in its individual state can effectively meet the working boundaries defined by the theoretical process parameters and specifications set by the target memory. Specifically, the matching criteria include two different judgment logics based on the specific physical properties and operational requirements of the parameters: the first is absolute consistency judgment, and the second is threshold range judgment. Absolute consistency means that for basic parameters that must have specific values ​​or attributes to function properly, "meeting the requirements" means that the calibration data of the candidate memory macrocell must be completely consistent with the theoretical data of the target memory; for example, for a specific process node or operating voltage, if the target memory requires the parameter to be A, then the parameter of the candidate cell must be exactly A, otherwise the underlying physical rules will not be compatible, causing the chip to be unable to be fabricated or operate normally. The threshold range determination refers to the fact that for parameters with performance tolerance or only requiring a certain minimum standard, such as clock frequency, read / write latency, or power consumption, "meeting the requirements" means that the calibration specifications of the candidate memory macrocell are within an effective range that can meet the theoretical specifications. For example, if the target memory requires a certain performance parameter to be greater than or equal to A, as long as the calibration parameter of the candidate cell is within the range greater than or equal to A, or if its calibration parameter does not exceed the limit when it is required to be less than or equal to a certain upper limit indicator, it can be determined that it meets the prerequisite for normal operation.

[0038] For example, suppose the requirements table specifies a 7nm process node and 0.8V operating voltage from a certain wafer foundry. The theoretical specifications require an overall architecture clock frequency of at least 1GHz and a read / write latency of no more than 2 nanoseconds. Here, the process node and operating voltage are parameters whose values ​​must be exactly the same, while the clock frequency and read / write latency must fall within corresponding threshold ranges. Therefore, when the system searches the process library files, for parameters like the process node and voltage that must be strictly matched, only if the process node of the storage macrocell is 7nm (the same as the target memory's 7nm process node) or the calibration voltage is 0.8V (the same as the target memory's operating voltage of 0.8V) can the system determine that the calibration process parameters of the storage macrocell meet the theoretical process parameters required by the target memory. For parameters such as clock frequency and read / write latency, if the clock frequency of the storage macrocell is 1.2 GHz (greater than or equal to the clock frequency of the target memory of 1 GHz), or the read / write latency of the storage macrocell is 1.2 nanoseconds (less than or equal to the read / write latency of the target memory of 2 nanoseconds), then the calibration specifications of the storage macrocell can be considered to meet the theoretical specifications of the target memory.

[0039] In step S3, based on preset generation rules, at least one target memory architecture scheme composed of one or more of the candidate memory macrocells is determined; wherein, the generation rules include: performing performance parameter back calculation on the architecture as a whole to obtain the corresponding actual process parameters and actual specifications, wherein the actual process parameters and actual specifications should meet the requirements of the theoretical process parameters and theoretical specifications; wherein the theoretical specifications, calibration specifications, and actual specifications do not include bit width and depth.

[0040] It should be understood that determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells means that the determined target memory architecture (scheme) is one or more, and each target memory architecture is composed of one or more candidate memory macrocells.

[0041] The generation rules refer to the underlying constraints that the system must follow when constructing the target memory architecture. The purpose of back-calculating the performance parameters of the architecture as a whole to verify that its actual process parameters and specifications meet the requirements of the theoretical process parameters and specifications is to address the inevitable changes in physical characteristics brought about by multi-cell splicing. Specifically, when multiple candidate memory macrocells are used to construct the target memory, additional address decoding logic circuits, multiplexer data paths, and long interconnect traces are inevitably introduced between the multiple macrocells. These added peripheral circuits and wiring loads generate non-negligible parasitic capacitances and logic cascading delays. Therefore, some of the actual process parameters and specifications exhibited by the spliced ​​architecture as a whole will degrade or surge due to these superimposed physical losses, thus significantly differing from the calibration parameters and specifications of a single memory macrocell in an ideal isolated state. Therefore, it is necessary to mathematically quantify and include these physical losses generated by splicing in the overall account through performance parameter back-calculation to confirm whether the overall actual performance of the generated architecture, after deducting losses, still meets the theoretical process parameters and specifications set by the chip designer in the requirements information table.

[0042] It should be noted that the actual process parameters and specifications obtained through parameter back-calculation mentioned in this disclosure do not refer to the measurement data obtained by physical instruments after the chip is fabricated into a silicon wafer, nor to the final results obtained through extremely time-consuming dynamic timing simulation after the back-end physical layout and routing are completed. Essentially, these actual process parameters and specifications refer to the physical characteristic estimations performed by the system during the architecture generation stage, based on the analytical model of the underlying circuitry and static timing analysis theory. The system rapidly derives the overall predicted parameters at a purely mathematical level based on the calibration data of each individual macrocell and the theoretical delay and power consumption model corresponding to the structure formed by the assembled memory macrocells. The core purpose of this theoretical-level pre-calculation mechanism is to significantly shorten the scheme evaluation cycle, enabling the system to quickly and accurately eliminate invalid (candidate memory macrocell) combinations that are destined to fail to converge in physical performance from a massive number of splicing combinations with extremely low computing power costs.

[0043] In some embodiments of this disclosure, the theoretical specifications, calibration specifications, and actual specifications include at least one of the following: clock frequency, read / write latency, dynamic power consumption, static power consumption, physical area, operating voltage, and operating temperature.

[0044] It should be understood that when the theoretical specifications of the target memory include at least one of clock frequency, read / write latency, dynamic power consumption, static power consumption, physical area, operating voltage, and operating temperature, the calibration specifications of the individual candidate macrocells selected during matching should also include all the parameters included in the theoretical specifications. Similarly, the actual specifications of the target memory architecture composed of several individual candidate macrocells will also include all the parameters included in the calibration specifications, that is, all the parameters included in the theoretical specifications.

[0045] In some embodiments of this disclosure, when multiple candidate memory macrocells are spliced ​​together to form a target memory architecture, the generation rules further include at least one of the following constraints: splicing follows the principle of prioritizing splicing of similar types; splicing follows the principle of prioritizing splicing of width; the signal fan-out corresponding to the total bit width of the target memory architecture does not exceed a preset maximum fan-out threshold; the number of logic levels corresponding to the total depth of the target memory architecture does not exceed a preset maximum logic level threshold; and the physical aspect ratio of the target memory architecture does not exceed a preset ratio range.

[0046] In some embodiments of this disclosure, the principle of prioritizing similar cells during splicing means that when splicing multiple candidate memory macrocells to form a target capacity (target bit width and target depth), candidate memory macrocells with completely identical specifications (bit width and depth) should be prioritized for combination. This simplifies the complexity of the underlying physical wiring to the greatest extent and ensures timing consistency.

[0047] For example, when constructing a target memory with a specific total capacity, it is preferable to use two candidate memory macrocells of identical specifications in a symmetrical array arrangement, rather than using a large-capacity candidate memory macrocell and multiple small-capacity candidate memory macrocells in a heterogeneous combination. This is because if the latter is used, the edges of its physical layout are often uneven, which will not only generate some unusable silicon area during back-end placement and routing, but also cause the access speed of the entire spliced ​​architecture to deviate in different address ranges due to the inherent differences in read and write latency between candidate memory macrocells of different specifications. This will cause timing misalignment at the system level, resulting in timing problems. Solving this problem requires setting additional timing compensation logic, which is relatively more complex and will lead to waste of area and power consumption.

[0048] In some embodiments of this disclosure, the principle of prioritizing width (i.e., bit width) during splicing means that when splicing multiple candidate memory macrocells to form a target capacity (i.e., target bit width and target depth), if the target memory has expansion requirements in both the bit width and depth directions (both requiring splicing), then horizontal splicing in the bit width direction is prioritized, followed by vertical splicing in the depth direction. This significantly simplifies the routing complexity of the peripheral multiplexer array architecture and address decoding logic, thereby optimizing the overall chip area and timing alignment capabilities.

[0049] For example, when using a width-first concatenation principle, multiple horizontal candidate macrocells within the same logic word block can completely share the same set of low-order address lines and chip select enable signals. These multiple candidate macrocells synchronously read data and directly form a complete wide word bus at the output. In the subsequent vertical depth concatenation, only a single layer of multiplexers needs to be set at the end of the overall data bus to perform word-block level selection using high-order address bits. Conversely, if a depth-first concatenation principle is adopted, the candidate macrocells are first concatenated vertically into several independent deep columns that meet the target depth through a multiplexer tree, and then these deep columns are arranged horizontally to reach the total bit width. This approach requires each parallel deep column to have its own independent parallel multiplexer tree and corresponding control logic. This not only increases the number of physical calls to the multiplexers and the area occupied, but also results in extremely complex control signal wiring between the horizontally parallel data bits. This parallel redundant control structure is very likely to cause uncontrollable timing offsets between different bits of the same data bus, making it difficult for the back-end timing convergence.

[0050] In some embodiments of this disclosure, the signal fan-out corresponding to the total bit width of the target memory architecture not exceeding a preset maximum fan-out threshold means that when multiple candidate memory macrocells are horizontally spliced ​​together to meet the total bit width (i.e. target bit width) requirement of the target memory, the total number of memory macrocell input pins that a single global signal (such as a clock signal, address bus, or read / write enable control signal) inside the chip needs to drive simultaneously in parallel must be strictly controlled within a preset upper limit of the underlying physical driving capability.

[0051] In some embodiments of this disclosure, the number of logic levels corresponding to the total depth of the target memory architecture not exceeding a preset maximum logic level threshold means that when multiple candidate memory macrocells are horizontally spliced ​​together to meet the total depth (i.e., target depth) requirement of the target memory, the number of series layers of address decoding logic and combinational logic gates generated by the multiplexer array inevitably introduced by vertical stacking must be strictly limited to the maximum propagation delay range that can be tolerated in this clock cycle of the critical path.

[0052] It should be understood that when performing large-scale expansion in the depth direction (i.e., splicing multiple candidate memory macrocells), signals need to pass through multiple layers of cascaded combinational logic gates between the source and destination registers. As the required depth capacity increases, the number of logic levels in the data path also accumulates. Since each logic gate generates inherent gate-level intrinsic delay and line load delay, if the number of logic levels is too large, these accumulated cascaded delays will exhaust the available timing margin within this clock cycle. Once the accumulated cascaded delay exceeds the physical limit of the clock cycle, the chip will be unable to operate normally at the preset target clock frequency. Therefore, setting a maximum logic level threshold can, to some extent, eliminate invalid architecture schemes that are destined to fail to achieve timing convergence due to excessive vertical splicing.

[0053] In some embodiments of this disclosure, the physical aspect ratio of the target memory architecture not exceeding a preset range means that the aspect ratio of the overall layout formed by the multiple candidate memory macrocells after splicing does not exceed a preset range. This effectively reduces wiring congestion, makes the target memory module easier to match and nest with other modules, and improves the utilization rate of silicon wafer area.

[0054] For example, when assembling sixteen candidate memory macrocells, without setting aspect ratio constraints, the system might generate a 1x16 linear structure. While this extreme aspect ratio scheme is logically valid, it is extremely difficult to arrange physically, and due to the large horizontal span, the skewness of the internal clock tree and power supply voltage drop become difficult to control. By presetting the aspect ratio range, the sixteen macrocells are forced to be arranged into a 4x4 or 2x8 array.

[0055] It should be understood that setting the physical aspect ratio restricts the appearance structure formed by the multiple candidate memory macrocells after splicing, rather than restricting the splicing rules. The aforementioned vertical and horizontal splicing are merely figurative references to the splicing rules. In the actual layout of each candidate memory macrocell, regardless of whether it is logically vertical or horizontal splicing, it can be arranged in various geometric forms such as horizontal, vertical, or matrix in physical space according to actual needs. That is, horizontal or vertical splicing refers to the connection method between each candidate memory macrocell, while how to physically arrange each candidate memory macrocell on the circuit board or chip layout is unrelated to the splicing rules. The two are decoupled at the physical implementation level.

[0056] like Figure 2 As shown, in some embodiments of this disclosure, the generation rule further includes several preference conditions, and the method for determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells includes: step S31: generating several initial target memory architecture schemes under the premise of satisfying the theoretical process parameters and theoretical specifications; step S32: mapping each preference condition to a corresponding fitness function; step S33: iteratively evolving each initial architecture scheme based on a non-dominated sorting genetic algorithm and scoring it according to the fitness function during the evolution process to select a set of candidate architectures on the Pareto optimal boundary; and step S34: selecting at least one initial architecture scheme from the set of candidate architectures as the target memory architecture scheme.

[0057] In step S32, each of the preference conditions is mapped to a corresponding fitness function.

[0058] The preferred conditions refer to the further optimization directions proposed by chip designers for the target memory architecture, provided that basic hard constraints (theoretical process parameters, theoretical specifications, other relevant constraints, etc.) are met. It should be understood that in complex chip designs, power consumption, performance, and area are often difficult to achieve simultaneously; therefore, designers need to set priorities based on specific application scenarios. For example, in high-performance computing chips, the preferred condition might be to maximize clock frequency; while in wearable device chips, the preferred condition tends to minimize static power consumption or minimize physical area.

[0059] In some embodiments of this disclosure, the preference conditions include at least one of: dynamic power consumption for read / write, static leakage power consumption, critical path latency, physical aspect ratio, and cabling congestion.

[0060] It should be understood that dynamic power consumption during read / write operations refers to the energy loss caused by signal switching and capacitor charging / discharging during data access operations. For energy-sensitive applications such as smartphones and wearable devices, this metric is crucial for evaluating architectural competitiveness. Static leakage power consumption characterizes the leakage current power consumption of memory in its standby state when powered on but not performing any operations, due to the physical characteristics of transistors. At advanced process nodes, static leakage often accounts for a significant proportion of total power consumption and is a core consideration for achieving long battery life designs. Critical path latency refers to the longest logical path within the architecture from the signal input to the data output. Routing congestion assesses the density of interconnect wires between memory macrocells. Lower routing congestion ensures that metal layer resources are not exhausted in subsequent back-end physical design stages, thus avoiding design rework due to incomplete routing.

[0061] In practical applications, chip designers can weight or combine these conditions according to specific application scenarios. For example, for high-performance server chips, the system can prioritize critical path latency and wiring congestion as the main evolutionary guidelines; while for low-power IoT devices, static leakage power and area utilization can be used as the core scoring criteria. This preference-based mapping mechanism ensures that the Pareto optimal solution selected by the genetic algorithm can accurately meet the customized design needs of different market segments.

[0062] The fitness function refers to a set of structured evaluation formulas used in non-dominated sorting genetic algorithms. It takes the physical attributes (i.e., the physical attributes corresponding to the preference conditions) of each generated memory architecture scheme as input variables, and through a specific mathematical mapping, outputs a fitness score that characterizes the scheme's superiority or inferiority under a specific preference dimension. When there are one or more preference conditions, the fitness function can also be one or more, and each fitness function uniquely corresponds to a preference condition.

[0063] In step S33, based on the non-dominated sorting genetic algorithm, each initial architecture scheme is iteratively evolved and scored according to the fitness function during the evolution process to select a set of candidate architectures that are on the Pareto optimal boundary.

[0064] It should be understood that the non-dominated sorting genetic algorithm refers to a heuristic multi-objective optimization algorithm based on the principles of biological evolution. Its core logic lies in seeking the optimal balance among multiple conflicting optimization objectives through iterative evolution. Specifically, the algorithm first calculates the fitness function (one or more) for each of the current architecture schemes to obtain the fitness function results of each architecture scheme under the preference conditions of area, power consumption, and delay. The algorithm evaluates the dominance relationship of each architecture scheme based on the fitness function results. That is, if the performance of scheme A is not inferior to scheme B in all preference dimensions, and is superior to scheme B in at least one dimension, then scheme A is determined to dominate scheme B. By comparing each pair, the architecture schemes are divided into different levels. One or more architecture schemes in the first level, that is, those not dominated by any other scheme, constitute the Pareto optimal boundary. This algorithm can both exclude dominated schemes that perform poorly in the physical attributes corresponding to each preference condition and select architecture schemes that perform better in the physical attributes corresponding to the preset preference conditions from among the architectures that are non-dominated to each other.

[0065] In step S34, at least one initial architecture scheme is selected from the candidate architecture set as the target memory architecture scheme.

[0066] It should be understood that there is usually more than one architecture scheme that meets the Pareto optimal boundary selected by the non-dominated sorting genetic algorithm. Therefore, the system needs to randomly select one architecture scheme as the final architecture scheme, or select one architecture scheme according to preset conditions, or send all architecture schemes that meet the Pareto optimal boundary to the chip designer for them to determine the final architecture scheme.

[0067] In some embodiments of this disclosure, the automatic generation method of memory architecture further includes: step S4: after determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells, generating a corresponding file list according to the target memory architecture scheme, calling a compilation tool to compile and verify the file list, and retaining the architecture scheme that passes the compilation and verification as the final target memory architecture scheme.

[0068] The file list is a key middleware component in integrated circuit back-end design. It compiles the paths to all hardware description language source files, timing model library files, physical library files, and corresponding pin connection definition scripts required to construct the target memory architecture. For example, the file list can be a Filelist file.

[0069] Compiling and verifying the aforementioned file list using compilation tools can filter out invalid architectural schemes that appear optimal at the algorithmic level but cannot be recognized or parsed in actual circuit design software. Through compilation simulation, the usability (or yield rate) of the final target memory architecture scheme in the real chip manufacturing process can be improved.

[0070] like Figure 3 As shown, a second aspect of this disclosure provides an automatic generation method system for memory architecture, comprising: an information acquisition module for acquiring a process library file and a target memory requirement information table; a candidate memory macrocell matching module for retrieving and extracting at least one candidate memory macrocell that meets matching conditions from the process library file based on the theoretical process parameters and theoretical specifications of the target memory in the requirement information table; wherein, the candidate memory macrocell meeting the matching conditions means that the calibration process parameters and calibration specifications of the candidate memory macrocell meet the requirements of the theoretical process parameters and theoretical specifications of the target memory; and an architecture scheme generation module for determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells based on preset generation rules; wherein, the generation rules include: performing performance parameter back-calculation on the architecture as a whole to obtain the corresponding actual process parameters and actual specifications, wherein the actual process parameters and actual specifications should meet the requirements of the theoretical process parameters and theoretical specifications; wherein the theoretical specifications, calibration specifications, and actual specifications do not include bit width and depth.

[0071] It should be understood that the specific process of each module performing the above-mentioned steps has been described in detail in the above method embodiments, and will not be repeated here for the sake of brevity.

[0072] A third aspect of this disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the automatic generation method of the memory architecture described in any of the preceding claims.

[0073] A fourth aspect of this disclosure provides a computer program product including computer program code that, when run on a computer, causes the computer to implement the automatic generation method of the memory architecture described in any of the preceding claims.

[0074] The fifth aspect of this disclosure provides an electronic terminal including a memory, a processor, and a computer program stored on the memory, wherein the processor executes the computer program to implement the automatic generation method of the memory architecture described in any of the preceding claims.

[0075] like Figure 4As shown, the various components in the device are coupled together via a bus system 104. It is understood that the bus system 104 is used to enable communication between these components. In addition to a data bus, the bus system 104 also includes a power bus, a control bus, and a status signal bus.

[0076] The user interface 105 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0077] It is understood that memory 102 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this disclosure are intended to include, but are not limited to, these and any other suitable categories of memory.

[0078] The memory 102 in this embodiment is used to store various types of data to support the operation of the device 100. Examples of this data include any executable program for operation on the device 100, such as the operating system 1021 and application programs 1022; the operating system 1021 contains various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 1022 may contain various applications, such as a media player, a browser, etc., for implementing various application services. The methods provided in this embodiment may be included in the application program 1022.

[0079] The methods disclosed in the above embodiments of this disclosure can be applied to processor 101, or implemented by processor 101. Processor 101 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 101 or by instructions in the form of software. The processor 101 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 101 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. General-purpose processor 101 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of this disclosure can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0080] In an exemplary embodiment, the apparatus 100 may be used by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs) to perform the aforementioned method.

[0081] This concludes the detailed description of an automatic generation method, system, medium, program, and electronic terminal for a memory architecture according to this disclosure. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions of this disclosure based on the above description.

Claims

1. A method for automatically generating a memory architecture, characterized in that, include: Obtain the process library files and the target memory requirements table; Based on the theoretical process parameters and theoretical specifications of the target memory in the demand information table, at least one candidate memory macrocell that meets the matching conditions is retrieved and extracted from the process library file; wherein, the candidate memory macrocell meets the matching conditions means that the calibration process parameters and calibration specifications of the candidate memory macrocell meet the requirements of the theoretical process parameters and theoretical specifications of the target memory. Based on preset generation rules, at least one target memory architecture scheme composed of one or more of the candidate memory macrocells is determined; wherein, the generation rules include: performing performance parameter back-calculation on the architecture as a whole to obtain the corresponding actual process parameters and actual specifications, wherein the actual process parameters and actual specifications should meet the requirements of the theoretical process parameters and theoretical specifications; wherein the theoretical specifications, calibration specifications, and actual specifications do not include bit width and depth.

2. The method for automatically generating a memory architecture according to claim 1, characterized in that, When concatenating multiple candidate memory macrocells into a target memory architecture, the generation rules also include at least one of the following constraints: concatenation of similar types is prioritized; concatenation of width is prioritized; and the signal fan-out corresponding to the total bit width of the target memory architecture does not exceed a preset maximum fan-out threshold. The total depth of the target memory architecture corresponds to no more than the preset maximum logic level threshold; The physical aspect ratio of the target memory architecture does not exceed a preset range.

3. The method for automatically generating a memory architecture according to claim 1, characterized in that, The generation rules also include several preference conditions, and the method for determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells includes: Under the premise of meeting the theoretical process parameters and theoretical specifications, several initial architecture schemes for target memory are generated; Each of the aforementioned preference conditions is mapped to a corresponding fitness function; Based on the non-dominated sorting genetic algorithm, each initial architecture scheme is iteratively evolved and scored according to the fitness function during the evolution process to select a set of candidate architectures that are on the Pareto optimal boundary. At least one initial architecture scheme is selected from the candidate architecture set as the target memory architecture scheme.

4. The method for automatically generating a memory architecture according to claim 3, characterized in that, The preference conditions include at least one of the following: dynamic power consumption for reading and writing, static leakage power consumption, critical path latency, physical aspect ratio, and cabling congestion.

5. The method for automatically generating a memory architecture according to claim 1, characterized in that, After determining at least one target memory architecture scheme composed of one or more of the candidate memory macrocells, a corresponding file list is generated according to the target memory architecture scheme, and the file list is compiled and verified by a compilation tool. The architecture scheme that passes the compilation verification is retained as the final target memory architecture scheme.

6. The method for automatically generating a memory architecture according to claim 1, characterized in that, The theoretical specifications, calibration specifications, and actual specifications include at least one of the following: clock frequency, read / write latency, dynamic power consumption, static power consumption, physical area, operating voltage, and operating temperature.

7. A method system for automatically generating memory architecture, characterized in that, include: The information acquisition module is used to acquire process library files and target memory requirement information tables; The candidate storage macrocell matching module is used to retrieve and extract at least one candidate storage macrocell that meets the matching conditions from the process library file based on the theoretical process parameters and theoretical specifications of the target memory in the demand information table; wherein, the candidate storage macrocell meets the matching conditions means that the calibration process parameters and calibration specifications of the candidate storage macrocell meet the requirements of the theoretical process parameters and theoretical specifications of the target memory. An architecture scheme generation module is used to determine at least one target memory architecture scheme composed of one or more of the candidate memory macrocells based on preset generation rules; wherein, the generation rules include: performing performance parameter back calculation on the architecture as a whole to obtain the corresponding actual process parameters and actual specifications, wherein the actual process parameters and actual specifications should meet the requirements of the theoretical process parameters and theoretical specifications; wherein the theoretical specifications, calibration specifications, and actual specifications do not include bit width and depth.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1-6.

9. A computer program product, characterized in that, The computer program product includes computer program code that, when run on a computer, causes the computer to implement the method as described in any one of claims 1-6.

10. An electronic terminal, comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method according to any one of claims 1-6.

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