Coordination control method, system and device for multi-machine parallel SVG, and storage medium

Abstract

The invention discloses a coordination control method, system and device for a multi-machine parallel SVG and a storage medium, and relates to the technical field of dynamic reactive compensation of a power system, and the method comprises the steps: employing a chain SVG circuit topological graph, constructing a direct-hanging SVG simulation model, and carrying out the simulation analysis to make a control strategy; a control strategy real-time verification platform is constructed to verify the control strategy, a communication conversion protocol of the SVG control system is converted into a real-time simulation communication adaptation protocol supported by the simulation system, and early-stage principle verification is completed; a rotating coordinate system PI double-closed-loop grid-connected control strategy is adopted, reactive current loop setting is generated, a coordination control strategy is executed in a multi-machine parallel connection scene, reactive hedging is restrained, and dynamic response is unified. According to the method, reactive current loop setting is generated by adopting a rotating coordinate system PI double-closed-loop grid-connected control strategy, and unified setting and consistent response with current inner loop rapid tracking and outer layer reactive target mapping as the core are achieved.

Description

Technical Field

[0001] This invention relates to the field of dynamic reactive power compensation technology for power systems, specifically to a coordinated control method, system, device, and storage medium for multi-machine parallel SVG. Background Technology

[0002] With the continuous increase in the installed capacity and grid-connected voltage levels of new energy sources such as offshore wind power and centralized photovoltaic power, the demand for dynamic reactive power support and power quality regulation in power systems has significantly increased. Static Var Generators (SVG), due to their rapid and continuous reactive power regulation capabilities, are gradually becoming core voltage support equipment in wind farms, photovoltaic power plants, and weak grid scenarios. To adapt to engineering applications with higher voltage levels and larger capacities, chain-cascaded direct-connected SVGs achieve direct output from the high-voltage side through series connection of power units. Combined with current closed-loop control and pulse width modulation strategies based on a rotating coordinate system, voltage stability and dynamic reactive power compensation can be achieved over a wide range of operating conditions. Meanwhile, facing complex scenarios such as grid-connected disturbances and high / low voltage ride-throughs, simulation modeling and real-time semi-physical verification are gradually becoming important means for control strategy development and engineering acceptance.

[0003] In existing multi-machine parallel SVG engineering applications, significant shortcomings remain in control strategies and verification links: First, multi-machine parallel systems often employ independent closed-loop or low-bandwidth coordination methods for each machine, lacking system constraints on the consistency of reactive power command allocation and response under parallel conditions. This easily leads to reactive power offsetting under constant voltage or voltage control modes, resulting in the cancellation of the equivalent reactive power output of the parallel system. This makes it difficult to achieve a stable and predictable voltage support effect, and dynamic differences between devices can trigger shocks or even oscillations. Second, for high-voltage cascaded topologies such as chain-connected SVG, control strategies typically rely on offline simulation or single-machine testing and verification. It is difficult to replicate real-world network disturbances and parallel coupling effects under real controller closed-loop, real communication links, and strict real-time constraints. This results in a lack of repeatable verification basis for strategy parameter tuning, leading to uncertainty in engineering implementation. Third, interface barriers often exist between semi-physical verification systems and control system communication protocols. Inconsistent support for specific high-speed communication protocols / data channels by simulation platforms makes it difficult for controllers to seamlessly integrate into real-time simulation environments such as RT-LAB. Summary of the Invention

[0004] In view of the above-mentioned problems, the present invention is proposed.

[0005] Therefore, the technical problem solved by this invention is that existing methods for coordinated control of multi-parallel static var generators (SVG) suffer from insufficient reactive power offsetting, inconsistency in reactive power command allocation and response, lack of a reproducible simulation-strategy-real-time closed-loop verification link for chain-connected SVGs, insufficient reliability of parameter tuning, and mismatch between the communication protocol of the hardware-in-the-loop simulation platform and the control system, making it difficult for the controller to access the real-time verification environment. The invention also addresses how to achieve coordinated reactive power control in multi-parallel scenarios and ensure dynamic consistency response and engineering feasibility through real-time hardware-in-the-loop verification.

[0006] To address the aforementioned technical problems, this invention provides the following technical solution: a coordinated control method for multi-machine parallel SVG, comprising: constructing a direct-connected SVG simulation model using a chain-type SVG circuit topology; performing simulation analysis to formulate a control strategy; constructing a real-time verification platform for the control strategy to verify the control strategy; converting the communication conversion protocol of the SVG control system into a real-time simulation communication adaptation protocol supported by the simulation system to complete the preliminary principle verification; employing a rotating coordinate system PI dual-closed-loop grid-connected control strategy to generate a reactive current loop setpoint; executing the coordinated control strategy in a multi-machine parallel scenario to suppress reactive power offset and unify dynamic response.

[0007] As a preferred embodiment of the coordinated control method of multi-machine parallel SVG described in this invention, the chain-type SVG circuit topology includes high-voltage output through series connection of power units within each phase and three-phase star connection, wherein the power units adopt a general H-bridge topology.

[0008] As a preferred embodiment of the coordinated control method for multi-machine parallel SVG described in this invention, the step of constructing a direct-connected SVG simulation model and performing simulation analysis to formulate a control strategy includes constructing a direct-connected SVG simulation model, performing simulation analysis on voltage stability, voltage fluctuation, three-phase voltage imbalance, and harmonics before and after connection, and formulating a control strategy.

[0009] As a preferred embodiment of the coordinated control method for multi-machine parallel SVG described in this invention, the construction of a real-time verification platform for the control strategy includes: using a combination of theoretical analysis and computer simulation for parameter design and controller implementation; and verifying the functionality and adaptability of the control strategy based on the real-time verification platform.

[0010] As a preferred embodiment of the coordinated control method for multi-machine parallel SVG described in this invention, the real-time verification platform for the control strategy includes an experiment management subsystem, a real-time simulation subsystem, a signal interface subsystem, and a test controller.

[0011] As a preferred embodiment of the coordinated control method for multi-machine parallel SVG described in this invention, the verification control strategy includes a dual-closed-loop design scheme based on a proportional-integral controller in a rotating coordinate system: using a current loop as the inner loop; using a voltage loop to regulate the DC voltage of the power unit, with the voltage loop as the outer loop and its output serving as the active current loop reference; using a regulator as the outer loop and its output serving as the reactive current loop reference; and a control strategy output mechanism for generating reactive current references for each SVG under grid-connected control.

[0012] As a preferred embodiment of the coordinated control method for multi-machine parallel SVG described in this invention, the coordinated control strategy implemented in the multi-machine parallel scenario includes the following: For scenarios where reactive power compensation in wind power / photovoltaic power plants requires the parallel operation of two or more SVGs, reactive power offsetting will occur if a parallel control strategy is not added. A master-slave parallel strategy and a centralized coordination system using an SVG integrated controller with high-speed fiber optic interconnection are adopted for coordinated control. The master-slave parallel strategy includes a parallel fiber optic communication rate of 2.5G, supporting dynamic switching between master and slave machines to prevent system-wide shutdown due to the failure of any single machine. The coordination logic is reflected in the fact that the master-slave relationship ensures consistency of the parallel operation state and continuity of control execution in the generated reactive current loop. The centralized coordination system using an SVG integrated controller with high-speed fiber optic interconnection includes the use of a single SVG integrated controller, with high-speed fiber optic connections between SVGs. Each parallel SVG uploads its own CT and PT signals and operating status. The integrated controller configures and issues reactive current commands based on the operating status of each device, the amount of reactive power, and the system voltage and current signals.

[0013] Another objective of this invention is to provide a coordinated control system for multi-machine parallel SVG, which solves the problems of current multi-machine parallel static var generator (SVG) coordinated control methods in multi-machine parallel scenarios by executing a coordinated control strategy, including achieving reactive power coordinated control in multi-machine parallel scenarios and ensuring dynamic consistency response and engineering feasibility through real-time semi-physical verification.

[0014] As a preferred embodiment of the coordinated control system for multi-parallel SVG described in this invention, the system includes: a parallel architecture selection module, a centralized allocation module, and a fast and consistent execution module. The parallel architecture selection module determines the control organization method—either master-slave parallel operation or centralized coordination by an integrated controller—based on the number of parallel SVGs in a scenario with multiple SVGs connected in parallel, and establishes a high-speed fiber optic communication foundation. The centralized allocation module collects the CT / PT and operating status information uploaded by each SVG, and the integrated controller performs unified calculations of the reactive power regulation target, forming and issuing reactive current commands to each SVG, thus implementing the parallel coordination target at the current closed-loop execution entry point of each SVG. The fast and consistent execution module relies on high-speed communication to achieve information exchange and response consistency, completes current loop calculation and PWM modulation in grid-connected control, and, when needed, the integrated controller centrally performs voltage loop judgment calculations to meet constant voltage step response requirements, while ensuring continuous parallel operation through an online bypass mechanism.

[0015] Another object of the present invention is to provide a coordinated control device for a multi-machine parallel SVG, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program as a step to implement a coordinated control method for a multi-machine parallel SVG.

[0016] Another object of the present invention is to provide a coordinated control storage medium for a multi-machine parallel SVG, wherein a computer program is stored thereon, and when the computer program is executed by a processor, the steps of a coordinated control method for a multi-machine parallel SVG are implemented.

[0017] The beneficial effects of this invention are as follows: The coordinated control method for multi-machine parallel SVG provided by this invention constructs a direct-connect SVG simulation model using a chain-type SVG circuit topology diagram, and performs simulation analysis on key indicators of voltage stability, reactive power response, and power quality before and after connection to the system. This achieves a calculable characterization of equivalent electrical parameters and control action paths under cascaded topology, enabling the identification of potential coupling sensitivity points and extreme operating conditions in the parallel system during the early stages of strategy development. This achieves the beneficial effects of constraining the control strategy boundary with simulation evidence, reducing on-site trial and error costs, and improving the predictability of the solution. A real-time control strategy verification platform is constructed to perform real-time closed-loop verification of the control strategy. The SVG control system communication conversion protocol is adapted to a real-time simulation communication adaptation protocol supported by the simulation system. Combined with self-developed conversion hardware / protocol, principle verification is completed. This is used to test the stability, latency sensitivity, and portability of the strategy under strict real-time and interface constraints, thereby achieving the beneficial effects of transforming offline simulation conclusions into reproducible experimental conclusions, improving the credibility of engineering implementation, and enhancing the verifiability of acceptance. By adopting a rotating coordinate system PI dual closed-loop grid-connected control strategy to generate reactive current loop input and executing a coordinated control strategy in multi-machine parallel scenarios, a unified input and consistent response with the core of rapid tracking of the inner current loop and mapping of the outer reactive target is achieved. This is used to suppress reactive current offsetting in constant voltage / voltage regulation mode and reduce the impact and oscillation risks caused by dynamic differences between machines, thereby achieving the beneficial effects of improving the equivalent reactive power support capability, dynamic response consistency and voltage support stability of the parallel system. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a chain SVG circuit topology diagram for a coordinated control method of multi-machine parallel SVG provided in Embodiment 1 of the present invention.

[0020] Figure 2 This is a schematic diagram of a real-time verification platform for a coordinated control method of a multi-machine parallel SVG provided in Embodiment 1 of the present invention.

[0021] Figure 3 This invention provides a three-layer balanced control strategy for the system, sub-items, and units under grid-connected conditions for a coordinated control method of a multi-machine parallel SVG provided in Embodiment 1 of the present invention.

[0022] Figure 4This is a schematic diagram of the control strategy under grid-connected conditions for a coordinated control method of a multi-machine parallel SVG provided in Embodiment 1 of the present invention.

[0023] Figure 5 This is a diagram of a parallel system of four or more SVGs, which is a method for coordinated control of multiple parallel SVGs provided in Embodiment 1 of the present invention. Detailed Implementation

[0024] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0025] Example 1, referring to Figures 1-5 As an embodiment of the present invention, a coordinated control method for multi-machine parallel SVG is provided, comprising: S1: Using a chain-type SVG circuit topology, construct a direct-connected SVG simulation model, conduct simulation analysis, and formulate control strategies.

[0026] Furthermore, the high-power water-cooled high-voltage static var generator adopts a chain-type SVG circuit topology, whose main circuit topology is consistent with that of the traditional air-cooled SVG, such as... Figure 1 As shown, the chain-type SVG circuit topology includes: a series link of power units within a phase 101, a power unit module 102, a DC support section of the power unit 103, a three-phase phase branch 104, a star connection point / neutral point connection structure 105, and a three-phase output terminal 106.

[0027] The chain-type high-voltage static var generator (SVG) achieves high-voltage output through series connection of power units within each phase and a three-phase star connection. The power units adopt a common H-bridge topology, which is technically mature and reliable, and can greatly improve the reliability, flexibility and maintainability of the high-voltage static var generator equipment.

[0028] It should be noted that a direct-connected SVG simulation model was established to simulate and analyze various power quality indicators such as voltage stability, voltage fluctuation, three-phase voltage imbalance, and harmonics before and after the direct-connected SVG was connected to the system. Various control strategies for the direct-connected SVG were formulated based on the actual situation. The parameters of the SVG device and the implementation of the controller were designed by combining theoretical analysis and computer simulation calculation. The function and adaptability of the strategy were verified based on the real-time verification platform 200.

[0029] S2: Construct a real-time verification platform for control strategies to verify control strategies. Convert the communication conversion protocol of the SVG control system into a real-time simulation communication adaptation protocol supported by the simulation system to complete the preliminary principle verification.

[0030] Furthermore, the real-time verification platform 200 for the basic control strategy consists of four parts: the test management subsystem 201, the real-time simulation subsystem 202, the signal interface subsystem 203, and the test controller 204. Its system configuration is as follows: Figure 2 As shown.

[0031] It should be noted that, regarding the selection of control strategy, this invention adopts the most widely used proportional-integral controller dual-closed-loop design scheme based on a rotating coordinate system, including a three-level equalization control strategy 301 for the system, sub-items, and inter-units, and a current loop calculation and PWM modulation strategy 305 under grid-connected conditions. The main advantages are simple structure and excellent performance. The three-level equalization control strategy for the system, sub-items, and inter-units is particularly noteworthy.

[0032] The current loop, acting as the inner loop 302, determines the system's ability to achieve stable operation and rapid response. The DC voltage of the power unit is regulated via a voltage loop, which acts as the outer loop 303, and its output serves as the active current loop reference 304. Regulators for reactive power, power factor, etc., act as the outer loop 306, and their output serves as the reactive current loop reference 307. The control strategy under grid-connected conditions is as follows: Figure 3 and Figure 4 As shown.

[0033] It should also be noted that, Figure 3 and Figure 4 The three-layer equalization control strategy shown is manifested at the PWM output as follows: the system layer first forms a three-phase reference PWM quantity ( Figure 3 and Figure 4 The reference values, labeled gPWM.UrA, gPWM.UrB, and gPWM.UrC, are used to express the three-phase output requirements under grid-connected control objectives. Based on this, the sub-unit layer further introduces DC-side error equalization correction values ​​for each power unit of phases A, B, and C. Figure 3 and Figure 4 The units are labeled Udc_AErr_PWM[i], Udc_BErr_PWM[i], and Udc_CErr_PWM[i], where [i] represents the unit index), and are superimposed onto the corresponding phase reference PWM value through an adder node, ultimately forming the PWM drive output for each phase and each unit. Figure 3 and Figure 4(These are labeled PWM→VAs[i], PWM→VBs[i], and PWM→VCs[i]). The core meaning of this structure is: the system layer is responsible for the unified benchmark of the grid connection target, the sub-unit layer is responsible for the unit-by-unit injection of DC side equalization correction, and finally the grid connection control and unit equalization are compatiblely implemented at the PWM output end.

[0034] System layer correspondence: ; Wherein, PWM stands for Pulse Width Modulation, used to represent the modulation signal ultimately output to the power unit switching device drive side; VAs[i] represents the A-phase... The PWM output port name and output quantity name corresponding to each power unit; VAs[i]; where VA represents the output quantity corresponding to phase A; s indicates that the output quantity belongs to the PWM modulation output side; [i] indicates the first PWM output quantity in the same phase. The series power unit (or the first) (The modulation output channel); gPWM. UrA is the A-phase component in the three-phase reference PWM quantity of the system layer; where gPWM represents the variable structure prefix of the PWM reference; UrA represents the reference quantity name of phase A; Udc_AErr_PWM[i] represents the A-phase... The DC-side error equalization correction amount of the unit; Udc is the DC-side voltage, indicating that this amount comes from error information related to the DC-side voltage; A indicates that the error correction amount corresponds to phase A; Err represents the error; PWM indicates that the error amount participates in the output superposition in the form of PWM correction injection.

[0035] Sub-unit layer correspondence: ; Where VBs[i] represents the first phase of B. The PWM output port name and output quantity name corresponding to each power unit; where VB represents phase B, s is the naming suffix in the figure; gPWM.UrB represents the system layer phase B reference PWM quantity, which corresponds to gPWM.UrA, only the phase is changed from A to B; Udc_BErr_PWM[i] represents the PWM quantity of phase B. The error equalization correction amount on the DC side of the unit has the same meaning as Udc_AErr_PWM[i], except that the phase is changed from A to B.

[0036] The final output corresponds to: ; Where VCs[i] represents the first phase of phase C. Each power unit corresponds to a PWM output port name and output quantity name; where VC represents phase C, and s is... Figure 3The naming suffix is ​​gPWM. UrC indicates the system-level C-phase reference PWM quantity; Udc_CErr_PWM[i] indicates the C-phase i-th... Unit DC-side error equalization correction amount.

[0037] In the schematic diagram of current loop calculation and PWM modulation strategy under grid-connected conditions, the controller first completes the current loop calculation (including positive and negative sequence branches) to obtain the voltage modulation related components, and then sends them to the modulation link; there is a normalization coefficient in the modulation link. This is used to scale the voltage-related quantities entering the modulation calculation, thereby increasing the subsequent modulation depth. The calculations have a consistent dimensional scale basis; subsequently, an explicit amplitude calculation formula is obtained. and use The threshold condition-driven modulation mode selection flag SVG_PWM_MODE switches between two modulation modes: SVPWM (SVG_PWM_MODE=1) and SPWM (SVG_PWM_MODE=0). Finally, the system layer three-phase reference PWM quantity gPWM. UrA / B / C is output (and the unit equalization correction quantity is superimposed in the three-layer equalization structure described in the previous section before the output of each unit PWM).

[0038] The normalized coefficient X is expressed as ; Where X represents the normalization coefficient, which is used to normalize certain voltage / modulation-related quantities entering the modulation calculation link according to the DC side average voltage and the number of units in series. Uys represents the system-related voltage quantity marked as is, located in the numerator position; it participates in the calculation of X as the reference quantity for normalization. This represents the number of power units connected in series, located in the denominator and parallel to the power unit. Multiplication indicates the number of power units connected in series in each phase of a cascaded SVG; The DC-side average voltage is the average value of the DC-side voltage over a certain range, used to reflect the overall level of the DC-side voltage.

[0039] The modulation depth / amplitude index M is expressed as: ; Where M represents the modulation depth / amplitude index, used to quantify the vector amplitude entering the modulation module and as the core quantity for modulation mode switching judgment; Umd_P represents the name of a component that appears and participates in the amplitude calculation of M; where Um represents the voltage / modulation amount related to modulation; d represents the d-axis component; _P indicates that the component belongs to the positive sequence channel / positive sequence related component; Umq_P represents the name of another component that appears as is and participates in the amplitude calculation of M; where q represents the q-axis component.

[0040] The modulation mode switching conditions are indicated by two key threshold labels near the modulation mode selection logic: the upper label. The bottom side is marked with SVG_PWM_MODE=1 && M<0.93, and SVPWM (SVG_PWM_MODE=1) and SPWM (SVG_PWM_MODE=0) are marked in the module. This is represented as: ; Where M represents the modulation depth / amplitude index.

[0041] ; Wherein, SVG_PWM_MODE represents the modulation mode selection flag, used to indicate the current modulation mode category; SVPWM represents the name of the space vector pulse width modulation mode; SPWM represents the name of the sinusoidal pulse width modulation mode; SVG_PWM_MODE=1 means that the mode flag is 1 when SVPWM is selected; SVG_PWM_MODE=0 means that the mode flag is 0 when SPWM is selected; 0 is the value of the mode flag.

[0042] The above descriptions of thresholds and mode indicators are in Figure 3 and Figure 4 The side description box already explains the engineering intent: to balance modulation margin / impact under specific operating conditions with harmonic levels under normal operating conditions by switching modulation modes. The instruction manual can directly state the selection of SVPWM or SPWM based on M and the threshold; no additional criteria are needed.

[0043] In summary, the grid-connected current loop calculation and PWM modulation strategy can be expressed using normalized coefficients as follows: ; The modulation calculation scale is standardized, and this is achieved through: ; The modulation depth index M is obtained, and then combined with the threshold condition. &\& SVG_PWM_MODE=1 The value of SVG_PWM_MODE is driven, thus switching between SVPWM (SVG_PWM_MODE=1) and SPWM (SVG_PWM_MODE=0), ultimately forming the system-level three-phase reference PWM quantities gPWM.URA, gPWM.URB, and gPWM.URC. The three-level equalization control strategy, based on these system-level reference quantities, superimposes the DC-side equalization error correction quantities Udc_AErr_PWM[i], Udc_BErr_PWM[i], and Udc_CErr_PWM[i] of each phase and unit through an adder node, and outputs them to the PWM drive ports PWM→VAs[i] and PWM of each phase and unit. Their equivalent formulas are as follows: ; This achieves a unified output at the system level for grid-connected control objectives and a unified landing at the PWM output terminal for the unit-level injection correction of DC-side equalization in the chain-cascaded structure, satisfying the requirements of grid connection control objectives. Figure 3 and Figure 4 The system illustrates the collaborative relationship between two types of functions—system-sub-item-unit three-layer equalization control and grid-connected current loop calculation + PWM modulation strategy—within the same control link.

[0044] S3: Adopts a rotating coordinate system PI dual closed-loop grid-connected control strategy to generate reactive current loop input, and executes a coordinated control strategy in multi-machine parallel scenarios to suppress reactive power offset and unify dynamic response.

[0045] Furthermore, for large-scale wind or solar power plants requiring reactive power compensation involving two or more SVG units operating in parallel, without a parallel control strategy, reactive power offsetting can occur, especially in constant voltage operation mode. After this offsetting, the entire system's reactive power becomes zero, rendering it ineffective for compensation. Simultaneously, the varying response speeds of multiple devices can also impact the system, potentially causing system oscillations in severe cases. To address the SVG parallel operation issue, two technical solutions are available, as follows: Option 1: For systems with four or fewer units operating in parallel, a master-slave parallel strategy is adopted. The parallel fiber optic communication rate is 2.5G, supporting dynamic master-slave switching, ensuring that the entire system will not shut down due to the failure of any one unit.

[0046] Option 2: A parallel system with four or more units, using one SVG integrated controller 401, with high-speed fiber optic connections 402 between SVGs, achieving a communication rate of 2.5 Gbit / s. The system structure is as follows. Figure 5 .

[0047] It should be noted that the characteristics of this control strategy scheme are as follows: A. All parallel-connected SVGs upload their own CT and PT signals, as well as their current operating status.

[0048] B. The SVG integrated controller configures and issues reactive current commands based on the current operating status of each device, the amount of reactive power, and the system voltage and current signals.

[0049] C. High-speed fiber optic communication of 2.5Gbit / s is adopted, which can transmit information between all parallel devices within 20us, achieving a fast response effect, and ultimately achieving the same response speed of the parallel system as that of a single device.

[0050] D. This control strategy is particularly effective in voltage response. Due to the use of high-speed communication, the voltage loop judgment and calculation are completed by the SVG integrated controller, and the entire parallel system fully meets the requirement of a constant voltage step response speed of 30ms.

[0051] Example 2, one embodiment of the present invention, provides a coordinated control system for a multi-machine parallel SVG, including a parallel architecture selection module, a centralized allocation module, and a fast and consistent execution module.

[0052] The parallel architecture selection module is used to determine the control organization mode of master-slave parallel operation or centralized coordination by the integrated controller based on the number of parallel SVGs in the scenario of multiple SVGs connected in parallel, and to build a high-speed fiber optic communication foundation. The fixed centralized allocation module is used to collect the CT / PT and operating status information uploaded by each SVG, and the integrated controller performs unified calculation of reactive power regulation target, forms and sends reactive current command to each SVG, and implements the parallel coordination target to the current closed loop execution entry of each SVG. The fast and consistent execution module is used to realize information exchange and response consistency by relying on high-speed communication, completes current loop calculation and PWM modulation in grid-connected control, and performs voltage loop judgment calculation by the integrated controller when needed to meet the constant voltage step response requirements, while ensuring continuous operation of parallel operation through online bypass mechanism.

[0053] This embodiment also provides a computer device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the coordinated control method for multi-machine parallel SVG proposed in the above embodiment.

[0054] This embodiment also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the coordinated control method for multi-machine parallel SVG as proposed in the above embodiments.

[0055] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0056] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-including system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0057] More specific examples of computer-readable media (a non-exhaustive list) include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0058] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0059] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A coordinated control method for multi-machine parallel SVG, characterized in that, include: A direct-connected SVG simulation model was constructed using a chain-type SVG circuit topology (100), and simulation analysis was conducted to formulate a control strategy. Construct a real-time verification platform for control strategies (200) to verify control strategies, convert the communication conversion protocol of the SVG control system into a real-time simulation communication adaptation protocol supported by the simulation system, and complete the preliminary principle verification; A rotating coordinate system PI dual-closed-loop grid-connected control strategy is adopted to generate a reactive current loop command. In multi-machine parallel scenarios, a coordinated control strategy is executed to suppress reactive current offset and unify dynamic response.

2. The coordinated control method for multi-machine parallel SVG as described in claim 1, characterized in that: The chain-type SVG circuit topology (100) includes, High voltage output is achieved through series connection of power units within each phase and three-phase star connection, with the power units adopting a general H-bridge topology.

3. The coordinated control method for multi-machine parallel SVG as described in claim 2, characterized in that: The process of constructing a direct-attached SVG simulation model, conducting simulation analysis, and formulating control strategies includes... A simulation model of direct-connected SVG is constructed to simulate and analyze voltage stability, voltage fluctuation, three-phase voltage imbalance, and harmonics before and after connection, and control strategies are formulated.

4. The coordinated control method for multi-machine parallel SVG as described in claim 1 or 2, characterized in that: The construction of a real-time verification platform (200) for control strategies includes verifying control strategies, including: The parameter design and controller implementation are carried out by combining theoretical analysis and computer simulation. The control strategy real-time verification platform (200) verifies the function and adaptability of the control strategy.

5. The coordinated control method for multi-machine parallel SVG as described in claim 4, characterized in that: The real-time verification platform (200) for the control strategy includes a test management subsystem (201), a real-time simulation subsystem (202), a signal interface subsystem (203), and a test controller (204).

6. The coordinated control method for multi-machine parallel SVG as described in any one of claims 1, 2, 3 or 5, characterized in that: The verification control strategy includes, Dual-loop design scheme of proportional-integral controller based on rotating coordinate system: The current loop is used as the inner loop (302); The DC voltage of the power unit is regulated by a voltage loop, which serves as the outer loop (303) and the output serves as the active current loop reference (304). The regulator is used as the outer loop (306), and the output is used as the reactive current loop reference (307). The control strategy outputs the reactive current given generation mechanism for each SVG under grid-connected control.

7. The coordinated control method for multi-machine parallel SVG as described in claim 1, characterized in that: The execution of the coordination control strategy in a multi-machine parallel scenario includes, For scenarios where reactive power compensation in wind / photovoltaic power plants requires the parallel operation of two or more SVG units, reactive power offsetting will occur if a parallel control strategy is not added. Therefore, a master-slave parallel operation strategy and a centralized coordination control system using an SVG integrated controller and high-speed fiber optic interconnection are adopted for coordinated control. The master-slave parallel operation strategy includes a parallel fiber optic communication rate of 2.5G, supports dynamic master-slave switching, and avoids system-wide shutdown due to failure of any one of the machines. The coordination logic is reflected in the fact that the master-slave relationship ensures the consistency of the parallel operation status and the continuity of control execution based on the given reactive current loop. The centralized coordination of the SVG integrated controller with high-speed fiber optic interconnection includes the use of one SVG integrated controller (401), and the SVGs are connected by high-speed fiber optics (402); each parallel SVG uploads its own CT and PT signals and operating status, and the integrated controller configures and issues reactive current command according to the operating status of each device, reactive power magnitude and system voltage and current signals.

8. A coordinated control system for a multi-machine parallel SVG, employing the coordinated control method for a multi-machine parallel SVG as described in any one of claims 1 to 7, characterized in that: This includes a parallel architecture selection module, a centralized allocation module, and a fast and consistent execution module; The parallel architecture selection module is used to determine the control organization mode of master-slave parallel operation or centralized coordination by integrated controller based on the number of parallel SVGs in the scenario of multiple SVGs connected in parallel, so as to build a high-speed optical fiber communication foundation. The fixed-centralized allocation module is used to collect the CT / PT and operating status information uploaded by each SVG. The integrated controller performs unified calculation on the reactive power adjustment target, forms and sends the reactive current command to each SVG, and implements the parallel coordination target to the current closed-loop execution entry of each SVG. The fast and consistent execution module is used to achieve information exchange and response consistency through high-speed communication. It completes current loop calculation and PWM modulation in grid-connected control, and when needed, the integrated controller centrally completes voltage loop judgment calculation to meet the constant voltage step response requirements. At the same time, it ensures continuous operation of parallel units through an online bypass mechanism.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the coordinated control method for the multi-machine parallel SVG as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the coordinated control method for the multi-machine parallel SVG as described in any one of claims 1 to 7.

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