Power consumption adjusting method for generating test excitation by automatic test pattern

Abstract

The invention relates to a power consumption adjusting method for generating test excitation by an automatic test pattern. The method comprises the following steps: providing a test register module; analyzing the distribution condition of clock gating units ICG in the integrated circuit; and dynamically controlling an enabling signal of the ICG through the test register module based on an analysis result of the ICG distribution condition, so as to realize power consumption adjustment of ATPG test excitation generated by an automatic test pattern. By dynamically controlling the enable signal of the clock gating unit, the power consumption adjustment method for ATPG test excitation is realized, and the problems that the yield is reduced due to over-high test power consumption, the traditional threshold adjustment effect is poor and the like are solved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and to a method for adjusting the power consumption of Automatic Test Pattern Generation (ATPG) test stimuli. In particular, it relates to a method for adjusting the power consumption of ATPG test stimuli by dynamically controlling the enable signal of the clock gating unit. This method is simple, efficient, and can be dynamically adapted to the chip circuit structure. Background Technology

[0002] In the production and testing of integrated circuits (ICs), ATPG technology is one of the core means to ensure chip yield. It generates specific test stimulus signals to simulate the working scenario of the chip in order to detect whether the chip has design defects or manufacturing failures.

[0003] However, ATPG test stimuli face a technical challenge in practical applications: excessive power consumption. The signal switching rate of the test stimuli is much higher than that of the chip under normal operating conditions, leading to a sudden increase in local power consumption during testing. This not only easily causes problems such as chip overheating and decreased signal integrity, but also causes the test results of the Automatic Test Equipment (ATE) to exceed the preset specifications, ultimately resulting in a large number of chips that should have passed being wrongly judged as "failed," thus reducing IC yield. To address this issue, existing technologies mainly rely on adjusting the threshold parameter of the ATPG tool to limit the power consumption of the test stimuli. However, this method can only indirectly constrain the power consumption at the level of "test stimulus generation rules," and cannot match the actual circuit structure and power distribution of the chip. Therefore, its effect on improving the actual power consumption during testing is very limited. At the same time, excessive adjustment of the threshold can also lead to a decrease in the coverage of the test stimuli, missing the detection of some faults, which further affects the reliability of the test. Therefore, its impact on actual power consumption is not significant. Summary of the Invention

[0004] This invention provides a power consumption adjustment method for automatically generating test stimuli using test patterns. Specifically, it provides a method for adjusting the power consumption of ATPG test stimuli by dynamically controlling the enable signal of the clock gating unit. This method addresses technical problems such as decreased yield due to excessive test power consumption and poor performance of traditional threshold adjustment methods, while also balancing test coverage with circuit implementation complexity.

[0005] This invention provides a power consumption adjustment method for automatically generating test stimuli from test patterns, comprising the following steps: Provides a test register module; Analyze the distribution of clock gating units (ICGs) in integrated circuits; and Based on the analysis of ICG distribution, the enable signal of ICG is dynamically controlled through the test register module to achieve power consumption adjustment of ATPG test excitation for automatic test pattern generation.

[0006] Furthermore, the test register module is configured to output a preset binary signal to control the enable terminal of the ICG.

[0007] Furthermore, the test register module is simple to configure and easy to reconfigure. A test register module is provided, including: Select a D-type flip-flop with reset function and a D-type flip-flop with set function; and The test register module is automatically generated using a Python script, that is, the hardware description language code (Verilog code) of the test register module is automatically generated. The input parameters of the Python script include D-type flip-flops with reset function, D-type flip-flops with set function, and a parameter configuration list. The parameter configuration list records the name and default value of each register.

[0008] Furthermore, the D-type flip-flop with reset function and the D-type flip-flop with set function are standard units in the component library.

[0009] Further analysis of the distribution of ICG includes: The number of ICGs within the target clock domain and the number of registers fanned out by each ICG are counted from the clock domain dimension to estimate the test power consumption of that region.

[0010] Further analysis of the distribution of ICG includes: The number of ICGs at each design level and the number of registers fanned out by each ICG are statistically analyzed to refine the power consumption distribution.

[0011] Furthermore, based on the analysis results of the ICG distribution, the enable signal of the ICG is dynamically controlled through the test register module, including: When the enable signal of the ICG is dynamically controlled via clock domain control, the following steps are included: The target control signal is output through a test register module; The target control signal is mixed with the original functional signal of the integrated circuit through a logic AND gate to form the final ICG target enable signal; and The target enable signal of the ICG is input to the test enable terminal of the ICG in the target clock domain to achieve power consumption regulation in that area.

[0012] Furthermore, based on the analysis results of the ICG distribution, the enable signal of the ICG is dynamically controlled through the test register module, including: When the enable signal for the dynamic control of the ICG is controlled at the design level, the following steps are included: The target control signal is output through a test register module; Each target control signal is mixed with the original functional signal of the integrated circuit; and Each mixed signal is input to the corresponding ICG test enable terminal within the target design level to achieve power consumption adjustment at that level.

[0013] Furthermore, when the enable signal of the ICG is dynamically controlled using a hybrid clock domain and design-level control method, the following steps are included: Configure at least two test register modules, where the first test register module is responsible for clock domain control, and the second test register module is responsible for design-level control; and The first test register module outputs a clock domain control signal, which is mixed with the original function signal and then input to the ICG test enable terminal of the corresponding clock domain; the second test register module outputs a design-level control signal, which is mixed with the original function signal and then input to the ICG test enable terminal of the corresponding design level, so as to realize joint power consumption adjustment of the clock domain and the design level.

[0014] Furthermore, the preset binary signal is 0 or 1. By adjusting the preset binary signal, the ICG enable state can be dynamically switched, thereby precisely adjusting the power consumption of the ATPG test excitation.

[0015] The present invention has at least the following beneficial effects: 1) The present invention uses a test register module that is simple to configure and easy to reconfigure to dynamically control the activation of the ICG enable signal. It can generate an ATPG test stimulus configuration that is within the technical specifications based on the actual power consumption of the automatic test equipment. The method of the present invention can reduce the impact of the power consumption of the ATPG test stimulus on the test stimulus, thereby improving the IC yield to a certain extent. The hybrid control can improve the IC yield from 97.21% to 99.11%; 2) The present invention realizes the dynamic adjustment of the power consumption of the ATPG test stimulus, avoiding ATE test failure caused by excessive power consumption; 3) The test register module of the present invention is simple to configure and easy to reconfigure, and can adapt to the control requirements of different ICGs. Attached Figure Description

[0016] To further illustrate the above and other advantages and features of the various embodiments of the present invention, a more specific description of the embodiments of the invention will be presented with reference to the accompanying drawings. It is to be understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by identical or similar reference numerals for clarity.

[0017] Figure 1 The circuit code diagram of the test register module in some embodiments of the present invention is shown; Figure 2 This diagram illustrates the contents of the parameter configuration list file in the test register script program in some embodiments of the present invention; Figure 3 A schematic diagram of the control ICG enable signal circuit under clock domain A in some embodiments of the present invention is shown; Figure 4 The following are schematic diagrams of control ICG enable signal circuits under different hierarchical structures in some embodiments of the present invention; Figure 5 The diagram illustrates a circuit diagram of the ICG enable signal designed in some embodiments of the present invention, which optimizes the combination of clock domain and different hierarchical structures. Detailed Implementation

[0018] It should be noted that the components in the accompanying drawings may be shown exaggerated for illustrative purposes and may not be to scale.

[0019] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0020] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0021] It should also be noted that, in the embodiments of the present invention, only a portion of the parts or components may be shown for clarity and simplicity. However, those skilled in the art will understand that, under the teachings of the present invention, the required parts or components can be added as needed for specific scenarios.

[0022] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0023] It should also be noted that in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] It should also be noted that, in the embodiments of the present invention, the term "clock domain A" refers to any circuit region that "shares the same clock," that is, "clock domain A" refers to any clock domain of the target control, including but not limited to the CPU core clock domain, peripheral interface clock domain, DDR controller clock domain, PCIe clock domain, etc., specifically selected according to the power hotspot area in the chip design; the term "design A" or "design A" is just a general name / number for a specific design module, used to refer to "the target design module whose power consumption needs to be controlled," and does not correspond to a fixed function. That is, design A is "an independent circuit module divided by function / structure" in the chip, that is, "design A" or "design A" refers to any design level module of the target control, including but not limited to the CPU subsystem, peripheral subsystem, storage subsystem, interface subsystem, IP core, etc., specifically selected according to the power hotspot module in the chip design.

[0025] Furthermore, the embodiments of the present invention describe the process steps in a specific order. However, this is only for the convenience of distinguishing each step, and is not a limitation on the order of each step. In different embodiments of the present invention, the order of each step can be adjusted according to the process.

[0026] In the following embodiments, IC_1 is a test chip, which is the "ELYNX" chip from EVAS Intelligence.

[0027] The following embodiment provides a power consumption adjustment method for automatically generating test stimuli from test patterns, including the following steps: A test register module is provided, configured to output a preset binary signal, which is either 0 or 1. By adjusting the preset binary signal, the enable state of the ICG can be dynamically switched, controlling the enable terminal of the ICG and thus precisely adjusting the power consumption of the ATPG test stimulus. The test register module is simple to configure and easy to reconfigure. The provided test register module includes: Select D-type flip-flops with reset function (DFFRBXXX) and D-type flip-flops with set function (DFFSBXXX), and implement the shift register function through series flip-flops to output preset 0 / 1 control signals; and The test register module is automatically generated using a Python script, which means that the hardware description language code of the test register module is automatically generated. The input parameters of the Python script include D-type flip-flops with reset function, D-type flip-flops with set function, and a parameter configuration list. The parameter configuration list records the name and default value of each register. The D-type flip-flops with reset function and D-type flip-flops with set function are standard units in the component library. Analysis of ICG distribution includes: The number of ICGs within the target clock domain and the number of registers fanned out by each ICG are counted from the clock domain dimension to estimate the test power consumption of this region. This analysis refines the power consumption distribution by statistically analyzing the number of ICGs at each design level and the number of registers fanned out by each ICG; and... Based on the analysis of ICG distribution, the enable signal of ICG is dynamically controlled by the test register module to achieve automatic test pattern generation and power consumption adjustment of ATPG test excitation.

[0028] Figure 1 The diagram shows the circuit code for the test register module. For circuits like the test register module, custom specs can be generated using the Python programming language. For example, the circuit can contain registers with reset and set functions. When the ICG enable signal requires a 0 / 1 value, the output signals of these registers can be quickly hooked up to the ICG enable signal. We can generate the following test register script (test_register.py) to create these simple and easily reconfigurable test register modules: test_register.py<reset DFF cell type><set DFF cell type><value_setting_list> The program's principle is explained as follows: The parameter `reset DFF cell type` (D-type flip-flop type with reset function) selects the register type with reset function for the standard cell in the component library. The parameter `set DFF cell type` (D-type flip-flop type with set function) selects the register type with reset function in the standard cell of the component library; The contents of the parameter value_setting_list file can be found here. Figure 2 .

[0029] Based on the analysis results of ICG distribution, the enable signal of ICG is dynamically controlled through the test register module, including: Figure 3The diagram illustrates a circuit for controlling the ICG enable signal under clock domain A. The circuit controls the ICG enable signal fanned out by clock domain A. When the dynamic control method for the ICG enable signal is clock domain control, the following steps are included: The target control signal is output through a test register module; The target control signal is mixed with the original functional signal of the integrated circuit through a logic AND gate to form the final ICG target enable signal; and The target enable signal of the ICG is input to the test enable terminal of the ICG in the target clock domain to achieve power consumption regulation in that area.

[0030] Figure 4 The diagram illustrates the circuitry for controlling the ICG enable signal under different hierarchical structures of Design A. It shows how the ICG enable signals at different levels are controlled according to the hierarchical structure of Design A. When the dynamic control of the ICG enable signal is achieved through design-level control, the following steps are included: The target control signal is output through a test register module; Each target control signal is mixed with the original functional signal of the integrated circuit; and Each mixed signal is input to the corresponding ICG test enable terminal within the target design level to achieve power consumption adjustment at that level.

[0031] Figure 5 This diagram illustrates a circuit for controlling the ICG enable signal in Design A using a combination of clock domain and different hierarchical structures. It optimizes the control of the ICG enable signal by combining the advantages of both the clock domain and the hierarchical structure of Design A. Specifically, `test_register_inst1` controls the ICG enable signal in a specific clock domain, and `test_register_inst2` controls the ICG enable signal at a specific level within Design A. When the dynamic control of the ICG enable signal involves a hybrid approach of clock domain and design-level control, the following steps are included: Configure at least two test register modules, where the first test register module is responsible for clock domain control, and the second test register module is responsible for design-level control; and The first test register module outputs a clock domain control signal, which is mixed with the original function signal and then input to the ICG test enable terminal of the corresponding clock domain; the second test register module outputs a design-level control signal, which is mixed with the original function signal and then input to the ICG test enable terminal of the corresponding design level, so as to realize joint power consumption adjustment of the clock domain and the design level.

[0032] By using the three ICG enable control methods described above, we can effectively and dynamically adjust the activation of the ICG enable signal, thereby reducing the impact of ATPG test excitation power consumption on IC yield.

[0033] The optimization results for IC yield were tested using the three methods described above. Table 1 shows the impact of different methods of controlling the ICG enable signal on integrated circuit yield. The comparison reveals that IC yield can be effectively improved. This indicates that dynamically adjusting the activation of the ICG enable signal significantly improves the regulation of ATPG test excitation power consumption. Furthermore, we should also pay attention to rationally analyzing how to better dynamically adjust the activation of the ICG enable signal; excessive control can increase the complexity of the circuit logic.

[0034] Table 1. Impact of different methods of controlling the ICG enable signal on integrated circuit yield. While some embodiments of the present invention have been described in this application, those skilled in the art will understand that these embodiments are merely illustrative. Numerous variations, alternatives, and improvements will arise in those skilled in the art under the teachings of this invention without departing from its scope. The appended claims are intended to define the scope of the invention and thereby cover methods and structures within the scope of the claims themselves and their equivalents.

Claims

1. A method for adjusting the power consumption of an automatic test pattern generation test stimulus, characterized in that, Includes the following steps: Provides a test register module; Analyze the distribution of clock gating units (ICGs) in integrated circuits; as well as Based on the analysis of ICG distribution, the enable signal of ICG is dynamically controlled through the test register module to achieve automatic test pattern generation and power consumption adjustment of ATPG test excitation.

2. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 1, characterized in that, The test register module is configured to output a preset binary signal to control the enable terminal of the ICG.

3. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 1, characterized in that, The test register module is simple to configure and easy to reconfigure. The test register module includes: Select a D-type flip-flop with reset function and a D-type flip-flop with set function; and The test register module is automatically generated by a Python script. The input parameters of the Python script include D-type flip-flops with reset function, D-type flip-flops with set function, and a parameter configuration list. The parameter configuration list records the name and default value of each register.

4. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 3, characterized in that, The D-type flip-flop with reset function and the D-type flip-flop with set function are standard units in the component library.

5. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 1, characterized in that, Analysis of ICG distribution includes: The number of ICGs within the target clock domain and the number of registers fanned out by each ICG are counted from the clock domain dimension to estimate the test power consumption of that region.

6. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 1, characterized in that, Analysis of ICG distribution includes: The number of ICGs at each design level and the number of registers fanned out by each ICG are statistically analyzed to refine the power consumption distribution.

7. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 1, characterized in that, Based on the analysis results of ICG distribution, the enable signal of ICG is dynamically controlled through the test register module, including: When the enable signal of the ICG is dynamically controlled via clock domain control, the following steps are included: The target control signal is output through a test register module; The target control signal is mixed with the original functional signal of the integrated circuit through a logic AND gate to form the final ICG target enable signal; and The target enable signal of the ICG is input to the test enable terminal of the ICG in the target clock domain to achieve power consumption regulation in that area.

8. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 1, characterized in that, Based on the analysis results of ICG distribution, the enable signal of ICG is dynamically controlled through the test register module, including: When the enable signal for the dynamic control of the ICG is controlled at the design level, the following steps are included: The target control signal is output through a test register module; Each target control signal is mixed with the original functional signal of the integrated circuit; and Each mixed signal is input to the corresponding ICG test enable terminal within the target design level to achieve power consumption adjustment at that level.

9. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 1, characterized in that, When the enable signal of the ICG is dynamically controlled using a hybrid clock domain and design-level control method, the following steps are included: Configure at least two test register modules, where the first test register module is responsible for clock domain control, and the second test register module is responsible for design-level control; and The first test register module outputs a clock domain control signal, which is mixed with the original function signal and then input to the ICG test enable terminal of the corresponding clock domain; the second test register module outputs a design-level control signal, which is mixed with the original function signal and then input to the ICG test enable terminal of the corresponding design level, so as to realize joint power consumption adjustment of the clock domain and the design level.

10. The power consumption adjustment method for automatically generating test stimuli using test patterns according to claim 1, characterized in that, The preset binary signal is 0 or 1. By adjusting the preset binary signal, the ICG enable state can be dynamically switched.

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