A line coding method and device based on scrambling and dynamic programming

Abstract

The application provides a line coding and decoding method and device based on scrambling and dynamic programming, and relates to the technical field of line coding. The method comprises the following steps: obtaining an original data packet, setting the order of a binary scrambling polynomial according to the length of the original data packet, constructing the binary scrambling polynomial, and generating a scrambling table matrix; performing first-stage scrambling on the original data packet according to the scrambling table matrix, a maximum processing round parameter and a bit detection threshold, generating a temporary data payload and a first-stage scrambling round count variable; performing second-stage scrambling on the temporary data payload, generating a data payload and a second-stage scrambling round count variable, and then generating a coded data packet; performing bit-by-bit analysis on the coded data packet to obtain a to-be-decoded data payload, a first-stage scrambling and a second-stage scrambling round count variable; and performing a decoding operation on the to-be-decoded data payload to output a decoded data packet. The application is used for efficiently suppressing the occurrence probability of a long continuous same-value bit sequence, so as to improve the reliability of signal transmission.

Description

Technical Field

[0001] This invention relates to the field of line coding technology in the field of data coding and transmission technology, and in particular to a line coding and decoding method and apparatus based on scrambling and dynamic programming, which is suitable for high-reliability and high-efficiency data processing scenarios such as digital communication. Background Technology

[0002] As display technology rapidly advances towards higher resolutions and higher refresh rates, the high-speed serial interface transmission rate between the TCON (Timing Controller), the core transmission channel, and the source driver is constantly increasing. Against this backdrop, issues related to signal integrity, clock synchronization, and bit error rate control are becoming increasingly prominent. In particular, long consecutive bit sequences in the data stream can easily cause the clock data recovery circuit at the receiving end to lose lock, leading to communication interruptions or increased bit error rates.

[0003] To address these issues, existing technologies typically employ scrambling or line coding schemes. While traditional scrambling techniques (Linear Feedback Shift Register) do not incur additional bandwidth overhead, they cannot deterministically eliminate long sequences in worst-case data modes, making it difficult to fully guarantee communication reliability. Line coding techniques (such as 8b / 10b coding), although ensuring transition density, introduce up to 20% bandwidth overhead, limiting effective transmission throughput.

[0004] Therefore, there is an urgent need for a new binary data encoding and decoding method that can effectively suppress the occurrence of long consecutive bit sequences and maintain high encoding efficiency while ensuring clock synchronization and data reliability, so as to meet the performance requirements in data communication scenarios. Summary of the Invention

[0005] To address the low efficiency of traditional line coding in existing technologies, this invention provides a line coding and decoding method and apparatus based on scrambling and dynamic programming. The technical solution is as follows: On the one hand, a circuit encoding and decoding method based on scrambling and dynamic programming is provided. This method is implemented by a circuit encoding and decoding device based on scrambling and dynamic programming, and includes: S1. Obtain multiple raw data packets to be encoded, and set the order of the binary scrambling polynomial according to the length of the raw data packets; set the bit detection threshold and maximum processing round parameters for the first-level scrambling code and the second-level scrambling code; initialize the round count variables for the first-level scrambling code and the second-level scrambling code.

[0006] S2. Construct a binary scrambling polynomial based on the selected multi-order binary primitive polynomial and the set order of the binary scrambling polynomial, and generate a scrambling table matrix based on the binary scrambling polynomial.

[0007] S3. Obtain any original data packet to be encoded. Perform first-level scrambling on the obtained original data packet according to the scrambling table matrix, the maximum processing round parameter of the first-level scrambling code, and the bit detection threshold. Generate a temporary data payload and an updated first-level scrambling code round count variable. The length of the temporary data payload is the length of the original data packet.

[0008] S4. Determine whether to perform second-level scrambling based on the maximum processing round parameter of the second-level scrambling code. If second-level scrambling is to be performed, then perform second-level scrambling on the temporary data payload according to the scrambling code table matrix, the maximum processing round parameter of the second-level scrambling code, and the bit detection threshold, and generate the data payload and the updated second-level scrambling round count variable; wherein, the length of the data payload is the length of the original data packet.

[0009] S5. Combining the preset transition edge flag bits, generate an encoded data packet based on the data payload, the updated first-level scrambling code, and the round count variables of the second-level scrambling code; wherein, the length of the encoded data packet is the sum of the length of the original data packet, the maximum processing round parameter of the first-level scrambling code, the maximum processing round parameter of the second-level scrambling code, and the number of transition edge flag bits.

[0010] S6. Parse the encoded data packet bit by bit to obtain the data payload to be decoded, the first-level scrambling code, and the round count variables of the second-level scrambling code.

[0011] S7. Decode the payload of the data to be decoded according to the scrambling table matrix, the first-level scrambling code, and the round count variables of the second-level scrambling code, and output the decoded data packet.

[0012] Optionally, S2 includes: S21. Construct a binary scrambling polynomial based on the selected multi-order binary primitive polynomial and the set order of the binary scrambling polynomial; initialize the state vector of the multi-bit shift register to a sequence of all 1s; initialize the scrambling table matrix to a matrix of all zeros; let... .

[0013] S22. Sequentially save the values ​​in the state vector of the multi-bit shift register into the scrambling table matrix. OK.

[0014] S23, Order ,judge Is it true? If true, proceed to step S24; if false, proceed to step S25; where, Let be the order of the binary scrambling polynomial.

[0015] S24. Update the multi-bit shift register state vector based on the shift register, and proceed to step S22.

[0016] S25. Output scrambling code table matrix; wherein, the scrambling code table matrix includes Lines, each line Bit.

[0017] Optionally, S3 includes: S31. Obtain any original data packet to be encoded, and initialize a temporary data payload based on the obtained original data packet; wherein the length of the temporary data payload is the length of the original data packet.

[0018] S32. Calculate the maximum number of processing rounds of the first-level scrambling code based on the maximum number of processing rounds parameter of the first-level scrambling code, and set the round count variable of the first-level scrambling code to 0.

[0019] S33. Detect whether there is a long consecutive value sequence in the temporary data payload whose length reaches or exceeds the bit detection threshold of the first level scrambling code; if it exists, proceed to step S34; if it does not exist, proceed to step S37.

[0020] S34. Based on the scrambling code table matrix, the sequence number of the obtained original data packet, and the current first-level scrambling code round count variable, generate the first-level scrambling code sequence.

[0021] S35. XOR the temporary data payload with the first-level scrambling sequence bitwise to generate the updated temporary data payload.

[0022] S36. Update the first-level scrambling code round count variable; determine whether the updated first-level scrambling code round count variable is less than the maximum number of processing rounds for the first-level scrambling code; if it is less, proceed to step S33; if it is not less, proceed to step S37.

[0023] S37. Output the temporary data payload and the updated first-level scrambling code round count variable.

[0024] Optionally, S4 includes: S41. Determine whether the maximum processing round parameter of the second-level scrambling code is 0; if yes, set the second-level scrambling code round count variable to 0 and execute step S48; if no, execute step S42.

[0025] S42. Initialize the data payload according to the temporary data payload; wherein, the length of the data payload is the length of the original data packet.

[0026] S43. Calculate the maximum number of processing rounds for the second-level scrambling code based on the maximum number of processing rounds parameter for the second-level scrambling code, and set the round count variable for the second-level scrambling code to 0.

[0027] S44. Detect whether there is a long consecutive value sequence in the data payload whose length reaches or exceeds the bit detection threshold of the second-level scrambling code; if it exists, proceed to step S45; if it does not exist, proceed to step S48.

[0028] S45. Based on the scrambling code table matrix, the sequence number of the obtained original data packet, the updated first-level scrambling code round count variable, and the current second-level scrambling code round count variable, generate the second-level scrambling code sequence.

[0029] S46. XOR the data payload with the second-level scrambling sequence bitwise to generate the updated data payload.

[0030] S47. Update the second-level scrambling code round count variable; determine whether the updated second-level scrambling code round count variable is less than the maximum number of processing rounds for the second-level scrambling code; if it is less, proceed to step S44; if it is not less, proceed to step S48.

[0031] S48, Output data payload and updated second-level scrambling code round count variable.

[0032] Optionally, S5 includes: S51. Set the packet header according to the binary representation of the updated first-level scrambling round count variable; wherein the length of the packet header is the maximum processing round parameter bits of the first-level scrambling code.

[0033] S52. Determine whether the maximum processing round parameter of the second-level scrambling code is greater than or equal to 1; if so, set the packet tail according to the updated second-level scrambling code round count variable; wherein, the length of the packet tail is the maximum processing round parameter bit of the second-level scrambling code.

[0034] S53. Combining the preset transition edge flag bits, the encoded data packet is obtained according to the data payload, packet header and packet tail; wherein, the length of the encoded data packet is the sum of the original data packet length, the maximum processing round parameter of the first level scrambling code, the maximum processing round parameter of the second level scrambling code and the number of transition edge flag bits.

[0035] Optionally, S6 includes: S61. Extract the number of bits corresponding to the maximum processing round parameter of the first-level scrambling code from the preset position of the encoded data packet, and calculate the updated first-level scrambling code round count variable.

[0036] S62. Determine whether the maximum processing round parameter of the second-level scrambling code is greater than or equal to 1. If yes, extract the number of bits corresponding to the maximum processing round parameter of the second-level scrambling code from the preset position of the encoded data packet and calculate the updated second-level scrambling code round count variable. If no, set the second-level scrambling code round count variable to 0.

[0037] S63. Set the payload of the data to be decoded according to the encoded data packet.

[0038] Optionally, S7 includes: S71. Based on the sum of the updated first-level scrambling code and second-level scrambling code round count variables, calculate the total reverse scrambling code round count variable; determine whether the total reverse scrambling code round count variable is 0; if yes, proceed to step S76; if no, proceed to step S72.

[0039] S72. Set the total reverse scrambling round count variable to 0.

[0040] S73. Based on the scrambling code table matrix, the sequence number of the encoded data packet, and the current total reverse scrambling round count variable, generate a scrambling code sequence.

[0041] S74. XOR the data payload to be decoded with the scrambling sequence bitwise to generate the updated data payload.

[0042] S75. Update the total reverse scrambling round count variable; determine whether the updated total reverse scrambling round count variable is less than the value obtained by subtracting one from the sum of the updated first-level scrambling round count variables and the second-level scrambling round count variables; if yes, proceed to step S73; if no, proceed to step S76.

[0043] S76. Obtain the decoded data packet based on the updated data payload and output it.

[0044] On the other hand, a circuit encoding and decoding apparatus based on scrambling and dynamic programming is provided. This apparatus is applied to a circuit encoding and decoding method based on scrambling and dynamic programming. The apparatus includes: The data acquisition module is used to acquire multiple raw data packets to be encoded, set the order of the binary scrambling polynomial according to the length of the raw data packets, set the bit detection threshold and maximum processing round parameters for the first-level and second-level scrambling codes, and initialize the round count variables for the first-level and second-level scrambling codes.

[0045] The scrambling table pre-generation module is used to construct a binary scrambling polynomial based on the selected multi-order binary primitive polynomial and the set order of the binary scrambling polynomial, and to generate a scrambling table matrix based on the binary scrambling polynomial.

[0046] The first-level scrambling module is used to acquire any original data packet to be encoded, and to perform first-level scrambling on the acquired original data packet according to the scrambling table matrix, the maximum processing round parameter of the first-level scrambling, and the bit detection threshold, generating a temporary data payload and an updated first-level scrambling round count variable; wherein, the length of the temporary data payload is the length of the original data packet.

[0047] The second-level scrambling module is used to determine whether to perform second-level scrambling based on the maximum processing rounds parameter of the second-level scrambling. If second-level scrambling is to be performed, the temporary data payload is scrambled according to the scrambling table matrix, the maximum processing rounds parameter of the second-level scrambling, and the bit detection threshold, generating the data payload and the updated second-level scrambling round count variable; wherein, the length of the data payload is the length of the original data packet.

[0048] The encoded data packet generation module is used to generate encoded data packets by combining preset transition edge flag bits, data payload, updated first-level scrambling code, and second-level scrambling code round count variables; wherein, the length of the encoded data packet is the sum of the length of the original data packet, the maximum processing round parameter of the first-level scrambling code, the maximum processing round parameter of the second-level scrambling code, and the number of transition edge flag bits.

[0049] The encoded data packet parsing module is used to parse the encoded data packet bit by bit to obtain the data payload to be decoded, the first-level scrambling code, and the round count variables of the second-level scrambling code.

[0050] The decoded data packet output module is used to perform decoding operations on the payload of the data to be decoded based on the scrambling table matrix, the first-level scrambling code, and the round count variables of the second-level scrambling code, and output the decoded data packet.

[0051] On the other hand, a circuit encoding and decoding device based on scrambling and dynamic programming is provided. The circuit encoding and decoding device based on scrambling and dynamic programming includes: a processor; a memory, wherein computer-readable instructions are stored in the memory, and when the computer-readable instructions are executed by the processor, any one of the circuit encoding and decoding methods based on scrambling and dynamic programming described above is implemented.

[0052] On the other hand, a computer-readable storage medium is provided, wherein at least one instruction is stored in the storage medium, the at least one instruction being loaded and executed by a processor to implement any of the above-described methods of circuit encoding and decoding based on scrambling and dynamic programming.

[0053] The beneficial effects of the technical solutions provided in the embodiments of the present invention include at least the following: The proposed technical solution in this invention can effectively control the frequency of occurrence of long consecutive bit sequences exceeding a threshold, and can effectively identify and destroy long consecutive bit sequences in data packets. Specifically, when At that time, the technical solution can ensure that the data stream exceeds the set threshold with an extremely low probability. A long sequence of consecutive values; for parameter settings The technical solution ensures that the data stream exceeds the set threshold with an extremely low probability. Based on long consecutive value sequences, further suppress sequences with lengths between to The occurrence of long consecutive bit sequences between values ​​is addressed through this dynamic programming strategy. By controlling the probability of long consecutive bit sequences with a specific threshold to a theoretically extremely low level, a balance between coding efficiency and transmission reliability is achieved. This significantly reduces bit errors, lockouts, and synchronization errors at the transmitting and receiving ends caused by such sequences, thereby improving the reliability and security of data during communication.

[0054] The proposed encoding scheme boasts high encoding efficiency, flexible and scalable structure, and supports adjustments to parameters such as data packet length, detection threshold, and scrambling rounds based on actual application requirements, achieving a balance between processing overhead and signal quality. For example, when the data packet length is... Bit, , , With the right bit parameters, the encoding efficiency can reach up to 98.62%, and for purely random input sequences, the encoded data shows... The probability of a long consecutive bit sequence is extremely low (theoretically, it appears in a data packet). The probability of a sequence of bits with the same value as the company commander is lower than ).

[0055] The decoding process is simple and efficient. By utilizing the reflexivity of the XOR operation, the receiving end can quickly restore the original data without complex synchronous searches, thus improving the overall operating efficiency of the system. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a flowchart of a line encoding and decoding method based on scrambling and dynamic programming provided by an embodiment of the present invention; Figure 2 This is a schematic diagram of the compilation and decoding process provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the encoding process in Embodiment 1 provided by the present invention; Figure 4 These are schematic diagrams of the decoding process in Embodiments 1 and 2 provided by the present invention; Figure 5 These are schematic diagrams of the scrambling polynomials in Embodiments 1 and 2 provided in this invention. Figure 6 This is a schematic diagram of the encoding process in Embodiment 2 provided by the present invention; Figure 7This is a block diagram of a circuit encoding and decoding device based on scrambling and dynamic programming provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a circuit encoding and decoding device based on scrambling and dynamic programming provided in an embodiment of the present invention. Detailed Implementation

[0058] The technical solution of the present invention will now be described with reference to the accompanying drawings.

[0059] In embodiments of the present invention, words such as "exemplarily," "for example," etc., are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" in the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present the concept in a concrete manner. Furthermore, in embodiments of the present invention, the meaning expressed by "and / or" can be both, or either one.

[0060] In the embodiments of this invention, the terms "image" and "picture" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning. Similarly, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, without emphasizing the distinction between them, they convey the same meaning.

[0061] In this embodiment of the invention, sometimes a subscript such as W1 may be written in a non-subscript form such as W1. When the difference is not emphasized, the meaning they express is the same.

[0062] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0063] This invention provides a circuit encoding and decoding method based on scrambling and dynamic programming. This method can be implemented by a circuit encoding and decoding device based on scrambling and dynamic programming, which can be a terminal or a server. Figure 1 The flowchart shown is for a circuit encoding and decoding method based on scrambling and dynamic programming. The processing flow of this method may include the following steps: S1. Obtain multiple raw data packets to be encoded, and set the order of the binary scrambling polynomial according to the length of the raw data packets; set the bit detection threshold and maximum processing round parameters for the first-level scrambling code and the second-level scrambling code; initialize the round count variables for the first-level scrambling code and the second-level scrambling code.

[0064] In one feasible implementation, let the original data packet length be... Bit, the order of the binary scrambling polynomial is ,and Divisible , Set the bit detection threshold for the first-level scrambling code. Bit detection threshold of the second-level scrambling code ( or ), and the maximum number of processing rounds corresponding to the two levels. ( )and (( ),like ,but Initialize the scrambling round count variable for the currently processed data packet. .

[0065] S2. Construct a binary scrambling polynomial based on the selected multi-order binary primitive polynomial and the set order of the binary scrambling polynomial, and generate a scrambling table matrix based on the binary scrambling polynomial.

[0066] In one feasible implementation, based on a given Pre-generated scrambling table of binary scrambling polynomial It contains Lines, each line Bits. Specifically, this may include the following steps S21-S25: S21. Select one Bivariate primitive polynomials of order two as scrambling polynomials ,in ,for , .initialization Bit shift register state vector It is a sequence of all 1s, that is, for , Initialize the scrambling table matrix. for It is an all-zero matrix. (By...) Begin iteratively executing steps S22-S25.

[0067] S22, will The median values ​​are saved sequentially to the scrambling code table. Okay, that is .

[0068] S23, Update ,like If so, proceed to step S24; otherwise, proceed to step S25.

[0069] S24, Generation based on shift register update Bit shift register state vector That is, let bits be ,renew ,in Indicates two Bitwise XOR between bit vectors This represents the multiplication of two bits, i.e. , Return to step S22.

[0070] S25, Output generated Scrambling table matrix .

[0071] S3. Obtain any original data packet to be encoded. Perform first-level scrambling on the obtained original data packet according to the scrambling table matrix, the maximum processing round parameter of the first-level scrambling code, and the bit detection threshold. Generate a temporary data payload and an updated first-level scrambling code round count variable. The length of the temporary data payload is the length of the original data packet.

[0072] In one feasible implementation, the first to be encoded is obtained. indivual Bit raw data packet The original data packets are subjected to first-level scrambling (detection and processing). (bit length along with value sequence), generate Bit Temporary Data Payload With scrambling round count variable Specifically, it may include the following steps S31-S37: S31, Order Bit temporary data payload Initialize to raw data packets ,Right now .

[0073] S32, Based on the first-level maximum processing round parameter Calculate the maximum number of processing rounds Let the scrambling round count variable... Starting from 0, iteratively execute steps S33-S36.

[0074] S33, Detect the current Bit Temporary Data Payload Does it exist in Bit length along with value sequence: If detected, continue to steps S34-S36; otherwise, proceed to step S37.

[0075] S34, Based on scrambling table matrix Data packet sequence number and count variables ,generate Bit scrambling sequence Among them, for , equal The Middle OK Bit scrambling sequence.

[0076] S35, will and XOR the bits to generate the updated temporary data payload. ,Right now .

[0077] S36. Update the counter variable ,like If not, return to step S33; otherwise, proceed to step S37.

[0078] S37, Generation Bit Temporary Data Payload With scrambling round count variable .

[0079] S4. Determine whether to perform second-level scrambling based on the maximum processing round parameter of the second-level scrambling code. If second-level scrambling is to be performed, then perform second-level scrambling on the temporary data payload according to the scrambling code table matrix, the maximum processing round parameter of the second-level scrambling code, and the bit detection threshold, and generate the data payload and the updated second-level scrambling round count variable; wherein, the length of the data payload is the length of the original data packet.

[0080] In one feasible implementation, based on Bit Temporary Data Payload Perform a second level of scrambling (detection and processing). (bit length along with value sequence), generate Bit data payload With scrambling round count variable Specifically, it may include the following steps S41-S48: S41, if Let it be 0. Proceed directly to step S48; otherwise, proceed to step S42.

[0081] S42, Order Bit data payload Initialize as temporary data payload ,Right now .

[0082] S43, Based on the second-level maximum processing round parameter Calculate the maximum number of processing rounds Let the scrambling round count variable... Starting from 0, iteratively execute steps S44-S47.

[0083] S44, Detect the current status Bit data payload Does it exist in Bit length along with value sequence: If detected, continue with steps S45-S47; otherwise, proceed to step S408.

[0084] S45, Based on scrambling table matrix Data packet sequence number and count variables and ,generate Bit scrambling sequence Among them, for , equal The Middle OK Bit scrambling sequence.

[0085] S46, will and XOR the bits to generate the updated result. Bit data payload ,Right now .

[0086] S47. Update the counter variable ,like If not, return to step S44; otherwise, proceed to step S48.

[0087] S48, Generation Bit data payload With scrambling round count variable .

[0088] S5. Combining the preset transition edge flag bits, generate an encoded data packet based on the data payload, the updated first-level scrambling code, and the round count variables of the second-level scrambling code; wherein, the length of the encoded data packet is the sum of the length of the original data packet, the maximum processing round parameter of the first-level scrambling code, the maximum processing round parameter of the second-level scrambling code, and the number of transition edge flag bits.

[0089] In one feasible implementation, for example, the number of transition edge flag bits is 3, according to Bit data payload With variables , The total length generated is Bit-encoded data packets The coding efficiency is Specifically, it may include the following steps S51-S53: S51, Let Bit header for The binary representation of, i.e. .

[0090] S52, if Then let Bit tail for The binary representation of, i.e. .

[0091] S53, Set , , ,in Represents a pair of bits Logical negation operation.

[0092] Furthermore, set , , The total length generated is Bit-encoded data packets .

[0093] S6. Parse the encoded data packet bit by bit to obtain the data payload to be decoded, the first-level scrambling code, and the round count variables of the second-level scrambling code.

[0094] Step S6: Obtain the code to be decoded Bit-encoded data packets ,right Perform bit-by-bit parsing to obtain the payload of the data to be decoded. and scrambling round count , Specifically, it may include the following steps S61-S63: S61, based on ,for ,set up ,calculate For example, if the maximum number of processing rounds for the first-level scrambling code is 3, then the first 3 bits of the encoded data packet are extracted, and the binary representation of these 3 bits is converted into decimal, which is used as the first-level scrambling code round count variable.

[0095] S62, if For ,set up ,calculate Otherwise, let .

[0096] S63, Set Bit-to-decode data payload equal That is, for , .

[0097] S7. Decode the payload of the data to be decoded according to the scrambling table matrix, the first-level scrambling code, and the round count variables of the second-level scrambling code, and output the decoded data packet.

[0098] Step S7: Based on the scrambling table Counting the number of scrambling rounds , ,right Bit data payload Perform decoding operation and output. Bit data packets Decoding data packets With the original data packet Equal. Specifically, this may include the following steps S71-S76: S71, Based on Count Variables and Calculate the total number of reverse scrambling rounds. .like If the value is 0, proceed directly to step S76; otherwise, proceed to step S72.

[0099] S72, Set the total number of scrambling rounds count variable Starting from 0, iteratively execute steps S73-S75.

[0100] S73, Based on scrambling table matrix Data packet sequence number and count variables ,generate Bit scrambling sequence Among them, for , equal The Middle OK Bit scrambling sequence.

[0101] S74, will and XOR the bits to generate the updated data payload. ,Right now .

[0102] S75, Update the counter variable ,like If not, return to step S73; otherwise, proceed to S76.

[0103] S76, Output Bit-decoded data packets .

[0104] like Figure 2 The encoding / decoding flowchart shown specifically includes: inputting the raw data packet, where the raw data packet is the transmission payload for the high-speed serial link, and its specific content includes, but is not limited to, pixel-level display data (Video Payload) for the internal interface of the display panel (e.g., TCON-SD interface) and idle data in the blanking area; setting parameters; pre-generating the LFSR (Linear Feedback Shift Register) scrambling table; performing multi-level conditional scrambling processing; dynamically encapsulating the encoded data packet; outputting the final encoded data packet; the decoder receiving the encoded data packet; parsing the data packet structure; performing reverse scrambling recovery operation; and outputting the decoded data packet. The advantages of this invention are: by introducing a conditional triggering mechanism, it maintains high encoding efficiency while improving transmission reliability. It can effectively control the frequency of occurrence of long consecutive bit sequences exceeding a threshold, and can effectively identify and destroy long consecutive bit sequences in data packets, thereby significantly reducing bit errors, lockouts, and synchronization errors at the transmitting and receiving ends caused by such sequences, and improving the reliability and security of data during communication. Furthermore, this invention supports flexible parameter configuration, allowing for a trade-off between signal quality and processing complexity based on the actual application scenario.

[0105] Example 1: As Figure 3 , Figure 4 As shown in Table 1, this embodiment provides an efficient data encoding and decoding method based on scrambling and dynamic programming strategies. The present invention includes the following steps: Table 1 is based on polynomials. The generated state table

[0106] Step S1: The input parameters selected in this embodiment are as follows: Bit raw data packet =[11111,11101,11100,11000,01110,01001,11101,11010,11001,10000,10101,00000,00000,00000,00010,00000,00010,00000,00000,00000], a 5th-order bivariate primitive polynomial As a scrambling polynomial, such as Figure 5 As shown, Set the bit detection threshold for the first-level scrambling code. Bit detection threshold for the second-level scrambling code And the maximum number of processing rounds corresponding to the two levels. and Initialize the scrambling round count variable for the currently processed data packet. ; Step S2: Pre-generate a scrambling code table based on the given 5th-order binary scrambling polynomial. It contains 31 rows, each with 5 bits; Step S201: Select a 5th-order bivariate primitive polynomial as the scrambling polynomial. Initialize the register state vector Initialize the scrambling table matrix. It is a 31×5 matrix consisting entirely of zeros. Begin by iteratively executing steps S202-S205; Step S202: ... The median values ​​are saved sequentially to the scrambling code table. Okay, that is ; Step S203: Update ,like If so, proceed to step S204; otherwise, proceed to step S205. Step S204: Generate a 5-bit shift register state vector based on shift register update. That is, let bits be ,renew ,in Indicates two Bitwise XOR between bit vectors This represents the multiplication of two bits, i.e. , Return to step S202; Step S205: Output the generated 31 × 5 scrambling table matrix. ; Step S3: Obtain the first 100-bit raw data packet to be encoded. [11111,11101,11100,11000,01110,01001,11101,11010,11001,10000,10101,00000,00000,00000,00010,00000,00010,00000,00000,00000], perform the first-level scrambling on the original data packet (detect and process the 8-bit long consecutive value sequence) to generate a 100-bit temporary data payload. [00000,00000,00000,10110,01001,11000,00111,10111,01101,11010,10000,10000,01000,00100,00000,00001,10000,01001,10110,01011] and scrambling round count variable ; Step S301: Create a 100-bit temporary data payload Initialize to raw data packets ,Right now [11111,11101,11100,11000,01110,01001,11101,11010,11001,10000,10101,00000,00000,00000,00010,00000,00010,00000,00000,00000]; Step S302: Based on the first-level maximum processing round parameter Calculate the maximum number of processing rounds Let the scrambling round count variable... Starting from 0, iteratively execute steps S303-S306; (1) : Step S303: Detect the current 100-bit temporary data payload. If there is an 8-bit long sequence of linked values, continue executing steps S304-S306; Step S304: Based on the scrambling table matrix Data packet sequence number and count variables Generate a 100-bit scrambling sequence [11111,11101,11100,01110,00111,10001,11010,01101,10100,01010,00101,10000,01000,00100,00010,00001,10010,01001,10110,01011], where for , equal The Middle A 5-bit scrambling sequence; Step S305: ... and XOR the bits to generate the updated temporary data payload. ,Right now [00000,00000,00000,10110,01001,11000,00111,10111 01101 11010 10000 10000,01000,00100,00000,00001,10000,01001,10110,01011]; Step S306: Update the counter variable ,at this time Execute step S307; Step S307: Generate a 100-bit temporary data payload [00000,00000,00000,10110,01001,11000,00111,10111,01101 11010,10000,10000,01000,00100,00000,00001,10000,01001,10110,01011] and scrambling round count variable ; Step S4: Based on 100-bit temporary data payload [00000,00000,00000,10110,01001,11000,00111,10111,01101 11010,10000,10000,01000,00100,00000,00001,10000,01001,10110,01011], perform a second-level scrambling (detect and process the 14-bit long consecutive value sequence) to generate a 100-bit data payload. and scrambling round count variable ; Step S401: Execute step S402; Step S402: Generate a 100-bit data payload Initialize as temporary data payload ,Right now [00000,00000,00000,10110,01001,11000,00111,10111,01101,11010,10000,10000,01000,00100,00000,00001,10000,01001,10110,01011]; Step S403: Based on the second-level maximum processing round parameter Calculate the maximum number of processing rounds Let the scrambling round count variable... Starting from 0, iteratively execute steps S404-S407; : Step S404: Detect the current 100-bit data payload. If a 14-bit long sequence of values ​​exists, continue executing steps S405-S407; Step S405: Based on the scrambling table matrix Data packet sequence number and count variables and Generate a 100-bit scrambling sequence [10111,11001,11110,01111,10101,11000,01100,00110,00011,10011,11011,11111,11101,11100,01110,00111,10001,11010,01101,10100], where for , equal The Middle A 5-bit scrambling sequence; Step S406: ... and Perform a bitwise XOR operation to generate the updated 100-bit data payload. ,Right now [10111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,0111110101,11000,01110, 00110,00001,10011,11011,11111]; Step S407: Update the counter variable ,because Return to step S404; : Step S404: No current 100-bit data payload detected. If there is a 14-bit long sequence of linked values, proceed to step S408; Step S408: Generate a 100-bit temporary data payload = [10111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,01111 10101,11000,01110, 00110,00001,10011,11011,11111]; Step S5: Payload based on 100 bits of data With variables , The total length generated is Bit-encoded data packets [0,1,010111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,01111 10101,11000,01110, 00110,00001,10011,11011,11111,0,100], with a coding efficiency of ; Step S501: Set a 1-bit packet header for The binary representation of, i.e. for The binary representation of; Step S502: Set a 3-bit packet tail for The binary representation of, i.e. ; Step S503: Let ; ; ; Step S504: Let , , The total length generated is Bit-encoded data packets [0,1,010111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,01111,10101,11000,01110,00110,00001,10011,11011,11111,0,100]; Step S6: Obtain the 107-bit encoded data packet to be decoded. [0,1,010111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,01111,10101,11000,01110, 00110,00001,10011,11011,11111,0,100], for Perform bit-by-bit parsing to obtain the payload of the data to be decoded. [10111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,01111,10101,11000,01110,00110,00001,10011,11011,11111] and scrambling round count. , ; Step S601: Based on ,for ,set up ,calculate ; Step S602: If For ,set up ,calculate ; Step S603: Set the payload of 100 bits of data to be decoded. That is, for , ; Step S7: Based on the scrambling table Counting the number of scrambling rounds , For 100-bit data payload The code [10111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,01111,10101,11000,01110, 00110,00001,10011,11011,11111] is decoded to output a 100-bit data packet. [11111,11101,11100,11000,01110,01001,11101,11010,11001,10000,10101,00000,00000,00000,00010,00000,00010,00000,00000,00000], decode data packet With the original data packet equal.

[0107] Step S701: Based on the count variable , Calculate the total number of reverse scrambling rounds. Execute step S702; Step S702: Set the total number of scrambling rounds count variable. Starting from 0, iteratively execute steps S703-S705; (1) : Step S703: Based on the scrambling table matrix Data packet sequence number and count variables Generate a 100-bit scrambling sequence [11111,11101, 11100,01110,00111,10001,11010,01101,10100,01010,00101,10000,01000,00100, 00010,00001,10010,01001,10110,01011], where for , equal The Middle A 5-bit scrambling sequence; Step S704: ... and XOR the bits to generate the updated data payload. ,Right now [01000,00100,00010,10111,11011,10001,10001,11100,11010,00011,01110,11111,11101,11100,01100,00111,10011,11010, 01101,10100]; Step S705: Update the counter variable ,because Return to step S703; (2) : Step S703: Based on the scrambling table matrix Data packet sequence number and count variables Generate a 100-bit scrambling sequence [10111,11001,11110,01111,10101,11000,01100,00110,00011,10011,11011,11111,11101,11100,01110,00111,10001,11010,01101,10100], where for , equal The Middle A 5-bit scrambling sequence; Step S704: ... and XOR the bits to generate the updated data payload. ,Right now [11111,11101,11100,11000,01110,01001,11101,11010,11001,10000,10101,00000,00000,00000,00010,00000,00010,00000,00000,00000]; Step S705: Update the counter variable ,at this time Execute step S706; Step S706: Output a 100-bit data packet [11111,11101,11100,11000,01110,01001,11101,11010,11001,10000,10101,00000,00000,00000,00010,00000,00010,00000,00000,00000].

[0108] Example 2: As Figure 4 , Figure 6 As shown in Table 1, this embodiment provides an efficient data encoding and decoding method based on scrambling and dynamic programming strategies. The present invention includes the following steps: Step S1: In this embodiment, the input parameter selected is the raw data packet. [00001,11111,10000,10000,01100,00011,00010,00001,11011,00110,11000,00101,11110,01011,11101,11101,10010,00000,00000,10101]; Length Bit, 5th order bivariate primitive polynomial As a scrambling polynomial Set the bit detection threshold for the first-level scrambling code. Bit detection threshold for the second-level scrambling code And the maximum number of processing rounds corresponding to the two levels. and Initialize the scrambling round count variable for the currently processed data packet. and data packet sequence number count variable ; Step S2: Pre-generate a scrambling code table based on the given 5th-order binary scrambling polynomial. It contains 31 rows, each with 5 bits; Step S201: Select a 5th-order bivariate primitive polynomial as the scrambling polynomial. Initialize the register state vector Initialize the scrambling table matrix. It is a 31×5 matrix consisting entirely of zeros. Begin by iteratively executing steps S202-S205; Step S202: ... The median values ​​are saved sequentially to the scrambling code table. Okay, that is ; Step S203: Update ,like If so, proceed to step S204; otherwise, proceed to step S205. Step S204: Generate a 5-bit shift register state vector based on shift register update. That is, let bits be ,renew Return to step S202; Step S205: Output the generated 31 × 5 scrambling table matrix. .

[0109] Step S3: Obtain the first 100-bit raw data packet to be encoded. [00001,11111,10000,10000,01100,00011,00010,00001,11011,00110,11000,00101,11110,01011,11101,11101,10010,00000,00000,10101], perform the first-level scrambling on the original data packet (detect and process the 10-bit long consecutive value sequence) to generate a 100-bit temporary data payload. [0100111011100101000111110010101010001010011001111100110010101011100111000111011100011101110001100111101101010] and scrambling round count variable ; Step S301: Create a 100-bit temporary data payload Initialize to raw data packets ,Right now [00001,11111,10000,10000,01100,00011,00010,00001,11011,00110,11000,00101,11110,01011,11101,11101,10010,00000,00000,10101]; Step S302: Based on the first-level maximum processing round parameter Calculate the maximum number of processing rounds Let the scrambling round count variable... Starting from 0, iteratively execute steps S303-S306; : Step S303: Detect the current 100-bit temporary data payload. If a 10-bit long sequence of values ​​exists, continue executing steps S304-S306; Step S304: Based on the scrambling table matrix Data packet sequence number and count variables Generate a 100-bit scrambling sequence [11111,11101,11100,01110,00111,10001,11010,01101,10100,01010,00101,10000,01000,00100,00010,00001,10010,01001,10110,01011], where for , equal The Middle A 5-bit scrambling sequence; Step S305: ... and XOR the bits to generate the updated temporary data payload. ,Right now [11110,00010,01100,11110,01011,10010,11000,01100,01111,01100,11101,10101,10110,01111,11111,11100,00000,01001,10110,11110]; Step S306: Update the counter variable ,at this time Return to step S303; : Step S303: Detect the current 100-bit temporary data payload. If a 10-bit long sequence of values ​​exists, continue executing steps S304-S306; Step S304: Based on the scrambling table matrix Data packet sequence number and count variables Generate a 100-bit scrambling sequence [10111,11001,11110,01111,10101,11000,01100,00110,00011,10011,11011,11111,11101,11100,01110,00111,10001,11010,01101,10100], where for , equal The Middle A 5-bit scrambling sequence; Step S305: ... and XOR the bits to generate the updated temporary data payload. ,Right now [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010]; Step S306: Update the counter variable ,at this time Return to step S303 to continue the detection; : Step S303: No current 100-bit temporary data payload detected. If there is a 10-bit long sequence of linked values, proceed to step S307. Step S307: Generate a 100-bit temporary data payload [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010] and scrambling round count variable ; Step S4: Based on 100-bit temporary data payload [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010], perform a second-level scrambling (detect and process the 0-bit long consecutive value sequence), and generate a 100-bit data payload. [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010] and scrambling round count variable ; Step S401: Let it be 0. Proceed directly to step S408; Step S408: Generate a 100-bit temporary data payload [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010] and scrambling round count variable .

[0110] Step S5: Payload based on 100 bits of data [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010] and variables , Generate an encoded data packet with a total length of 105 bits. [1,01,1,01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010,1], encoding efficiency is ; Step S501: Set a 2-bit packet header for The binary representation of, i.e. ; Step S503: Let ; ; ; Step S504: Let , [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010], generating an encoded data packet with a total length of 105 bits. [1,01,1,01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010,1]; Step S6: Obtain the 105-bit encoded data packet to be decoded. [1,01,1,01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010,1], for Perform bit-by-bit parsing to obtain the payload of the data to be decoded. and scrambling round count , Includes the following steps: Step S601: Based on ,for ,set up ,calculate ; Step S602: ,make ; Step S603: Set the payload of 100 bits of data to be decoded. [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010]; Step S7: Based on the scrambling table Counting the number of scrambling rounds , For 100-bit data payload [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010] is decoded to output a 100-bit data packet. [00001,11111,10000,10000,01100,00011,00010,00001,11011,00110,11000,00101,11110,01011,11101,11101,10010,00000,00000,10101], decode data packet With the original data packet equal.

[0111] Step S701: Based on the count variable and Calculate the total number of reverse scrambling rounds. Execute step S702; Step S702: Set the total number of scrambling rounds count variable. Starting from 0, iteratively execute steps S703-S705; (1)C = 0: Step S703: Based on the scrambling table matrix Data packet sequence number and count variables Generate a 100-bit scrambling sequence [11111,11101,11100,01110,00111,10001,11010,01101,10100,01010,00101,10000,01000,00100,00010,00001,10010,01001,10110,01011], where for , equal The Middle A 5-bit scrambling sequence; Step S704: ... [01001,11011,10010,10001,11110,01010,10100,01010,01100,11111,00110,01010,01011,10011,10001,11011,10001,10011,11011,01010] and [11111,11101,11100,01110,00111,10001,11010,01101,10100,01010,00101,10000,01000,00100,00010,00001,10010,01001,10110,01011] are bitwise XORed to generate the updated data payload. ,Right now [10110,00110,01110,11111,11001,11011,01110,00111,11000,10101,00011,11010,00011,10111,10011,11010,00011,11010 01101,00001]; Step S705: Update the counter variable Return to step S703; (2) : Step S703: Based on the scrambling table matrix Data packet sequence number and count variables Generate a 100-bit scrambling sequence [10111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,01111,10101,11000,01110,00110,00001,10011,11011,11111], where for , equal The Middle A 5-bit scrambling sequence; Step S704: ... [10110,00110,01110,11111,11001,11011,01110,00111,11000,10101,00011,11010,00011,10111,10011,11010,00011,11010,01101,00001] and [10111,11001,11110,11001,11100,00000,01011,10001,01110,01001,01011,01111,10101,11000,01110,00110,00001,10011,11011,11111] is bitwise XORed to generate the updated data payload. ,Right now [00001,11111,10000,10000,01100,00011,00010,00001,11011,00110,11000,00101,11110,01011,11101,11101,10010,00000,00000,10101]; Step S705: Update the counter variable ,at this time Execute step S706; Step S706: Output a 100-bit decoded data packet [00001,11111,10000,10000,01100,00011,00010,00001,11011,00110,11000,00101,11110,01011,11101,11101,10010,00000,00000,10101].

[0112] In this embodiment of the invention, a pre-generated LFSR scrambling code table and multi-level thresholds are used. , Dynamic programming strategy. This involves initiating first- or second-level dynamic scrambling based on packet sequence numbers only when a long sequence exceeds a threshold, with extremely low overhead. The method encapsulates round information and transition edges using a bit-by-bit approach. It utilizes iterative XOR to effectively disrupt long consecutive bit sequences at arbitrary positions, controlling the probability of long consecutive bit sequences at a specific threshold to a theoretically extremely low level, thus achieving a balance between coding efficiency and transmission reliability.

[0113] Figure 7 This is a block diagram illustrating a circuit encoding and decoding apparatus based on scrambling and dynamic programming, according to an exemplary embodiment. The apparatus is used in a circuit encoding and decoding method based on scrambling and dynamic programming. (Refer to...) Figure 7 The device includes a data acquisition module 310, a scrambling table pre-generation module 320, a first-level scrambling module 330, a second-level scrambling module 340, an encoded data packet generation module 350, an encoded data packet parsing module 360, and a decoded data packet output module 370.

[0114] Figure 8 This is a schematic diagram of the structure of a circuit encoding and decoding device based on scrambling and dynamic programming provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the encoding / decoding device based on scrambling and dynamic programming can include the above-mentioned... Figure 7 The circuit encoding and decoding apparatus shown is based on scrambling and dynamic programming. Optionally, the circuit encoding and decoding apparatus 410 based on scrambling and dynamic programming may include a first processor 2001.

[0115] Optionally, the scrambling and dynamic programming-based circuit coding and decoding device 410 may also include a memory 2002 and a transceiver 2003.

[0116] The first processor 2001, memory 2002, and transceiver 2003 can be connected via a communication bus.

[0117] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A circuit encoding and decoding method based on scrambling and dynamic programming, characterized in that, The method includes: S1. Obtain multiple raw data packets to be encoded, and set the order of the binary scrambling polynomial according to the length of the raw data packets; set the bit detection threshold and maximum processing round parameters for the first-level scrambling code and the second-level scrambling code; initialize the round count variables for the first-level scrambling code and the second-level scrambling code. S2. Construct a binary scrambling polynomial based on the selected multi-order binary primitive polynomial and the set order of the binary scrambling polynomial, and generate a scrambling table matrix based on the binary scrambling polynomial. S3. Obtain any original data packet to be encoded, and perform first-level scrambling on the obtained original data packet according to the scrambling table matrix, the maximum processing round parameter of the first-level scrambling code, and the bit detection threshold, generating a temporary data payload and an updated first-level scrambling code round count variable; wherein, the length of the temporary data payload is the length of the original data packet; S4. Determine whether to perform second-level scrambling based on the maximum processing round parameter of the second-level scrambling code. If second-level scrambling is to be performed, then perform second-level scrambling on the temporary data payload according to the scrambling code table matrix, the maximum processing round parameter of the second-level scrambling code, and the bit detection threshold, and generate the data payload and the updated second-level scrambling round count variable; wherein, the length of the data payload is the length of the original data packet. S5. Combining the preset transition edge flag bits, generate an encoded data packet based on the data payload, the updated first-level scrambling code, and the round count variables of the second-level scrambling code; wherein, the length of the encoded data packet is the sum of the length of the original data packet, the maximum processing round parameter of the first-level scrambling code, the maximum processing round parameter of the second-level scrambling code, and the number of the transition edge flag bits; S6. Parse the encoded data packet bit by bit to obtain the data payload to be decoded, the first-level scrambling code, and the round count variables of the second-level scrambling code. S7. Decode the payload of the data to be decoded according to the scrambling table matrix, the first-level scrambling code, and the round count variables of the second-level scrambling code, and output the decoded data packet.

2. The line encoding and decoding method based on scrambling and dynamic programming according to claim 1, characterized in that, S2 includes: S21. Construct a binary scrambling polynomial based on the selected multi-order binary primitive polynomial and the set order of the binary scrambling polynomial; initialize the state vector of the multi-bit shift register to a sequence of all 1s; initialize the scrambling table matrix to a matrix of all zeros; let... ; S22. Sequentially save the values ​​in the state vector of the multi-bit shift register into the scrambling table matrix. OK; S23, Order ,judge Is it true? If true, proceed to step S24; if false, proceed to step S25; where, Let be the order of the binary scrambling polynomial; S24. Update the multi-bit shift register state vector based on the shift register, and proceed to step S22; S25. Output scrambling code table matrix; wherein, the scrambling code table matrix includes Lines, each line Bit.

3. The line encoding and decoding method based on scrambling and dynamic programming according to claim 1, characterized in that, The S3 includes: S31. Obtain any original data packet to be encoded, and initialize a temporary data payload based on the obtained original data packet; wherein, the length of the temporary data payload is the length of the original data packet; S32. Calculate the maximum number of processing rounds of the first-level scrambling code based on the maximum number of processing rounds parameter of the first-level scrambling code, and set the round count variable of the first-level scrambling code to 0. S33. Detect whether there is a long consecutive value sequence in the temporary data payload whose length reaches or exceeds the bit detection threshold of the first level scrambling code; if it exists, proceed to step S34; if it does not exist, proceed to step S37. S34. Based on the scrambling code table matrix, the sequence number of the obtained original data packet, and the current first-level scrambling code round count variable, generate the first-level scrambling code sequence. S35. XOR the temporary data payload with the first-level scrambling sequence bitwise to generate the updated temporary data payload. S36. Update the first-level scrambling code round count variable; determine whether the updated first-level scrambling code round count variable is less than the maximum number of processing rounds for the first-level scrambling code; if it is less, proceed to step S33; if it is not less, proceed to step S37. S37. Output the temporary data payload and the updated first-level scrambling code round count variable.

4. The line encoding and decoding method based on scrambling and dynamic programming according to claim 1, characterized in that, The S4 includes: S41. Determine if the maximum processing round parameter of the second-level scrambling code is 0; if yes, set the second-level scrambling code round count variable to 0 and execute step S48; if no, execute step S42. S42. Initialize the data payload according to the temporary data payload; wherein, the length of the data payload is the length of the original data packet; S43. Calculate the maximum number of processing rounds of the second-level scrambling code based on the maximum number of processing rounds parameter of the second-level scrambling code, and set the round count variable of the second-level scrambling code to 0. S44. Detect whether there is a long consecutive value sequence in the data payload whose length reaches or exceeds the bit detection threshold of the second-level scrambling code; if it exists, proceed to step S45; if it does not exist, proceed to step S48. S45. Based on the scrambling code table matrix, the sequence number of the original data packet, the updated first-level scrambling code round count variable, and the current second-level scrambling code round count variable, generate the second-level scrambling code sequence. S46. XOR the data payload with the second-level scrambling sequence bitwise to generate the updated data payload; S47. Update the second-level scrambling code round count variable; determine whether the updated second-level scrambling code round count variable is less than the maximum number of processing rounds for the second-level scrambling code; if it is less, proceed to step S44; if it is not less, proceed to step S48. S48, Output data payload and updated second-level scrambling code round count variable.

5. The circuit encoding and decoding method based on scrambling and dynamic programming according to claim 1, characterized in that, The S5 includes: S51. Set the packet header according to the binary representation of the updated first-level scrambling round count variable; wherein, the length of the packet header is the maximum processing round parameter bits of the first-level scrambling code; S52. Determine whether the maximum processing round parameter of the second-level scrambling code is greater than or equal to 1; if so, set the packet tail according to the updated second-level scrambling code round count variable; wherein, the length of the packet tail is the maximum processing round parameter bit of the second-level scrambling code; S53. Combining the preset transition edge flag bits, an encoded data packet is obtained based on the data payload, packet header, and packet tail; wherein, the length of the encoded data packet is the sum of the original data packet length, the maximum processing round parameter of the first-level scrambling code, the maximum processing round parameter of the second-level scrambling code, and the number of the transition edge flag bits.

6. The circuit encoding and decoding method based on scrambling and dynamic programming according to claim 1, characterized in that, The S6 includes: S61. Extract the number of bits corresponding to the maximum processing round parameter of the first-level scrambling code from the preset position of the encoded data packet, and calculate the updated first-level scrambling code round count variable. S62. Determine whether the maximum processing round parameter of the second-level scrambling code is greater than or equal to 1. If yes, extract the number of bits corresponding to the maximum processing round parameter of the second-level scrambling code from the preset position of the encoded data packet and calculate the updated second-level scrambling code round count variable. If no, set the second-level scrambling code round count variable to 0. S63. Set the payload of the data to be decoded according to the encoded data packet.

7. The line encoding and decoding method based on scrambling and dynamic programming according to claim 1, characterized in that, The S7 includes: S71. Based on the sum of the updated first-level scrambling code and second-level scrambling code round count variables, calculate the total reverse scrambling code round count variable; determine whether the total reverse scrambling code round count variable is 0; if yes, proceed to step S76; if no, proceed to step S72. S72. Set the total reverse scrambling code round count variable to 0; S73. Generate a scrambling sequence based on the scrambling table matrix, the sequence number of the encoded data packet, and the current total reverse scrambling round count variable; S74. XOR the data payload to be decoded with the scrambling sequence bitwise to generate the updated data payload. S75. Update the total reverse scrambling round count variable; determine whether the updated total reverse scrambling round count variable is less than the value obtained by subtracting one from the sum of the updated first-level scrambling round count variables and the second-level scrambling round count variables; if yes, proceed to step S73; if no, proceed to step S76. S76. Obtain the decoded data packet based on the updated data payload and output it.

8. A circuit encoding and decoding apparatus based on scrambling and dynamic programming, wherein the circuit encoding and decoding apparatus based on scrambling and dynamic programming is used to implement the circuit encoding and decoding method based on scrambling and dynamic programming as described in any one of claims 1-7, characterized in that, The device includes: The data acquisition module is used to acquire multiple raw data packets to be encoded, set the order of the binary scrambling polynomial according to the length of the raw data packets, set the bit detection threshold and maximum processing round parameters for the first-level and second-level scrambling codes, and initialize the round count variables for the first-level and second-level scrambling codes. The scrambling table pre-generation module is used to construct a binary scrambling polynomial based on the selected multi-order binary primitive polynomial and the set order of the binary scrambling polynomial, and to generate a scrambling table matrix based on the binary scrambling polynomial. The first-level scrambling module is used to acquire any original data packet to be encoded, and to perform first-level scrambling on the acquired original data packet according to the scrambling table matrix, the maximum processing round parameter of the first-level scrambling, and the bit detection threshold, generating a temporary data payload and an updated first-level scrambling round count variable; wherein, the length of the temporary data payload is the length of the original data packet; The second-level scrambling module is used to determine whether to perform second-level scrambling based on the maximum processing rounds parameter of the second-level scrambling. If second-level scrambling is to be performed, the temporary data payload is scrambled according to the scrambling table matrix, the maximum processing rounds parameter of the second-level scrambling, and the bit detection threshold, generating the data payload and the updated second-level scrambling round count variable; wherein, the length of the data payload is the length of the original data packet; The encoded data packet generation module is used to combine preset transition edge flag bits with data payload, updated first-level scrambling code and second-level scrambling code round count variables to generate encoded data packets; wherein, the length of the encoded data packet is the sum of the length of the original data packet, the maximum processing round parameter of the first-level scrambling code, the maximum processing round parameter of the second-level scrambling code and the number of transition edge flag bits; The encoded data packet parsing module is used to parse the encoded data packet bit by bit to obtain the data payload to be decoded, the first-level scrambling code, and the round count variables of the second-level scrambling code. The decoded data packet output module is used to perform decoding operations on the payload of the data to be decoded based on the scrambling table matrix, the first-level scrambling code, and the round count variables of the second-level scrambling code, and output the decoded data packet.

9. A circuit encoding and decoding device based on scrambling and dynamic programming, characterized in that, The circuit encoding and decoding device based on scrambling and dynamic programming includes: processor; A memory storing computer-readable instructions that, when executed by the processor, implement the method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains program code that can be invoked by a processor to execute the method as described in any one of claims 1 to 7.

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