Deep-space high-bit-rate signal receiving and demodulating device
By utilizing the inherent positional relationship of I/Q signals before distortion through a fully digital demodulation device, effective reception and demodulation of high-code-rate signals in deep space can be achieved. This simplifies hardware design, improves the adaptability and reliability of the device, and supports adaptive processing of various modulation signals.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- THE 54TH RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
- Filing Date
- 2026-01-30
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional deep-space high-bit-rate demodulation devices have complex hardware designs, require high signal sampling rates and digital resampling processing, have long detection times, and cannot effectively receive high-bit-rate signals.
The fully digital demodulation device, composed of digital quadrature downconversion, low-pass filtering unit, digital resampling, and matched filtering unit, utilizes the inherent positional relationship between the I and Q signals before distortion. It achieves symbol alignment and decimation processing through timing error extraction, carrier Doppler frequency offset estimation, and carrier lock-in unit, thus simplifying the reception process.
It achieves effective reception and demodulation of high-code-rate signals from deep space, reduces hardware design complexity, improves the adaptability and reliability of the device, and supports adaptive processing of different modulation signals such as OQPSK and QPSK.
Smart Images
Figure CN122027423A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of communication and data transmission, and in particular to a deep space high code rate signal receiving and demodulation device, which can be used for receiving and demodulating deep space high code rate signals. Background Technology
[0002] As the data transmission volume in deep space communication increases, the code rate of deep space communication signals is gradually increasing, and higher-order modulation schemes are increasingly being used. After the actual signal passes through the transmitting power amplifier, it will produce unique inherent distortions, manifested as an inherent intra-symbol misalignment between the I and Q signals within a single transmission symbol. This makes traditional high-code-rate receivers and demodulators unable to effectively receive such signals. To address this issue, traditional deep-space high-code-rate demodulation devices detect the energy values of the I and Q signals after integration and cleaning, and adjust the integration and cleaning window positions of the I and Q signals accordingly to achieve effective signal reception. However, the hardware design and processing of these devices are complex, requiring high signal sampling rates or additional digital resampling processes, and necessitating a long detection time to complete the sliding detection of the integration and cleaning window positions, ultimately achieving effective signal reception. Summary of the Invention
[0003] The purpose of this invention is to overcome the shortcomings of the aforementioned background technology and provide a deep-space high-code-rate signal receiving and demodulation device. This invention features high reliability, high stability, and low implementation complexity.
[0004] The objective of this invention is achieved as follows:
[0005] A deep-space high-code-rate signal receiving and demodulation device includes a digital quadrature down-conversion unit 1, a low-pass filter unit 2, a digital resampling unit 3, a matched filter unit 4, a first half-symbol shift unit 5-1, a second half-symbol shift unit 5-2, a third half-symbol shift unit 5-3, a coherent AGC unit 6, a carrier error compensation unit 7, a first decimation unit 8-1, a second decimation unit 8-2, a third decimation unit 8-3, a carrier phase error extraction unit 9, a timing error extraction unit 10, an incoherent AGC unit 11, a carrier Doppler frequency offset estimation unit 12, and a carrier lock-in unit 13.
[0006] Furthermore, the digital quadrature downconversion unit 1 performs digital downconversion processing on the intermediate frequency sampling signal, and uses the input carrier Doppler frequency offset estimation signal to complete the carrier coarse synchronization of the input intermediate frequency sampling signal, while generating and outputting two orthogonal baseband signals, I and Q.
[0007] The low-pass filter unit 2 processes the I / Q quadrature baseband signals output by the digital quadrature downconverter unit 1 and transmits the processed I / Q quadrature baseband signals to the digital resampling unit 3.
[0008] The digital resampling unit 3 uses the input symbol rate setting value and timing error to complete the timing synchronization of the I / Q quadrature baseband signals, and at the same time generates and outputs the I / Q quadrature baseband signals with 2 times sampling.
[0009] The matched filter unit 4 filters the I / Q quadrature baseband signals sampled twice and outputs them; the output I / Q quadrature baseband signals are split to generate two sets of I / Q quadrature baseband signals, wherein the first set of I / Q quadrature baseband signals is transmitted to the first half-symbol shift unit 5-1, and the second set of I / Q quadrature baseband signals is transmitted to the incoherent AGC unit 11.
[0010] The first half-symbol shifting unit 5-1, based on the input modulation scheme setting value, when the modulation scheme setting value is OQPSK, keeps the input I signal unchanged and outputs it, and delays and shifts the input Q signal by one sampling time and outputs it; when the modulation scheme setting value is other modulation schemes, both the I and Q signals remain unchanged and are output.
[0011] The coherent AGC unit 6 receives the signal output by the first half-symbol shift unit 5-1, performs power detection on the peak point position signals of the I / Q channels in the received signal, and adjusts the power of the input signal according to the detection value before outputting it.
[0012] The carrier error compensation unit 7 receives the signal output by the coherent AGC unit 6 and performs carrier phase error compensation processing on the input I / Q quadrature baseband signal according to the input carrier phase error value, thereby completing the carrier synchronization of the signal and outputting the carrier-synchronized I / Q quadrature baseband signals; the I / Q quadrature baseband signals output by the carrier error compensation unit 7 are split to generate three sets of I / Q quadrature baseband signals, wherein the first set of I / Q quadrature baseband signals is transmitted to the timing error extraction unit 10, the second set of I / Q quadrature baseband signals is transmitted to the first decimation unit 8-1, and the third set of I / Q quadrature baseband signals is transmitted to the third half-symbol shift unit 5-3;
[0013] The timing error extraction unit 10 calculates the input I / Q quadrature baseband signal, generates a timing error, and transmits the timing error to the digital resampling unit 3;
[0014] The first extraction unit 8-1 extracts the peak point position signal of the input signal and transmits the extracted signal to the carrier phase error extraction unit 9;
[0015] The carrier phase error extraction unit 9 calculates the carrier phase error of the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the carrier phase error to the carrier phase error compensation unit 7;
[0016] The third half-symbol shifting unit 5-3 controls and periodically detects the carrier lock indication signal output by the carrier lock detection unit 13 through an internal timer. When the carrier is locked at the detection time, it maintains the existing signal output state. When the carrier is unlocked at the detection time, it keeps the Q-channel signal unchanged and cyclically switches the I-channel signal between direct output and delayed output by one sampling moment. After switching, it maintains the switching output state of the output signal until the next carrier lock detection moment, and switches the output signal according to the new detection result. The output signal of the third half-symbol shifting unit 5-3 is transmitted to the third decimation unit 8-3.
[0017] The third extraction unit 8-3 extracts the peak point position signal of the input signal and transmits the extracted signal to the carrier detection and locking unit 13;
[0018] The carrier lock detection unit 13 detects the carrier lock status of the input signal and transmits the detected carrier lock status to the third half-symbol shift unit 5-3 and the second half-symbol shift unit 5-2 respectively.
[0019] The incoherent AGC unit 11 detects the total power of the input signal at the peak point and the zero-crossing point, adjusts the power of the input signal according to the detected value, and then outputs it to the second half-symbol shift unit 5-2;
[0020] The second half-symbol shifting unit 5-2 controls and periodically detects the carrier lock indication signal output by the carrier lock detection unit 13 through an internal timer. When the carrier is locked at the detection time, it maintains the existing signal output state. When the carrier is unlocked at the detection time, it keeps the Q-channel signal unchanged and cyclically switches the I-channel signal between direct output and delayed output by one sampling moment. After switching, it maintains the switching output state of the output signal until the next carrier lock detection moment, and switches the output signal according to the new detection result. The output signal of the second half-symbol shifting unit 5-2 is transmitted to the second decimation unit 8-2.
[0021] The second extraction unit 8-2 extracts the peak point position signal of the input signal and transmits the extracted signal to the carrier Doppler frequency offset estimation unit 12;
[0022] The carrier Doppler frequency offset estimation unit 12 performs carrier Doppler frequency offset estimation on the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the frequency offset estimation value to the digital quadrature downconversion unit 1.
[0023] Compared with the prior art, the present invention has the following advantages:
[0024] 1. Compared with traditional demodulation devices, this invention addresses the inherent distortion characteristics of high-code-rate deep-space signals after power amplification. By utilizing the inherent positional relationship between the I / Q signals before distortion and the impact of distortion on different receiving and demodulation modules, a receiving processing method involving symbol alignment and decimation is employed before the timing error extraction unit, the carrier Doppler frequency offset estimation unit, and the carrier lock-in unit. This method achieves effective reception and demodulation of high-code-rate deep-space signals, thereby simplifying the reception process and improving the effectiveness of the device.
[0025] 2. This device utilizes a carrier-locked indication signal to automatically switch symbol alignment strategies, enabling adaptive processing of different modulation signals such as OQPSK, QPSK, and 8PSK in deep space high-code-rate signals. It can also be applied to high-code-rate signal reception in other scenarios, improving the adaptability of the device.
[0026] 3. This device can be implemented using an FPGA chip in a fully digital manner, which can reduce the complexity of the device hardware design and at the same time meet the requirements for rapid equipment upgrades. Attached Figure Description
[0027] Figure 1 This is a block diagram illustrating the principle of the present invention. Detailed Implementation
[0028] Reference Figure 1 A deep-space high-code-rate signal receiving and demodulation device includes a digital quadrature down-conversion unit 1, a low-pass filter unit 2, a digital resampling unit 3, a matched filter unit 4, a first half-symbol shift unit 5-1, a second half-symbol shift unit 5-2, a third half-symbol shift unit 5-3, a coherent AGC unit 6, a carrier error compensation unit 7, a first decimation unit 8-1, a second decimation unit 8-2, a third decimation unit 8-3, a carrier phase error extraction unit 9, a timing error extraction unit 10, an incoherent AGC unit 11, a carrier Doppler frequency offset estimation unit 12, and a carrier lock-in unit 13.
[0029] The digital quadrature downconversion unit 1 performs digital downconversion processing on the intermediate frequency (IF) sampled signal and uses the input carrier Doppler frequency offset estimation signal to complete the carrier coarse synchronization of the input IF sampled signal. Simultaneously, it generates and outputs two quadrature baseband signals (I and Q channels). These two quadrature baseband signals are processed by the low-pass filter unit 2 and then transmitted to the digital resampling unit 3. The digital resampling unit 3 uses the input symbol rate setting value and timing error to complete the timing synchronization of the I and Q quadrature baseband signals. It also generates and outputs two quadrature baseband signals (I and Q channels) with double sampling. These double-sampled I and Q quadrature baseband signals are filtered by the matched filter unit 4 and then output. The output I and Q quadrature baseband signals are then split to generate two sets of I / Q quadrature baseband signals. The baseband signal is transmitted to the first half-symbol shift unit 5-1. The first half-symbol shift unit 5-1, based on the input modulation scheme setting value, maintains the input I-channel signal while delaying and shifting the input Q-channel signal by one sampling time when the modulation scheme setting value is OQPSK. When the modulation scheme setting value is other modulation schemes, both the I and Q-channel signals remain unchanged and are output. The coherent AGC unit 6 receives the signal output by the first half-symbol shift unit 5-1, performs power detection on the peak point position signals of the I and Q channels in the received signal, and adjusts the power of the input signal according to the detection value before outputting it. The carrier error compensation unit 7 receives the signal output by the coherent AGC unit 6 and adjusts the power of the input signal according to the input carrier phase error value. The carrier error compensation unit 7 performs carrier phase error compensation processing on the I / Q quadrature baseband signals to achieve carrier synchronization. The synchronized I / Q quadrature baseband signals are then output. The I / Q quadrature baseband signals output by the carrier error compensation unit 7 are further split to generate three sets of I / Q quadrature baseband signals. The first set of I / Q quadrature baseband signals is transmitted to the timing error extraction unit 10. The timing error extraction unit 10 calculates the timing error from the input I / Q quadrature baseband signals and transmits the timing error to the digital resampling unit 3. The second set of I / Q quadrature baseband signals output by the carrier error compensation unit 7 is transmitted to the first decimation unit 8-1. The first decimation unit 8-1 extracts the peak position signal of the input signal and transmits the extracted signal... The signal is input to the carrier phase error extraction unit 9. The carrier phase error extraction unit 9 calculates the carrier phase error of the input I / Q quadrature baseband signal according to the input modulation scheme settings and transmits the carrier phase error to the carrier phase error compensation unit 7. The third set of I / Q quadrature baseband signals output by the carrier error compensation unit 7 is transmitted to the third half-symbol shift unit 5-3. The third half-symbol shift unit 5-3 controls and periodically detects the carrier lock indication signal output by the carrier lock detection unit 13 through an internal timer. When the carrier is locked at the detection time, the existing signal output state is maintained; when the carrier is unlocked at the detection time, the Q-channel signal remains unchanged, and the I-channel signal is cyclically switched between direct output and delayed output with a one-sampling-time offset.After switching, the output signal remains in a switched output state until the next carrier lock detection time. Based on the new detection result, the output signal is switched. The output signal of the third half-symbol shift unit 5-3 is transmitted to the third decimation unit 8-3. The third decimation unit 8-3 extracts the peak position signal of the input signal and transmits the extracted signal to the carrier lock detection unit 13. The carrier lock detection unit 13 detects the carrier lock state of the input signal and transmits the detected carrier lock state to the third half-symbol shift unit 5-3 and the second half-symbol shift unit 5-2 respectively. The second set of I / Q quadrature baseband signals output by the matched filter unit 4 is transmitted to the incoherent AGC unit 11. The incoherent AGC unit 11 detects the total power of the input signal at the peak point and zero-crossing point, adjusts the power of the input signal according to the detection value, and then outputs it. The I / Q quadrature baseband signals output by the incoherent AGC unit 11 are transmitted to the second half-symbol shift unit 5-2. The second half-symbol shift unit 5-2 controls and periodically detects the carrier lock indication signal output by the carrier lock detection unit 13 through an internal timer. When the carrier is locked at the detection time, it maintains the existing signal output state. When the carrier is unlocked at the detection time, it keeps the Q-channel signal unchanged and cyclically switches the I-channel signal between direct output and delayed output by one sampling moment. After switching, it maintains the switching output state of the output signal until the next carrier lock detection moment, and switches the output signal according to the new detection result. The output signal of the second half-symbol shift unit 5-2 is transmitted to the second decimation unit 8-2. The second decimation unit 8-2 extracts the peak position signal of the input signal and transmits the extracted signal to the carrier Doppler frequency offset estimation unit 12. The carrier Doppler frequency offset estimation unit 12 performs carrier Doppler frequency offset estimation on the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the frequency offset estimate to the digital quadrature downconverter unit.
[0030] This device utilizes the above principles to achieve the purpose of receiving and demodulating high-bit-rate signals from deep space.
[0031] In this example, the digital quadrature downconversion unit 1, low-pass filter unit 2, digital resampling unit 3, matched filter unit 4, first half-symbol shift unit 5-1 to third half-symbol shift unit 5-3, coherent AGC unit 6, carrier error compensation unit 7, first decimation unit 8-1 to third decimation unit 8-3, carrier phase error extraction unit 9, timing error extraction unit 10, incoherent AGC unit 11, carrier Doppler frequency offset estimation unit 12, and carrier lock-in unit 13 are all implemented using FPGA.
[0032] Compared to traditional demodulation devices, this invention addresses the inherent distortion characteristics of high-bit-rate deep-space signals after power amplification by employing symbol alignment and decimation processing before the timing error extraction unit, carrier Doppler frequency offset estimation unit, and carrier lock-in unit. This achieves effective reception and demodulation of high-bit-rate deep-space signals. Utilizing a carrier lock-in indication signal, this device automatically switches symbol alignment strategies, enabling adaptive processing of different modulation signals such as OQPSK, QPSK, and 8PSK in high-bit-rate deep-space signals. Furthermore, it can be applied to high-bit-rate signal reception in other scenarios, improving the device's adaptability and effectiveness. This device can be implemented entirely digitally, reducing hardware design complexity and facilitating implementation and widespread adoption.
Claims
1. A deep-space high-bit-rate signal receiving and demodulation device, characterized in that, It includes a digital quadrature downconversion unit (1), a low-pass filter unit (2), a digital resampling unit (3), a matched filter unit (4), a first half-symbol shift unit (5-1), a second half-symbol shift unit (5-2), a third half-symbol shift unit (5-3), a coherent AGC unit (6), a carrier error compensation unit (7), a first decimation unit (8-1), a second decimation unit (8-2), a third decimation unit (8-3), a carrier phase error extraction unit (9), a timing error extraction unit (10), an incoherent AGC unit (11), a carrier Doppler frequency offset estimation unit (12), and a carrier lock-in unit (13).
2. The deep space high-bit-rate signal receiving and demodulation device according to claim 1, characterized in that, The digital orthogonal downconversion unit (1) performs digital downconversion processing on the intermediate frequency sampling signal and uses the input carrier Doppler frequency offset estimation signal to complete the carrier coarse synchronization of the input intermediate frequency sampling signal, while generating and outputting two orthogonal baseband signals, I and Q. The low-pass filter unit (2) processes the I / Q quadrature baseband signals output by the digital quadrature downconverter unit (1) and transmits the processed I / Q quadrature baseband signals to the digital resampling unit (3). The digital resampling unit (3) uses the input symbol rate setting value and timing error to complete the timing synchronization of the I / Q quadrature baseband signals, and at the same time generates and outputs the I / Q quadrature baseband signals with 2 times sampling. The matched filter unit (4) filters the I / Q quadrature baseband signals sampled twice and outputs them; the output I / Q quadrature baseband signals are split to generate two sets of I / Q quadrature baseband signals, wherein the first set of I / Q quadrature baseband signals is transmitted to the first half-symbol shift unit (5-1), and the second set of I / Q quadrature baseband signals is transmitted to the incoherent AGC unit (11). The first half-symbol shift unit (5-1) operates according to the input modulation scheme setting value. When the modulation scheme setting value is OQPSK, it keeps the input I signal unchanged and outputs it, and delays and shifts the input Q signal by one sampling time and outputs it. When the modulation scheme setting value is other modulation schemes, both the I and Q signals remain unchanged and are output. The coherent AGC unit (6) receives the signal output by the first half-symbol shift unit (5-1), performs power detection on the peak point position signals of the I / Q channels in the received signal, and outputs the signal after adjusting the power of the input signal according to the detection value. The carrier error compensation unit (7) receives the signal output by the coherent AGC unit (6) and performs carrier phase error compensation processing on the input I / Q quadrature baseband signal according to the input carrier phase error value, thereby completing the carrier synchronization of the signal and outputting the I / Q quadrature baseband signals after carrier synchronization; the I / Q quadrature baseband signals output by the carrier error compensation unit (7) are split to generate three sets of I / Q quadrature baseband signals, wherein the first set of I / Q quadrature baseband signals is transmitted to the timing error extraction unit (10), the second set of I / Q quadrature baseband signals is transmitted to the first decimation unit (8-1), and the third set of I / Q quadrature baseband signals is transmitted to the third half-symbol shift unit (5-3). The timing error extraction unit (10) calculates the input I / Q quadrature baseband signal, generates timing error, and transmits the timing error to the digital resampling unit (3). The first extraction unit (8-1) extracts the peak point position signal of the input signal and transmits the extracted signal to the carrier phase error extraction unit (9). The carrier phase error extraction unit (9) calculates the carrier phase error of the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the carrier phase error to the carrier phase error compensation unit (7). The third half-symbol shifting unit (5-3) controls and periodically detects the carrier lock indication signal output by the carrier lock detection unit (13) through an internal timer. When the carrier is locked at the detection time, it maintains the existing signal output state. When the carrier is unlocked at the detection time, it keeps the Q-channel signal unchanged and cyclically switches the I-channel signal to either direct output or delayed output by one sampling time. After switching, it maintains the switching output state of the output signal until the next carrier lock detection time, and switches the output signal according to the new detection result. The output signal of the third half-symbol shifting unit (5-3) is transmitted to the third decimation unit (8-3). The third extraction unit (8-3) extracts the peak point position signal of the input signal and transmits the extracted signal to the carrier detection and locking unit (13). The carrier lock detection unit (13) detects the carrier lock status of the input signal and transmits the detected carrier lock status to the third half-symbol shift unit (5-3) and the second half-symbol shift unit (5-2), respectively. The incoherent AGC unit (11) detects the total power of the input signal at the peak point and the zero-crossing point, adjusts the power of the input signal according to the detected value, and then outputs it to the second half-symbol shift unit (5-2). The second half-symbol shift unit (5-2) controls and periodically detects the carrier lock indication signal output by the carrier lock detection unit (13) through an internal timer. When the carrier is locked at the detection time, it maintains the existing signal output state. When the carrier is unlocked at the detection time, it keeps the Q-channel signal unchanged and cyclically switches the I-channel signal to either direct output or delayed output by one sampling time. After switching, it maintains the switching output state of the output signal until the next carrier lock detection time, and switches the output signal according to the new detection result. The output signal of the second half-symbol shift unit (5-2) is transmitted to the second decimation unit (8-2). The second extraction unit (8-2) extracts the peak point position signal of the input signal and transmits the extracted signal to the carrier Doppler frequency offset estimation unit (12). The carrier Doppler frequency offset estimation unit (12) performs carrier Doppler frequency offset estimation on the input I / Q quadrature baseband signal according to the input modulation scheme setting parameters, and transmits the frequency offset estimation value to the digital quadrature downconversion unit (1).