Resource regulation and control method, device and system based on heterogeneous performance indexes, equipment and medium
By acquiring heterogeneous performance parameters in each scheduling cycle of the FPGA circuit, calculating priority service weights, and performing resource regulation, the problems of low efficiency and poor stability of FPGA resource regulation in the prior art are solved, and efficient and stable resource management is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI ANLOGIC INFOTECH CO LTD
- Filing Date
- 2026-02-03
- Publication Date
- 2026-05-12
AI Technical Summary
Existing FPGA resource management methods are inefficient and can easily interrupt current tasks when reconfiguring or dynamically allocating resources, affecting the stability of business processing.
In each preset scheduling cycle, the heterogeneous performance parameters of the FPGA circuit are acquired, the priority service weights are determined based on the heterogeneous performance index values, and the FPGA circuit is regulated through resource control parameters, including priority weight calculation and resource allocation for communication latency, sensing detection rate and buffer level.
It improved the timeliness and efficiency of resource allocation, simplified the allocation process, avoided task interruption, and ensured the stability of business processing.
Smart Images
Figure CN122028207A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of resource regulation, and in particular to a resource regulation method, apparatus, system, equipment and medium based on heterogeneous performance indicators. Background Technology
[0002] With the advancement of wireless communication technology, the application scale of various communication devices is expanding, and the computational demands are becoming increasingly diverse. Faced with this diversity, single-function communication devices are no longer sufficient to meet the needs. Therefore, maximizing the efficiency of communication devices with limited resources has become an urgent problem to solve. This is especially true for Field-Programmable Gate Arrays (FPGAs), which serve as the primary computing resource for wireless communication devices, as the requirements for computational flexibility and speed during task execution are becoming increasingly stringent.
[0003] To receive and process data from different tasks, one common method for FPGA resource management is to configure and monitor the FPGA using software. Specifically, this involves first loading the configuration file (bitstream) onto the FPGA via interfaces such as JTAG and SPI. Then, various tools (e.g., Xilinx Vivado or Intel Quartus system analyzers) are used to monitor resource usage in real time. Finally, based on the monitoring results, partial reconfiguration is performed, reloading certain areas of the FPGA and quickly switching functions by reconfiguring hardware paths. Alternatively, intelligent algorithms (such as reinforcement learning) can be used to dynamically allocate resources and optimize throughput.
[0004] However, the above method has the following technical problems: from loading the configuration file and monitoring the resource status to completing the configuration adjustment, each step takes a long time, resulting in low overall processing efficiency. Furthermore, the process of reconfiguring or dynamically allocating resources requires interrupting currently running tasks, which not only further reduces processing efficiency but may also cause task errors, severely impacting the stability of business processing. Summary of the Invention
[0005] This invention provides a resource regulation method, apparatus, equipment, and medium based on heterogeneous performance indicators, which can solve one or more technical problems existing in the prior art.
[0006] A first aspect of this invention provides a resource regulation method based on heterogeneous performance indicators, the method comprising: In each preset scheduling cycle, the heterogeneous performance parameters of the FPGA circuit are acquired, and the heterogeneous performance parameters include several different heterogeneous performance index values. If any of the heterogeneous performance index values does not meet the corresponding index threshold, then the heterogeneous performance index values are used to determine different priority service weights. Several resource control parameters are determined based on the priority service weights, and the FPGA circuit is resource-controlled based on these parameters.
[0007] A second aspect of this invention provides a resource regulation device based on heterogeneous performance indicators, the device comprising: The acquisition module is used to acquire the heterogeneous performance parameters of the FPGA circuit in each preset scheduling cycle. The heterogeneous performance parameters include several different heterogeneous performance index values. The determination module is used to determine different priority business weights based on the heterogeneous performance index values if any one of the heterogeneous performance index values does not meet the corresponding index threshold. The control module is used to determine several resource control parameters according to the priority service weights, and to control the resources of the FPGA circuit according to the several resource control parameters.
[0008] A third aspect of this invention provides a resource regulation system based on heterogeneous performance indicators, the system comprising: Processing modules, FPGA circuits, and RF front-end devices; The FPGA circuit is connected to the processing module and the RF front-end device, respectively. The processing module is applicable to the resource regulation method based on heterogeneous performance indicators as described above.
[0009] Compared to existing technologies, the resource regulation method, apparatus, device, and medium based on heterogeneous performance indicators provided by this invention have the following advantages: This invention can acquire heterogeneous performance parameters of the FPGA circuit in each preset scheduling cycle; if any heterogeneous performance indicator value does not meet the corresponding indicator threshold, different priority service weights are determined using the heterogeneous performance indicator value; several resource regulation parameters are determined according to the priority service weights, and resource regulation of the FPGA circuit is performed based on these parameters. This invention can acquire performance parameters in each cycle, and when any performance parameter is not met, resource regulation is performed based on the heterogeneous performance indicator value, which not only improves the timeliness of regulation but also simplifies the regulation process and improves regulation efficiency. Attached Figure Description
[0010] Figure 1 This is a flowchart illustrating a resource regulation method based on heterogeneous performance indicators provided in an embodiment of the present invention. Figure 2This is an operation flowchart of a resource regulation method based on heterogeneous performance indicators provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a resource regulation device based on heterogeneous performance indicators according to an embodiment of the present invention; Figure 4 This is a structural block diagram of a resource regulation system based on heterogeneous performance indicators provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a resource regulation system based on heterogeneous performance indicators provided in an embodiment of the present invention. Detailed Implementation
[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0012] With the advancement of wireless communication technology, the application scale of various communication devices is expanding, and the computational demands are becoming increasingly diverse. Faced with this diversity, single-function communication devices are no longer sufficient to meet the needs. Therefore, maximizing the efficiency of communication devices with limited resources has become an urgent problem to solve. This is especially true for Field-Programmable Gate Arrays (FPGAs), which serve as the primary computing resource for wireless communication devices, as the requirements for computational flexibility and speed during task execution are becoming increasingly stringent.
[0013] To receive and process data from different tasks, one common method for FPGA resource management is to configure and monitor the FPGA using software. Specifically, this involves first loading the configuration file (bitstream) onto the FPGA via interfaces such as JTAG and SPI. Then, various tools (e.g., Xilinx Vivado or Intel Quartus system analyzers) are used to monitor resource usage in real time. Finally, based on the monitoring results, partial reconfiguration is performed, reloading certain areas of the FPGA and quickly switching functions by reconfiguring hardware paths. Alternatively, intelligent algorithms (such as reinforcement learning) can be used to dynamically allocate resources and optimize throughput.
[0014] However, the above method has the following technical problems: from loading files and monitoring resources to adjusting configurations, each step is time-consuming and inefficient. Furthermore, reconfiguring or dynamically allocating resources requires interrupting the current task, further reducing efficiency. In addition, interrupting the task may cause errors and reduce the stability of business processing.
[0015] To address the aforementioned issues, the following specific embodiments will provide a detailed description and explanation of a resource regulation method, apparatus, device, and medium based on heterogeneous performance indicators provided in this application.
[0016] To solve one or more technical problems existing in the prior art, referring to Figure 1 The diagram shows a flowchart of a resource regulation method based on heterogeneous performance indicators provided by an embodiment of the present invention.
[0017] As an example, the resource regulation method based on heterogeneous performance indicators may include: S11. Obtain the heterogeneous performance parameters of the FPGA circuit in each preset scheduling cycle. The heterogeneous performance parameters include several different heterogeneous performance index values.
[0018] To improve the efficiency of control, users can preset a control duration, such as 5ms or 10ms. Each control duration corresponds to a control cycle. At the beginning of each preset scheduling cycle, the heterogeneous performance parameters of the FPGA circuit can be obtained, which may include several different heterogeneous performance index values.
[0019] In one embodiment, the heterogeneous performance metrics are communication latency, sensing detection rate, and cache level. It should be noted that the cache level represents the occupancy status of shared cache resources in the scheduling system; it is the ratio between the current amount of data to be processed and the corresponding available cache capacity, a capacity occupancy ratio, often referred to as cache occupancy level in engineering.
[0020] S12. If any of the heterogeneous performance index values does not meet the corresponding index threshold, then different priority service weights are determined using the index threshold, wherein the index threshold is calculated based on the heterogeneous performance index value.
[0021] After obtaining the values corresponding to communication latency, sensing detection rate, and buffer level, these values can be compared with their corresponding threshold values to determine whether they meet the requirements.
[0022] If the communication delay, the sensing detection rate, or the buffer level does not meet the corresponding threshold, it is determined that the resources available for the FPGA circuit to execute the current service are insufficient to meet the service requirements. Therefore, resource adjustment is necessary based on the currently executed service.
[0023] To determine the threshold value corresponding to each heterogeneous performance index, the threshold value can be calculated based on each heterogeneous performance index value.
[0024] For example, there are three heterogeneous performance metrics: communication latency, sensing detection rate, and buffer level. The threshold value for the communication latency metric can be calculated using the communication latency value. Similarly, the threshold value for the sensing detection rate metric can be calculated using the sensing detection rate value. Finally, the threshold value for the buffer level metric can be calculated using the buffer level value.
[0025] To align with the actual situation of current business operations, different priority business weights can be determined using indicator thresholds. These priority business weights can be weighted values for prioritizing the execution of different business tasks.
[0026] In an optional embodiment, the step of determining different priority service weights using the indicator threshold if any one of the heterogeneous performance index values does not meet the corresponding index threshold may include the following sub-steps: S121. Normalize and smooth each of the heterogeneous performance index values to obtain several processing performance index values.
[0027] S122. Determine whether each of the processing performance index values meets the corresponding index threshold.
[0028] S123. If any of the heterogeneous performance index values does not meet the corresponding index threshold, then each of the processing performance index values is used to calculate the communication priority service weight and the perception priority service weight.
[0029] After collecting heterogeneous performance index values, these values can be normalized and smoothed to obtain processing performance index values. By mapping heterogeneous performance indexes such as communication latency, sensing detection rate, and buffer level to a unified emergency metric, a basis for prioritizing and allocating communication and sensing resources within the scheduling cycle can be provided.
[0030] In one embodiment, the processing performance index value can be expressed as follows: ; In the above formula, It is a performance indicator value, x t It is a heterogeneous performance index value (where L) tFor communication delay, P d，t For the perception detection rate, W t For buffer water level; This represents a performance metric for handling communication latency. This represents the processing performance metric of the detection rate. (where α is the performance index value for buffer water level processing), α = 0.2.
[0031] Next, it is determined whether each processing performance metric value meets the corresponding metric threshold.
[0032] For example, the processing performance index value of the buffer level can be determined. Is it greater than the water level threshold W? hi It can determine the processing performance index value of communication latency. Is it greater than the communication delay threshold L? max It can determine the processing performance index value of the sensing detection rate. Is it less than the perception detection rate threshold P? d,min .
[0033] If the performance index of buffer water level processing is Greater than the water level threshold W hi Communication latency processing performance index Greater than the communication delay threshold L max Or the processing performance index of the sensing detection rate. Less than the perception detection rate threshold P d,min Then, the communication priority service weight and the perception priority service weight are calculated using each of the aforementioned processing performance index values. The communication priority service weight represents the weight value for prioritizing resource allocation in processing communication services, and the perception priority service weight represents the weight value for prioritizing resource allocation in processing perception services.
[0034] In one embodiment, the water level threshold W hi The cache water level can be determined based on the cache water level itself. Alternatively, the cache water level threshold (e) can be calculated by using the processing performance metric value of the cache water level. W Specifically, the cache water level threshold e W It can be represented as follows: ; Among them, W hi This represents a cache high-water threshold of 80%; W lo This represents the low water level threshold, which can be set to 50%. `clip(z,0,1)` indicates a restriction between 0 and 1. When the water level is low, it means there are no constraints. Specifically, the condition for a low water level is as follows: ; When the water level is within the warning range, the buffer water level threshold e is at this time. W The constraint is linearly enhanced; specifically, the condition for the water level to be within the warning zone is shown in the following equation: ; If the current water level is too high, strong constraints are required. The condition for a high current water level is as follows: ; For water level constraints, a "congestion coefficient λ" can be defined, which can be expressed as follows: ; Where, k W =0.3, for example, in a high-water-level scenario, the cache water level threshold e W =1, λ=0.7, the amount of data entering the FIFO in the next scheduling cycle will be 0.7 of the original amount.
[0035] The role of the cache water level: The cache water level W is the ratio of shared cache resource capacity utilization, used to determine whether the system is in a congested state, and is an important constraint on scheduling strategies. When W ≥ W0 hi When W reaches 80%, congestion protection mode can be entered to prioritize stability; when W is in the warning range, e is generated through normalization. W Dynamically adjust the intensity of resource allocation.
[0036] In one embodiment, the processing performance metrics include: a processing performance metric for communication latency and a processing performance metric for sensing detection rate. As an example, the step of calculating the communication priority service weight and the perception priority service weight using the indicator thresholds may include the following sub-steps: S1231. Calculate the degree of communication delay default using the processing performance index value of the communication delay, and calculate the communication priority service weight value using the degree of communication delay default and the preset first service weight value.
[0037] S1232. Calculate the degree of perceived violation using the processing performance index value of the perceived detection rate, and calculate the perceived priority service weight value using the degree of perceived violation and the preset second service weight value.
[0038] In one embodiment, the degree of communication delay breach e L It can be represented as follows: ; Among them, L max For communication delay limits (communication service SLA); e L The degree of communication delay breach represents the relative proportion of delays exceeding the upper limit (0 indicates no exceedance), eL It is a dimensionless normalized degree of default.
[0039] In one embodiment, the degree of violation e is sensed and detected. Pd It can be represented as follows: ; Among them, P d,min This represents the minimum required detection rate; e Pd To detect the degree of default, e represents the relative gap below the threshold (0 represents compliance). Pd The normalized degree of default is dimensionless.
[0040] In one embodiment, the communication priority service weight S c The calculation can be shown in the following formula: ; In the above formula, S c W represents the priority weight for communication services. L This is the preset first business weight value.
[0041] In one embodiment, the perception priority service weight S s The calculation can be shown in the following formula: ; In the above formula, S s To perceive priority business weights, W Pd This is a preset second business weight value.
[0042] It should be noted that in scenarios where communication and sensing are balanced, W L =W Pd = 1, in a scenario where communication is guaranteed, W L =1.5, W Pd = 1.0.
[0043] In a non-congestion state (cache level W is below the high threshold W) hi ), can be based on the urgency level S of the communication service c With perception of business urgency S s The comparison results determine the scheduling priority mode: When S c When Ss>θ, the communication service is determined to be a priority service; When Ss - S c When the value is greater than θ, the sensing service is determined as the priority service; When the difference between the two values is within the dead zone threshold θ, a balanced scheduling mode is adopted.
[0044] When the cache level exceeds the high threshold, the system can enter congestion protection mode, and the scheduling strategy prioritizes ensuring system stability.
[0045] S13. Determine several resource control parameters according to the priority service weights, and perform resource control on the FPGA circuit according to the several resource control parameters.
[0046] After calculating the priority service weights, several resource control parameters can be determined using the priority service weights, and then the FPGA circuit can be resource-controlled based on these parameters.
[0047] After adjustment, the FPGA circuit can perform service processing according to the updated resources in the next preset scheduling cycle, which enables the FPGA circuit to meet the service processing requirements in the next cycle.
[0048] In one embodiment, the step of determining a plurality of resource control parameters based on the priority service weights and performing resource control on the FPGA circuit based on the plurality of resource control parameters may include the following sub-steps: S131. Several resource control parameters are determined using the priority business weights.
[0049] S132. Write a number of the resource regulation parameters into the hardware scheduler of the FPGA circuit so that the hardware scheduler performs resource regulation according to the number of the resource regulation parameters in the next preset scheduling cycle.
[0050] In one embodiment, resource control parameters may include: a communication resource ratio, a bandwidth quota, and a burst length. The communication resource ratio is the processing time slice ratio, the bandwidth quota is the communication bandwidth, and the burst length is an adaptive adjustment value for emergency situations.
[0051] After calculating several resource control parameters, these parameters can be written into the hardware scheduler of the FPGA circuit. This allows the hardware scheduler to perform resource control and updates based on these parameters in the next preset scheduling cycle. After the update, business processing can be performed based on the resource control parameters in the next preset scheduling cycle.
[0052] Specifically, AXI-Lite can be used to send data to the HW-Scheduler hardware scheduler of the FPGA circuit. The HW-Scheduler hardware scheduler of the FPGA circuit can, within the next epoch cycle, arbitrate the AXI bus access of the communication link or sensing link in real time based on parameters, limit bandwidth and time slice occupancy, and at the same time feed back data such as resource utilization, forming a closed loop of "acquisition-computation-feedback".
[0053] After the hardware scheduler writes several resource control parameters into the shadow register, it checks the configuration validity flag at the scheduling cycle boundary and atomically loads the time slice ratio, bandwidth quota, and burst length parameters in the shadow register into the active register. During the scheduling period, the hardware scheduler selects the service type of the current service based on the time slice parameter and limits the cumulative data transmission volume of each service during the scheduling period through the bandwidth budget counter; when it is detected that the bandwidth quota is exhausted or there is no available data for the current service, the scheduler prohibits the corresponding service from continuing to initiate bus access requests or switches to other services in advance. At the end of the scheduling cycle, the hardware scheduler latches the bandwidth utilization and latency statistics and writes them into the monitoring register, so that the processing system can update the policy in the next scheduling cycle.
[0054] The scheduling execution latency has been reduced from milliseconds to microseconds, meeting the real-time requirements of fast-fading channels and burst pulses; moreover, service switching can be completed without reconstructing hardware paths during the control process, avoiding interruptions and frame drops; in addition, hardware-level arbitration reduces CPU usage and improves overall efficiency.
[0055] As an example, determining several resource control parameters using the priority business weights may include the following sub-steps: S1311. Calculate the communication resource ratio using the priority service weight.
[0056] S1312. Calculate the service scheduling duration using the communication resource ratio and the preset scheduling period, and calculate the bandwidth quota using the communication resource ratio.
[0057] S1313, Adjust the burst length value based on the cache water level threshold.
[0058] In one embodiment, the proportion of communication resources for communication services and the proportion of communication resources for sensing services can be calculated.
[0059] In one embodiment, the proportion of communication resources for communication services The proportion of communication resources for sensing services It can be represented as follows: ; In the above formula, r c r represents the resource allocation ratio of communication services within the current scheduling cycle. min To be the minimum percentage, r min =0.1.
[0060] Specifically, the resource allocation coefficient r of communication services in the current scheduling cycle. c It can be represented as follows: ; In the above formula, ϵ is a regularization constant, which needs to be calculated for the allocation of time slots within each scheduling cycle. To avoid division by zero, ϵ = 10. -3 To avoid division by zero errors. c r represents the resource allocation ratio of communication services within the current scheduling cycle. s To sense the resource proportion of the business in the current scheduling cycle.
[0061] r c and r s It is not a time length itself, but a dimensionless scaling factor, which is used to calculate the scaling parameter of time slices; and It is a proportional parameter that has passed the minimum proportion constraint.
[0062] In addition, based on the aforementioned communication resource proportion The time slice ratio of communication services and sensing services within a preset scheduling period can be determined. This time slice ratio can be expressed as a percentage and must satisfy... and The sum of the two is 100%.
[0063] Specifically, this can be achieved through the communication priority service weight S. c Similarly, the proportion of communication resources for communication services can be calculated using the perceived priority service weight S. s Calculate the proportion of communication resources used for sensing services.
[0064] In one embodiment, the service scheduling duration T of the communication service comn It is a time slice, and its calculation can be shown in the following formula: ; In the above formula, T comn The service scheduling duration for communication services; T epoch The duration of the preset scheduling period can also represent a time window of a scheduling period, which can be 1ms, a data frame period, or a preset fixed duration. This represents the proportion of communication resources used in communication services.
[0065] In one embodiment, the service scheduling duration T of the sensing service sense It is a time slice, and its calculation can be shown in the following formula: ; In the above formula, T sense To sense the duration of business scheduling.
[0066] In one embodiment, the bandwidth quota value for communication services and the bandwidth quota value for sensing services can be expressed as follows: ; In the above formula, B c B is the bandwidth quota value for communication services. s The bandwidth quota value for sensing services; where B total =R axi *T epoch R axi It is the effective available bandwidth of AXI, T epoch It is the duration of the scheduling cycle.
[0067] It should be noted that the congestion coefficient λ directly affects the bandwidth quota calculation, referring to the above formula (B c =λ*r c ′*B total When W = W hi At that time, e W =1, λ=0.7, meaning that the bandwidth quotas for both communication and sensing are reduced to 70% of the original plan, limiting the amount of data input and avoiding buffer overflow.
[0068] In one embodiment, the burst length value can be adjusted according to the cache level threshold. The burst length is adaptively adjusted according to the cache level and the emergency status of the corresponding service. When the cache level is high or the corresponding service is in a restricted state, a smaller burst length is selected; when the system load is low and the service allows, a larger burst length is selected.
[0069] Specifically, the burst length value can be adjusted as follows: ; ; ; Burst's priority is to ensure throughput: ; ; It should be noted that the adjustment rules in the above formula are not completely independent, but are based on the same set of scheduling parameters, and are adjusted differently by different bias directions and constraint strengths. For example, in a communication-priority service scenario, subsequent scheduling time slice allocation is biased towards communication (communication time slice ratio r). c With the addition of features such as 'upward bias', bandwidth quotas are tilted towards communication, and burst length strategies are more aggressive. Under the perception priority mode, the proportion of perception time slices increases, bandwidth resources are tilted towards perception, and burst length priority ensures throughput stability. Under balanced scheduling, resources are allocated according to the computation ratio to maintain the overall resource utilization efficiency of the system.
[0070] Reference Figure 2The diagram shows an operation flowchart of a resource regulation method based on heterogeneous performance indicators provided by an embodiment of the present invention.
[0071] Specifically, the operation process of the resource regulation method based on heterogeneous performance indicators may include the following steps: The first step is to obtain heterogeneous performance parameters (KPIs) for each scheduling epoch, including: communication latency L and sensing detection rate P. d And the cache water level W.
[0072] The second step is to ensure that the cache water level W is greater than the high-order cache water level W. hi This can perform cache protection actions and allow the primary task to yield, reducing BW_cap by 0.7, decreasing burst length, and yielding 10% of the time slice. It also marks ALERT.W. hi It takes effect immediately with the current Epoch.
[0073] Third step, if the communication delay L is greater than the maximum communication delay L... max It can perform communication protection actions, increase communication bandwidth, increase the time slice ratio of communication services, and take effect in the next Epoch.
[0074] Fourth step, if the perception detection rate P d Less than the minimum detection rate P d_min It can perform perception enhancement actions, increase perception bandwidth, and increase burst length by one level, which will take effect in the next epoch.
[0075] Step 5: If the cache level W is less than the high-order cache level W... hi The communication delay L is less than the maximum communication delay L. max And the perception detection rate P d Greater than the minimum detection rate P d_min If no threshold is set, then regular weighted arbitration will be executed.
[0076] The sixth step is to update the register parameters and write them to the double buffer during execution.
[0077] Step 7: Cooldown time and hold option system, cooldown=2, hold=2.
[0078] Step 8: Proceed to the next epoch.
[0079] In this embodiment, the present invention provides a resource regulation method based on heterogeneous performance indicators. Its advantages are as follows: the present invention can acquire heterogeneous performance parameters of the FPGA circuit in each preset scheduling cycle; if any heterogeneous performance indicator value does not meet the corresponding indicator threshold, different priority service weights are determined using the heterogeneous performance indicator value; several resource regulation parameters are determined according to the priority service weights, and resource regulation of the FPGA circuit is performed according to these parameters. The present invention can acquire performance parameters in each cycle, and when any performance parameter is not met, resource regulation is performed based on the heterogeneous performance indicator value, which not only improves the timeliness of regulation but also simplifies the regulation process and improves regulation efficiency.
[0080] This invention also provides a resource regulation device based on heterogeneous performance indicators, see [link to relevant documentation]. Figure 3 The diagram shows a schematic representation of a resource regulation device based on heterogeneous performance indicators according to an embodiment of the present invention.
[0081] As an example, the resource regulation device based on heterogeneous performance indicators may include: The acquisition module 201 is used to acquire the heterogeneous performance parameters of the FPGA circuit in each preset scheduling cycle. The heterogeneous performance parameters include several different heterogeneous performance index values. The determination module 202 is used to determine different priority service weights based on the heterogeneous performance index values if any one of the heterogeneous performance index values does not meet the corresponding index threshold. The control module 203 is used to determine a number of resource control parameters according to the priority service weights, and to control the resources of the FPGA circuit according to the number of resource control parameters.
[0082] Optionally, if any one of the heterogeneous performance index values does not meet the corresponding index threshold, then different priority service weights are determined using the heterogeneous performance index values, including: Each of the heterogeneous performance index values is normalized and smoothed to obtain several processing performance index values. Determine whether each of the processing performance index values meets the corresponding index threshold; If any of the heterogeneous performance index values does not meet the corresponding index threshold, then the communication priority service weight and perception priority service weight are calculated using each of the processing performance index values.
[0083] Optionally, the processing performance index values include: the processing performance index value of communication latency and the processing performance index value of sensing detection rate; The calculation of communication priority service weights and perception priority service weights using the aforementioned indicator thresholds includes: The degree of communication delay violation is calculated using the processing performance index value of the communication delay, and the priority service weight value of communication is calculated using the degree of communication delay violation and the preset first service weight value. The degree of perceived violation is calculated using the processing performance index value of the perceived detection rate, and the perceived priority service weight value is calculated using the degree of perceived violation and the preset second service weight value.
[0084] Optionally, the step of determining a plurality of resource control parameters based on the priority service weights, and performing resource control on the FPGA circuit based on the plurality of resource control parameters, includes: Several resource control parameters are determined using the aforementioned priority business weights; Several resource regulation parameters are written into the hardware scheduler of the FPGA circuit so that the hardware scheduler can perform resource regulation according to the several resource regulation parameters in the next preset scheduling cycle.
[0085] Optionally, the indicator threshold includes: a buffer water level threshold; The method of determining several resource control parameters using the priority business weights includes: The communication resource ratio is calculated using the aforementioned priority service weights; The service scheduling duration is calculated using the communication resource ratio and the preset scheduling period, and the bandwidth quota value is calculated using the communication resource ratio. Adjust the burst length value based on the cache water level threshold.
[0086] This invention also provides a resource regulation system based on heterogeneous performance indicators, see [link to relevant documentation]. Figure 4 The diagram shows a structural block diagram of a resource regulation system based on heterogeneous performance indicators provided by an embodiment of the present invention.
[0087] As an example, the resource regulation system based on heterogeneous performance indicators may include: a processing module, an FPGA circuit, and an RF front-end device; The FPGA circuit is connected to the processing module and the RF front-end device, respectively. The processing module is applicable to the resource regulation method based on heterogeneous performance indicators as described in the above embodiments.
[0088] Reference Figure 5 The diagram shows a schematic representation of a resource regulation system based on heterogeneous performance indicators according to an embodiment of the present invention.
[0089] The processing module is PS, the FPGA circuit is PL, and the RF front-end device is RF front-end.
[0090] Processing System (PS): Responsible for global strategy generation, KPI collection, and control parameter distribution.
[0091] Programmable logic (PL): includes a communication acceleration unit, a perception acceleration unit, a hardware scheduler (HW-Scheduler), a monitoring module (MON), and a shared storage interface module.
[0092] AXI interconnect bus architecture: connects the above modules and supports multi-master and multi-slave access and bandwidth arbitration.
[0093] Among them, the processing system PS is responsible for calculating the scheduling strategy parameters based on the KPIs reported by the monitoring module; The programmable logic (PL) is responsible for executing the specific data path; The hardware scheduler HW-Scheduler is located inside the PL and is responsible for real-time arbitration and bandwidth control of AXI access to the communication link and the sensing link according to the scheduling parameters issued by the PS within the scheduling cycle (Epoch).
[0094] The FPGA circuit includes: a hardware scheduler (HW-Scheduler), an IP soft core (AXI DMA), a communication link, a sensing link, and a buffer pool; The hardware scheduler and the IP soft core are respectively connected to the processing module; The communication link and the sensing link are respectively connected to the RF front-end device; The cache pool is connected to the hardware scheduler, the IP soft core, the communication link, and the sensing link, respectively.
[0095] (1) The PS side performs smoothing and normalization processing on the KPIs reported by MON; (2) Calculate the urgency of communication services and the urgency of perception services based on the normalized KPIs; (3) Determine the scheduling mode based on the urgency comparison results and the buffer level status; (4) Generation time slice ratio, bandwidth quota and burst length parameters; (5) Write the parameters into the shadow register of HW-Scheduler through the AXI-Lite interface, and it will take effect in the next scheduling cycle.
[0096] Traditional solutions only optimize spectrum and time slot resources, neglecting the coordinated management of on-chip resources such as computing, storage, and bus bandwidth, resulting in unbalanced resource allocation and low utilization. This invention adopts a PS+PL heterogeneous architecture, deploying the computing tasks of communication links and sensing links on the PL layer acceleration unit, and achieving unified management and control of computing, storage, and bandwidth resources through the AXI bus; This invention introduces three core KPIs: communication latency, sensing detection rate, and cache level, transforming the resource requirements of heterogeneous services into a unified urgency indicator, providing a quantitative basis for resource allocation. Meanwhile, this invention calculates three types of parameters based on urgency: time slice ratio, bandwidth quota, and burst length, to achieve coordinated allocation of time, bandwidth, and cache resources, avoiding the limitations of single-dimensional resource scheduling.
[0097] Existing technologies rely on scheduling strategies issued by the CPU software layer, resulting in latency in the millisecond range, which cannot meet the real-time requirements of fast-fading channels and sudden pulses.
[0098] The present invention deploys a hardware scheduler (HW-Scheduler) in the PL layer, which can embed the core arbitration logic in the FPGA hardware, directly control the AXI bus access in real time, and reduce the arbitration latency to the microsecond level to meet the low latency requirements of the sensing service. Based on this, the PS layer is responsible for strategy calculation and parameter distribution within the cycle (updated at the microsecond level), while the PL layer is responsible for real-time execution, avoiding the scheduling overhead of the software layer; In addition, scheduling parameters can be updated at fixed intervals (such as 1ms) to ensure policy flexibility while avoiding latency fluctuations caused by frequent configuration.
[0099] The current technology requires reconfiguration of hardware paths when switching between communication and sensing services, lacks threshold triggering and protection mechanisms, and is prone to interruption when services change abruptly.
[0100] This invention determines service priority based on urgency difference and dead zone threshold θ, and can achieve smooth switching between three modes: communication priority, perception priority, and balanced scheduling without reconstructing hardware paths. Furthermore, the scheduling parameters are stored in a shadow register and are atomically loaded into the active register at the boundary of the next epoch cycle, thus avoiding service interruption during the parameter update process.
[0101] Those skilled in the art will understand that, for ease of description and brevity, the specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0102] Furthermore, this application also provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the resource regulation method based on heterogeneous performance indicators as described in the above embodiments.
[0103] Furthermore, embodiments of this application also provide a computer-readable storage medium storing a computer-executable program, the computer-executable program being used to cause a computer to execute the resource regulation method based on heterogeneous performance indicators as described in the above embodiments.
[0104] In the description of the embodiments of the present invention, it should be noted that the terms "above," "below," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. When an element such as a layer, region, or substrate is referred to as being "above" or "on top of" another element, it may be directly on the other element, or there may be an intermediate element. Conversely, when an element is referred to as being "directly on" or "above" another element, there is no intermediate element. It should also be understood that when an element is referred to as being "below" or "under" another element, it may be directly below or under the other element, or there may be an intermediate element. Conversely, when an element is referred to as being "directly below" or "under" another element, there is no intermediate element. Unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0105] Those skilled in the art will understand that embodiments of this application may also include computer program products. Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0106] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), devices, and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0107] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0108] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0109] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A resource regulation method based on heterogeneous performance indicators, characterized in that, The method includes: In each preset scheduling cycle, the heterogeneous performance parameters of the FPGA circuit are acquired, and the heterogeneous performance parameters include several different heterogeneous performance index values. If any of the heterogeneous performance index values does not meet the corresponding index threshold, then the heterogeneous performance index values are used to determine different priority service weights. Several resource control parameters are determined based on the priority service weights, and the FPGA circuit is resource-controlled based on these parameters.
2. The resource regulation method based on heterogeneous performance indicators according to claim 1, characterized in that, If any of the heterogeneous performance index values does not meet the corresponding index threshold, then different priority service weights are determined using the heterogeneous performance index values, including: Each of the heterogeneous performance index values is normalized and smoothed to obtain several processing performance index values. Determine whether each of the processing performance index values meets the corresponding index threshold; If any of the heterogeneous performance index values does not meet the corresponding index threshold, then the communication priority service weight and perception priority service weight are calculated using each of the processing performance index values.
3. The resource regulation method based on heterogeneous performance indicators according to claim 2, characterized in that, The processing performance metrics include: the processing performance metrics for communication latency and the processing performance metrics for sensing detection rate. The calculation of communication priority service weights and perception priority service weights using the aforementioned indicator thresholds includes: The degree of communication delay violation is calculated using the processing performance index value of the communication delay, and the priority service weight value of communication is calculated using the degree of communication delay violation and the preset first service weight value. The degree of perceived violation is calculated using the processing performance index value of the perceived detection rate, and the perceived priority service weight value is calculated using the degree of perceived violation and the preset second service weight value.
4. The resource regulation method based on heterogeneous performance indicators according to claim 1, characterized in that, The step of determining several resource control parameters based on the priority service weights, and then controlling the resources of the FPGA circuit based on these parameters, includes: Several resource control parameters are determined using the aforementioned priority business weights; Several resource regulation parameters are written into the hardware scheduler of the FPGA circuit so that the hardware scheduler can perform resource regulation according to the several resource regulation parameters in the next preset scheduling cycle.
5. The resource regulation method based on heterogeneous performance indicators according to claim 4, characterized in that, The indicator thresholds include: buffer water level threshold; The method of determining several resource control parameters using the priority business weights includes: The communication resource ratio is calculated using the aforementioned priority service weights; The service scheduling duration is calculated using the communication resource ratio and the preset scheduling period, and the bandwidth quota value is calculated using the communication resource ratio. Adjust the burst length value based on the cache water level threshold.
6. A resource regulation device based on heterogeneous performance indicators, characterized in that, The device includes: The acquisition module is used to acquire the heterogeneous performance parameters of the FPGA circuit in each preset scheduling cycle. The heterogeneous performance parameters include several different heterogeneous performance index values. The determination module is used to determine different priority business weights based on the heterogeneous performance index values if any one of the heterogeneous performance index values does not meet the corresponding index threshold. The control module is used to determine several resource control parameters according to the priority service weights, and to control the resources of the FPGA circuit according to the several resource control parameters.
7. A resource regulation system based on heterogeneous performance indicators, characterized in that, The system includes: a processing module, an FPGA circuit, and an RF front-end device; The FPGA circuit is connected to the processing module and the RF front-end device, respectively. The processing module is applicable to the resource regulation method based on heterogeneous performance indicators as described in any one of claims 1-5.
8. The resource regulation system based on heterogeneous performance indicators according to claim 7, characterized in that, The FPGA circuit includes: a hardware scheduler, an IP soft core, a communication link, a sensing link, and a buffer pool; The hardware scheduler and the IP soft core are respectively connected to the processing module; The communication link and the sensing link are respectively connected to the RF front-end device; The cache pool is connected to the hardware scheduler, the IP soft core, the communication link, and the sensing link, respectively.
9. An electronic device, comprising: A memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, when the processor executes the program, it implements the resource regulation method based on heterogeneous performance indicators as described in any one of claims 1-5.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the resource regulation method based on heterogeneous performance indicators as described in any one of claims 1-5.