Technological method applied to manufacturing of MOS (Metal Oxide Semiconductor) device
By forming an oxide layer on the polysilicon layer and performing ion implantation during the fabrication of MOS devices, the threshold voltage fluctuation problem caused by uneven predoping of the polysilicon gate is solved, thus improving the electrical performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICONDUCTOR MANUFACTURING (WUXI) LTD
- Filing Date
- 2026-01-16
- Publication Date
- 2026-05-12
AI Technical Summary
In the prior art, the threshold voltage of MOS devices fluctuates greatly, mainly due to the polysilicon depletion effect caused by uneven predoping of the polysilicon gate, which affects the electrical performance of the device.
An oxide layer is formed on the polysilicon layer, and the surface morphology is repaired and the surface uniformity is improved by TEOS deposition process. Ion implantation is performed on the oxide layer to suppress the polysilicon gate depletion effect.
By improving the surface uniformity of the polysilicon layer, the fluctuation of the device threshold voltage is reduced, thereby improving the device's electrical performance.
Smart Images
Figure CN122028451A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a process method applied in the fabrication of MOS devices. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs, referred to as "MOS" in this application) are electronic devices widely used in analog and digital circuits. The following explanation uses an N-type MOS (negative-type MOS, NMOS) device as an example to illustrate the operating state of MOS devices: refer to Figure 1 This shows a schematic cross-sectional view of an NMOS device in its operating state. For example, such as... Figure 1 As shown, a gate dielectric layer 120 is formed on the substrate 110, and a polysilicon gate 130 is formed on the gate dielectric layer 120. The substrate 110 is doped with P-type (positive) impurities, and the polysilicon gate 130 is doped with N-type impurities. When a voltage is applied to the polysilicon gate 130, the polysilicon gate 130 attracts free electrons from the substrate 110 to the region above the substrate 110 near the gate dielectric layer 120, forming an inversion layer 1101. Simultaneously, carriers of the opposite conductivity type accumulate in the region of the polysilicon gate 130 near the gate dielectric layer 120, forming a polysilicon depletion layer 1301 to maintain electrical neutrality. This charge accumulation process will inevitably deplete the charge of the nearby semiconductor. When the charge in the semiconductor is completely depleted, the semiconductor device becomes almost equivalent to an insulator, which is equivalent to increasing the equivalent oxide thickness (EOT) of the gate dielectric layer.
[0003] In view of this, related technologies have proposed a polysilicon gate pre-doping process to suppress the polysilicon depletion effect (PDE) and reduce the equivalent thickness of the gate dielectric layer. However, taking NMOS devices as an example, in the polysilicon gate pre-doping process, phosphorus (P) is used as the dopant source. The distribution of phosphorus in polysilicon is uneven, and polysilicon depletion occurs near the gate dielectric, resulting in large fluctuations in the threshold voltage of the NMOS device and reducing the electrical performance of the device. Summary of the Invention
[0004] This application provides a process method for fabricating MOS devices, which can solve the problem of large threshold voltage fluctuations in MOS devices in related technologies. The method includes: A polysilicon layer is formed on a gate dielectric layer, the gate dielectric layer being formed on a substrate, and the polysilicon layer being used to form the polysilicon gate of the MOS device; An oxide layer is formed on the polysilicon layer using a TEOS deposition process. The oxide layer is used to repair the surface morphology of the polysilicon layer and improve the uniformity of the polysilicon layer surface. Photoresist is covered on the oxide layer, and the photoresist in the target area is removed by exposure and development in sequence, so that the oxide layer in the target area is exposed. Ion implantation is performed on the polysilicon layer in the target region to suppress the depletion effect of the polysilicon gate when the MOS device is operating.
[0005] In some embodiments, after an oxide layer is formed on the polycrystalline silicon layer by a TEOS deposition process, the thickness of the oxide layer is 50 angstroms to 200 angstroms.
[0006] In some embodiments, the thickness of the polycrystalline silicon layer is 800 to 2000 angstroms.
[0007] In some embodiments, during the formation of an oxide layer on the polycrystalline silicon layer by a TEOS deposition process, the amount of TEOS introduced is 4 to 6 grams.
[0008] In some embodiments, during the formation of an oxide layer on the polycrystalline silicon layer using a TEOS deposition process, the flow rate of the carrier gas is 3000 SCCM to 5000 SCCM.
[0009] In some embodiments, during the formation of an oxide layer on the polycrystalline silicon layer using the TEOS deposition process, the temperature within the reaction chamber is between 350 and 450 degrees Celsius.
[0010] In some embodiments, during the formation of an oxide layer on the polycrystalline silicon layer using a TEOS deposition process, the pressure within the reaction chamber is 4 to 6 Torr.
[0011] The technical solution of this application has at least the following advantages: By forming an oxide layer on the polysilicon layer using the TEOS deposition process during the fabrication of MOS devices before predoping the polysilicon layer, the surface morphology of the polysilicon layer is repaired and the surface uniformity of the polysilicon layer is improved. This improves the uniformity of impurity distribution in the polysilicon layer after subsequent ion implantation, reduces the depletion effect, and lowers the fluctuation of the device threshold voltage. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0013] Figure 1 This is a cross-sectional schematic diagram of an NMOS device in its operating state; Figure 2 This is a flowchart of a process method applied in the fabrication of MOS devices according to an exemplary embodiment of this application; Figures 3 to 5 This is a schematic diagram of the manufacturing process of a process method provided in an exemplary embodiment of this application. Detailed Implementation
[0014] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0015] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0016] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0017] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0018] refer to Figure 2 It illustrates a flowchart of a process method applied to the fabrication of MOS devices according to an exemplary embodiment of this application, such as... Figure 2 As shown, the method includes: Step S1: A polysilicon layer is formed on the gate dielectric layer. The gate dielectric layer is formed on the substrate, and the polysilicon layer is used to form the polysilicon gate of the MOS device.
[0019] refer to Figure 3 This illustrates a cross-sectional schematic diagram after a polysilicon layer has been formed on the gate dielectric layer. For example, such as... Figure 3 As shown, a polysilicon layer 230 can be formed on the gate dielectric layer 220 by a deposition process in a furnace tube. The thickness of the polysilicon layer 230 is 800 Å to 2000 Å. The gate dielectric layer 220 is formed on a substrate 210 (which can be a silicon (Si) substrate). A silicon dioxide (SiO2) layer can be formed on the substrate 210 by a thermal oxidation process to form the gate dielectric layer 220.
[0020] Step S2: An oxide layer is formed on the polycrystalline silicon layer using the TEOS deposition process. The oxide layer is used to repair the surface morphology of the polycrystalline silicon layer and improve the uniformity of the polycrystalline silicon layer surface.
[0021] refer to Figure 4 It shows a schematic cross-sectional view after the oxide layer has been formed. For example, such as... Figure 4 As shown, the TEOS deposition process is a chemical vapor deposition (CVD) process in which tetraethoxysilane (TEOS, chemical formula: Si(OC2H5)4) is introduced into the reaction as a silicon source. The TEOS deposition process forms an oxide layer 231 (which mainly contains silicon dioxide) on the polycrystalline silicon layer 230 to repair the surface morphology of the polycrystalline silicon layer 230 and improve its surface uniformity. The thickness of the oxide layer 231 is 50 angstroms to 200 angstroms.
[0022] During the formation of oxide layer 231 on polycrystalline silicon layer 230 by TEOS deposition process, the improvement of subsequent predoping effect can be ensured by controlling at least one of the reaction conditions such as TEOS flow rate, carrier gas (inert gas introduced in the reaction), temperature in the reaction chamber and pressure in the reaction chamber.
[0023] Optionally, during the formation of oxide layer 231 on polycrystalline silicon layer 230 by TEOS deposition process, the amount of TEOS introduced is 4 grams (g) to 6 grams; optionally, during this process, the flow rate of carrier gas is 3000 standard cubic centimeters per minute (SCCM) to 5000 SCCM; optionally, during this process, the temperature in the reaction chamber is 350 degrees Celsius (°C) to 450 degrees Celsius; optionally, during this process, the pressure in the reaction chamber is 4 Torr to 6 Torr.
[0024] Step S3: Cover the oxide layer with photoresist, and remove the photoresist in the target area by exposure and development in sequence, so as to expose the oxide layer in the target area.
[0025] Step S4: Ion implantation is performed on the polysilicon layer in the target region to suppress the depletion effect of the polysilicon gate when the MOS device is working.
[0026] refer to Figure 5 This illustrates a cross-sectional schematic diagram of ion implantation into a polycrystalline silicon layer in a target region. For example, such as... Figure 5 As shown, photoresist 300 is coated on the oxide layer 231. The photoresist in the target area is removed by exposure and development, exposing the oxide layer 231 in the target area. Ion implantation is then performed to pre-dope the polysilicon layer 230 to suppress the depletion effect. If the MOS device is an NMOS device, the doped impurities include phosphorus, and the impurities doped in the substrate 210 are P-type impurities.
[0027] In summary, in the embodiments of this application, by forming an oxide layer on the polysilicon layer through TEOS deposition process before predoping the polysilicon layer during the fabrication of the MOS device, the surface morphology of the polysilicon layer is repaired and the surface uniformity of the polysilicon layer is improved. This improves the uniformity of impurity distribution in the polysilicon layer after subsequent ion implantation, improves the depletion effect, and reduces the fluctuation of the device threshold voltage.
[0028] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A process method applied in the fabrication of MOS devices, characterized in that, include: A polysilicon layer is formed on a gate dielectric layer, the gate dielectric layer being formed on a substrate, and the polysilicon layer being used to form the polysilicon gate of the MOS device; An oxide layer is formed on the polysilicon layer using a TEOS deposition process. The oxide layer is used to repair the surface morphology of the polysilicon layer and improve the uniformity of the polysilicon layer surface. Photoresist is covered on the oxide layer, and the photoresist in the target area is removed by exposure and development in sequence, so that the oxide layer in the target area is exposed. Ion implantation is performed on the polysilicon layer in the target region to suppress the depletion effect of the polysilicon gate when the MOS device is operating.
2. The method according to claim 1, characterized in that, After an oxide layer is formed on the polycrystalline silicon layer using the TEOS deposition process, the thickness of the oxide layer is 50 to 200 angstroms.
3. The method according to claim 2, characterized in that, The thickness of the polycrystalline silicon layer is between 800 angstroms and 2000 angstroms.
4. The method according to any one of claims 1 to 3, characterized in that, During the formation of an oxide layer on the polycrystalline silicon layer using a TEOS deposition process, 4 to 6 grams of TEOS are introduced.
5. The method according to claim 4, characterized in that, During the formation of the oxide layer on the polycrystalline silicon layer using the TEOS deposition process, the carrier gas flow rate is 3000 SCCM to 5000 SCCM.
6. The method according to claim 5, characterized in that, During the formation of an oxide layer on the polycrystalline silicon layer using the TEOS deposition process, the temperature inside the reaction chamber is between 350 and 450 degrees Celsius.
7. The method according to claim 6, characterized in that, During the formation of an oxide layer on the polycrystalline silicon layer using the TEOS deposition process, the pressure inside the reaction chamber is 4 to 6 Torr.